Fast charging circuit, CC detection module with rectification and fast charging cable

Abstract

The present invention provides a fast charging circuit, a CC detection module with rectification, and a fast charging line, wherein the positive electrode of a diode D2 is connected to a rectifier input end, and the negative electrode of the diode D2 is respectively connected to the positive electrode of a diode D1 and an input end of an inverter; one end of a switch unit is connected to the negative electrode of the diode D2, and the other end is respectively connected to the negative electrode of the diode D1, one end of a capacitor C1, and a control end of the inverter, and the switch unit establishes or disconnects the connection between the negative electrode of the diode D2 and the capacitor C1 based on a communication signal; the other end of the capacitor C1 is grounded; the output end of the inverter is connected to the gate of an NMOS tube Q1; the drain of the NMOS tube Q1 is connected to a detection signal input end through a resistor R1, the drain of the NMOS tube Q1 is also connected to the gate of the NMOS tube Q2, and the source of the NMOS tube Q1 is grounded; the drain of the NMOS tube Q2 is connected to the detection signal input end through a resistor R2, and the source of the NMOS tube Q2 is grounded.

Description

Technical Field

[0001] The present invention relates to the field of charging technology, and in particular to a fast charging circuit, a CC detection module with rectification, and a fast charging cable. Background Art

[0002] Some mobile phones on the market currently support USB PD (USB-Power Delivery) fast charging function. USB PD is one of the current mainstream fast charging protocols and is a fast charging specification developed by the USB-IF (USB Implementers Forum). USB PD increases power delivery through USB cables and connectors, expanding the cable bus power supply capability in USB applications. This specification can achieve higher voltage and current, with a maximum power delivery of 100 watts, and can freely change the direction of power delivery.

[0003] Take one of the chargers on the market that supports USB PD fast charging as an example. Figure 1 As shown, it is a schematic diagram of a fast charging circuit 100 that supports USB PD fast charging function. The fast charging circuit includes an input interface terminal 1, an output interface terminal 4, a CC (Configuration Channel) detection module 2 and a verification module 3. Each module and port is packaged together with a printed circuit board on a fast charging circuit. The fast charging circuit 100 is connected to an adapter (not shown in the figure) through the input interface terminal 1, and is connected to a mobile phone (not shown in the figure) through the output interface terminal 4 to form a complete charging system. Among them, when the adapter connected to the fast charging circuit 100 is connected to the power supply, the detection signal CC is output to the CC detection module 2. The detection signal CC is a current source with a constant output of 3V / 320uA (in this circuit, the CC detection module 2 acts as a load, and the load voltage is recorded as VLOAD), and outputs a charging voltage VBUS of 5V or 15V to the fast charging circuit 100. The value of the output charging voltage VBUS is adjusted according to whether the data verification is passed or the value of the load voltage VLOAD of the CC detection module 2. When it is detected that the data verification is passed, the charging voltage VBUS will switch from 5V to 15V, and when it is detected that the load voltage VLOAD rises, it will be reset from 15V to 5V. When the mobile phone is connected to the fast charging circuit 100 connected to the adapter, the power signal SB and the communication signal SA are respectively provided to the fast charging circuit 100 through two different pins of the output interface terminal 4. The power signal SB is used to provide a voltage for driving the verification module 3 to operate, and the other function is to provide an adjustment signal for changing the value of the above-mentioned load voltage VLOAD. The communication signal SA is used as a signal for establishing communication between the mobile phone and the fast charging circuit 100 for data verification.

[0004] The disadvantage of the above-mentioned fast charging circuit 100 is that in addition to receiving the communication signal SA sent from the mobile phone, the charging output adjustment of the adapter also needs to receive the power signal SB from the mobile phone. On the one hand, this must require that the mobile phone and the output interface terminal 4 respectively retain pins for sending and receiving the power signal SB, making the circuit structure of the interface terminal complicated; on the other hand, the requirement to send the communication signal SA and the power signal SB at the same time brings a very severe challenge to the mobile phone with low battery.

[0005] Therefore, a fast charging circuit that no longer requires receiving a power signal SB from a mobile phone is desired without affecting the stable regulation of the charging output. Summary of the invention

[0006] In view of the above, the present invention provides a fast charging circuit, a CC detection module with rectification, and a fast charging cable.

[0007] A CC detection module with rectification, the CC detection module with rectification comprising a rectification input end, a diode D2, a switch unit, a detection signal input end, a diode D1, a resistor R1, a resistor R2, an NMOS tube Q1, an NMOS tube Q2, an inverter, a capacitor C1 and a load voltage output end; the detection signal input end is used to receive a detection signal sent by an adapter; the rectification input end is used to receive a communication signal sent by a mobile phone end; the positive electrode of the diode D2 is connected to the rectification input end, and the negative electrode of the diode D2 is respectively connected to the positive electrode of the diode D1 and the input end of the inverter; one end of the switch unit is connected to the negative electrode of the diode D2, and the other end is respectively connected to the negative electrode of the diode D1, one end of the capacitor C1 and the input end of the inverter; The control end of the inverter is connected, and the switch unit establishes or disconnects the connection between the cathode of the diode D2 and the capacitor C1 based on the communication signal; the other end of the capacitor C1 is grounded; the output end of the inverter is connected to the gate of the NMOS tube Q1; the drain of the NMOS tube Q1 is connected to the detection signal input end through the resistor R1, the drain of the NMOS tube Q1 is also connected to the gate of the NMOS tube Q2, and the source of the NMOS tube Q1 is grounded; the drain of the NMOS tube Q2 is connected to the detection signal input end through the resistor R2, and the source of the NMOS tube Q2 is grounded; the load voltage output end is located between the detection signal input end and the resistor R2, and is used to output the load voltage;

[0008] When the communication signal verification passes, the charging voltage of the fast charging circuit increases, and when the load voltage of the CC detection module increases, the charging voltage of the fast charging circuit decreases.

[0009] Preferably, the switch unit includes a first input node, a second input node, an SR latch and a PMOS tube P1; the first input node is connected to the cathode of the diode D2; the first input end of the SR latch is connected to the first input node, the second input end of the SR latch is connected to the second input node, the output end of the SR latch is connected to the control end of the PMOS tube P1, the drain of the PMOS tube P1 is connected to the cathode of the diode D2, and the source of the PMOS tube P1 is connected to one end of the capacitor C1.

[0010] Preferably, the communication signal verification method is to perform data verification through an encryption algorithm or a challenge handshake authentication protocol.

[0011] Preferably, the capacitance value of the capacitor C1 is 0.1 uF.

[0012] The beneficial effect of the CC detection module with rectification is that, on the basis of reducing the input pins and achieving stable and controllable switching of the charging output Vbus of the adapter, since only one capacitor is provided in the circuit, the cost is further reduced.

[0013] A fast charging circuit including the above-mentioned CC detection module with rectification includes an input interface end, an output interface end and a verification module.

[0014] The input interface end is used to connect with the adapter to receive the detection signal and the charging voltage from the adapter, and provide the detection signal and the charging voltage to the CC detection module with rectification and the output interface end respectively, wherein the detection signal is used to power the CC detection module with rectification;

[0015] The output interface end is used to connect to the mobile phone end to receive the communication signal from the mobile phone end and provide the charging voltage to the mobile phone end;

[0016] The verification module is used to perform data verification according to the communication signal;

[0017] When the communication signal verification passes, the charging voltage increases, and when the load voltage of the CC detection module increases, the charging voltage decreases.

[0018] Preferably, the verification module is an encryption module, which is used to perform encryption verification on data through an encryption algorithm.

[0019] Preferably, the verification module is a handshake module, which verifies the data based on the challenge handshake authentication protocol.

[0020] Preferably, the CC detection module with rectification and the verification module are packaged on one chip.

[0021] Preferably, the CC detection module with rectification is packaged on a first chip, and the verification module is packaged on a second chip.

[0022] The beneficial effect of the above-mentioned fast charging circuit is that, on the basis of reducing the input pins and achieving stable and controllable switching of the charging output Vbus of the adapter, since the circuit only has one capacitor, the cost is further reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0024] Figure 1 A structural principle diagram of a fast charging circuit provided as the background technology of the present invention;

[0025] Figure 2 A circuit structure diagram of a CC detection module provided by the prior art of the present invention;

[0026] Figure 3 A circuit structure diagram of a CC detection module with rectification for a fast charging circuit provided in an embodiment of the present invention;

[0027] Figure 4 A circuit structure diagram of a switch unit provided in an embodiment of the present invention;

[0028] Figure 5 A waveform diagram of a communication signal and an interrupt signal provided by an embodiment of the present invention;

[0029] Figure 6 A waveform diagram of a communication signal circuit provided by an embodiment of the present invention;

[0030] Figure 7 A structural schematic diagram of a fast charging circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0033] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0034] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0035] like Figure 2 As shown, it is a circuit structure diagram of the existing CC detection module 2. The CC detection module 2 includes a detection signal input terminal S1, which is used to receive the detection signal CC sent from the adapter, and also includes a first resistor R1 and a second resistor R2 connected to the detection signal input terminal S1, and also includes a first NMOS tube Q1 and a second NMOS tube Q2 connected to the first resistor R1 and the second resistor R2, respectively, and the control end of the second NMOS tube Q2 is connected to the drain end of the first NMOS tube Q1, and the other ends of the first NMOS tube Q1 and the second NMOS tube Q2 are both grounded. It also includes an adjustment signal input terminal S2, which is used to receive a power signal SB sent from the mobile phone end. It also includes a first diode D1 whose positive electrode is connected to the adjustment signal input terminal S2, and a first capacitor C1 connected to the negative electrode of the first diode D1, and the other end of the first capacitor C1 is grounded. It also includes an inverter U1, the input end of the inverter U1 is connected to the adjustment signal input terminal S2, the output end is connected to the control end of the first NMOS tube Q1, and the control end of the inverter U1 is connected to the non-grounded end of the first capacitor C1.

[0036] The following is a circuit structure diagram of the CC detection module 2 to describe the detailed charging process of the fast charging circuit 100.

[0037] During the first charging state of the fast charging circuit 100, that is, the mobile phone is not connected to the charging line 100, at this time, since the power signal SB is not provided to the fast charging circuit 100, the first capacitor C1 is out of power, the inverter U1 does not work, and the first NMOS tube Q1 is cut off; since the detection signal input terminal S1 of the CC detection module 2 is always provided with the detection signal CC (3V / 320uA current source), and the driving voltage provided by the line of "detection signal input terminal S1-first resistor R1-gate of the second NMOS tube Q2" is already higher than the threshold voltage (0.8V) for turning on the second NMOS tube Q2, Q2 is turned on. Therefore, the CC detection module 2 is equivalent to the load connected to the second resistor R2, so VLOAD = 4.99*320uA = 1.6V. Since the mobile phone is not connected, the communication signal SA is not received, there is no data verification, and the adapter maintains a charging output of 5V.

[0038] During the second charging state of the fast charging circuit 100, that is, the mobile phone is connected to the charging line 100, a 3.3V power signal SB is provided to the fast charging circuit, the first capacitor C1 starts to charge, the inverter U1 works and inputs a high level (3.3V high-level power signal SB), the inverter U1 outputs a low level after inversion, and the first NMOS tube Q1 is still cut off; similarly to the previous state, the second NMOS tube Q2 is turned on. The CC detection module 2 is still equivalent to the load connected to the second resistor R2, VLOAD = 4.99K * 320uA = 1.6V. After the mobile phone is connected, if the communication signal SA sent by the mobile phone passes the data verification, the adapter switches from the 5V charging output to the 15V output; if the data verification fails, the 5V charging output is still maintained.

[0039] During the third charging state of the fast charging circuit 100, that is, the mobile phone unplugs the charging cable 100, the 3.3V power signal SB is no longer provided, and the charged capacitor C1 begins to discharge, so the inverter U1 still keeps working, and at this time, since the power signal SB disappears, the input of the inverter U1 switches from a high level to a low level, and the low level is inverted to output a high level, and the first NMOS tube Q1 is turned on; due to the conduction of the first NMOS tube Q1, the control node voltage of the second NMOS tube Q2 is directly grounded, so that the second NMOS tube Q2 is cut off. Therefore, the CC detection module 2 is equivalent to the load connected to the resistor R1, so VLOAD = 130K * 320uA = 4.2V. The adapter detects the rise of the load voltage VLOAD and resets the charging output from 15V to 5V.

[0040] As shown in the following table, the changes in key parameters corresponding to the above charging process are listed.

[0041]

[0042] In view of the fact that the existing fast charging circuit 100 requires the mobile phone end and the output interface end 4 to respectively retain pins for sending and receiving the power signal SB, which makes the circuit structure of the interface end complex and the sending of the communication signal SA and the power signal SB at the same time poses a severe challenge to the mobile phone with low battery, the present invention provides a fast charging circuit 1000, a rectifier module 50 for the fast charging circuit and a CC detection module 20 with rectification for the fast charging circuit.

[0043] Embodiment 1

[0044] The embodiment of the present invention provides a CC detection module 2000 with rectification for a fast charging circuit. Figure 3 As shown, it is a circuit structure diagram of the CC detection module 2000 with rectification for the fast charging circuit. The CC detection module with rectification includes a rectifier input terminal AID, a diode D2, a switch unit K, a detection signal input terminal S1, a diode D1, a resistor R1, a resistor R2, an NMOS tube Q1, an NMOS tube Q2, an inverter U1, a capacitor C1 and a load voltage output terminal Vload. The detection signal input terminal S1 is used to receive the detection signal CC sent from the adapter. The rectifier input terminal AID is used to connect to the output interface terminal to receive the communication signal SA from the mobile phone terminal. The positive electrode of the diode D2 is connected to the rectifier input terminal AID, and the negative electrode of the diode D2 is respectively connected to the positive electrode of the diode D1 and the input terminal of the inverter U1. One end of the switch unit K is connected to the negative electrode of the diode D2, and the other end is respectively connected to the negative electrode of the diode D1, one end of the capacitor C1 and the control end of the inverter U1. The switch unit K establishes or disconnects the connection between the negative electrode of the diode D2 and the capacitor C1 based on the communication signal SA. The other end of the capacitor C1 is grounded. The output end of the inverter U1 is connected to the gate of the NMOS tube Q1. The drain of the NMOS tube Q1 is connected to the detection signal input terminal S1 through the resistor R1, and the drain of the NMOS tube Q1 is also connected to the gate of the NMOS tube Q2, and the source of the NMOS tube Q1 is grounded. The drain of the NMOS tube Q2 is connected to the detection signal input terminal S1 through the resistor R2, and the source of the NMOS tube Q2 is grounded. The load voltage output terminal Vload is located between the detection signal input terminal S1 and the resistor R2, and is used to output the load voltage VLOAD.

[0045] Specifically, the switch unit K selects the connection state or disconnection state of the diode D2 and the capacitor C1 based on the control of the interruption signal DISCONNECT, and the interruption signal DISCONNECT is generated based on the change of the communication signal SA.

[0046] Optionally, the circuit structure of a switch unit K provided in this embodiment is as follows: Figure 4As shown, the switch unit K includes a first input node A1, a second input node A2, an SR latch and a PMOS tube P1. The first input node A1 is connected to the cathode of the diode D2. The first input terminal AID of the SR latch is connected to the first input node A1, the second input terminal AID of the SR latch is connected to the second input node A2, and the output terminal S4 of the SR latch is connected to the control terminal of the PMOS tube P1. The drain of the PMOS tube P1 is connected to the cathode of the diode D2, and the source of the PMOS tube P1 is connected to one end of the capacitor C1. The first input node A1 is used to receive the communication signal SA passing through the diode D2, and the second input node A2 is used to receive the interrupt signal DISCONNECT passing through the diode D2.

[0047] And optionally, the waveform of the interrupt signal DISCONNECT in the switch unit K provided in the embodiment is as follows: Figure 5 As shown. In the waveform diagram, the value 1 represents that the communication signal SA is at a high level at this time, that is, within a unit time t, when the actual duty cycle is greater than the set value, the signal will be in a "1" state within the unit time t. For example, when the set value is 60%, then within the unit time t, when the ratio of the high level time to the sum of the low level and high level time is greater than or equal to 60%, the signal will be in a "1" state within the unit time t. The interrupt signal DISCONNECT will be converted from the original low level to a high level after detecting that the communication signal SA is in a low level state for more than the threshold time △t. Exceeding the threshold time △t means that the communication signal SA has been disconnected (corresponding to the mobile phone being unplugged from the fast charging circuit). Optionally, the threshold time △t is 60us, which is set by the internal logic of the fast charging circuit.

[0048] The detailed process of the CC detection module 2000 with rectification for fast charging circuit to realize the switching of the charging output Vbus of the adapter is as follows:

[0049] When the mobile phone is not connected to the output interface of the fast charging circuit, the communication signal SA is not provided to the fast charging circuit and the CC detection module 20 with rectification. This state is exactly the same as the corresponding state described above. The CC detection module 2000 with rectification is equivalent to the load connected to the resistor R2, so VLOAD = 4.99 * 320uA = 1.6V. Since the mobile phone is not connected, the communication signal SA is not received, there is no data verification, and the adapter maintains a 5V charging output.

[0050] When the mobile phone is connected to the output interface of the fast charging circuit, it starts to provide a communication signal SA to the rectifier input terminal AID of the CC detection module 20 with rectification. Among them, a waveform diagram of a communication signal SA provided in the embodiment is as follows: Figure 6 shown.

[0051] At the beginning stage (t0-t1 time period) when the communication signal SA is connected to the rectifier input terminal AID, the communication signal SA sent by the mobile phone has passed the data verification, and the communication signal SA presents a continuous high level state (this feature is a special feature of the fast charging circuit communication signal. After passing the data verification, the communication signal presents a continuous high level of 80uS, which is slightly different for different fast charging circuits). Therefore, the SR latch output terminal S4 in the switch unit K outputs a low level, and the PMOS tube P1 is turned on, that is, the diode D2 and the capacitor C1 are turned on. The high-level communication signal SA causes the capacitor C1 to start charging, and at the same time, the high level causes

[0052] The inverter U1 works and the input terminal inputs a high level. The inverter U1 outputs a low level after inversion, so that the NMOS tube Q1 is still turned off; similarly to the previous stage, the NMOS tube Q2 is turned on. The CC detection module 2000 with rectification is still equivalent to the load connected to the resistor R2, VLOAD = 4.99K * 320uA = 1.6V. Since the communication signal SA has passed the data verification, the charging output of the adapter is 15V at this time.

[0053] In the second stage (t1-t2 time period), the state of the switch unit K is still in the on state, and the communication signal SA begins to appear in the low level state. During this low level period, the interrupt signal DISCONNECT is low level, so the SR latch in the switch unit K maintains the previous output state (output low level), so the PMOS tube P1 is still turned on, that is, the diode D2 and the capacitor C1 are turned on. Similarly, the CC detection module 2000 with rectification is still equivalent to the load connected to the resistor R2, VLOAD = 4.99K * 320uA = 1.6V. The adapter maintains a 15V charging output.

[0054] In the third stage (after t2), the fast charging circuit unplugs the mobile phone and no longer provides the communication signal SA to the rectifier input terminal AID. When it is detected that the communication signal SA is disconnected for more than 60us (as shown at time t4 in the figure), the interrupt signal DISCONNECT of the input switch unit K is converted to a high level. Therefore, at this time, the SR latch outputs a high level, and the PMOS tube P1 is cut off, that is, the circuit between the diode D2 and the capacitor C1 is broken, causing the input end of the inverter U1 to change from the original high level to a low level, and the low level is inverted and outputs a high level, causing the NMOS tube Q1 to turn on; due to the conduction of the NMOS tube Q1, the control node voltage of the NMOS tube Q2 is directly grounded, so that the NMOS tube Q2 is cut off. Therefore, the CC detection module 2000 with rectification is equivalent to the load connected to the resistor R1, so VLOAD = 130K * 320uA = 4.2V. The adapter detects the rise of the load voltage VLOAD and resets the charging output from 15V to 5V.

[0055] Among them, the above-mentioned data verification method is encryption verification, that is, the data is verified through symmetric encryption algorithms, asymmetric encryption algorithms and linear hash algorithms (i.e. signature algorithms). Symmetric encryption algorithms include AES (Advanced Encryption Standard), DES (Data Encryption Standard) and 3DES (Triple Advanced Encryption Standard); asymmetric encryption algorithms include RSA (an algorithm designed by three mathematicians Rivest, Shamir and Adleman), DSA (Digital Signature Algorithm) and ECC (Elliptic Cryptography Algorithm); linear hash algorithms (i.e. signature algorithms) include MD5 (Message-Digest Algorithm 5), SHA1 (Secure Hash Algorithm) and HMAC (Hash-based Message Authentication Code).

[0056] The above data verification method may also be handshake authentication, that is, verifying the data based on the challenge handshake authentication protocol.

[0057] Since the capacitor C1 needs to play the role of charging and discharging in the circuit to maintain the high level output of the signal, the capacitance value of the capacitor C1 cannot be too small and needs to be greater than 50pF. Optionally, the capacitance value of the capacitor C1 is 0.1uF.

[0058] Optionally, the CC detection module 2000 with rectification provided in the embodiment of the present invention is independent of other modules in the fast charging circuit and is packaged on an integrated circuit chip.

[0059] Optionally, the CC detection module 2000 with rectification provided in the embodiment of the present invention and other modules in the fast charging circuit are packaged on the same integrated circuit chip.

[0060] The CC detection module 2000 with rectification provided by this solution has the beneficial effect of reducing input pins and achieving stable and controllable switching of the charging output Vbus of the adapter, and further reducing costs because only one capacitor is provided in the circuit.

[0061] Embodiment 2

[0062] The embodiment of the present invention provides a fast charging circuit 1000 including a CC detection module 2000 with rectification. Figure 7 , which is a structural schematic diagram of the fast charging circuit 1000. Figure 1The difference of the fast charging circuit 100 shown is that the pin for receiving the power signal SB is no longer provided on the output interface terminal 4 of the fast charging circuit 1000. The fast charging circuit 1000 includes an input interface terminal 1, an output interface terminal 4, a CC detection module 2 with rectification, and a verification module 3. The input interface terminal 1 is used to connect to the adapter, and the input interface terminal 1 is also connected to the CC detection module 2 with rectification and the output interface terminal 4, respectively. The output interface terminal 4 is also used to connect to the mobile phone terminal, and the output interface terminal 4 is also connected to the verification module 3. The input interface terminal 1 is used to receive the detection signal CC and the charging voltage VBUS from the adapter, and provide the detection signal CC to the CC detection module 2 with rectification and provide the charging voltage VBUS to the output interface terminal 4. Specifically, when the adapter connected to the fast charging circuit 1000 is connected to the power supply, the detection signal CC and the charging voltage VBUS are output to the CC detection module 2 with rectification. The detection signal CC is a current source with a constant output of 3V / 320uA. When the output interface terminal 4 is connected to the mobile phone terminal, the charging voltage VBUS is provided to the mobile phone terminal, thereby forming a complete charging system. The output interface terminal 4 is used to receive the communication signal SA from the mobile phone terminal. The verification module 3 is used to perform data verification based on the communication signal SA. The detection signal CC is used to power the CC detection module 2 with rectification. When the communication signal SA passes the verification, the charging voltage VBUS increases. When the load voltage VLOAD of the CC detection module 2 with rectification increases, the charging voltage VBUS decreases.

[0063] The verification module 3 may be an encryption module, which performs encryption verification on data through symmetric encryption algorithms, asymmetric encryption algorithms and linear hash algorithms (i.e., signature algorithms). Symmetric encryption algorithms include AES (Advanced Encryption Standard), DES (Data Encryption Standard) and 3DES (Triple Advanced Encryption Standard); asymmetric encryption algorithms include RSA (an algorithm designed by three mathematicians Rivest, Shamir and Adleman), DSA (Digital Signature Algorithm) and ECC (Elliptic Cryptography Algorithm); linear hash algorithms (i.e., signature algorithms) include MD5 (Message-Digest Algorithm 5), SHA1 (Secure Hash Algorithm) and HMAC (Hash-based Message Authentication Code).

[0064] The verification module 3 may also be a handshake module, which verifies the data based on the challenge handshake authentication protocol.

[0065] like Figure 3 As shown, the CC detection module 2 with rectification includes a rectifier input terminal AID, a diode D2, a switch unit K, a detection signal input terminal S1, a diode D1, a resistor R1, a resistor R2, an NMOS tube Q1, an NMOS tube Q2, an inverter U1, a capacitor C1 and a load voltage output terminal Vload. The detection signal input terminal S1 is used to receive the detection signal CC sent from the adapter. The rectifier input terminal AID is used to connect to the output interface terminal to receive the communication signal SA from the mobile phone terminal. The positive electrode of the diode D2 is connected to the rectifier input terminal AID, and the negative electrode of the diode D2 is respectively connected to the positive electrode of the diode D1 and the input terminal of the inverter U1. One end of the switch unit K is connected to the negative electrode of the diode D2, and the other end is respectively connected to the negative electrode of the diode D1, one end of the capacitor C1 and the control end of the inverter U1. The switch unit K establishes or disconnects the connection between the negative electrode of the diode D2 and the capacitor C1 based on the communication signal SA. The other end of the capacitor C1 is grounded. The output end of the inverter U1 is connected to the gate of the NMOS tube Q1. The drain of the NMOS tube Q1 is connected to the detection signal input terminal S1 through the resistor R1, and the drain of the NMOS tube Q1 is also connected to the gate of the NMOS tube Q2, and the source of the NMOS tube Q1 is grounded. The drain of the NMOS tube Q2 is connected to the detection signal input terminal S1 through the resistor R2, and the source of the NMOS tube Q2 is grounded. The load voltage output terminal Vload is located between the detection signal input terminal S1 and the resistor R2, and is used to output the load voltage VLOAD.

[0066] Specifically, the switch unit K selects the connection state or disconnection state of the diode D2 and the capacitor C1 based on the control of the interruption signal DISCONNECT, and the interruption signal DISCONNECT is generated based on the change of the communication signal SA.

[0067] Optionally, the circuit structure of a switch unit K provided in this embodiment is as follows: Figure 4 As shown, the switch unit K includes a first input node A1, a second input node A2, an SR latch and a PMOS tube P1. The first input node A1 is connected to the cathode of the diode D2. The first input terminal AID of the SR latch is connected to the first input node A1, the second input terminal AID of the SR latch is connected to the second input node A2, and the output terminal S4 of the SR latch is connected to the control terminal of the PMOS tube P1. The drain of the PMOS tube P1 is connected to the cathode of the diode D2, and the source of the PMOS tube P1 is connected to one end of the capacitor C1. The first input node A1 is used to receive the communication signal SA passing through the diode D2, and the second input node A2 is used to receive the interrupt signal DISCONNECT passing through the diode D2.

[0068] And optionally, the waveform of the interrupt signal DISCONNECT in the switch unit K provided in the embodiment is as follows: Figure 5 As shown. In the waveform diagram, the value 1 represents that the communication signal SA is at a high level at this time, that is, within a unit time t, when the actual duty cycle is greater than the set value, the signal will be in a "1" state within the unit time t. For example, when the set value is 60%, then within the unit time t, when the ratio of the high level time to the sum of the low level and high level time is greater than or equal to 60%, the signal will be in a "1" state within the unit time t. The interrupt signal DISCONNECT will be converted from the original low level to a high level after detecting that the communication signal SA is in a low level state for more than the threshold time △t. Exceeding the threshold time △t means that the communication signal SA has been disconnected (corresponding to the mobile phone being unplugged from the fast charging circuit). Optionally, the threshold time △t is 60us, which is set by the internal logic of the fast charging circuit.

[0069] The detailed process of the fast charging circuit 1000 to implement the switching of the charging voltage VBUS is as follows:

[0070] When the mobile phone is not connected to the output interface of the fast charging circuit, the communication signal SA is not provided to the fast charging circuit and the CC detection module 20 with rectification. This state is exactly the same as the corresponding state described above. The CC detection module 2000 with rectification is equivalent to the load connected to the resistor R2, so VLOAD = 4.99 * 320uA = 1.6V. Since the mobile phone is not connected, the communication signal SA is not received, there is no data verification, and the adapter maintains a 5V charging output.

[0071] When the mobile phone is connected to the output interface of the fast charging circuit, it starts to provide a communication signal SA to the rectifier input terminal AID of the CC detection module 20 with rectification. Among them, a waveform diagram of a communication signal SA provided in the embodiment is as follows: Figure 6 shown.

[0072] At the beginning stage (t0-t1 time period) when the communication signal SA is connected to the rectifier input terminal AID, the communication signal SA sent by the mobile phone has passed the data verification, and the communication signal SA presents a continuous high level state (this feature is a special feature of the fast charging circuit communication signal. After passing the data verification, the communication signal presents a continuous high level of 80uS, which is slightly different for different fast charging circuits). Therefore, the SR latch output terminal S4 in the switch unit K outputs a low level, and the PMOS tube P1 is turned on, that is, the diode D2 and the capacitor C1 are turned on. The high-level communication signal SA causes the capacitor C1 to start charging. At the same time, the high level causes the inverter U1 to work and the input terminal inputs a high level. The inverter U1 outputs a low level after inversion, so that the NMOS tube Q1 is still cut off; similarly to the previous stage, the NMOS tube Q2 is turned on. The CC detection module 2000 with rectification is still equivalent to the load connected to the resistor R2, VLOAD = 4.99K*320uA = 1.6V. Since the communication signal SA has passed the data verification, the charging output of the adapter is 15V at this time.

[0073] In the second stage (t1-t2 time period), the state of the switch unit K is still in the on state, and the communication signal SA begins to appear in the low level state. During this low level period, the interrupt signal DISCONNECT is low level, so the SR latch in the switch unit K maintains the previous output state (output low level), so the PMOS tube P1 is still turned on, that is, the diode D2 and the capacitor C1 are turned on. Similarly, the CC detection module 2000 with rectification is still equivalent to the load connected to the resistor R2, VLOAD = 4.99K * 320uA = 1.6V. The adapter maintains a 15V charging output.

[0074] In the third stage (after t2), the fast charging circuit unplugs the mobile phone and no longer provides the communication signal SA to the rectifier input terminal AID. When it is detected that the communication signal SA is disconnected for more than 60us (as shown at time t4 in the figure), the interrupt signal DISCONNECT of the input switch unit K is converted to a high level. Therefore, at this time, the SR latch outputs a high level, and the PMOS tube P1 is cut off, that is, the circuit between the diode D2 and the capacitor C1 is broken, causing the input end of the inverter U1 to change from the original high level to a low level, and the low level is inverted and outputs a high level, causing the NMOS tube Q1 to turn on; due to the conduction of the NMOS tube Q1, the control node voltage of the NMOS tube Q2 is directly grounded, so that the NMOS tube Q2 is cut off. Therefore, the CC detection module 2000 with rectification is equivalent to the load connected to the resistor R1, so VLOAD = 130K * 320uA = 4.2V. The adapter detects the rise of the load voltage VLOAD and resets the charging output from 15V to 5V.

[0075] Since the capacitor C1 mentioned above needs to play the role of charging and discharging in the circuit to maintain the high level output of the signal, the capacitance value of the capacitor C1 cannot be too small and must be greater than 50pF. Optionally, the capacitance value of the capacitor C1 is 0.1uF.

[0076] Optionally, one of the packaging methods of the fast charging circuit 1000 provided in an embodiment of the present invention is that the rectifier module 5, CC detection module 2 and verification module 3 are integrated and packaged on one chip.

[0077] Optionally, another packaging method of the fast charging circuit 1000 provided in an embodiment of the present invention is that the CC detection module 2 is packaged on a first chip, the verification module 3 is packaged on a second chip, and the rectifier module 5 is packaged on a third chip, that is, the CC detection module 2 and the verification module 3 are two independently packaged chips, and the rectifier module 5 is independent of the two chips, and is designed as a circuit on a reference circuit board.

[0078] Optionally, another packaging method of the fast charging circuit 1000 provided in an embodiment of the present invention is that the CC detection module 2 and the rectifier module 5 are packaged on a first chip, and the verification module 3 is packaged on a second chip, that is, the CC detection module 2 and the rectifier module 5 are integrated and packaged on one chip, and the verification module 3 is independently packaged on another chip.

[0079] The beneficial effect of the fast charging circuit 1000 provided by the present solution, including the CC detection module 2000 with rectification, is that, on the basis of reducing the input pins and achieving stable and controllable switching of the charging output Vbus of the adapter, since only one capacitor is provided in the circuit, the cost is further reduced.

[0080] The above-mentioned diode D1 can also be the first diode D1, the diode D2 can also be the second diode D2, the resistor R1 can also be the first resistor R1, the resistor R2 can also be the second resistor R2, the NMOS tube Q1 can also be the first NMOS tube Q1, the NMOS tube Q2 can also be the second NMOS tube Q2, the capacitor C1 can also be the first capacitor C1, and the PMOS tube P1 can also be the first PMOS tube P1.

[0081] This embodiment also provides a fast charging cable, which includes the above-mentioned fast charging circuit 1000.

Claims

1. A CC detection module with rectification, characterized in that: The CC detection module with rectification includes a rectification input end, a diode D2, a switch unit, a detection signal input end, a diode D1, a resistor R1, a resistor R2, an NMOS tube Q1, an NMOS tube Q2, an inverter, a capacitor C1 and a load voltage output end; the detection signal input end is used to receive a detection signal sent by an adapter; the rectification input end is used to receive a communication signal sent by a mobile phone; the positive electrode of the diode D2 is connected to the rectification input end, and the negative electrode of the diode D2 is respectively connected to the positive electrode of the diode D1 and the input end of the inverter; one end of the switch unit is connected to the negative electrode of the diode D2, and the other end is respectively connected to the negative electrode of the diode D1, one end of the capacitor C1 and the control end of the inverter, and the switch unit The element establishes or disconnects the connection between the cathode of the diode D2 and the capacitor C1 based on the communication signal; the other end of the capacitor C1 is grounded; the output end of the inverter is connected to the gate of the NMOS tube Q1; the drain of the NMOS tube Q1 is connected to the detection signal input end through the resistor R1, the drain of the NMOS tube Q1 is also connected to the gate of the NMOS tube Q2, and the source of the NMOS tube Q1 is grounded; the drain of the NMOS tube Q2 is connected to the detection signal input end through the resistor R2, and the source of the NMOS tube Q2 is grounded; the load voltage output end is located between the detection signal input end and the resistor R2, and is used to output the load voltage; the capacitance value of the capacitor C1 is greater than 50pF; The switch unit includes a first input node, a second input node, an SR latch and a PMOS tube P1; the first input node is connected to the cathode of the diode D2; the first input end of the SR latch is connected to the first input node, the second input end of the SR latch is connected to the second input node, the output end of the SR latch is connected to the control end of the PMOS tube P1, the drain of the PMOS tube P1 is connected to the cathode of the diode D2, and the source of the PMOS tube P1 is connected to one end of the capacitor C1; When the communication signal verification passes, the charging voltage of the fast charging circuit increases, and when the load voltage of the CC detection module increases, the charging voltage of the fast charging circuit decreases.

2. The CC detection module with rectification according to claim 1, characterized in that: The communication signal verification method is to perform data verification through an encryption algorithm or a challenge handshake authentication protocol.

3. The CC detection module with rectification according to claim 2, characterized in that: The capacitance value of the capacitor C1 is 0.1uF.

4. A fast charging circuit comprising the CC detection module with rectification as claimed in claim 1, characterized in that: It includes an input interface terminal, an output interface terminal and a verification module; The input interface end is used to connect with the adapter to receive the detection signal and the charging voltage from the adapter, and provide the detection signal and the charging voltage to the CC detection module with rectification and the output interface end respectively, wherein the detection signal is used to power the CC detection module with rectification; The output interface end is used to connect to the mobile phone end to receive the communication signal from the mobile phone end and provide the charging voltage to the mobile phone end; The verification module is used to perform data verification according to the communication signal; When the communication signal verification passes, the charging voltage increases, and when the load voltage of the CC detection module increases, the charging voltage decreases.

5. The fast charging circuit according to claim 4, characterized in that: The verification module is an encryption module, which is used to perform encryption verification on data through an encryption algorithm.

6. The fast charging circuit according to claim 4, characterized in that: The verification module is a handshake module, which verifies data based on the challenge handshake authentication protocol.

7. The fast charging circuit according to claim 4, characterized in that: The CC detection module with rectification and the verification module are packaged on one chip.

8. The fast charging circuit according to claim 4, characterized in that: The CC detection module with rectification is packaged on a first chip, and the verification module is packaged on a second chip.

9. A fast charging cable, characterized in that: Comprising the fast charging circuit as claimed in claim 4.

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