Spare replacement in memory systems

Abstract

The present application is directed to spare replacement in a memory system. As part of a background operation, a controller may assign spare bits to replace bits of a codeword and save an indication of the spare bit assignment in a memory array. The codeword may include a set of bits that each correspond to a respective minimum substitution region MSR within a memory medium holding the codeword. The MSR corresponding to the bit to be replaced may include a number of erroneous bits relative to a threshold. During a read operation, the controller may identify the spare bit in a first portion of the codeword, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit simultaneously with receiving a second portion of the codeword.

Description

[0001] Cross-references

[0002] This patent application claims priority to PCT Application No. PCT / US2019 / 043050, filed by Pawlowski on July 23, 2019, entitled “SPARE SUBSTITUTION IN MEMORY SYSTEM,” which claims priority to U.S. Patent Application No. 16 / 516,916, filed by Pawlowski on July 19, 2019, entitled “SPARE SUBSTITUTION IN MEMORY SYSTEM,” and U.S. Provisional Patent Application No. 62 / 702,808, filed by Pawlowski on July 24, 2018, entitled “SPARE SUBSTITUTION IN MEMORY SYSTEM,” each of which is assigned to the present assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to spare replacement in memory systems. Background Art

[0004] The following relates generally to operating a memory subsystem or memory system, and more specifically, to spare replacement in a memory system.

[0005] A computing system may include a memory subsystem or memory system that includes various memory devices and controllers coupled to one or more buses to manage information in numerous electronic devices, such as computers, wireless communication devices, the Internet of Things, cameras, digital displays, etc. Memory devices are widely used to store information in such electronic devices. Information is stored by programming different states of the memory device. For example, a binary device has two logical states that are usually labeled as logical "1" or logical "0". In other systems, more than two states can be stored in the memory device. In order to access the stored information, the components of the electronic device can read or sense the stored states in the memory device. In order to store information, the components of the electronic device can write or program the states in the memory device.

[0006] There are different types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, non-AND (NAND) memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory cells can maintain their logic state for a long period of time even in the absence of external power. Volatile memory devices such as DRAM can lose their stored state when disconnected from the external power supply.

[0007] Improving computing systems may include enhancing the performance of memory systems, such as reducing power consumption, increasing memory capacity and reliability, improving read / write speeds, providing non-volatility through the use of permanent memory media, or reducing manufacturing costs at a certain performance point, among other metrics. Summary of the invention

[0008] A method is described. In some examples, the method may include: receiving a first portion of a codeword from a memory medium, the codeword including a set of bit fields indicating a plurality of data bursts across a plurality of channels; based at least in part on receiving the first portion of the codeword, identifying a spare bit in the first portion of the codeword to replace the set of bit fields; based at least in part on identifying the spare bit, determining the set of bit fields to be replaced by the spare bit; based at least in part on determining the set of bit fields to be replaced by the spare bit, receiving a second portion of the codeword; and replacing the set of bit fields in the second portion of the codeword with the spare bit concurrently with receiving the second portion of the codeword.

[0009] A method is described. In some examples, the method may include: reading a codeword from a memory medium including a set of minimum substitution regions (MSRs), the codeword including a plurality of bits that each correspond to a respective MSR of the set; identifying a number of erroneous bits in the codeword using an error control operation based at least in part on a size of one or more MSRs of the set; setting a value of a counter associated with the MSRs of the set based at least in part on identifying the number of erroneous bits in the codeword, the MSRs of the set corresponding to the number of erroneous bits; determining the value of the counter relative to a threshold based at least in part on the value of the counter; and assigning spare bits of the codeword to the number of erroneous bits based at least in part on the value of the counter relative to the threshold.

[0010] A method is described. In some examples, the method may include: reading a codeword from a memory medium including a plurality of minimum substitution regions (MSRs), the codeword including a set of bit fields indicating a plurality of channels associated with the memory medium, wherein each bit field of the set corresponds to a respective one of the plurality of MSRs associated with a counter; based at least in part on reading the codeword, identifying a first number of counters associated with channels of the plurality of channels, the first number of counters each having a value equal to or greater than a first threshold; based at least in part on identifying the first number of counters, determining that the first number is equal to or greater than a second threshold; and assigning a spare channel of the codeword to the channel of the plurality of channels based at least in part on determining that the first number is equal to or greater than the second threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a computing system that supports spare replacement in a memory system according to aspects disclosed herein is described.

[0012] Figure 2 An example of a computing system that supports spare replacement in a memory system according to aspects disclosed herein is described.

[0013] Figure 3

[0013] An example of a codeword format that supports alternate substitution in a memory system according to aspects disclosed herein is described.

[0014] Figure 4 Examples of configurations of memory dies and configurations of memory media to support spare replacement in a memory system according to aspects disclosed herein are described.

[0015] Figure 5 A block diagram is shown of an apparatus supporting spare replacement in a memory system according to aspects disclosed herein.

[0016] Figures 6 to 8 One or more methods of supporting spare replacement in a memory system according to aspects disclosed herein are described. DETAILED DESCRIPTION

[0017] The performance of a computing system, such as a server including a memory system or subsystem, may depend on various factors, such as supplying reliable information to the computing system with low latency, such as load-to-use latency. In the context of a computing system or subsystem, data that carries information may be referred to as a codeword. In some cases, a codeword may include a certain amount of user data and other bits that carry various information, such as bits that support error control operations, to provide reliable user data with low latency. A codeword may be associated with an element of a computing system, such as a memory medium of a memory system or subsystem, and the codeword may be transmitted and received during one or more access operations or background operations, or both. Background operations in a computing system may refer to processing programs that run without user intervention, such as access commands from a host device.

[0018] In some cases, memory cells of one or more memory dies in a memory medium may support a limited number of access operations (e.g., read cycles or write cycles or both) before becoming unreliable or having problems. When a memory cell is unreliable, the information generated by the memory cell may become erroneous or invalid, and such memory cells (or the information generated by the memory cells) may be referred to as error bits. When a certain number of memory cells associated with a codeword generate error bits, the codeword (e.g., user data in the codeword) may become erroneous or invalid beyond the error recovery capabilities of the memory system or subsystem. Therefore, replacing the error bits in the codeword with spare bits can improve the reliability of the system by providing reliable data to the host. In addition, the concepts disclosed herein can support spare replacement without introducing a large amount of delay and can facilitate low-latency operation of computing systems.

[0019] The memory array of the memory die may be configured to include a set of minimum replacement regions (MSRs). The MSRs may be configured as reasonable fault containment regions to effectively manage (e.g., replace, substitute) error bits in the memory array. In some cases, the MSRs may include groups of memory cells configured as data cells associated with error control operations. In addition, at least some (if not all) of the set may be associated with a counter configured to count the number of error bits in each MSR in the set. A group of MSRs of a channel set across a memory medium (e.g., a group of MSRs operating in parallel) may maintain a certain number of codewords. In some cases, a group of MSRs configured to generate the number of codewords may be referred to as an MSR stripe or MSR zone.

[0020] In some cases, as part of a background operation, a controller (e.g., a port manager associated with a memory medium) may read a codeword from a memory medium that includes a set of MSRs. The codeword may include a plurality of bits that each correspond to a respective MSR in the set. The controller may use an error control operation to identify the number of error bits in the codeword and set a value of a counter associated with the MSR in the set that corresponds to the number of error bits. In addition, the controller may determine a value of a counter relative to a threshold, wherein the counter is associated with an MSR that includes at least one error bit in the number, and the controller may assign a spare bit of the codeword to replace the error bit (e.g., the MSR corresponding to the error bit). The controller may write an indication of the spare bit assignment for the error bit, which may include saving the indication in a separate memory array (e.g., a static random access memory (SRAM) cell) that may be configured to save such an indication. In some cases, the controller may transmit information (e.g., one or more indications of the spare bit assignment) to a non-volatile memory prior to a power change or loss event.

[0021] During a read operation, the controller may identify spare bits in the first portion of the codeword to determine the erroneous bits to be replaced based on accessing a memory array (e.g., an SRAM cell) containing a spare bit assignment indication. In some cases, the controller may replace the erroneous bits with spare bits simultaneously with receiving the second portion of the codeword. The codeword may have been configured according to a codeword format that supports low-latency operation to generate reliable user data sent to the host with spare bits ready. For example, the first portion of the codeword may correspond to a first data burst (e.g., an initial data burst) containing one or more spare bits, and the second portion of the codeword may correspond to one or more additional data bursts after the initial data burst in time. In this way, spare bits (e.g., spare bits that replace erroneous bits during a read operation) can be multiplexed into the bit stream of the codeword in a series of data bursts, which adds little or substantially no additional latency (except for the latency of the multiplexing component).

[0022] Below is Figure 1 The features of the present disclosure introduced herein are further described at an exemplary system level in the context of Figures 2 to 4 Specific examples of configurations of the system and the storage media of the system are described in the context of. These and other features of the present disclosure are further illustrated by and described with reference to the following: Figure 5 Device diagram and operations involving spare replacement in a memory system Figures 6 to 8 Flowchart of the process.

[0023] Figure 1An example of a computing system 100 supporting standby replacement in a memory system according to aspects disclosed herein is described. The computing system 100 may include a host device 105 coupled to a device 140 via a host interface 115 (also referred to as a host link). The host device 105 may be or include a server, a system-on-chip (SoC), a central processing unit (CPU), or a graphics processing unit (GPU), among other examples. In some examples, the host device 105 may access (e.g., read from, write to) one or more memory media 130 located in the device 140 via the host interface 115.

[0024] The host interface 115 (e.g., a host link) may be compatible with or employ a protocol (e.g., Gen-Z, a Cache Coherent Interconnect for Accelerators (CCIX) protocol) to facilitate access operations between the host device 105 and the one or more storage media 130. The host interface 115 may be configured to transfer data at a first data transfer rate (e.g., 25 gigabytes per second (GBps)) in at least one direction (e.g., a transmit direction or a receive direction). In some examples, when the transaction size is 64 bytes, the 25 GBps data transfer rate may support approximately 586 million transactions per second. In other examples, when the transaction size is 128 bytes, the 25 GBps data transfer rate may support approximately 312.5 million transactions per second.

[0025] In some cases, device 140 may be referred to as a memory system or subsystem or a memory device. In some cases, device 140 may include a power management component. The power management component may monitor power levels, which may indicate a change or loss of power associated with device 140 or computing system 100. In some cases, power levels may fluctuate beyond a normal range to indicate such a power change or loss event. Device 140 may include a controller 120 that may be coupled to one or more storage media 130 via a channel 125. In some cases, channel 125 may be referred to as an aggregate channel 125, which includes as described in reference Figure 2 125). Device 140 may include a non-volatile memory 131 coupled to controller 120 via channel 126. In some examples, controller 120, one or more memory media 130, or non-volatile memory 131, or any combination thereof, may be integrated with, in contact with, or placed on a board (e.g., a peripheral component interconnect express (PCIe) board). In some cases, non-volatile memory 131 may be integrated as part of controller 120.

[0026] Controller 120 may include various functional blocks that facilitate the operation of device 140 and one or more storage media 130. In some cases, power management components may be integrated as part of controller 120. In some cases, controller 120 may include aspects of an interface controller to accommodate different specifications, constraints, or characteristics associated with host interface 115, channel 125, channel 126, or any combination thereof. In some examples, controller 120 may be an ASIC, a general purpose processor, other programmable logic device, a discrete hardware component (e.g., a chiplet), or may be a combination of components.

[0027] In some cases, controller 120 may read data from or write data to storage medium 130 (e.g., storage medium 130-a) in conjunction with a local controller (e.g., a controller local to storage medium 130-a) that may perform various operations (e.g., write data to a memory cell, read data from a memory cell, perform operations based on a reference Figure 3 In some examples, the local controller may send the requested data to controller 120 via one of channels 125, which may be an example of an aggregated channel.

[0028] Each memory medium (e.g., memory medium 130-a) may include multiple memory dies (e.g., forty-four (44) memory dies) to obtain a specified or desired memory capacity of the memory medium. In some examples, the memory dies may include a three-dimensional cross-point array of memory cells, which may include structures or components formed of chalcogenides (e.g., including 3D XPoint TM In some examples, a codeword (e.g., a codeword including 128 bytes of user data) may be partitioned across multiple memory dies within a memory medium (e.g., memory medium 130-a).

[0029] In some cases, each memory die of a plurality of memory dies (e.g., each 3DXP memory die) may generate a certain amount of data (e.g., 128 bits of data) as a unit from the memory die associated with an access operation (e.g., a read operation). The amount of data (e.g., 128 bits of data) may include a sequence of bursts (e.g., sixteen (16) bursts), each burst including a certain amount of data (e.g., eight (8) bits of data) transmitted from the memory die via a bus (e.g., an 8-bit wide bus). As an example, when the memory medium includes eleven (11) memory dies operating in parallel, and when each memory die of the eleven (11) memory dies generates eight (8) bits of data at a given burst, the memory medium may generate 88 bits of data for a given burst. Since eleven (11) memory dies can generate data over a total of sixteen (16) bursts, each burst including 88 bits of data from the eleven (11) memory dies, a data unit associated with the memory medium during an access operation (e.g., a data unit transmitted via a channel (e.g., an aggregate channel)) can include 1,408 bits.

[0030] Thus, in this example, a codeword (e.g., a unit of data during a transaction of an access operation) associated with the memory medium may include 1,408 bits. In some cases, a burst may be referred to as a channel burst or a data burst. In some cases, a channel between controller 120 and a memory medium (e.g., memory medium 130-a) may include a plurality of channels, each of which may be associated with a reference Figure 3 and 4 The described memory media (eg, memory media 130 - a ) are associated with one or more memory dies.

[0031] The memory medium (eg, memory medium 130-a) may include a set of memory dies each including a memory array. Each memory die in the set (eg, each memory array) may be configured to include the memory arrays described in reference to FIG. Figure 4 The described MSR sets. The MSRs can be configured as reasonable fault containment areas to effectively manage (e.g., replace, substitute) error bits in the memory array. In addition, at least some (if not all) of the set can be associated with a counter configured to count the number of error bits in each MSR in the set.

[0032] Channels 125 may be configured to transmit data (e.g., codewords) between controller 120 and one or more storage media 130. Each of channels 125 (e.g., channel 125-a, which may be an example of an aggregate channel) may include multiple other channels (e.g., channels with smaller bandwidth than channel 125-a) for transmitting data (e.g., codewords) in parallel. In some cases, a codeword may include user data (e.g., 128 bytes of user data in a codeword) and other data sets (e.g., the remaining data in the codeword used to generate reliable data with low latency). Each of channels 125 (e.g., channel 125-a, which may be an example of an aggregate channel) may include other channels to carry information related to various auxiliary functions (e.g., metadata). In some cases, a codeword format (which may also be referred to as a codeword layout) or a forwarded codeword layout (e.g., a forwarded codeword layout) may define how each of channels 125 (e.g., channel 125-a) may transmit data (e.g., codewords) between controller 120 and one or more storage media 130.

[0033] The non-volatile memory 131 may include an array of non-volatile memory cells that can maintain their logic state for a long period of time even without external power. For example, the non-volatile memory cells may be or include 3D XPoint TM Memory cells, PCM cells, FeRAM cells, or flash (e.g., NAND flash, NOR flash) memory cells, among other examples. In addition, non-volatile memory 131 can be configured to exchange information with controller 120 via channel 126. For example, non-volatile memory 131 can receive information from controller 120 via channel 126 and save the information when a change or loss of power associated with computing system 100 is detected.

[0034] In some cases, a memory subsystem or system that may include device 140 may include a power management component for managing power change or disappearance events. The power management component may be operable to detect a power change or disappearance symbol (e.g., a power level indicating that a power change or disappearance may occur) and transmit an indication of the power change or disappearance symbol to controller 120. Controller 120 may transfer information (e.g., an indication of an error state associated with a codeword, one or more indications of spare bit assignments for error bits) stored in a memory array (e.g., an SRAM memory array) in controller 120 upon receiving the indication to non-volatile memory 131. Non-volatile memory 131 may save the information so that the information may be retained in the absence of power to the memory subsystem or memory system that may include device 140. When power to computing system 100 is restored or otherwise adjusted, controller 120 may retrieve the information from non-volatile memory 131 to resume operations that have been interrupted by a power change or disappearance event based on the information retained in non-volatile memory 131.

[0035] In some cases, as part of one or more background operations, the controller 120 may read a codeword from a memory medium (e.g., the memory medium 130) that includes a set of MSRs. The codeword may include a plurality of bits that may each correspond to a respective MSR in the set. The controller 120 may use an error control operation to identify a number of erroneous bits in the codeword, and set (e.g., initially set, update) a value of a counter associated with the MSRs in the set (e.g., the MSRs in the set that include the number of erroneous bits) based on identifying the number of erroneous bits in the codeword. In addition, the controller 120 may determine a value of the counter relative to a threshold, and assign spare bits of the codeword to the number of erroneous bits based on the value of the counter relative to the threshold. In some cases, the threshold may be referred to as a bit-level replacement threshold.

[0036] In some cases, the controller 120 may write an indication of the spare bit assignment for the number of erroneous bits to a memory array of the controller 120 based on assigning the spare bits of the codeword. The memory array may be configured to store a plurality of such indications associated with the spare bits and may include SRAM cells. In some cases, the controller 120 may configure (e.g., program, adjust) a threshold value associated with an error rate (e.g., a raw bit error rate (RBER)) associated with the memory medium based on identifying the number of erroneous bits in the codeword. In other cases, the controller 120 may configure a threshold value for the size of the MSR in the set based on identifying the number of erroneous bits in the codeword.

[0037] Figure 2An example of a computing system 200 that supports spare replacement in a memory system according to aspects disclosed herein is illustrated. The computing system 200 may be a reference Figure 1 1. The computing system 200 may include a host device 205 coupled to a memory subsystem or system 220 using at least one host interface (e.g., host interface 215-a). In some cases, host interface 215 may be referred to as one or more host links. Host device 205 may be a reference Figure 1 The host interface 215 may be a reference to an example of a host device 105 described herein. Figure 1 An example of a host interface 115 is described. In some examples, the host interface 215 can be configured to transfer data at a first data transfer rate (eg, 50 GBps, 25 GBps in each direction).

[0038] The computing system 200 may include a memory subsystem or system 220. The memory subsystem or system 220 may be a reference Figure 1 200. The memory subsystem or system 220 may be referred to as a memory device. The memory subsystem or system 220 may include a controller 230. In some cases, the memory subsystem or system 220 may include a power management component. The power management component may monitor power levels that may indicate a change or loss of power associated with the memory subsystem or system 220 or the computing system 200. In some cases, the power levels may fluctuate beyond a normal range to indicate such a power change or loss event. The controller 230 may be a reference Figure 1 An example of controller 120 is depicted. Controller 230 can include interface component 210 and multiple port managers 260. In some cases, power management components can be integrated as part of controller 230.

[0039] The interface component 210 can be configured to facilitate data exchange between the host device 205 and the memory subsystem or system 220 through the host interface 215. The interface component 210 can be configured to exchange data with multiple port managers 260 (e.g., using signal paths 250). Each of the signal paths 250 can be configured to exchange data at a rate (e.g., 12.8 GBps) that is different from the first data transfer rate of the host interface 215. In some cases, the interface component 210 can be configured to provide a routing network function to allow more than one host interface (e.g., host interface 215-a and host interface 215-b) to be associated with multiple port managers 260.

[0040] The memory subsystem or system 220 may include non-volatile memory 296. The non-volatile memory 296 may be configured to communicate information with the controller 230 via the channel 292. The non-volatile memory 296 may be a reference Figure 1 The example of non-volatile memory 131 described in the embodiment of FIG. 29 is a channel 292. Figure 1 Examples of channel 126 described herein or including aspects of channel 126. In addition, non-volatile memory 296 may be configured to communicate information with port manager 260 in controller 230. For example, when port manager 260 receives an indication of a change or loss of power associated with computing system 200 or memory subsystem or system 220, port manager 260 may transmit various information (e.g., one or more indications of spare bit assignments for error bits) to non-volatile memory 296 via channel 292 and save the information in non-volatile memory 296. In some cases, non-volatile memory 296 may be integrated as part of controller 230.

[0041] Each port manager in the plurality of port managers 260 (e.g., port manager 260-b) may be coupled to a storage medium (e.g., storage medium 295-b) via an aggregate channel (e.g., aggregate channel 290-b). In some cases, each port manager in the plurality of port managers may be coupled to a different one or more storage media 295. In some examples, individual port managers in the plurality of port managers 260 (e.g., port manager 260-a) may operate independently of one another (e.g., independently of port managers 260-b, 260-c, and 260-c) and may support access operations or background operations associated with the one or more storage media 295. The one or more storage media 295 may be referenced to a plurality of storage media 295. Figure 1 An example of one or more storage media 130 is described. In some cases, each of the one or more storage media 295 can be referred to as a media port.

[0042] Each aggregate channel in aggregate channels 290 may include one or more channels 291. In some cases, channels 291 may be referred to as logical channels 291. In some examples, each channel 291 may be associated with one or more memory dies in a memory medium (e.g., memory medium 295-a) and may have a smaller bandwidth than the bandwidth of an aggregate channel (e.g., aggregate channel 290-b). In some examples, an aggregate channel (e.g., aggregate channel 290-a) may include eleven (11) channels 291 (e.g., channels 291-a through 291-k). For clarity, multiple channels 291 (e.g., channel 291-a through channel 291-k) are depicted for port manager 260-a, representing one of the aggregated channels 290 (e.g., aggregated channel 290-a), while other aggregated channels 290 (e.g., aggregated channels 290-b, 290-c, and 290-d) are depicted for port managers 260-b, 260-c, and 260-d, and the multiple channels 291 associated with each aggregated channel are not shown.

[0043] An individual memory medium (e.g., memory medium 295-a) of the one or more memory media 295 may include one or more memory devices (e.g., 3DXP memory dies). In some cases, the memory devices in the individual memory media may be configured to operate in parallel to obtain a desired (or specified) aggregate bandwidth via one of the aggregate channels 290. As an example, a 3DXP memory die may be configured to have an 8-bit wide data bus and may be associated with each of the channels 291 (e.g., channel 291-a) such that each channel 291 is 8 bits wide. Additionally, the 3DXP memory die may be configured to generate 128 bits of data during a sequence of sixteen (16) bursts, where each burst may generate 8 bits of wide data via channel 291. Thus, the 128 bits of data may be considered a single unit of data generated by each 3DXP memory die based on an access command (or during background operation) to read a memory cell within the 3DXP memory die.

[0044] In some cases, a codeword (or forwarded codeword) may be configured to include a set of bit fields indicating a plurality of data bursts (e.g., a sequence of sixteen (16) bursts) associated with a plurality of channels (e.g., eleven (11) channels 291-a through 291-k producing 88 bits of data per data burst). Thus, in some cases, a codeword may include 1,408 bits of information. The description herein may be understood in terms of a logical view of a memory medium. A greater number of physical 3DXP memory dies may be present in the memory medium than the number of logical 3DXP memory dies to account for overhead associated with various access operations (e.g., read operations, write operations) or background operations associated with the memory medium. Within the memory medium, a codeword may be divided into portions and written to or read from more than one die (e.g., 128 bytes of user data maintained across ten (10) 3DXP memory dies), as described with reference to FIG. Figure 3 described.

[0045] Various examples described herein use 3DXP memory dies (e.g., including 3D XPoint TM Memory units) are used to illustrate the manner in which the memory medium 295 may be configured and operated in conjunction with the port manager 260 according to the methods, apparatus, and systems disclosed herein for supporting spare replacement in a memory system. In some cases, the memory medium 295 may include other types of memory devices that employ memory technologies other than 3DXPoint memory technology, such as FeRAM technology, PCM technology, MRAM technology, and other technologies. Thus, the concepts disclosed herein are not limited to a particular memory technology (e.g., 3DXPoint TM memory technology).

[0046] The memory medium (eg, memory medium 295-a) may include a set of memory dies each including a memory array. Each memory die in the set (eg, each memory array) may be configured to include the memory arrays described in reference to FIG. Figure 4The described MSR set. The MSRs may be configured as reasonable fault containment zones to effectively manage (e.g., replace, substitute) error bits in the memory array. In some cases, each bit in the codeword (e.g., each bit in the 1,408 bits in the codeword) may be associated with a corresponding MSR in a set (e.g., 1,408 MSRs). A set of MSRs across a channel set of a memory medium (e.g., channels 291-a to 291-k of the memory medium 295-a) may be configured to operate in parallel to maintain or generate a certain number of codewords. In some cases, a group of MSRs configured to generate the number of codewords may be referred to as an MSR stripe or MSR zone. In addition, at least some (if not all) of the set may be associated with a counter configured to count the number of error bits in each MSR in the set.

[0047] In some cases, as part of a read operation, a port manager (e.g., port manager 260-a) receives a first portion of a codeword from a memory medium (e.g., memory medium 295-a). The codeword may include a set of bit fields indicating a plurality of data bursts across a plurality of channels (e.g., channels 291-a to 291-k). The port manager may identify a spare bit in the first portion of the codeword to replace the set of bit fields. The port manager may determine, based on identifying the spare bit, the set of bit fields to be replaced by the spare bit. The port manager may also receive a second portion of the codeword (e.g., one or more other data bursts), the second portion including a set of bit fields to be replaced by the spare bit. In some cases, the port manager may replace the set of bit fields in the second portion of the codeword with the spare bit (e.g., simultaneously with receiving the second portion of the codeword). Thus, the spare bit may be multiplexed into the bit stream of the codeword in a series of data bursts, which adds little or substantially no additional latency (other than the latency of the multiplexing component).

[0048] In some cases, the port manager may access a memory array of the port manager to determine a bit field of a set in the second portion of the codeword that is to be replaced by a spare bit. The memory array may be configured to maintain an indication of a spare bit assignment for the bit field of the set of codewords and may include an SRAM cell. In some cases, the port manager may perform an error control operation for the codeword based on replacing the bit field of the set in the second portion with a spare bit. In some cases, the size of a memory array (e.g., an SRAM cell) for maintaining an indication of a spare bit assignment may be based on an identification of a channel in a plurality of channels, a number of spare bits in a codeword, an identification of one or more MSRs of a number of MSRs associated with a codeword, a number of bits associated with a forwarded codeword in a memory medium, an error correction capability for an indication of a spare bit assignment, a number of memory dies corresponding to a channel in a plurality of channels, a number of MSRs in the number of memory dies, or a bit indicating a change in a spare bit assignment, or any combination thereof, as well as other examples.

[0049] Figure 3 An example of a codeword format 300 (also referred to as a codeword layout 300) supporting alternate substitution in a memory system according to aspects disclosed herein is illustrated. The codeword format 300 may be an example of a codeword format for an entire codeword. A codeword may include information indicating a plurality of channels (e.g., reference Figure 2 A set of bit fields for multiple data bursts for the described channels 291-a to 291-k). Figure 3 Also included are formats 301 to 305 (also referred to as layouts) that describe the layout for individual channels (e.g., reference Figure 2 Various configurations of channel 291-a) are described. Figure 3 Also illustrated is a format 306, which may correspond to a portion of a codeword (eg, a subset of a bit field during one or more first data bursts across multiple channels).

[0050] As an example of a codeword format and structure, the codeword format 300 may include a codeword that may be accessed by a memory medium (e.g., reference codeword 300 ) in response to an access command or during background operation, or both. Figure 1 and 2 1,408 data bits). The codeword may include 128 bytes (e.g., 1,024 bits) of user data. The remaining bit fields (e.g., 384 bits of data) within the codeword may carry various information that may be helpful in conveying accurate user data during access operations or during background operations, or both. In addition, the remaining bits carrying the various information may be configured to facilitate low latency operations (e.g., standby substitution) associated with the codeword during access operations.

[0051] Codeword format 300 may span multiple channels (eg, channels 310-a through 310-k). One of the channels (eg, channels 310-a through 310-k) may be a reference Figure 2 An example of a channel 291 (e.g., channel 291-a) is described or includes aspects thereof. In some cases, each channel in the plurality of channels 310 (e.g., channel 310-a) may be associated with one or more 3DXP dies, which may include an 8-bit wide data bus. For example, each channel may generate a total of 128 bits of data as a single object of a transaction (e.g., communication, operation) associated with an access command (e.g., read command) or a background operation, or both. In addition, the 128 bits of data may be generated as a sequence of sixteen (16) data bursts, each data burst being configured to generate eight (8) bits of data on an 8-bit wide data bus. Thus, each of each channel within the codeword format (e.g., channels 310-a to 310-k) may correspond to 128 bits of data comprising sixteen (16) groups of 8-bit data, such as G7…G0 for channel 310-g, where G7…G0 may represent a series of eight (8) zeros and ones, where G7 may be the most significant bit (e.g., the eighth bit of the series of eight (8) zeros and ones) and G0 may be the least significant bit (e.g., the first bit of the series of eight (8) zeros and ones)), where each of the sixteen (16) groups of 8-bit data may be associated with one of the sixteen (16) data bursts.

[0052] In one example, the codeword format 300 may span eleven (11) channels and each of the eleven (11) channels may generate 8 bits of data at each data burst, and a total of 88 bits of data may be generated across the eleven (11) channels at each data burst (e.g., a first data burst 320-1 of 88 bits of data). Thus, the codeword format 300 may include 1,408 bits of data (e.g., a first data burst 320-1 through a 16th data burst 320-16, each data burst generating 88 bits of data) as a single object for a transaction of a memory medium (e.g., memory medium 130-a or memory medium 295-a). The codeword format 300 may support reliable transactions (e.g., conveying accurate user data content) with low latency (e.g., a low number of clock edges to generate user data).

[0053] Each field (e.g., each bit field) or set of fields (e.g., a set of bit fields) within a codeword may contain information that facilitates reliable transactions of user data with low latency. In some cases, one or more fields (e.g., bit fields) within the codeword format may be configured to indicate a codeword condition (e.g., using one or more CwCon bits). A codeword may be configured in one of a plurality of possible states (e.g., four states) indicated using CwCon bits. In some cases, one or more fields within the codeword format may be configured to indicate the number of access operations (e.g., read operations, write operations) associated with a codeword (e.g., WrCnt bits). In some cases, one or more fields within the codeword format may be configured to indicate that a portion of a codeword may be invalid (e.g., using a poison bit).

[0054] In some cases, one or more fields within the codeword format may be configured as cyclic redundancy check (CRC) bits that can identify error bits associated with error control operations. In some cases, one or more fields within the codeword format may be configured as codeword error control code bits (e.g., CwECC bits) that support error control operations. In some cases, one or more fields within the codeword format may be configured as XOR bits. Each of the XOR bits may include a digital or Boolean logical exclusive OR (XOR) product of corresponding bits of other channels of the corresponding data burst. Thus, the XOR bits may support repairing corresponding bits of other channels and may be referred to as repair bits. In some cases, each XOR bit (e.g., XOR / sub bit or XORSub bit) may take a field within the codeword instead of repairing the field.

[0055] In some cases, one or more fields within the codeword format may be configured as spare bits (e.g., CRC / spare bits, XORSub / spare bits). Bits configured as spare bits may be configured as CRC bits or XOR bits (or XORSub bits) as well as other alternatives. As an example, Figure 3 The codeword format 300 depicted in FIG. 300 may include up to twenty two (22) spare bits, such as twenty (20) CRC / spare bits and two (2) XORSub / spare bits. That is, some CRC bits may be configured as spare bits. Similarly, some repair bits (e.g., XORSub bits) may be configured as spare bits. Thus, the number of spare bits within a codeword may be configurable because the number of spare bits may be interchangeable with the number of CRC bits or XORSub bits. In some cases, the codeword format 300 may be configured based on a mature memory technology (e.g., 3D XPoint) used to construct the memory medium (e.g., memory medium 130, memory medium 295). TM , FeRAM, MRAM technology) to determine the number of spare bits in the codeword.

[0056] In some cases, spare bits may be configured to operate as spares to replace bits of a codeword that are designated as failed (e.g., erroneous bits). In some cases, bits that are designated as having failed may be associated with MSRs of a memory die (e.g., MSRs that include a number of memory cells that may have become erroneous or unreliable). Spare bits (e.g., MSRs corresponding to spare bits) may be routed (e.g., multiplexed using a multiplexing component) to replace (e.g., substitute) bits that are designated as having failed (e.g., MSRs corresponding to erroneous bits) to support reliable transactions of user data within a codeword.

[0057] Still reference Figure 3 , various fields (eg, bit fields) within a codeword format may be configured (eg, arranged) to support low latency operations during access operations associated with a memory medium. Figure 3 Formats 301-305 are included that illustrate various configurations of 8-bit groups for individual channels (e.g., each of channels 310-a-310-k). For example, each of formats 301-305 includes eight (8) bit groups that a memory device (e.g., a 3DXP die) within a memory medium (e.g., memory medium 295-a) may generate at a given burst of data. Example formats are described below, though the disclosure herein is not limited to these examples.

[0058] Format 301 may include one or more (e.g., three) fields of CwCon bits, one or more (e.g., two) fields of CRC / spare bits (which may be configured as CRC bits or spare bits), and one or more (e.g., three) fields of CRC bits. Format 302 may include one or more (e.g., three) fields of CwCon bits, one or more (e.g., two) fields of CRC / spare bits (which may be configured as CRC bits or spare bits), one or more (e.g., two) fields of CRC bits, and one or more WrCnt bits (e.g., counter bits).

[0059] Format 303 may include CwCon bits for one or more (e.g., three) fields, CRC / spare bits (which may be configured as CRC bits or spare bits) for one or more (e.g., two) fields, and WrCnt bits (e.g., counter bits) for one or more (e.g., three) fields. Format 304 may include CwCon bits for one or more (e.g., three) fields, CRC / spare bits (which may be configured as CRC bits or spare bits) for one or more (e.g., two) fields, WrCnt bits (e.g., counter bits) for one or more (e.g., two) fields, and inhibit bits (e.g., bits indicating invalidity of a portion of a codeword) for one or more (e.g., two) fields. Format 305 may include CwCon bits for one or more (e.g., three) fields, XORSub / spare bits (which may be configured as XORSub bits or spare bits) for one or more (e.g., two) fields, and XORSub bits for one or more (e.g., three) fields.

[0060] The codeword format 300 may also illustrate a 1,024-bit user data field (e.g., channels 310-a to 310-h on the second data burst 320-2 to the 16th data burst 320-16, and channels 310-i and 310-j on the second data burst 320-2 to the fifth data burst 320-5), a CwECC field (e.g., channels 310- and 310-j on the 6th data burst 320-6 to the 16th data burst 320-16), and an XOR / subfield (e.g., channel 310-k on the second data burst 320-2 to the 16th data burst 320-16).

[0061] As an example of a codeword format that supports low latency operation, a subset of the bit fields corresponding to a first data burst (e.g., first data burst 320-1) may be configured as illustrated in format 306. In format 306, each group of 8-bit channels 310-a (e.g., A7 ... A0) and channels 310-b (e.g., B7 ... B0) may be configured to have format 301. Also, a group of 8-bit channels 310-c (e.g., C7 ... C0) may be configured to have format 302. At least some, if not all, of the groups of 8-bit channels 310-d (e.g., D7 ... D0) through channels 310-i (e.g., I7 ... I0) may be configured to have format 303. A group of 8-bit channels 310-j (e.g., J7 ... J0) may be configured to have format 304. Furthermore, a group of 8-bit channels 310-k (e.g., K7 ... K0) may be configured to have format 305.

[0062] Since a subset of the bit fields corresponding to the first data burst (e.g., first data burst 320-1) of codeword format 300 is configured (e.g., 88 bits in total, including eight (8) bits from each of eleven (11) channels), the first data burst of 88 bits (e.g., 88 bits of format 306) may include information that facilitates low-latency, reliable transactions for access operations associated with the codeword (e.g., reading 1,024 bits of user data). In some cases, a port manager (e.g., port manager 260-a) may receive a first portion of a codeword associated with a memory medium (e.g., bits corresponding to first data burst 320-1 of format 306). The port manager may parse (e.g., interpret) the first portion of the codeword (e.g., identify spare bits) concurrently with receiving additional portions of the codeword (e.g., bits corresponding to second data burst 320-2 of codeword format 300, etc.) during subsequent data bursts. Thus, the port manager may parallelize various operations associated with the codeword to provide reliable, low-latency communications or information exchanges with a host.

[0063] As an example, within a first data burst (e.g., first data burst 320-1) as depicted in format 306, there may be up to twenty-two (22) spare bit fields, two fields per channel, across eleven (11) channels (e.g., channels 310-a through 310-k). In some cases, as part of a read operation, a controller (e.g., reference 320-1) may select a first data burst (e.g., first data burst 320-1) and select one of the second data bursts (e.g., first data burst 320-2). Figure 1 and 2 The controller 120 or port manager 260-a described above may be configured to store the data from a storage medium (e.g., reference Figure 1 and 2 The memory medium 130-a or memory medium 295-a described receives a first portion of a codeword (e.g., a first data burst 320-1). The codeword may include a set of bit fields indicating multiple data bursts across multiple channels (e.g., channels 310-a to 310-k).

[0064] The controller may identify a spare bit in a first portion of the codeword (e.g., one of the twenty-two (22) spare bits in the first data burst 320-1) to replace the bit field of the set. The controller may determine the bit field of the set to be replaced by the spare bit based on identifying the spare bit (e.g., the D1 bit of the channel 310-d within the third data burst 320-3). In addition, the controller may receive a second portion of the codeword (e.g., the second data bursts 320-2 to 320-16 or any portion thereof, one or more additional data bursts). In some cases, the port manager 260-a may replace the bit field of the set in the second portion of the codeword with the spare bit simultaneously with receiving the second portion of the codeword (e.g., the fourth data bursts 320-4 to 320-16 or any portion thereof). That is, in some cases, the port manager 260-a may replace the bit field of the set in the second portion of the codeword with the spare bit without increasing the number of clock edges used to process a sequence of data bursts (e.g., 16 data bursts). For example, port manager 260-a may receive a burst of data and replace a bit field over a first number of clock cycles while outputting a burst of data with the replaced bit field in the same number of clock cycles (e.g., the first number of clock cycles). In some cases, this may also be referred to as in-line, concurrent, parallel, or simultaneous error correction. Thus, the spare bits may be multiplexed into the bit stream of the codeword in a series of data bursts, which adds little or substantially no additional latency (other than the latency of the multiplexing components).

[0065] In some cases, the controller may access a memory array of the controller to determine the bit field of the set in the second portion of the codeword that is to be replaced with the spare bit in the first portion (e.g., the D1 bit of the channel 310-d within the third data burst 320-3). The memory array may be configured to maintain an indication of the spare bit assignments for the bit field of the set of codewords and may include an SRAM cell. In some cases, the controller may perform an error control operation for the codeword based on replacing the bit field of the set in the second portion of the codeword with the spare bit.

[0066] In some cases, replacing the bit fields of the set in the second portion of the codeword with the spare bits may include replacing the bit fields of the set with the spare bits using different methods, which may include using a combination of hierarchical logic gates configured based on a plurality of channels (e.g., eleven (11) channels, i.e., channels 310-a through 310-k), etc. In some cases, the combination of hierarchical logic gates may be configured based on the number of bit fields of the set corresponding to a data burst in a plurality of data bursts (e.g., sixteen (16) data bursts), e.g., eight (8) bits. Further, in some cases, the first portion of the codeword may correspond to an initial data burst in the plurality of data bursts (e.g., first data burst 320-1) and the second portion of the codeword may correspond to one or more additional data bursts in the plurality of data bursts that are temporally subsequent to the initial data burst in the plurality of data bursts (e.g., second data bursts 320-2 through 320-16 or any portion thereof).

[0067] In this manner, the controller may receive spare bits in a first data burst of a codeword (e.g., up to 22 spare bits in the first data burst 320-1) and determine, based on accessing a memory array (e.g., an SRAM cell holding an indication of the spare bit assignment), that an erroneous bit is to be replaced, the controller may replace (e.g., substitute) the erroneous bit with the spare bit simultaneously with receiving an additional data burst (e.g., the second data burst to the sixteenth data burst, or any portion thereof) or simultaneously with output of a corrected data burst. For example, when the controller determines, based on accessing the memory array, that the D1 bit of the channel 310-d within the third data burst 320-3 is a first erroneous bit, the controller may replace the D1 bit of the channel 310-d within the third data burst 320-3 with the first spare bit (e.g., spare bit A4 of the channel 310-a in the first data burst 320-1) simultaneously with receiving an additional data burst (e.g., the fourth data burst 320-4, etc.). Thus, the controller may replace the erroneous bit with the spare bit before the controller performs an error control operation using information in the CwECC field.

[0068] Figure 4 An example of a configuration 401 of a memory array and a configuration 402 of a memory medium to support spare replacement in a memory system according to aspects disclosed herein is illustrated. The memory array depicted in configuration 401 may be a reference Figure 1 and 2 The memory medium depicted in configuration 402 may be an example of a memory die of a memory medium (eg, memory medium 130 or memory medium 295). Figure 1 and 2An example of a memory medium (eg, memory medium 130 or memory medium 295) is depicted. The memory medium depicted in configuration 402 may include a number of memory arrays (eg, forty-four (44) memory arrays) that may each be configured according to configuration 401.

[0069] Configuration 401 may include a memory array 410. In some cases, memory array 410 may include a set of memory cells (eg, 512 Gigabit memory cells, i.e., 2 39 Memory cells). Memory array 410 may be organized to have array width 415 and array depth 425. In some cases, array width 415 may be referred to as die width 415 and array depth 425 may be referred to as die depth 425. In addition, array width 415 and array depth 425 may each be divided into a number of partitions. In some cases, array width 415 may be divided into 128 sections. Thus, section 420 depicted in configuration 401 may represent one of the 128 sections in array width 415. Furthermore, each section (e.g., section 420) may be divided into 128 slices so that array depth 425 may be divided into 128 bars. Bars may be referred to as sections, subsections, portions, elements, etc. Thus, bar 430 depicted in configuration 401 may represent one of the 128 bars in array depth 425.

[0070] Thus, a memory array 410 (e.g., 512 Gigabit memory cells) may be divided into a number of segments 435 (e.g., segments 435-a, 435-b, or 435-c), each of which is depicted as a square within the memory array 410 as an example. In this example, the memory array 410 may include 16,384 segments resulting from dividing the array width 415 into 128 sections and each of the sections further divided into 128 bars (e.g., sections, sub-sections, portions, elements) in the array depth 425. Each segment 435 of the memory array 410 may be referred to as an MSR 435. In some cases, an MSR 435 may include a group of memory cells (e.g., 2 25 The MSR can be configured as a reasonable fault containment area to effectively manage (e.g., replace, substitute) erroneous bits in the memory array.

[0071] The number of sectors (e.g., 128 sectors) in array width 415 may be determined based on how the memory array in the memory die is constructed. For example, the memory array may have a certain number of tiles (e.g., 128 tiles), and the number of sectors in array width 415 may be based on the number of tiles of memory array 410. Similarly, the number of bars (e.g., 128 bars) in array depth 425 may be determined based on common characteristics associated with various functional components (e.g., row decoders, column decoders, etc.). Since memory array 410 is divided as depicted in configuration 401, each segment 435 (e.g., a 2 out of 16,384 MSRs in a memory array containing 512 Gigabits) may be a 512 Gigabit memory array. 25 The MSR of 2 memory cells) can provide a group of memory cells (e.g., data cells) to efficiently manage (e.g., replace, substitute) error bits in the memory array 410 without incurring significant overhead. In some cases, the unit size of the memory cells (e.g., 2 of the MSR) is 25 Memory cells) can be referred to as data granularity that supports efficient error control operations associated with storage media.

[0072] Still referring to configuration 401, a bar 430 spanning a number of sectors (e.g., 128 sectors) may represent a first number of bits (e.g., 128 bits) generated by memory array 410 as a portion of a codeword (e.g., a portion of a codeword comprising 1,408 bits). The first number of bits (e.g., 128 bits) of bar 430 may be further down-multiplexed to a second number of bits (e.g., eight (8) bits), wherein each set of the second number of bits (e.g., eight (8) bits) may be generated at a given data burst (e.g., one of sixteen (16) data bursts generating a total of 128 bits). Thus, bar 430 may generate a portion of a codeword, wherein each segment 435 (e.g., MSR 435) contributes one of the first number of bits (e.g., 128 bits) of the codeword. Furthermore, bar 430 (e.g., 128 bits generated over 16 data bursts) may correspond to a channel (e.g., referring to Figure 2 A complete codeword (e.g., a 1,408-bit codeword) can be generated when a number of memory arrays 410 (e.g., eleven (11) memory arrays 410) are operated in parallel such that each memory array can generate a portion of the bits that make up a complete codeword (e.g., each memory array 410 generates 128 bits over sixteen (16) data bursts across eleven (11) channels, equivalent to a total of 1,408-bit codewords).

[0073] Configuration 402 may include a collection of memory arrays 410 (eg, forty-four (44) memory arrays 410) to achieve a memory medium (eg, reference Figure 1and 2 The desired or specified capacity of the storage medium 130-storage medium 295 described above can be arranged to form a plurality of channels for the storage medium. In some cases, the storage medium can include eleven (11) channels (e.g., channels 440-a through 440-k) as illustrated in configuration 402. Each channel 440 can be a reference Figure 2 Examples of channels 291 (e.g., channels 291-a through 291-k) are described or include aspects thereof. In addition, each channel 440 can be configured to include a subset of memory arrays. In some cases, a channel (e.g., channel 440-a) can include four (4) memory arrays 410-a through 410-d. Thus, in some cases, each of the plurality of channels can include a total number of bars 430 (e.g., 512 bars) that corresponds to a multiple of the number of bars of memory array 410 (e.g., 128 bars) multiplied by the number of memory arrays 410 within the channel (e.g., four (4) memory arrays).

[0074] In some cases, a group of MSRs that generate codewords across multiple channels (e.g., eleven (11) channels, i.e., channels 440-a through 440-k) may be referred to as an MSR stripe (e.g., MSR stripe 445 depicted in configuration 402). MSR stripes may also be referred to as MSR zones. For example, the memory medium of configuration 402 includes 512 MSR stripes (e.g., 512 MSR zones). Moreover, the MSR stripes (e.g., MSR stripe 445) may correspond to a collective array depth (e.g., collective die depth) of the memory medium, for example, the MSR stripe 445 depicted in configuration 402 may correspond to the 130th array depth (e.g., the 130th MSR stripe out of a total array depth of 512 MSR stripes) of the memory medium, where each memory array 410 includes 128 MSR stripes. In some cases, a flag may be associated with an MSR stripe (or MSR region) to indicate a change in the spare bit assignment associated with the codewords retained in the MSR stripe (e.g., MSR stripe 345 or MSR region 345). The flag may be a flag for a controller (e.g., referring to Figure 1 and 2 Portions of a memory array (eg, SRAM memory cells) in the controller 120 or port manager 260 - a ) are depicted.

[0075] At least some, if not all, of the MSRs (e.g., MSR 435-a, MSR 435-b, MSR 435-c) of a memory array (e.g., memory array 410) may be associated with a counter configured to count the number of error bits therein. For example, as part of background operations, a port manager (e.g., reference Figure 2 The described port manager 260-a) may read a codeword from an MSR stripe (e.g., MSR stripe 445) and perform error control operations for the codeword. The port manager may identify a number of error bits and correct the number of error bits in the codeword using a set of bits in the codeword (e.g., bits that support error correction functions). Each error bit in the number of error bits (e.g., an erroneous or unreliable memory cell) may correspond to a corresponding MSR of the MSR stripe. The port manager may update a first counter associated with a first MSR of the MSR stripe to count the number of error bits (e.g., an error bit count) in the first MSR of the MSR stripe.

[0076] The port manager may sort the values ​​(e.g., error bit counts) stored in the counters for the codeword (e.g., 1,408 counters each corresponding to the 1,408 MSRs) to identify a subset of values ​​that are greater than the remaining values. For example, the port manager may sort the values ​​(e.g., error bit counts) in descending order to identify a subset of values ​​(e.g., 160 highest error bit counts out of the 1,408 error bit counts associated with the codeword). In this manner, the port manager may identify a subset of MSRs that each include a higher number of error bits than other MSRs. The port manager may identify the subset of MSRs (e.g., 160 MSRs out of the 1,408 MSRs) as candidates for replacement (e.g., replacing such MSRs with reliable MSRs (e.g., spare MSRs)). In some cases, the port manager may configure the number of values ​​for the subset based on the number of error bits identified in the codeword (e.g., 200 highest error bit counts instead of 160 highest error bit counts). In some cases, the number of such values ​​for a subset (e.g., a subset of MSRs identified as candidates for replacement) may be based on various factors (e.g., the memory technology of the memory devices used to manufacture the memory media, the maturity of such memory technology, memory media usage patterns).

[0077] In addition, the port manager may replace one or more MSRs with higher error bit counts (e.g., a subset of MSRs identified as candidates for replacement) with the set of spare MSRs until the set of spare MSRs is exhausted. The port manager may determine the replacement MSR based on the number of error bits (e.g., error bit count) in the MSR relative to a threshold (e.g., a bit level replacement threshold). In some cases, the port manager may determine to replace an MSR with an error bit count equal to or greater than the threshold with a spare MSR. The threshold may be based on a raw bit error rate (RBER) associated with the memory medium. In some cases, the threshold may be based on MSR size (e.g., 2 in the MSR). 25In some cases, the threshold value may be configurable (eg, programmable) to account for, for example, maturity of the technology used to fabricate the memory cells of the memory media, process variations that may affect the electrical characteristics of the memory cells of the memory media.

[0078] The port manager may designate a replacement MSR (e.g., a spare bit in a codeword) to replace any of the MSRs identified as candidates for replacement (e.g., an erroneous bit in a codeword). In some cases, the replacement bit (e.g., spare MSR) may be designated on a first-identify-first-assign basis. For example, during one or more background operations (e.g., media scrubber operations), the port manager may determine that the bit (e.g., reference bit) is Figure 3 The depicted A7 in the channel 310-a in the sixth data burst 320-6 is the first bit in the codeword that satisfies the threshold (e.g., the first MSR that contains a number of error bits equal to or greater than the bit-level replacement threshold). Next, an available spare bit (e.g., an MSR corresponding to the first spare bit, such as spare bit A4 of the channel 310-a in the first data burst 320-1) may be assigned to replace the first bit (e.g., A7 in the channel 310-a in the sixth data burst 320-6).

[0079] Later (e.g., during a later media cleaner operation), the port manager may determine another (e.g., reference Figure 3 The depicted B0 in channel 310-b in the third data burst 320-3 is the second bit in the codeword that satisfies the threshold (e.g., a second MSR that contains a number of erroneous bits that is equal to or greater than the bit-level replacement threshold). Next, a second available spare bit (e.g., another MSR corresponding to the second spare bit, such as spare bit A3 of channel 310-a in the first data burst 320-1) may be assigned to replace the second bit (e.g., B0 in channel 310-b in the third data burst 320-3).

[0080] The port manager may repeatedly assign spare bits to erroneous bits in the codeword until all spare bits are assigned (e.g., reference Figure 3The port manager may assign the available spare bits to a subset of erroneous bits, wherein the subset of MSRs corresponding to the subset of erroneous bits each contains a larger erroneous bit count therein than the other MSRs. Thus, the port manager may replace the most problematic MSRs (e.g., based on the erroneous bit counts in the MSRs) with the available spare bits.

[0081] The port manager may store information indicating spare assignments for codewords (e.g., spare bit assignments for corresponding erroneous bits) in a separate memory array. In some cases, the memory array may be integrated as part of the port manager. In some cases, the memory array may include static random access memory (SRAM) cells. The size of the memory array allocated for storing the information may be based on identification of a channel in a plurality of channels (e.g., eleven (11) channels), a number of spare bits in a codeword (e.g., up to twenty-two (22) spare bits), identification of one or more of a number of MSRs associated with a codeword (e.g., 1,408 MSRs), a number of bits associated with a forwarded codeword in a memory medium, an error correction capability for an indication of spare bit assignments, a number of memory dies corresponding to a channel in a plurality of channels (e.g., four (4) memory dies per channel), a number of MSR groups in the number of memory dies (e.g., 128 MSR bars), or a bit indicating a change in spare bit assignments (e.g., a flag indicating a change in spare assignments), or any combination thereof.

[0082] In some cases, the port manager may receive an indication of the power level from a power management component coupled to the port manager and transmit information stored in a memory array (e.g., an SRAM cell) (e.g., an indication of the spare bit assignment) to the referenced Figure 1 and 2 Non-volatile memory (eg, persistent memory) is described.

[0083] In some cases, the port manager may set a flag associated with the port manager based on assigning spare bits of the codeword to replace erroneous bits in the codeword. The flag may indicate a change in spare bit assignments (e.g., spare bits assigned to new erroneous bits of the codeword during a media scrubber operation) associated with the codeword held in an MSR group (e.g., MSR zone 345 or MSR stripe 345) that includes the corresponding MSR of the codeword. The flag may be part of a memory array (e.g., SRAM memory cells) in the port manager.

[0084] In some cases, the codeword may be configured to support channel replacement. Channel replacement may refer to replacing a bar (e.g., bar 430-a or bar 430-b) with another bar (e.g., bar 430-k) within the codeword. Bars may be referred to as sections, subsections, portions, elements, etc. Thus, channel replacement may refer to replacement in the die width 415 rather than in the die depth 425. In addition, when one of the channels contains a number of error bits (e.g., a number of MSRs corresponding to the number of error bits) that each satisfies a first threshold (e.g., a bit-level replacement threshold), one of the channels 440-a to 440-j in the codeword may be replaced by the channel 440-k in the codeword. If there is more than one such channel in the codeword, the port manager may determine to replace the worst channel (e.g., the channel containing the largest number of error bits that satisfies the bit-level replacement threshold).

[0085] In some cases, a controller (e.g., reference Figure 1 and 2 Controller 120 or port manager 260-a) may read a codeword from a storage medium (e.g., storage medium 130-a or storage medium 295-a) that includes a plurality of MSRs. The codeword may include information indicating a plurality of channels associated with the storage medium (e.g., reference Figures 2 to 4 A set of bit fields for channels 291-a to 291-k, channels 310-a to 310-k, or channels 440-a to 440-k) as described.

[0086] At least some, if not all, of the bit fields of the set may correspond to respective MSRs of a plurality of MSRs that may be associated with the counter. The controller may identify, based on the read codeword, a channel (e.g., reference channel) of the plurality of channels. Figure 3 and 4The controller may determine that the first number is equal to or greater than a second threshold (e.g., a channel-level replacement threshold). In some cases, the controller may assign a spare channel (e.g., a reference channel) of a codeword to a channel in the plurality of channels based on determining that the first number (e.g., the number of bit fields that satisfy the bit-level replacement threshold) is equal to or greater than the second threshold (e.g., the channel-level replacement threshold). Figure 3 and 4 channel 310-k or channel 440-k) described above.

[0087] In some cases, the controller may use an error control operation that may be based on the size of one or more of the multiple MSRs to identify the number of error bits and set (e.g., initially set, update) the value of a counter associated with a respective MSR that corresponds to the number of error bits, so that a first number of counters associated with a channel in the multiple can be identified based on setting (e.g., initially setting, updating) the value of the counter. In some cases, the controller may write an indication of a spare channel assignment for a channel in the multiple channels to a memory array (e.g., an SRAM cell) of the controller based on assigning the spare channel of the codeword. In some cases, the controller may set a flag associated with the controller based on assigning the spare channel of the codeword. The flag may indicate a change in the spare channel assignment associated with the codeword maintained in the memory medium. In some cases, the first threshold (e.g., a bit-level replacement threshold) may correspond to a configurable (e.g., programmable) value associated with assigning spare bits of the codeword to a bit field of the set. In some cases, the second threshold (e.g., a channel-level replacement threshold) may correspond to a second number of bit fields within a channel of the plurality of channels, each bit field of the second number being associated with a corresponding counter having a value equal to or greater than the first threshold (e.g., the bit-level replacement threshold).

[0088] In some cases, the controller may perform one or more background operations for a set of codewords maintained in a memory medium independently of access operations from a host, such as reading a codeword, identifying a number of erroneous bits in the codeword, updating a counter associated with a corresponding MSR corresponding to the number of erroneous bits in the codeword, determining a value of the counter relative to a threshold (e.g., a bit level substitution threshold), assigning a spare bit of the codeword to an erroneous bit, writing an indication of the spare bit assignment to a memory array (e.g., an SRAM cell), or setting a flag to indicate a change in spare assignments in an MSR stripe after assigning a new spare bit within the MSR stripe, or any combination thereof.

[0089] The set of codewords may include at least some, if not all, of the codewords held in the storage medium, and the controller may perform the background operation for all of the codewords one at a time (e.g., sequentially). In some cases, the set of codewords may include all of the codewords held in an MSR group (e.g., an MSR stripe 345 or an MSR region 345) that includes the codewords' respective MSRs. Furthermore, the controller may repeat the background operation for all of the codewords held in the storage medium (or MSR group), which may include periodically performing the background operation for one or more codewords in the storage medium (or MSR group). In some cases, the background operation may be referred to as a media scrubber operation (which may also be referred to as a media scrubbing function).

[0090] Figure 5 A block diagram 500 is shown of a controller 515 supporting spare replacement in a memory system according to aspects disclosed herein. The controller 515 may be a reference Figures 1 to 2 Controller 515 may include a bias component 520, a timing component 525, an access manager 530, a codeword manager 535, and an error control manager 540. Each of these modules may communicate with each other (e.g., via one or more buses) directly or indirectly.

[0091] Access manager 530 may receive a first portion of a codeword from a memory medium, the codeword including a set of bit fields indicating multiple bursts of data across multiple channels. In some cases, access manager 530 may receive a second portion of the codeword based on determining a set of bit fields to be replaced by spare bits.

[0092] In some cases, the access manager 530 may read a codeword from a memory medium that includes a set of minimum substitution regions (MSRs), the codeword including a plurality of bits that each correspond to a respective MSR of the set. In some cases, as part of a background operation independent of an access command from a host, the access manager 530 may retrieve the codeword, wherein identifying the number of erroneous bits may be based on retrieving the codeword. In some cases, the access manager 530 may retrieve a plurality of codewords from a subset of MSRs that include the respective MSRs by sequentially retrieving each codeword, wherein identifying the number of erroneous bits is based on sequentially retrieving each codeword.

[0093] In some cases, the access manager 530 may read a codeword from a memory medium comprising a plurality of minimum substitution regions (MSRs), the codeword comprising a set of bit fields indicating a plurality of channels associated with the memory medium, wherein each bit field of the set may correspond to a respective MSR of the plurality of MSRs associated with the counter.

[0094] The codeword manager 535 may identify spare bits in the first portion of the codeword to replace the bit field of the set based on receiving the first portion of the codeword. In some cases, the first portion of the codeword may correspond to an initial data burst in a plurality of data bursts, and the second portion of the codeword may correspond to one or more additional data bursts in the plurality of data bursts that are temporally subsequent to the initial data burst in the plurality of data bursts.

[0095] The error control manager 540 may determine the bit field of the set to be replaced with the spare bit based on identifying the spare bit. In some cases, the error control manager 540 may replace the bit field of the set in the second portion of the codeword with the spare bit simultaneously with receiving the second portion of the codeword. In some cases, the error control manager 540 may perform an error control operation for the codeword based on replacing the bit field of the set in the second portion of the codeword with the spare bit. In some cases, the error control manager 540 may access a memory array of the port manager, the memory array being configured to maintain an indication of the spare bit assignments for the bit field of the set of codewords, wherein determining the bit field of the set to be replaced with the spare bit in the second portion of the codeword may be based on accessing the memory array.

[0096] In some cases, the size of the memory array for maintaining an indication of spare bit assignments may be based on an identification of a channel among a plurality of channels, a number of spare bits in a codeword, an identification of a minimum substitution region (MSR) for a number of MSRs associated with the codeword, a number of bits associated with a forwarded codeword in a memory medium, an error correction capability for the indication of spare bit assignments, a number of memory dies corresponding to a channel among a plurality of channels, a number of MSRs in the number of memory dies, or bits indicating a change in spare bit assignments, or any combination thereof.

[0097] In some cases, replacing the bit field of the set in the second portion of the codeword with the spare bit may further include replacing the bit field of the set with the spare bit using a combination of hierarchical logic gates configured based on the plurality of channels based on the received second portion of the codeword. In some cases, replacing the bit field of the set in the second portion of the codeword with the spare bit may further include replacing the bit field of the set with the spare bit using a combination of hierarchical logic gates configured based on a number of bit fields of the set corresponding to a data burst in the plurality of data bursts based on the received second portion of the codeword.

[0098] In some cases, the error control manager 540 may identify the number of erroneous bits in the codeword using an error control operation that may be based on the size of one or more MSRs of the set. In some cases, the error control manager 540 may set a value of a counter associated with the set of MSRs corresponding to the number of erroneous bits based on identifying the number of erroneous bits in the codeword. In some cases, the error control manager 540 may determine a value of the counter relative to a threshold value based on the value of the counter. In some cases, the error control manager 540 may assign spare bits of the codeword to the number of erroneous bits based on the value of the counter relative to the threshold value.

[0099] In some cases, the error control manager 540 may replace the number of erroneous bits with spare bits of the codeword based on assigning spare bits of the codeword. In some cases, the error control manager 540 may write an indication of the spare bit assignment of the number of erroneous bits to a memory array of the port manager based on assigning spare bits of the codeword, the memory array being configured to store a plurality of such indications associated with a plurality of spare bits in the codeword. In some cases, the error control manager 540 may configure the threshold to be a raw bit error rate (RBER) associated with the memory medium based on identifying the number of erroneous bits in the codeword. In some cases, the error control manager 540 may configure the threshold to be a size of the MSR of the set based on identifying the number of erroneous bits in the codeword. In some cases, the error control manager 540 may set a flag associated with the port manager based on assigning spare bits of the codeword, the flag indicating a change in spare bit assignment associated with a codeword maintained in a subset of the MSRs that includes the corresponding MSR. In some cases, the subset of the MSRs may include a plurality of codewords.

[0100] In some cases, the error control manager 540 may, based on reading the codeword, identify a first number of counters associated with a channel in the plurality of channels, the first number of counters each having a value equal to or greater than a first threshold. In some cases, the error control manager 540 may determine that the first number is equal to or greater than a second threshold based on identifying the first number of counters. In some cases, the error control manager 540 may assign a backup channel for the codeword to a channel in the plurality of channels based on determining that the first number is equal to or greater than the second threshold.

[0101] In some cases, the error control manager 540 may identify the number of erroneous bits using an error control operation that may be based on a size of one or more of the plurality of MSRs. In some cases, the error control manager 540 may set a value of a counter associated with a respective MSR that each corresponds to the number of erroneous bits based on identifying the number of erroneous bits, wherein identifying a first number of counters associated with a channel of the plurality of channels may be based on setting the value of the counter. In some cases, the error control manager 540 may write an indication of an alternate channel assignment for a channel of the plurality of channels to a memory array of the port manager based on assigning the alternate channel for the codeword. In some cases, the error control manager 540 may set a flag associated with the port manager based on assigning the alternate channel for the codeword, the flag indicating a change in the alternate channel assignment associated with the codeword maintained in the memory medium.

[0102] In some cases, the first threshold may correspond to a configurable value associated with a bit field that assigns spare bits of the codeword to a set. In some cases, the second threshold may correspond to a second number of bit fields within a channel of the plurality of channels, each bit field in the second number being associated with a corresponding counter having a value equal to or greater than the first threshold.

[0103] Figure 6 A flowchart illustrating a method 600 for supporting spare replacement in a memory system according to aspects disclosed herein is shown. The operations of the method 600 may be referred to as Figures 1 to 2 For example, the operations of method 600 may be implemented by the controller or components thereof described herein. Figures 1 to 2 The controller 120 or controller 230 described herein may be executed. In some examples, the controller 230 may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the controller 230 may use dedicated hardware to perform aspects of the functions described below.

[0104] At 605, the controller 230 may receive a first portion of a codeword from a memory medium, the codeword comprising a set of bit fields indicating a plurality of data bursts across a plurality of channels. Figure 1-5 The described method performs the operation of 605. In some examples, the reference Figure 5 Aspects of the operations of access manager execution 605 are described.

[0105] At 610, the controller 230 may identify a spare bit in the first portion of the codeword to replace the bit field of the set based on receiving the first portion of the codeword. Figure 1-5 The described method performs the operation of 610. In some examples, the reference Figure 5 Aspects of the operations of the codeword manager performance 610 are described.

[0106] At 615, the controller 230 may determine the bit fields of the set to be replaced by the spare bits based on identifying the spare bits. Figure 1-5 The described method performs the operation of 615. In some examples, the reference Figure 5 Aspects of the operation of the error control manager execution 615 are described.

[0107] At 620, the controller 230 may receive a second portion of the codeword based on determining the bit field of the set to be replaced by the spare bit. Figure 1-5 The described method performs the operation of 620. In some examples, the reference Figure 5 Aspects of the operations of the access manager execution 620 are described.

[0108] At 625, the controller 230 may replace the bit fields of the set in the second portion of the codeword with the spare bits simultaneously with receiving the second portion of the codeword. Figure 1-5 The described method performs the operation of 625. In some examples, the reference Figure 5 Aspects of the operation of the error control manager execution 625 are described.

[0109] An apparatus for performing one or more methods, such as method 600, is described. The apparatus may include means for receiving a first portion of a codeword from a memory medium, the codeword including a set of bit fields indicating a plurality of data bursts across a plurality of channels; means for identifying a spare bit in the first portion of the codeword to replace the bit field of the set based on receiving the first portion of the codeword; means for determining the bit field of the set to be replaced by the spare bit based on identifying the spare bit; means for receiving a second portion of the codeword based on determining the bit field of the set to be replaced by the spare bit; and means for replacing the bit field of the set in the second portion of the codeword with the spare bit concurrently with receiving the second portion of the codeword.

[0110] Another apparatus for performing one or more methods, such as method 600, is described. The apparatus may include a memory medium and a controller in electronic communication with the memory medium, wherein the controller may be operable to receive a first portion of a codeword from the memory medium, the codeword including a set of bit fields indicating a plurality of data bursts across a plurality of channels; identify a spare bit in the first portion of the codeword to replace the set of bit fields based on receiving the first portion of the codeword; determine the set of bit fields to be replaced by the spare bit based on identifying the spare bit; receive a second portion of the codeword based on determining the set of bit fields to be replaced by the spare bit; and replace the set of bit fields in the second portion of the codeword with the spare bit concurrently with receiving the second portion of the codeword.

[0111] Some examples of the method 600 and apparatus described herein may additionally include a process, feature, means, or instruction for performing an error control operation for the codeword based on replacing the bit field of the set in the second portion with the spare bit. Some examples of the method 600 and apparatus described herein may additionally include a process, feature, means, or instruction for accessing a memory array of a port manager, the memory array being configured to maintain an indication of the spare bit assignments for the bit field of the set of codewords, wherein determining the bit field of the set in the second portion of the codeword to be replaced with the spare bit may be based on accessing the memory array.

[0112] In some examples of the method 600 and apparatus described herein, the size of the memory array for maintaining an indication of spare bit assignments may be based on an identification of a channel among a plurality of channels, a number of spare bits in a codeword, an identification of a minimum substitution region (MSR) of a number of MSRs associated with the codeword, a number of bits associated with a forwarded codeword in a memory medium, an error correction capability for the indication of spare bit assignments, a number of memory dies corresponding to a channel among a plurality of channels, a number of MSR groups in the number of memory dies, or a bit indicating a change in spare bit assignments, or any combination thereof.

[0113] In some examples of the methods 600 and apparatus described herein, replacing the bit fields of the set in the second portion of the codeword with spare bits may further include, based on receiving the second portion of the codeword, replacing the bit fields of the set with spare bits using a combination of hierarchical logic gates configured based on the number of bit fields of the set corresponding to a data burst in a plurality of data bursts. In some examples of the methods 600 and apparatus described herein, the first portion of the codeword may correspond to an initial data burst in the plurality of data bursts, and the second portion of the codeword may correspond to one or more additional data bursts in the plurality of data bursts that are temporally subsequent to the initial data burst in the plurality of data bursts.

[0114] Figure 7 A flowchart illustrating a method 700 for supporting spare replacement in a memory system according to aspects disclosed herein is shown. The operations of the method 700 may be referred to as Figures 1 to 2 The operations of method 700 may be implemented by the controller or components described herein. Figures 1 to 2 The controller 120 or controller 230 described herein may be executed. In some examples, the controller 230 may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the controller 230 may use dedicated hardware to perform aspects of the functions described below.

[0115] At 705, controller 230 may read a codeword from a memory medium including a set of minimum substitution regions (MSRs), the codeword including a plurality of bits that each correspond to a respective MSR of the set. Figure 1-5 The described method performs the operations of 705. In some examples, aspects of the operations of 705 may be described by reference to Figure 5 The described access manager is executed.

[0116] At 710, the controller 230 may use an error control operation that may be based on the size of one or more MSRs of the set to identify the number of error bits in the codeword. Figure 1-5 The described method performs the operations of 710. In some examples, aspects of the operations of 710 may be described with reference to Figure 5 The described error control manager is implemented.

[0117] At 715, the controller 230 may set a value of a counter associated with a set of MSRs corresponding to the number of erroneous bits in the identified codeword. Figure 1-5 The described method performs the operations of 715. In some examples, aspects of the operations of 715 may be described by reference to Figure 5 The described error control manager is implemented.

[0118] At 720, the controller 230 may determine a value of the counter relative to a threshold value based on the value of the counter. Figure 1-5 The described method performs the operations of 720. In some examples, aspects of the operations of 720 may be described by reference to Figure 5 The described error control manager is implemented.

[0119] At 725, controller 230 may assign spare bits of the codeword to the number of erroneous bits based on the value of the counter relative to the threshold. Figure 1-5 The described method performs the operations of 725. In some examples, aspects of the operations of 725 may be described by reference to Figure 5 The described error control manager is implemented.

[0120] An apparatus for performing one or more methods, such as method 700, is described. The apparatus may include means for reading a codeword from a memory medium including a set of minimum substitution regions (MSRs), the codeword including a plurality of bits that each correspond to a respective MSR of the set; means for identifying a number of erroneous bits in the codeword using an error control operation that may be based on a size of one or more of the MSRs of the set; means for setting a value of a counter associated with the MSRs of the set based on identifying the number of erroneous bits in the codeword, the MSRs of the set corresponding to the number of erroneous bits; means for determining a value of the counter relative to a threshold based on the value of the counter; and means for assigning spare bits of the codeword to the number of erroneous bits based on the value of the counter relative to the threshold.

[0121] Another apparatus for performing one or more methods, such as method 700, is described. The apparatus may include a memory medium and a controller in electronic communication with the memory medium, wherein the controller may be operable to read a codeword from the memory medium including a set of minimum substitution regions (MSRs), the codeword including a plurality of bits that each correspond to a respective MSR of the set; identify a number of erroneous bits in the codeword using an error control operation that may be based on a size of one or more of the MSRs of the set; based on identifying the number of erroneous bits in the codeword, set a value of a counter associated with the MSRs of the set, the MSRs of the set corresponding to the number of erroneous bits; determine a value of the counter relative to a threshold based on the value of the counter; and assign spare bits of the codeword to the number of erroneous bits based on the value of the counter relative to the threshold.

[0122] Some instances of the method 700 and apparatus described herein may additionally include processes, features, means, or instructions for replacing the number of erroneous bits with spare bits of the codeword based on assigning spare bits of the codeword. Some instances of the method 700 and apparatus described herein may additionally include processes, features, means, or instructions for writing an indication of the spare bit assignments of the number of erroneous bits to a memory array of the port manager based on assigning spare bits of the codeword, the memory array being configured to store a plurality of such indications associated with a plurality of spare bits in the codeword. Some instances of the method 700 and apparatus described herein may additionally include processes, features, means, or instructions for configuring a threshold to a raw bit error rate (RBER) associated with the memory medium based on identifying the number of erroneous bits in the codeword.

[0123] Some examples of the methods 700 and apparatus described herein may additionally include processes, features, means, or instructions for configuring a threshold to be a size of a set of MSRs based on the number of erroneous bits in the identified codeword. Some examples of the methods 700 and apparatus described herein may additionally include processes, features, means, or instructions for setting a flag associated with a port manager based on assigning spare bits of the codeword, the flag indicating a change in spare bit assignments associated with codewords maintained in a subset of MSRs that include the corresponding MSRs. In some examples of the methods 700 and apparatus described herein, the subset of MSRs may include multiple codewords.

[0124] In some examples of the methods 700 and apparatus described herein, reading a codeword from the memory medium may further include, as part of a background operation independent of an access command from a host, retrieving a codeword, wherein identifying the number of erroneous bits may be based on retrieving the codeword. In some examples of the methods 700 and apparatus described herein, reading a codeword from the memory medium may further include retrieving a plurality of codewords from a subset of MSRs including respective MSRs by sequentially retrieving each codeword, wherein identifying the number of erroneous bits may be based on sequentially retrieving each codeword.

[0125] Figure 8 A flowchart illustrating a method 800 for supporting spare replacement in a memory system according to aspects disclosed herein is shown. The operations of the method 800 may be referred to as Figures 1 to 2 The operations of method 800 may be implemented by the controller or components described herein. Figures 1 to 2 The controller 120 or controller 230 described herein may be executed. In some examples, the controller 230 may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the controller 230 may use dedicated hardware to perform aspects of the functions described below.

[0126] At 805, the controller 230 may read a codeword from a memory medium including a plurality of minimum substitution regions (MSRs), the codeword including a set of bit fields indicating a plurality of channels associated with the memory medium, wherein each bit field of the set may correspond to a respective MSR of the plurality of MSRs associated with the counter. Figure 1-5 The described method performs the operations of 805. In some examples, aspects of the operations of 805 may be described by reference to Figure 5 The described access manager is executed.

[0127] At 810, the controller 230 may identify a first number of counters associated with channels in the plurality of channels based on the read codeword, the first number of counters each having a value equal to or greater than a first threshold. Figure 1-5The described method performs the operations of 810. In some examples, aspects of the operations of 810 may be described by reference to Figure 5 The described error control manager is implemented.

[0128] At 815, the controller 230 may determine that the first number is equal to or greater than a second threshold based on the counter identifying the first number. Figure 1-5 The described method performs the operations of 815. In some examples, aspects of the operations of 815 may be described by reference to Figure 5 The described error control manager is implemented.

[0129] At 820, the controller 230 may assign a backup channel of the codeword to a channel in the plurality of channels based on determining that the first number is equal to or greater than a second threshold. Figure 1-5 The described method performs the operations of 820. In some examples, aspects of the operations of 820 may be described with reference to Figure 5 The described error control manager is implemented.

[0130] An apparatus for performing one or more methods, such as method 800, is described. The apparatus may include means for reading a codeword from a storage medium of a plurality of minimum substitution regions (MSRs), the codeword including a set of bit fields indicating a plurality of channels associated with the storage medium, wherein each bit field of the set may correspond to a respective one of the plurality of MSRs associated with a counter; means for identifying a first number of counters associated with a channel of a plurality of channels based on reading the codeword, the first number of counters each having a value equal to or greater than a first threshold; means for determining that the first number is equal to or greater than a second threshold based on identifying the first number of counters; and means for assigning a spare channel of the codeword to a channel of the plurality of channels based on determining that the first number is equal to or greater than the second threshold.

[0131] Another apparatus for performing one or more methods, such as method 800, is described. The apparatus may include a memory medium and a controller in electronic communication with the memory medium, wherein the controller may be operable to read a codeword from the memory medium including a plurality of minimum substitution regions (MSRs), the codeword including a set of bit fields indicating a plurality of channels associated with the memory medium, wherein each bit field of the set may correspond to a respective one of the plurality of MSRs associated with a counter; based on reading the codeword, identify a first number of counters associated with a channel of the plurality of channels, the first number of counters each having a value equal to or greater than a first threshold; based on identifying the first number of counters, determine that the first number is equal to or greater than a second threshold; and based on determining that the first number is equal to or greater than the second threshold, assign a spare channel of the codeword to a channel of the plurality of channels.

[0132] Some examples of the method 800 and apparatus described herein may additionally include a process, feature, means, or instruction for identifying a number of erroneous bits using an error control operation that may be based on a size of one or more of the plurality of MSRs. Some examples of the method 800 and apparatus described herein may additionally include a process, feature, means, or instruction for identifying a number of erroneous bits using an error control operation that may be based on a size of one or more of the plurality of MSRs. Some examples of the method 800 and apparatus described herein may additionally include a process, feature, means, or instruction for setting a value of a counter associated with a respective MSR that each corresponds to the number of erroneous bits based on identifying the number of erroneous bits, wherein identifying a first number of counters associated with a channel of the plurality of channels may be based on setting the value of the counter.

[0133] Some examples of the method 800 and apparatus described herein may additionally include a process, feature, means, or instruction for writing an indication of a backup channel assignment for a channel in a plurality of channels to a memory array of a port manager based on the backup channel for the assigned codeword. Some examples of the method 800 and apparatus described herein may additionally include a process, feature, means, or instruction for setting a flag associated with the port manager based on the backup channel for the assigned codeword, the flag indicating a change in the backup channel assignment associated with the codeword maintained in the memory medium.

[0134] In some examples of the methods 800 and apparatus described herein, the first threshold may correspond to a configurable value associated with assigning spare bits of a codeword to a bit field of a set. In some examples of the methods 800 and apparatus described herein, the second threshold may correspond to a second number of bit fields within a channel of the plurality of channels, each bit field in the second number being associated with a corresponding counter having a value equal to or greater than the first threshold.

[0135] It should be noted that the methods described herein describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and other embodiments are possible. Additionally, two or more examples from the methods may be combined.

[0136] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0137] The terms "electronic communication" and "coupling" refer to a relationship between components that supports the flow of electrons between the components. This may include a direct connection between the components or may include intermediate components. Components that are electronically communicating or coupled to each other may actively exchange electrons or signals (e.g., in an energized circuit) or may not actively exchange electrons or signals (e.g., in a de-energized circuit), but may be configured and operable to exchange electrons or signals as soon as the circuit is energized. By way of example, two components that are physically connected via a switch (e.g., a transistor) are in electronic communication or may be coupled regardless of the state of the switch (i.e., open or closed).

[0138] The chalcogenide material may be a material or alloy containing at least one of the elements S, Se and Te. The phase change material discussed herein may be a chalcogenide material. The chalcogenide material may include alloys of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-A s, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, T e-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-B i-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. As used herein, hyphenated chemical composition symbols indicate elements contained in a particular compound or alloy and are intended to represent all stoichiometric amounts involving the indicated elements. For example, Ge-Te may contain Ge x Te y , where x and y can be any positive integer. Other examples of variable resistance materials may include binary metal oxide materials or mixed valence oxides, including two or more metals, such as transition metals, alkaline earth metals and / or rare earth metals. Examples are not limited to one or more specific variable resistance materials associated with the memory element of the memory cell. For example, other examples of variable resistance materials can be used to form the memory element and can include chalcogenide materials, colossal magnetoresistive materials, or polymer-based materials, etc.

[0139] The devices discussed herein, including the memory media 130, may be formed on a semiconductor substrate such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0140] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred to" or "superior to" other examples. For the purpose of providing an understanding of the described techniques, the detailed description includes specific details. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in the form of block diagrams in order to avoid confusing the concepts of the described examples.

[0141] In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dashed line and a second label that distinguishes among similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label regardless of the second reference label.

[0142] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description herein may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0143] The various illustrative blocks and modules described in conjunction with the disclosure herein may be implemented or performed by a general purpose processor, a DSP, an ASIC, a field programmable gate array (FPGA), or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a combination of multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0144] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of the present disclosure and the appended claims. For example, due to the nature of the software, the functions described herein may be implemented using software, hardware, firmware, hard wiring, or any combination of these executed by a processor. The features of the implementation functions may also be physically located at various locations, including being distributed so that the various parts of the functions are implemented at different physical locations. In addition, as used herein (included in the claims), as used in a list of items (e.g., a list of items with a phrase such as "at least one of" or "one or more of"), "or" indicates a list containing endpoints, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as referring to a closed conditional set. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope disclosed herein. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on".

[0145] Computer-readable media include both non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage or other magnetic storage device device, or any other non-transitory media that can be used to carry or store the desired program code device in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. And, any connection is appropriately referred to as computer-readable media. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave is used to transmit software from a website, server or other remote source, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0146] The description herein is provided to enable those skilled in the art to make or use the present disclosure. Those skilled in the art will readily appreciate various modifications to the present disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for operating a memory system, comprising: receiving a read command to access a codeword stored at a memory medium included in a memory device; receiving a first portion of the codeword stored at the memory medium based at least in part on the read command, the codeword comprising a set of bit fields indicating a plurality of bursts of data across a plurality of channels; identifying, based at least in part on receiving the first portion of the codeword, spare bits in the first portion of the codeword stored at the memory medium to replace a bit field of the set; determining the bit field of the set to be replaced by the spare bit based at least in part on identifying the spare bit; receiving a second portion of the codeword stored at the memory medium based at least in part on the read command based at least in part on determining the bit field of the set to be replaced by the spare bits; and The bit fields of the set in the second portion of the codeword are replaced with the spare bits concurrently with receiving the second portion of the codeword.

2. The method according to claim 1, further comprising: An error control operation for the codeword is performed based at least in part on replacing the set of bit fields in the second portion of the codeword with the spare bits.

3. The method of claim 1, further comprising: accessing a memory array of a port manager, the memory array being configured to maintain an indication of a spare bit assignment for the bit field of the set of the codewords, wherein the bit field of the set in the second portion of the codeword to be replaced by the spare bit is determined based at least in part on accessing the memory array.

4. The method of claim 3 , wherein a size of the memory array used to hold the indication of the spare bit assignment is based at least in part on: Identification of a channel among the plurality of channels, a number of spare bits in the codeword, identification of a minimum replacement region MSR for a number of MSRs associated with the codeword, a number of bits associated with a forwarded codeword in the memory medium, an error correction capability for the indication of the spare bit assignment, a number of memory dies corresponding to a channel among the plurality of channels, a number of MSR groups in the number of memory dies, or a bit indicating a change in the spare bit assignment, or any combination thereof.

5. The method of claim 1 , wherein replacing the bit field of the set in the second portion of the codeword with the spare bits further comprises: Based at least in part on receiving the second portion of the codeword, the bit field of the set is replaced with the spare bit using a combination of hierarchical logic gates configured based at least in part on the plurality of channels.

6. The method of claim 1 , wherein replacing the bit field of the set in the second portion of the codeword with the spare bits further comprises: Based at least in part on receiving the second portion of the codeword, the bit fields of the set are replaced with the spare bits using a combination of hierarchical logic gates configured at least in part based on a number of bit fields of the set corresponding to data bursts in the plurality of data bursts.

7. The method according to claim 1, wherein: The first portion of the codeword corresponds to an initial data burst of the plurality of data bursts, and the second portion of the codeword corresponds to one or more additional data bursts of the plurality of data bursts that are temporally subsequent to the initial data burst of the plurality of data bursts.

8. A memory system comprising: one or more processors; as well as one or more memories coupled to the one or more processors and comprising instructions that, when executed by the one or more processors, cause the memory system to: receiving a read command for accessing a codeword stored at a memory medium included in a memory device; receiving a first portion of the codeword stored at the memory medium based at least in part on the read command, the codeword comprising a set of bit fields indicating a plurality of bursts of data across a plurality of channels; identifying, based at least in part on receiving the first portion of the codeword, spare bits in the first portion of the codeword stored at the memory medium to replace a bit field of the set; determining the bit field of the set to be replaced by the spare bit based at least in part on identifying the spare bit; receiving a second portion of the codeword stored at the memory medium based at least in part on the read command based at least in part on determining the bit field of the set to be replaced by the spare bits; and The bit fields of the set in the second portion of the codeword are replaced with the spare bits concurrently with receiving the second portion of the codeword.

9. The memory system of claim 8, wherein when the instructions are executed by the one or more processors, further cause the memory system to: An error control operation for the codeword is performed based at least in part on replacing the set of bit fields in the second portion of the codeword with the spare bits.

10. The memory system of claim 8, wherein when the instructions are executed by the one or more processors, further cause the memory system to: accessing a memory array of a port manager, the memory array being configured to maintain an indication of a spare bit assignment for the bit field of the set of the codewords, wherein the bit field of the set in the second portion of the codeword to be replaced by the spare bit is determined based at least in part on accessing the memory array.

11. The memory system of claim 10, wherein a size of the memory array used to hold the indication of the spare bit assignment is based at least in part on: Identification of a channel among the plurality of channels, a number of spare bits in the codeword, an MSR identification of a number of minimum substitution regions (MSRs) associated with the codeword, a number of bits associated with a forwarded codeword in the memory medium, an error correction capability of the indication for the spare bit assignment, a number of memory dies corresponding to a channel among the plurality of channels, a number of MSR groups in the number of memory dies, or a bit indicating a change in the spare bit assignment, or any combination thereof.

12. The memory system of claim 8, wherein replacing the bit field of the set in the second portion of the codeword with the spare bit further comprises: Based at least in part on receiving the second portion of the codeword, the bit field of the set is replaced with the spare bit using a combination of hierarchical logic gates configured at least in part based on the plurality of channels.

13. The memory system of claim 8, wherein replacing the bit field of the set in the second portion of the codeword with the spare bit further comprises: Based at least in part on receiving the second portion of the codeword, the bit fields of the set are replaced with the spare bits using a combination of hierarchical logic gates configured at least in part based on a number of bit fields of the set corresponding to data bursts in the plurality of data bursts.

14. The memory system of claim 8, wherein: The first portion of the codeword corresponds to an initial data burst of the plurality of data bursts, and the second portion of the codeword corresponds to one or more additional data bursts of the plurality of data bursts that are temporally subsequent to the initial data burst of the plurality of data bursts.

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