Semiconductor package including a rounded corner layer
By introducing side trenches and corner trenches into semiconductor packaging, and combining them with capillary bottom filling technology to form a rounded corner layer, the cracking problem caused by the diffusion of the rounded corner layer in semiconductor packaging is solved, thereby improving product reliability and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-10-10
- Publication Date
- 2026-03-17
AI Technical Summary
When multiple semiconductor chips are contained within a single package, there are frequent defects such as cracks and reduced product reliability.
By introducing side trenches and corner trenches in semiconductor packaging, the diffusion of rounded corner layers at the sides and corners of semiconductor chips is reduced. A capillary bottom filling process is used to form rounded corner layers to fill the space between the substrate and the semiconductor chip.
It improves the reliability of semiconductor packaging products, reduces the occurrence of cracks, and enhances the overall stability of the packaging.
Smart Images
Figure CN112652606B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a semiconductor package, and more specifically, to a semiconductor package including a fillet layer. Background Technology
[0002] As electronic devices shrink in size and weight and their functionality diversifies, semiconductor packages used in these devices are also being manufactured to be smaller, lighter, and more versatile. This can be achieved by placing multiple semiconductor chips, for example, in a stacked structure within a single package.
[0003] However, when there are many semiconductor chips in a single package, there may be problems such as frequent defects due to cracks and reduced product reliability. Summary of the Invention
[0004] A semiconductor package includes a substrate having a first semiconductor substrate. A first protective layer at least partially covers the top side of the first semiconductor substrate. A first semiconductor chip is disposed on the first protective layer and a first rounded corner layer. The first rounded corner layer fills the space between the first protective layer and the first semiconductor chip. The substrate includes a first side surface extending in a first direction and a second side surface and a third side surface extending from both ends of the first side surface in a second direction intersecting the first direction. The substrate includes a first corner region comprising a first corner formed by the first side surface and the second side surface. A second corner region is formed by the first side surface and the third side surface. A side region is disposed between the first corner region and the second corner region. A first protective layer in the side region includes a first side trench overlapping the first semiconductor chip. A portion of the first rounded corner layer fills the first side trench.
[0005] A semiconductor package includes a substrate having a semiconductor substrate. A protective layer at least partially covers the top side of the semiconductor substrate. A semiconductor chip is disposed on the protective layer and a rounded corner layer. The rounded corner layer fills the space between the protective layer and the semiconductor chip. The substrate includes a first side surface extending in a first direction and a second side surface extending from one end of the first side surface in a second direction intersecting the first direction. The substrate includes: a first corner region including a corner formed by the first and second side surfaces; and a first side surface region spaced apart from the corner and including a portion of the first side surface. The protective layer in the first side surface region includes a first side trench overlapping the semiconductor chip. The protective layer in the first corner region includes a corner trench overlapping the semiconductor chip. The volume of the first side trench is larger than the volume of the corner trench. A portion of the rounded corner layer fills the first side trench and the corner trench.
[0006] A semiconductor package includes a substrate having a first semiconductor substrate. A first protective layer at least partially covers the top side of the first semiconductor substrate. A first through-hole penetrates the first semiconductor substrate and the first protective layer. A first semiconductor chip is disposed on the first protective layer. A first bump electrically connects the first through-hole and the first semiconductor chip. A first rounded corner layer at least partially surrounds the first bump between the first protective layer and the first semiconductor chip. The substrate includes a first side surface extending in a first direction and a second side surface extending from one end of the first side surface in a second direction intersecting the first direction. The substrate includes a corner region comprising a corner formed by the first side surface and the second side surface. A side region spaced apart from the corner includes a portion of the first side surface. A first protective layer in the side region includes a first side trench overlapping the first semiconductor chip. A portion of the first rounded corner layer fills the first side trench.
[0007] However, the inventive concept is not limited to the exemplary embodiments described herein. The above and other aspects of the inventive concept will become more apparent to those skilled in the art upon reference to the detailed description of the inventive concept given below. Attached Figure Description
[0008] The above and other aspects of the present invention will become more apparent to those skilled in the art from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:
[0009] Figure 1 This is a layout diagram illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.
[0010] Figure 2 It is along Figure 1 The sectional view taken by line AA.
[0011] Figure 3 It is shown Figure 1 The layout diagram of the rounded corner layer of the semiconductor package.
[0012] Figure 4 This is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.
[0013] Figure 5 This is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.
[0014] Figure 6 This is a layout diagram illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.
[0015] Figure 7 This is a layout diagram illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.
[0016] Figure 8 This is a layout diagram illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.
[0017] Figure 9 It is along Figure 8 The sectional view taken by line BB.
[0018] Figure 10 This is a layout diagram illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.
[0019] Figure 11 It is along Figure 10 The sectional view taken by the CC line.
[0020] Figure 12 It is shown Figure 10 The layout diagram of the side grooves and corner grooves.
[0021] Figure 13 This is a layout diagram illustrating a semiconductor package according to some exemplary embodiments of the present disclosure.
[0022] Figure 14 This is a layout diagram illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. Detailed Implementation
[0023] In the following text, reference will be made to Figures 1 to 3 This disclosure describes semiconductor packages according to some exemplary embodiments.
[0024] In this specification, although terms such as "first" and "second" are used to describe various elements or components, these elements or components are not necessarily limited to these terms. These terms are only used to distinguish individual elements or components from other elements or components. Therefore, within the scope of the inventive concept, the first element or component described below may be a second element or component.
[0025] Figure 1 This is a layout diagram illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. Figure 2 It is along Figure 1 The sectional view taken by line AA.
[0026] Reference Figure 1 and Figure 2 A semiconductor package according to some exemplary embodiments of the present disclosure includes a substrate 100, a first semiconductor chip 200, a first bump 410, a first rounded corner layer 420, and a molding member 600.
[0027] The substrate 100 may be, for example, a printed circuit board (PCB), a ceramic substrate, or an interposer. Alternatively, the substrate 100 may be a semiconductor chip including semiconductor elements. The substrate 100 may be used as a support substrate for semiconductor packaging. For example, as described in more detail below, a first semiconductor chip 200 may be stacked on the substrate 100.
[0028] like Figure 1 As shown, the substrate 100 may include multiple corner regions CR1 to CR4 and multiple side regions ER11 to ER14. Hereinafter, the substrate 100 will be described as including only four corner regions CR1 to CR4 and four side regions ER11 to ER14. However, this is merely an example, and the number of corner regions and the number of side regions may vary depending on the shape of the substrate 100.
[0029] For example, the substrate 100 may include a first side surface SS1 to a fourth side surface SS4. The first side surface SS1 may extend primarily in a first direction Y. The second side surface SS2 may extend primarily from one end of the first side surface SS1 in a second direction X intersecting the first direction Y. The third side surface SS3 may extend primarily from one end of the second side surface SS2 in the first direction Y and may face the first side surface SS1. The fourth side surface SS4 may extend primarily from the other end of the first side surface SS1 in the second direction X and may face the second side surface SS2. In some exemplary embodiments of this disclosure, the first side surface SS1 to the fourth side surface SS4 may be generally rectangular in shape.
[0030] The first corner region CR1 may include a first corner formed by the first side surface SS1 and the fourth side surface SS4. The second corner region CR2 may include a second corner formed by the first side surface SS1 and the second side surface SS2. The third corner region CR3 may include a third corner formed by the second side surface SS2 and the third side surface SS3. The fourth corner region CR4 may include a fourth corner formed by the third side surface SS3 and the fourth side surface SS4.
[0031] The first side surface region ER11 may be interposed between the first corner region CR1 and the second corner region CR2. The first side surface region ER11 may be spaced apart from the first corner of the first corner region CR1 and the second corner of the second corner region CR2. In some exemplary embodiments of this disclosure, the first side surface region ER11 may include a portion of the first side surface SS1.
[0032] The second side region ER12 can be interposed between the second corner region CR2 and the third corner region CR3. The second side region ER12 can be spaced apart from the second corner of the second corner region CR2 and the third corner of the third corner region CR3. In some exemplary embodiments of this disclosure, the second side region ER12 may include a portion of the second side surface SS2.
[0033] The third side surface region ER13 can be inserted between the third corner region CR3 and the fourth corner region CR4. The third side surface region ER13 can be spaced apart from the third corner of the third corner region CR3 and the fourth corner of the fourth corner region CR4. In some exemplary embodiments of this disclosure, the third side surface region ER13 may include a portion of the third side surface SS3.
[0034] The fourth side region ER14 can be interposed between the first corner region CR1 and the fourth corner region CR4. The fourth side region ER14 can be spaced apart from the first corner of the first corner region CR1 and the fourth corner of the fourth corner region CR4. In some exemplary embodiments of this disclosure, the fourth side region ER14 may include a portion of the fourth side surface SS4.
[0035] In some exemplary embodiments of this disclosure, the distance from the center CP of the substrate 100 to the side surface of the substrate 100 in the side regions ER11 to ER14 may be less than the distance from the center CP of the substrate 100 to the side surface of the substrate 100 in the corner regions CR1 to CR4. For example, the distance DS1 from the center CP of the substrate 100 to the first side surface SS1 in the first side region ER11 may be less than the distance DS2 from the center CP of the substrate 100 to the first side surface SS1 in the first corner region CR1.
[0036] like Figure 2 As shown, the substrate 100 may include a first semiconductor substrate 110 and a first protective layer 130.
[0037] The first semiconductor substrate 110 may be, for example, bulk silicon or SOI (silicon-on-insulator). Alternatively, the first semiconductor substrate 110 may be a silicon substrate or may include (but is not limited to including) other materials, such as silicon germanium, SGOI (silicon germanium-on-insulator), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide and / or gallium antimonide.
[0038] The first protective layer 130 may at least partially cover the top side of the first semiconductor substrate 110. In some exemplary embodiments of this disclosure, the first protective layer 130 may at least partially cover the rear side of the first semiconductor substrate 110. For example, a semiconductor element may be formed on the front side of the first semiconductor substrate 110, and the first protective layer 130 may be formed on the rear side of the first semiconductor substrate 110.
[0039] The first protective layer 130 may include a non-conductive film (NCF). For example, the first protective layer 130 may include (but is not limited to) an insulating polymer. The first protective layer 130 may be formed by, for example, a spin coating process or a spray coating process, but is not limited to these methods.
[0040] The first protective layer 130 may include side trenches T11 to T14. The side trenches T11 to T14 may be formed, for example, by etching a portion of the first protective layer 130.
[0041] Side grooves T11 to T14 can be formed in the side regions ER11 to ER14. For example, as Figure 1 As shown, a first side groove T11 can be formed in the first side region ER11, a second side groove T12 can be formed in the second side region ER12, a third side groove T13 can be formed in the third side region T3, and a fourth side groove T14 can be formed in the fourth side region ER14.
[0042] In some exemplary embodiments of this disclosure, the side trenches T11 to T14 may at least partially overlap with the first semiconductor chip 200, which is described in more detail below. Here, the term "overlap" means overlap in a direction perpendicular to the top side of the substrate 100. For example, from a planar perspective, the side trenches T11 to T14 may be at least partially covered by the first semiconductor chip 200.
[0043] Although the first to fourth side grooves T11 to T14 are shown to have the same dimensions as each other, this is provided only as an example. For example, the first side grooves T11 to the fourth side grooves T14 may have different lengths, widths, or depths. Therefore, the first to fourth side grooves T11 to T14 may have different volumes.
[0044] Furthermore, although the first to fourth side trenches T11 to T14 are shown as symmetrical about the center CP of the substrate 100, this is provided only as an example. For example, the arrangement and shape of the first to fourth side trenches T11 to T14 can be varied depending on the process of forming the first rounded corner layer 420.
[0045] In some exemplary embodiments of this disclosure, the first side groove T11 and the third side groove T13 may both extend primarily in the first direction Y, and the second side groove T12 and the fourth side groove T14 may both extend primarily in the second direction X.
[0046] In some exemplary embodiments of this disclosure, the depth of the side grooves T11 to T14 may be less than the thickness of the first protective layer 130. For example, as Figure 2 As shown, the depths T11 of the first side trench and T13 of the third side trench can be less than the thickness of the first protective layer 130. For example, the height of the bottom side of the first side trench T11 and the height of the bottom side of the third side trench T13 can be greater than the height of the top side of the first semiconductor substrate 110.
[0047] In some exemplary embodiments of this disclosure, the first protective layer 130 in the corner regions CR1 to CR4 may not include grooves. For example, the side grooves T11 to T14 may not extend into the corner regions CR1 to CR4.
[0048] In some exemplary embodiments of this disclosure, the substrate 100 may further include a plurality of first through-holes 140 penetrating the first semiconductor substrate 110. The first through-holes 140 may have a cylindrical shape.
[0049] In some exemplary embodiments of this disclosure, the first through-hole 140 can penetrate the first semiconductor substrate 110 and the first protective layer 130. For example, the bottom side of the first through-hole 140 can be exposed from the bottom side of the first semiconductor substrate 110, and the top side of the first through-hole 140 can be exposed from the top side of the first protective layer 130.
[0050] In some exemplary embodiments of this disclosure, the first through-hole 140 may not overlap with the side grooves T11 to T14. For example, the top side of the first through-hole 140 may not be exposed from the side grooves T11 to T14.
[0051] In some exemplary embodiments of this disclosure, the first through-hole 140 may include a barrier film formed on a columnar surface and a buried conductive layer filling the interior of the barrier film. The barrier film may include (but is not limited to) at least one of Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB. The buried conductive layer may include (but is not limited to) at least one Cu alloy (such as one of Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, and CuW), W, W alloy, Ni, Ru, and Co.
[0052] In some exemplary embodiments of this disclosure, an insulating film may be inserted between the first semiconductor substrate 110 and the first through-hole 140. The insulating film may include (but is not limited to) oxide films, nitride films, carbide films, polymers, or combinations thereof.
[0053] The first semiconductor chip 200 may be stacked on the substrate 100. The first semiconductor chip 200 may include semiconductor elements. For example, the first semiconductor chip 200 may include a second semiconductor substrate 210 and a first semiconductor element layer 220.
[0054] The second semiconductor substrate 210 may be, for example, bulk silicon or SOI. Alternatively, the first semiconductor substrate 110 may be a silicon substrate, or may include (but not be limited to including) other materials, such as silicon germanium, SGOI, indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide and / or gallium antimonide.
[0055] The first semiconductor element layer 220 may be formed on the second semiconductor substrate 210. In some exemplary embodiments of this disclosure, the first semiconductor element layer 220 may be formed on the surface of the second semiconductor substrate 210 facing the first protective layer 130. For example, the first semiconductor element layer 220 may be interposed between the first protective layer 130 and the second semiconductor substrate 210.
[0056] The first semiconductor element layer 220 may include multiple individual elements of various types and interlayer insulating films. These individual elements may include various microelectronic components, such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) such as CMOS transistors (Complementary Metal-Insulator-Semiconductor Transistors), system LSIs (Large-Scale Integration), flash memory, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), PRAM (Phase-Change Random Access Memory), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), image sensors such as CIS (CMOS Image Sensor), MEMS (Micro-Electro-Mechanical Systems), active components, passive components, etc.
[0057] Individual elements of the first semiconductor element layer 220 may be electrically connected to conductive regions formed in the first semiconductor substrate 110. The first semiconductor element layer 220 may include conductive wiring or conductors that electrically connect at least two of the plurality of individual elements or electrically connect the plurality of individual elements and the conductive regions of the first semiconductor substrate 110. Furthermore, an insulating film may be used to electrically isolate individual elements from other adjacent individual elements.
[0058] The first bump 410 can be inserted between the substrate 100 and the first semiconductor chip 200. The first bump 410 can electrically connect the substrate 100 and the first semiconductor chip 200. For example, the first bump 410 is inserted between the first protective layer 130 and the first semiconductor element layer 220, and can be connected to the first through-hole 140 and the first semiconductor element layer 220.
[0059] In some exemplary embodiments of this disclosure, a plurality of first connection pads 190 may be formed on the first protective layer 130. The first connection pads 190 may be formed on the top side of the first protective layer 130 and may be connected to the top side of the first through-hole 140. A first bump 410 may be formed on the first connection pads 190. Therefore, the first bump 410 may be electrically connected to the first through-hole 140. In some exemplary embodiments of this disclosure, the width of the first connection pads 190 may be greater than the width of the first through-hole 140.
[0060] In some exemplary embodiments of this disclosure, a plurality of second connection pads 290 may be formed on the first semiconductor chip 200. The second connection pads 290 are formed on the bottom side of the first semiconductor chip 200 and may be connected to the first bump 410. Therefore, the first bump 410 may be electrically connected to the first semiconductor chip 200.
[0061] The first rounded corner layer 420 can be inserted between the substrate 100 and the first semiconductor chip 200. Furthermore, the first rounded corner layer 420 can at least partially surround the first bump 410, the first connection pad 190, and the second connection pad 290. The first rounded corner layer 420 can be a bottom filler layer filling the space between the substrate 100 and the first semiconductor chip 200.
[0062] The first rounded corner layer 420 may include (but is not limited to) such as epoxy resin. In some exemplary embodiments of this disclosure, the first rounded corner layer 420 may include filler. The filler may include, for example, silica. For example, the filler may have a particle size of 0.1 μm to several μm or smaller, and may have an average particle size of about 0.3 μm to 1 μm. In some exemplary embodiments of this disclosure, the first rounded corner layer 420 may include about 55 wt% to 75 wt% of filler relative to 100 wt% of the first rounded corner layer 420.
[0063] The first rounded corner layer 420 can be formed, for example, by a capillary bottom filling process, but the inventive concept is not limited thereto.
[0064] A portion of the first rounded corner layer 420 may fill the side grooves T11 to T14. For example, as Figure 2As shown, the lower part of the first rounded corner layer 420 can be filled with the first side groove T11 and the third side groove T13.
[0065] The molding component 600 may be formed on the substrate 100. The molding component 600 may at least partially cover the first rounded corner layer 420 and the first semiconductor chip 200. The molding component 600 may include, for example, a polymer such as a resin. For example, the molding component 600 may include (but is not necessarily limited to including) EMC (epoxy molding compound).
[0066] In the following text, reference will be made to Figures 1 to 3 The effects of semiconductor packaging according to some exemplary embodiments of the present disclosure are described.
[0067] Figure 3 It is shown Figure 1 This is a layout diagram of the rounded corner layer of a semiconductor package. For ease of explanation, it uses... Figure 1 and Figure 2 Repeated portions of the content to be explained will be briefly described or omitted. To the extent that an element has been omitted, it may be assumed that the omitted element is at least partially similar to a corresponding element described in detail elsewhere in this disclosure.
[0068] Reference Figure 3 Semiconductor packages according to some exemplary embodiments of the present disclosure can improve product reliability by reducing the amount of the first rounded corner layer 420 protruding from the side surface (side surface) of the first semiconductor chip 200.
[0069] For example, a capillary bottom fill process can be used to form a first rounded corner layer 420 to fill the space between the substrate 100 and the first semiconductor chip 200. In this process, the first rounded corner layer 420 can extend radially from the center CP of the substrate 100. Since the corners of the first semiconductor chip 200 are spaced further from the center CP of the substrate 100 than the side surfaces (lateral surfaces) of the first semiconductor chip 200, the amount of the first rounded corner layer 420 protruding from the outer peripheral surface of the first semiconductor chip 200 can increase as it moves further away from the corners of the first semiconductor chip 200. As a result, the first rounded corner layer 420 that excessively protrudes from the side surfaces (lateral surfaces) of the first semiconductor chip 200 can be exposed from the molding member 600 and cause defects such as cracks, leading to a decrease in the product reliability of the semiconductor package.
[0070] However, according to some exemplary embodiments of this disclosure, the semiconductor package may use side trenches T11 to T14 to reduce the amount of the first rounded corner layer 420 protruding from the side surface (side surface) of the first semiconductor chip 200. For example, side trenches T11 to T14 may be used in the side region ( Figure 1In the first protective layer (ER11 to ER14) Figure 2 In 130), as a result, since the amount of the first rounded corner layer 420 diffused from the center CP of the substrate 100 toward the side surface (side surface) of the first semiconductor chip 200 is reduced, a semiconductor package with improved product reliability can be provided.
[0071] Furthermore, in some exemplary embodiments of this disclosure, in the corner area ( Figure 1 The first protective layer 130 in CR1 to CR4 may not include trenches. In this case, the amount of the first rounded corner layer 420 diffusing from the center CP of the substrate 100 toward the corner of the first semiconductor chip 200 can be maintained. As a result, the first rounded corner layer 420 can be formed to more densely fill the space between the substrate 100 and the first semiconductor chip 200.
[0072] Figure 4 This is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. For ease of illustration, [the following is used]. Figures 1 to 3 Repeated portions of the explanation will be briefly described or omitted. To the extent that an element has been omitted, it can be assumed that the omitted element is at least partially similar to a corresponding element described in detail elsewhere in this disclosure.
[0073] Reference Figure 4 In a semiconductor package according to some exemplary embodiments of the present disclosure, the depth of the side trenches T11 to T14 is greater than or equal to the thickness of the first protective layer 130.
[0074] For example, as shown in the figure, the depth of the first side groove T11 and the depth of the third side groove T13 can be greater than or equal to the thickness of the first protective layer 130.
[0075] In some exemplary embodiments of this disclosure, the height of the bottom side of the side trenches T11 to T14 may be lower than or equal to the height of the top side of the first semiconductor substrate 110. For example, the bottom side of the first side trench T11 and the bottom side of the third side trench T13 may expose a portion of the first semiconductor substrate 110.
[0076] Figure 5 This is a cross-sectional view illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. For ease of illustration, [the following is used]. Figures 1 to 3 Repeated portions of the explanation will be briefly described or omitted. To the extent that an element has been omitted, it can be assumed that the omitted element is at least partially similar to a corresponding element described in detail elsewhere in this disclosure.
[0077] Reference Figure 5According to some exemplary embodiments of this disclosure, the semiconductor package further includes a second semiconductor chip 300, a second bump 510, and a second rounded corner layer 520.
[0078] The second semiconductor chip 300 may be stacked on the first semiconductor chip 200. The second semiconductor chip 300 may include semiconductor elements. For example, the second semiconductor chip 300 may include a third semiconductor substrate 310 and a second semiconductor element layer 320.
[0079] The third semiconductor substrate 310 may be, for example, bulk silicon or SOI. Alternatively, the first semiconductor substrate 110 may be a silicon substrate, or may include (but not be limited to including) other materials, such as silicon germanium, SGOI, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide.
[0080] The second semiconductor element layer 320 may be formed on the third semiconductor substrate 310. In some exemplary embodiments of this disclosure, the second semiconductor element layer 320 may be formed on the surface of the third semiconductor substrate 310 facing the second protective layer 230, which will be described in more detail below. For example, the second semiconductor element layer 320 may be interposed between the second protective layer 230 and the third semiconductor substrate 310.
[0081] Similar to the first semiconductor element layer 220, the second semiconductor element layer 320 may include multiple individual elements of various types and interlayer insulating films.
[0082] In some exemplary embodiments of this disclosure, the first semiconductor chip 200 may further include a second protective layer 230. The second protective layer 230 may at least partially cover the top side of the second semiconductor substrate 210. In some embodiments of this disclosure, the second protective layer 230 may at least partially cover the rear side of the second semiconductor substrate 210. For example, a first semiconductor element layer 220 may be formed on the front side of the second semiconductor substrate 210, and the second protective layer 230 may be formed on the rear side of the second semiconductor substrate 210. The second protective layer 230 may include a non-conductive film (NCF).
[0083] In some exemplary embodiments of this disclosure, the second protective layer 230 may include a fifth side trench T15 and a sixth side trench T17. For example, the fifth side trench T15 and the sixth side trench T17 may be formed by etching a portion of the second protective layer 230.
[0084] Similar to the first to fourth side trenches T11 to T14, fifth and sixth side trenches T15 and T17 may be formed in the side regions of the first semiconductor chip 200. In some exemplary embodiments of this disclosure, the fifth and sixth side trenches T15 and T17 may at least partially overlap with the second semiconductor chip 300. Since the arrangement of the fifth and sixth side trenches T15 and T17 is similar to that of the first and third side trenches T11 and T13, their detailed description will not be provided below. To the extent that the description of the omitted elements is appropriate, it may be assumed that the omitted elements are at least partially similar to their corresponding elements described in detail elsewhere in this disclosure.
[0085] In some exemplary embodiments of this disclosure, the first semiconductor chip 200 may further include a plurality of second through-holes 240 penetrating the second semiconductor substrate 210. The second through-holes 240 may have a cylindrical shape.
[0086] In some exemplary embodiments of this disclosure, the second through-hole 240 may penetrate the first semiconductor element layer 220, the second semiconductor substrate 210, and the second protective layer 230. For example, the bottom side of the second through-hole 240 may be exposed from the bottom side of the first semiconductor element layer 220, and the top side of the second through-hole 240 may be exposed from the top side of the second protective layer 230.
[0087] In some exemplary embodiments of this disclosure, the second through-hole 240 may not overlap with the fifth and sixth side grooves T15 and T17. For example, the top side of the second through-hole 240 may not be exposed from the fifth and sixth side grooves T15 and T17.
[0088] The second bump 510 can be inserted between the first semiconductor chip 200 and the second semiconductor chip 300. The second bump 510 can electrically connect the first semiconductor chip 200 and the second semiconductor chip 300. For example, the second bump 510 is inserted between the second protective layer 230 and the second semiconductor element layer 320, and can be connected to the second through-hole 240 and the second semiconductor element layer 320.
[0089] In some exemplary embodiments of this disclosure, a plurality of third connection pads 295 may be formed on the second protective layer 230. The third connection pads 295 are formed on the top side of the second protective layer 230 and may be connected to the top side of the second through-hole 240. A second bump 510 may be formed on the third connection pads 295. Therefore, the second bump 510 may be electrically connected to the second through-hole 240. In some exemplary embodiments of this disclosure, the width of the third connection pads 295 may be greater than the width of the second through-hole 240.
[0090] In some exemplary embodiments of this disclosure, a plurality of fourth connection pads 390 may be formed on the second semiconductor chip 300. The fourth connection pads 390 are formed on the bottom side of the second semiconductor chip 300 and may be connected to the second bump 510. Therefore, the second bump 510 may be electrically connected to the second semiconductor chip 300.
[0091] The second rounded corner layer 520 can be inserted between the first semiconductor chip 200 and the second semiconductor chip 300. Furthermore, the second rounded corner layer 520 can at least partially surround the second bump 510, the third connection pad 295, and the fourth connection pad 390. The second rounded corner layer 520 can be a bottom filler layer filling the space between the first semiconductor chip 200 and the second semiconductor chip 300.
[0092] The second rounded corner layer 520 may include (but is not limited to) for example, epoxy resin. The second rounded corner layer 520 may be formed by, for example, a capillary bottom filling process, but is not limited to this.
[0093] A portion of the second rounded corner layer 520 may fill the fifth and sixth side trenches T15 and T17. For example, the lower portion of the second rounded corner layer 520 may fill the fifth and sixth side trenches T15 and T17. Therefore, semiconductor packages according to some exemplary embodiments of this disclosure can improve product reliability by reducing the amount of the second rounded corner layer 520 protruding from the side surface (side surface) of the first semiconductor chip 200 and / or the side surface (side surface) of the second semiconductor chip 300.
[0094] In some exemplary embodiments of this disclosure, the molded component 600 may at least partially cover the first rounded corner layer 420, the first semiconductor chip 200, the second rounded corner layer 520, and the second semiconductor chip 300.
[0095] Figure 6 This is a layout diagram illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. For ease of illustration, [the diagram is used]. Figures 1 to 3 Repeated portions of the explanation will be briefly described or omitted. To the extent that an element has been omitted, it can be assumed that the omitted element is at least partially similar to a corresponding element described in detail elsewhere in this disclosure.
[0096] Reference Figure 6 In a semiconductor package according to some exemplary embodiments of the present disclosure, each side trench T11 to T14 includes a plurality of sub-side trenches.
[0097] For example, the first side groove T11 may include a first sub-side groove T11a and a second sub-side groove T11b. The first sub-side groove T11a and the second sub-side groove T11b may be spaced apart from each other in the first side region ER11.
[0098] In some exemplary embodiments of this disclosure, the first sub-side groove T11a and the second sub-side groove T11b may both extend primarily in the first direction Y.
[0099] In some exemplary embodiments of this disclosure, the first sub-side groove T11a and the second sub-side groove T11b may be arranged along the second direction X. For example, the first sub-side groove T11a may be closer to the first side surface SS1 than the second sub-side groove T11b. Furthermore, for example, the second sub-side groove T11b may be closer to the first side surface SS1 than the first sub-side groove T11a.
[0100] Although the first sub-side groove T11a and the second sub-side groove T11b are shown to have the same dimensions, this is merely an example. For instance, the first sub-side groove T11a and the second sub-side groove T11b may have different lengths, widths, or depths from each other. Therefore, the first sub-side groove T11a and the second sub-side groove T11b may have different volumes from each other.
[0101] Figure 7 This is a layout diagram illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. For ease of illustration, [the diagram is used]. Figure 1 , 2 The repeated parts of the content explained in section 6 will be briefly described or omitted. To the extent that the omitted elements are described, it can be assumed that the omitted elements are at least partially similar to the corresponding elements described in detail elsewhere in this disclosure.
[0102] Reference Figure 7 In a semiconductor package according to some exemplary embodiments of the present disclosure, a first sub-side trench T11a and a second sub-side trench T11b are arranged along a first direction Y.
[0103] For example, the first sub-side groove T11a may be closer to the first corner region CR1 than the second sub-side groove T11b. Furthermore, for example, the second sub-side groove T11b may be closer to the second corner region CR2 than the first sub-side groove T11a.
[0104] Figure 8 This is a layout diagram illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. Figure 9 It is along Figure 8 A sectional view taken by line BB. For ease of illustration, use... Figure 1 , Figure 2 and Figure 6 Repeated portions of the explanation will be briefly described or omitted. To the extent that an element has been omitted, it can be assumed that the omitted element is at least partially similar to a corresponding element described in detail elsewhere in this disclosure.
[0105] Reference Figure 8 and Figure 9 In a semiconductor package according to some exemplary embodiments of the present disclosure, the lengths of the side trenches T11 to T14 increase as they move away from the center CP of the substrate 100.
[0106] For example, the length L1 of the first sub-side groove T11a can be greater than the length L2 of the second sub-side groove T11b. Here, length refers to the length of the long side in an object, including the short side and the long side longer than the short side. For example, as shown in the figure, the first sub-side groove T11a and the second sub-side groove T11b can extend primarily in the first direction Y. For example, both the first sub-side groove T11a and the second sub-side groove T11b can include a long side extending in the first direction Y. In this case, the length L1 of the first sub-side groove T11a and the length L2 of the second sub-side groove T11b refer to the length in the first direction Y.
[0107] Although only the width W1 of the first sub-side groove T11a and the width W2 of the second sub-side groove T11b are shown to be the same, this is merely an example. For instance, the width W1 of the first sub-side groove T11a may differ from the width W2 of the second sub-side groove T11b. Here, width refers to the length of the short side in an object, including both the short side and the long side longer than the short side. For example, both the first sub-side groove T11a and the second sub-side groove T11b may include a short side extending in the second direction X. In this case, the width W1 of the first sub-side groove T11a and the width W2 of the second sub-side groove T11b refer to their length in the second direction X.
[0108] exist Figure 9 In the example shown, although the depth D1 of the first sub-side groove T11a is only shown to be the same as the depth D2 of the second sub-side groove T11b, this is merely an example. For instance, the depth D1 of the first sub-side groove T11a may be different from the depth D2 of the second sub-side groove T11b.
[0109] Figure 10 This is a layout diagram illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. Figure 11 It is along Figure 10 The sectional view taken by the CC line. Figure 12 It is shown Figure 10 A layout diagram of the side grooves and corner grooves. For ease of explanation, use... Figures 1 to 9Repeated portions of the explanation will be briefly described or omitted. To the extent that an element has been omitted, it can be assumed that the omitted element is at least partially similar to a corresponding element described in detail elsewhere in this disclosure.
[0110] Reference Figures 10 to 12 In a semiconductor package according to some exemplary embodiments of the present disclosure, the first protective layer 130 includes corner trenches T21 to T24.
[0111] For example, corner trenches T21 to T24 can be formed by etching a portion of the first protective layer 130.
[0112] Corner grooves T21 to T24 can be formed in corner regions CR1 to CR4. For example, as... Figure 10 As shown, a first corner groove T21 can be formed in the first corner region CR1, a second corner groove T22 can be formed in the second corner region T22, a third corner groove T23 can be formed in the third corner region CR3, and a fourth corner groove T24 can be formed in the fourth corner region CR4.
[0113] In some exemplary embodiments of this disclosure, the corner trenches T21 to T24 may at least partially overlap with the first semiconductor chip 200. For example, from a planar perspective, the corner trenches T21 to T24 may be at least partially covered by the first semiconductor chip 200.
[0114] In some exemplary embodiments of this disclosure, the volume of corner trenches T21 to T24 may be smaller than the volume of side trenches T11 to T14. The volume of a trench may be defined, for example, as the product of the length, width, and depth of each trench.
[0115] For example, such as Figure 12 As shown, the length L1 of the first side groove T11 can be greater than the length L3 of the first corner groove T21. Alternatively, for example, the width W1 of the first side groove T11 can be greater than the width W3 of the first corner groove T21. Alternatively, for example, as... Figure 11 As shown, the depth D1 of the first side groove T11 can be greater than the depth D3 of the first corner groove T21.
[0116] The amount of the first rounded corner layer 420 protruding from the side surface (side surface) of the first semiconductor chip 200 can be controlled by the volume of the side trenches T11 to 14 formed in the side regions ER11 to ER14 and the volume of the corner trenches T21 to T24 formed in the corner regions CR1 to CR4.
[0117] Figure 13This is a layout diagram illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. For ease of illustration, [the diagram is used]. Figures 1 to 12 Repeated portions of the explanation will be briefly described or omitted. To the extent that an element has been omitted, it can be assumed that the omitted element is at least partially similar to a corresponding element described in detail elsewhere in this disclosure.
[0118] Reference Figure 13 In a semiconductor package according to some exemplary embodiments of the present disclosure, the side trenches T11 to T14 have a curved shape when viewed from a planar perspective.
[0119] In some exemplary embodiments of this disclosure, the side trenches T11 to T14 may all be formed with a concave surface facing away from the center CP of the substrate 100. For example, as shown in the figure, the first side trench T11 may be formed with a concave surface facing the right, the second side trench T12 may be formed with a concave surface facing the top, the third side trench T13 may be formed with a concave surface facing the left, and the fourth side trench T14 may be formed with a concave surface facing the bottom.
[0120] In some exemplary embodiments of this disclosure, similar to the side grooves T11 to T14, the corner grooves T21 to T24 may all have a concave surface facing away from the center CP of the substrate 100.
[0121] Figure 14 This is a layout diagram illustrating a semiconductor package according to some exemplary embodiments of the present disclosure. For ease of illustration, [the diagram is used]. Figures 1 to 12 Repeated portions of the explanation will be briefly described or omitted. To the extent that an element has been omitted, it can be assumed that the omitted element is at least partially similar to a corresponding element described in detail elsewhere in this disclosure.
[0122] Reference Figure 14 In a semiconductor package according to some exemplary embodiments of the present disclosure, the substrate 100 further includes fifth to twelfth side regions ER21 to ER28.
[0123] The fifth side area ER21 can be inserted between the first corner area CR1 and the first side area ER11. The sixth side area ER22 can be inserted between the second corner area CR2 and the first side area ER11. The seventh side area ER23 can be inserted between the second corner area CR2 and the second side area ER12. The eighth side area ER24 can be inserted between the third corner area CR3 and the second side area ER12. The ninth side area ER25 can be inserted between the third corner area CR3 and the third side area ER13. The tenth side area ER26 can be inserted between the fourth corner area CR4 and the third side area ER13. The eleventh side area ER27 can be inserted between the fourth corner area CR4 and the fourth side area ER14. The twelfth side area ER28 can be inserted between the first corner area CR1 and the fourth side area ER14.
[0124] In some exemplary embodiments of this disclosure, the distance from the center CP of the substrate 100 to the side surface of the substrate 100 in the fifth to twelfth side regions ER21 to ER28 may be greater than the distance to the side surface of the substrate 100 in the first to fourth side regions ER11 to ER14. Additionally, in some exemplary embodiments of this disclosure, the distance from the center CP of the substrate 100 to the side surface of the substrate 100 in the fifth to twelfth side regions ER21 to ER28 may be less than the distance from the center CP of the substrate 100 to the side surface of the substrate 100 in the corner regions CR1 to CR4.
[0125] In some exemplary embodiments of this disclosure, the seventh to fourteenth side grooves T31 to T38 may be formed in the fifth to twelfth side regions ER21 to ER28. For example, as shown, each of the seventh to fourteenth side grooves T31, T32, T33, T34, T35, T36, T37 and T38 may be formed in the fifth to twelfth side regions ER21 to ER28.
[0126] In some exemplary embodiments of this disclosure, the seventh to fourteenth side trenches T31 to T38 may at least partially overlap with the first semiconductor chip 200.
[0127] In some exemplary embodiments of this disclosure, the volume of each of the seventh to fourteenth side trenches T31 to T38 may be smaller than the volume of each of the first to fourth side trenches T11 to T14. In some exemplary embodiments of this disclosure, the volume of each of the seventh to fourteenth side trenches T31 to T38 may be larger than the volume of each of the first to fourth corner trenches T21 to T24. The volume of a trench may be defined, for example, as the product of the length, width, and depth of each trench. The amount of the first rounded corner layer 420 protruding from the side surface (side surface) of the first semiconductor chip 200 can be controlled accordingly.
[0128] Those skilled in the art will understand that many variations and modifications can be made to the exemplary embodiments of the present disclosure described herein without substantially departing from the principles of the present disclosure.
[0129] This application claims priority to Korean Patent Application No. 10-2019-0125852, filed on October 11, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.
Claims
1. A semiconductor package comprising: a base substrate including a first semiconductor substrate, a first protective layer at least partially covering a top side of the first semiconductor substrate, and a first through-hole penetrating both the first semiconductor substrate and the first protective layer; a first connection pad on a top side of the first protective layer, the first connection pad connected to the first through-hole; a first semiconductor chip disposed on and electrically connected to the first connection pad; and a first round corner layer at least partially filling a space between the first protective layer and the first semiconductor chip, wherein the base substrate further includes a first side surface extending in a first direction, and a second side surface and a third side surface respectively extending from end portions of the first side surface in a second direction intersecting the first direction, wherein the base substrate further includes a first corner region including a first corner formed by the first side surface and the second side surface, a second corner region formed by the first side surface and the third side surface, and a side surface region between the first corner region and the second corner region, wherein the first protective layer in the side surface region includes a first side surface trench at least partially overlapping the first semiconductor chip, and wherein a first portion of the first round corner layer at least partially fills the first side surface trench, a depth of the first side surface trench is smaller than a thickness of a portion of the first protective layer not formed with the first side surface trench, a height of a bottom side of the first side surface trench is higher than a height of the top side of the first semiconductor substrate.
2. The semiconductor package of claim 1, wherein, the first semiconductor chip includes a second semiconductor substrate and a semiconductor element layer disposed between the second semiconductor substrate and the first round corner layer.
3. The semiconductor package of claim 1, further comprising: a second semiconductor chip disposed on the first semiconductor chip; and a second round corner layer at least partially filling a space between the first semiconductor chip and the second semiconductor chip. the first semiconductor chip includes a second semiconductor substrate and a second protective layer at least partially covering a top side of the second semiconductor substrate, 4. The semiconductor package of claim 3, wherein, wherein the second protective layer includes a second side surface trench at least partially overlapping the second semiconductor chip, and wherein a portion of the second round corner layer at least partially fills the second side surface trench. the first side surface trench extends in the first direction.
5. The semiconductor package of claim 1, wherein, the first protective layer in the first corner region and the second corner region is omitted of a trench.
6. The semiconductor package of claim 1, wherein, the first side surface trench includes a first sub-side surface trench and a second sub-side surface trench spaced apart from each other in the side surface region.
7. The semiconductor package of claim 1, wherein, 8. The semiconductor package of claim 7, wherein the first sub-side surface trench is closer to the first side surface than the second sub-side surface trench. a length of the first sub-side surface trench in the first direction is longer than a length of the second sub-side surface trench in the first direction.
9. The semiconductor package of claim 8, wherein, the first side surface trench forms a concave surface facing away from a center of the base substrate.
10. The semiconductor package of claim 1, wherein, 11. A semiconductor package comprising: a base substrate including a semiconductor substrate, a protective layer at least partially covering a top side of the semiconductor substrate, and a through-hole penetrating both the semiconductor substrate and the protective layer; a connection pad on a top side of the protective layer, the connection pad connected to the through-hole; a semiconductor chip disposed on the connection pad and electrically connected to the connection pad; and a round corner layer at least partially filling a space between the protective layer and the semiconductor chip, wherein the base substrate includes a first side surface extending in a first direction, and a second side surface extending from one end of the first side surface in a second direction intersecting the first direction, wherein the base substrate further includes a first corner region including a corner formed by the first side surface and the second side surface, and a first side region spaced apart from the corner and including a portion of the first side surface, wherein the protective layer in the first side region includes a first side trench at least partially overlapping the semiconductor chip, wherein the protective layer in the first corner region includes a corner trench at least partially overlapping the semiconductor chip, wherein a volume of the first side trench is greater than a volume of the corner trench, and wherein a portion of the round corner layer at least partially fills the first side trench and the corner trench, a depth of the first side trench is less than a thickness of a portion of the protective layer not formed with the first side trench, a height of a bottom side of the first side trench is higher than a height of the top side of the semiconductor substrate.
12. The semiconductor package of claim 11, wherein, a distance from a center of the base substrate to the first side surface in the first side region is less than a distance from the center of the base substrate to the first side surface in the first corner region.
13. The semiconductor package of claim 11, wherein, a depth of the first side trench is greater than a depth of the corner trench.
14. The semiconductor package of claim 11, wherein, the base substrate further includes a second side region spaced apart from the corner and including a portion of the second side surface, wherein the protective layer in the second side region includes a second side trench at least partially overlapping the semiconductor chip, and wherein a volume of the second side trench is greater than the volume of the corner trench.
15. The semiconductor package of claim 11, wherein, the base substrate further includes a second side region disposed between the first corner region and the first side region, wherein the protective layer in the second side region includes a second side trench at least partially overlapping the semiconductor chip, and wherein a volume of the second side trench is less than the volume of the first side trench and greater than the volume of the corner trench.
16. A semiconductor package, comprising: a base substrate including a first semiconductor substrate, a first protective layer at least partially covering a top side of the first semiconductor substrate, and a first through-hole penetrating both the first semiconductor substrate and the first protective layer; a first connection pad on a top side of the first protective layer, the first connection pad connected to the first through-hole; a semiconductor chip disposed on the first connection pad and electrically connected to the first connection pad; and a round corner layer at least partially filling a space between the first protective layer and the semiconductor chip, wherein the base substrate includes a first side surface extending in a first direction, and a second side surface extending from one end of the first side surface in a second direction intersecting the first direction, wherein the base substrate further includes a first corner region including a corner formed by the first side surface and the second side surface, and a first side region spaced apart from the corner and including a portion of the first side surface, wherein the protective layer in the first side region includes a first side trench at least partially overlapping the semiconductor chip, wherein the protective layer in the first corner region includes a corner trench at least partially overlapping the semiconductor chip, wherein a volume of the first side trench is greater than a volume of the corner trench, and wherein a portion of the round corner layer at least partially fills the first side trench and the corner trench, a depth of the first side trench is less than a thickness of a portion of the protective layer not formed with the first side trench, a height of a bottom side of the first side trench is higher than a height of the top side of the semiconductor substrate. a distance from a center of the base substrate to the first side surface in the first side region is less than a distance from the center of the base substrate to the first side surface in the first corner region. a depth of the first side trench is greater than a depth of the corner trench. the base substrate further includes a second side region spaced apart from the corner and including a portion of the second side surface, wherein the protective layer in the second side region includes a second side trench at least partially overlapping the semiconductor chip, and wherein a volume of the second side trench is greater than the volume of the corner trench. the base substrate further includes a second side region disposed between the first corner region and the first side region, wherein the protective layer in the second side region includes a second side trench at least partially overlapping the semiconductor chip, and wherein a volume of the second side trench is less than the volume of the first side trench and greater than the volume of the corner trench. a first semiconductor chip disposed on and electrically connected to the first connection pad; a first bump electrically connecting the first through-hole and the first semiconductor chip; and a first corner rounding layer at least partially surrounding the first bump, wherein the base substrate further includes a first side surface extending in a first direction and a second side surface extending from an end of the first side surface in a second direction that intersects the first direction, wherein the base substrate further includes a corner region including a corner formed by the first side surface and the second side surface and a side region spaced apart from the corner and including a portion of the first side surface, wherein the first protective layer in the side region includes a first side trench at least partially overlapping the first semiconductor chip, and wherein a portion of the first corner rounding layer at least partially fills the first side trench. a depth of the first side trench is less than a thickness of a portion of the first protective layer that is not formed with the first side trench, a height of a bottom side of the first side trench is higher than a height of the top side of the first semiconductor substrate.
17. The semiconductor package of claim 16, further comprising: a second connection pad disposed on a bottom side of the first semiconductor chip, wherein the first bump connects the first connection pad to the second connection pad. the first semiconductor chip includes a second semiconductor substrate and a semiconductor element layer disposed between the second semiconductor substrate and the first corner rounding layer, and 18. The semiconductor package of claim 17, wherein, wherein the second connection pad connects the semiconductor element layer to the first bump.
19. The semiconductor package of claim 16, further comprising: a second semiconductor chip on the first semiconductor chip; a second bump connecting the first semiconductor chip to the second semiconductor chip; and a second corner rounding layer at least partially surrounding the second bump between the first semiconductor chip and the second semiconductor chip. the first semiconductor chip includes a second semiconductor substrate, a second protective layer at least partially covering a top side of the second semiconductor substrate, and a second through-hole penetrating the second semiconductor substrate and the second protective layer, wherein the second protective layer includes a second side trench at least partially overlapping the second semiconductor chip, and 20. The semiconductor package of claim 19, wherein, wherein a portion of the second corner rounding layer at least partially fills the second side trench.
Citation Information
Patent Citations
Beam deflector, holographic display device having the same and method of driving the beam deflector
KR1020190125852A
Semiconductor package
CN107507825A