Non-volatile memory device

Abstract

A nonvolatile memory device is provided. The nonvolatile memory device includes a substrate, a first molding structure disposed on the substrate and including a plurality of first gate electrodes, a second molding structure disposed on the first molding structure and including a plurality of second gate electrodes, and a plurality of channel structures crossing the plurality of first gate electrodes and the plurality of second gate electrodes by penetrating the first molding structure and the second molding structure, wherein the first molding structure includes a first stack and a second stack spaced apart from each other, and the second molding structure includes a third stack stacked on the first stack, a fourth stack stacked on the second stack, and a first connection part connecting the third stack and the fourth stack.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0125849, filed on October 11, 2019, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a non-volatile memory device and a method of manufacturing the non-volatile memory device, and more specifically, to a non-volatile memory device including a word line dicing region and a method of manufacturing the non-volatile memory device. Background Technology

[0003] Semiconductor memory devices are broadly classified into volatile memory devices or non-volatile memory devices.

[0004] To meet consumer demand for improved performance and / or lower prices, the integration density of non-volatile memory devices has increased. The integration density of two-dimensional (2D) or planar memory devices is determined by the area occupied by each memory cell. Recently, three-dimensional (3D) memory devices in which the memory cells are arranged vertically have been developed. Summary of the Invention

[0005] Embodiments of this disclosure provide a non-volatile memory device with improved product reliability.

[0006] Embodiments of this disclosure provide a method for manufacturing a non-volatile memory device with improved product reliability.

[0007] However, the embodiments of this disclosure are not limited to those set forth herein. The above and other embodiments of this disclosure will become more apparent to those skilled in the art from the following detailed description of the disclosure.

[0008] According to embodiments of this disclosure, a non-volatile memory device is provided, the non-volatile memory device comprising: a substrate; a first molding structure located on the substrate and including a plurality of first gate electrodes; a second molding structure located on the first molding structure and including a plurality of second gate electrodes; and a plurality of channel structures intersecting the plurality of first gate electrodes and the plurality of second gate electrodes by penetrating the first molding structure and the second molding structure, wherein the first molding structure includes first stacked members and second stacked members spaced apart from each other, and the second molding structure includes a third stacked member stacked on the first stacked member, a fourth stacked member stacked on the second stacked member, and a first connecting portion connecting the third stacked member and the fourth stacked member.

[0009] According to the foregoing and other embodiments of this disclosure, a non-volatile memory device is provided, the non-volatile memory device comprising: a substrate; a first molding structure located on the substrate and including a plurality of first gate electrodes; a second molding structure located on the first molding structure and including a plurality of second gate electrodes; a plurality of channel structures intersecting the plurality of first gate electrodes and the plurality of second gate electrodes by penetrating the first molding structure and the second molding structure; and bit lines extending in a first direction and connected to the plurality of channel structures, wherein the first molding structure includes a first trench extending in a second direction intersecting the first direction to completely cut through the first molding structure, the second molding structure includes a plurality of second trenches exposing a portion of the first trench, and the plurality of second trenches are spaced apart from each other and arranged in the second direction.

[0010] According to embodiments of this disclosure, a non-volatile memory device is provided, the non-volatile memory device comprising: a substrate; a first molding structure located on the substrate and including a plurality of first gate electrodes; a second molding structure located on the first molding structure and including a plurality of second gate electrodes; a plurality of channel structures intersecting the plurality of first gate electrodes and the plurality of second gate electrodes by penetrating the first molding structure and the second molding structure; bit lines extending in a first direction and connected to the plurality of channel structures; and a first word line trench extending in a second direction intersecting the first direction, the first word line trench cutting through the plurality of first gate electrodes. The first molding structure includes a gate electrode and the plurality of second gate electrodes; a second word line trench extending in a second direction, the second word line trench cutting through the plurality of first gate electrodes and the plurality of second gate electrodes; and a first trench extending in a second direction between the first word line trench and the second word line trench, the first trench cutting through the plurality of first gate electrodes, wherein the first molding structure includes a first stack and a second stack separated by the first trench, and the second molding structure includes a third stack stacked on the first stack, a fourth stack stacked on the second stack, and a plurality of first connecting portions connecting the third stack and the fourth stack.

[0011] Other features and embodiments will become apparent from the accompanying detailed embodiments, drawings and claims. Attached Figure Description

[0012] The above and other embodiments and features of this disclosure will become more apparent from the detailed description of the embodiments with reference to the accompanying drawings.

[0013] Figure 1 This is a circuit diagram of a non-volatile memory device according to some embodiments of the present disclosure.

[0014] Figure 2 This is a layout diagram of a non-volatile memory device according to some embodiments of the present disclosure.

[0015] Figure 3 It is along Figure 2 The sectional view taken by line AA.

[0016] Figure 4 It is shown Figure 3 An enlarged sectional view of part R1.

[0017] Figure 5 It is along Figure 2 The sectional view taken by line BB.

[0018] Figure 6 It is along Figure 2 The sectional view taken by the CC line.

[0019] Figure 7 It is along Figure 2 The sectional view taken by line DD.

[0020] Figure 8 It is shown Figures 2 to 7 Partially exploded perspective view of the first molded structure MS1 and the second molded structure MS2.

[0021] Figure 9 This is a layout diagram of a non-volatile memory device according to some embodiments of the present disclosure.

[0022] Figure 10 It is along Figure 9 The sectional view taken by the line EE.

[0023] Figure 11 yes Figure 9 A partial exploded perspective view of a non-volatile memory device.

[0024] Figure 12 This is a partial exploded perspective view of a non-volatile memory device according to some embodiments of the present disclosure.

[0025] Figure 13 This is a partial exploded perspective view of a non-volatile memory device according to some embodiments of the present disclosure.

[0026] Figure 14 This is a partial exploded perspective view of a non-volatile memory device according to some embodiments of the present disclosure.

[0027] Figure 15 This is a partial exploded perspective view of a non-volatile memory device according to some embodiments of the present disclosure.

[0028] Figure 16 This is a cross-sectional view of a non-volatile memory device according to some embodiments of the present disclosure.

[0029] Figure 17 It is shown Figure 16 An enlarged sectional view of part R2.

[0030] Figures 18 to 26 The steps of a method for manufacturing a non-volatile memory device according to some embodiments of the present disclosure are shown.

[0031] Figures 27 to 30 The steps of a method for manufacturing a non-volatile memory device according to some embodiments of the present disclosure are shown. Detailed Implementation

[0032] The following will refer to Figures 1 to 17 This disclosure describes a non-volatile memory device according to some embodiments thereof.

[0033] Figure 1 This is a circuit diagram of a non-volatile memory device according to some embodiments of the present disclosure.

[0034] The memory cell array of a non-volatile memory device according to some embodiments of the present disclosure may include a common source line (CSL), multiple bit lines (BL), and / or multiple cell strings (CSTR).

[0035] Bit lines BL can be arranged in two dimensions. For example, bit lines BL can be spaced apart from each other and can extend in the first direction X. Multiple cell strings CSTR can be connected in parallel to each bit line BL. Cell strings CSTR can be connected together to the common source line CSL. That is, cell strings CSTR can be positioned between the common source line CSL and the bit line BL.

[0036] In some embodiments, the common source line (CSL) can be arranged in two dimensions. For example, the common source lines (CSL) can be spaced apart from each other and can extend in a second direction Y. The same voltage can be applied to the common source lines (CSL), or different voltages can be applied to the common source lines (CSL), so that the common source lines (CSL) can be controlled individually.

[0037] Each cell string (CSTR) may include a ground select transistor (GST), a string select transistor (SST), and multiple memory cell transistors (MCTs). The ground select transistor (GST) is connected to one of the common-source lines (CSL), the string select transistor (SST) is connected to one of the bit lines (BL), and the multiple memory cell transistors (MCTs) are disposed between the ground select transistor (GST) and the string select transistor (SST). Each memory cell transistor (MCT) may include a data storage element. The ground select transistor (GST), the string select transistor (SST), and the memory cell transistor (MCT) may be connected in series.

[0038] The common-source line CSL can be connected to the source of the ground-select transistor GST. Furthermore, the ground-select line GSL, multiple word lines (WL11 to WL1n and WL21 to WL2n), and the serial-select line SSL can be positioned between the common-source line CSL and the bit line BL. The ground-select line GSL can be used as the gate electrode of the ground-select transistor GST, and the word lines (WL11 to WL1n and WL21 to WL2n) can be used as the gate electrode of the memory cell transistor MCT, and the serial-select line SSL can be used as the gate electrode of the serial-select transistor SST.

[0039] Figure 2 This is a layout diagram of a non-volatile memory device according to some embodiments of the present disclosure. Figure 3 It is along Figure 2 The sectional view taken by line AA. Figure 4 It is shown Figure 3 An enlarged sectional view of part R1. Figure 5 It is along Figure 2 The sectional view taken by line BB. Figure 6 It is along Figure 2 The sectional view taken by the CC line. Figure 7 It is along Figure 2 The sectional view is taken from line DD. For convenience, in Figure 2 Bit line BL is not shown.

[0040] Reference Figures 2 to 7 A non-volatile memory device according to some embodiments of the present disclosure includes a substrate 100, a first molding structure MS1, a second molding structure MS2, a plurality of channel structures CS and / or a plurality of bit lines BL.

[0041] The substrate 100 may include a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate, or may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0042] The substrate 100 may include a cell array region CAR and a contact region CTR.

[0043] A memory cell array comprising multiple memory cells can be formed in a cell array region (CAR). The memory cell array may include multiple memory cells, multiple word lines electrically connected to the multiple memory cells, and bit lines BL electrically connected to the multiple memory cells. For example, a first molding structure MS1, a second molding structure MS2, a channel structure CS, and bit lines BL can be formed in the cell array region (CAR).

[0044] The contact region (CTR) can be located near the cell array region (CAR). Multiple gate electrodes (GSL, WL11 to WL1n, WL21 to WL2n, and SSL) can be stacked in a stepped manner. Furthermore, memory cell contacts (not shown) connected to the gate electrodes (GSL, WL11 to WL1n, WL21 to WL2n, and SSL) can be formed in the contact region (CTR). For example, the memory cell contacts can be formed to connect to the gate electrodes (GSL, WL11 to WL1n, WL21 to WL2n, and SSL) via a first interlayer insulating film 140 and a second interlayer insulating film 165.

[0045] A first molded structure MS1 may be formed on a substrate 100. The first molded structure MS1 may include a plurality of first gate electrodes (GSL and WL11 to WL1n) and a plurality of first insulating patterns 110, and the first gate electrodes (GSL and WL11 to WL1n) and the first insulating patterns 110 may be alternately stacked on the substrate 100. For example, the first gate electrodes (GSL and WL11 to WL1n) and the first insulating patterns 110 may be in the shape of layers extending in a first direction X and a second direction Y. The first gate electrodes (GSL and WL11 to WL1n) and the first insulating patterns 110 may be alternately stacked in a third direction Z that intersects (i.e., is perpendicular to) the top surface of the substrate 100.

[0046] In some embodiments, the first gate electrode (GSL and WL11 to WL1n) may include a ground select line GSL and a plurality of first word lines WL11 to WL1n, and the ground select line GSL and the first word lines WL11 to WL1n are sequentially stacked on the substrate 100. In some embodiments, the ground select line GSL may be the lowermost gate electrode among the first gate electrodes (GSL and WL11 to WL1n).

[0047] A second molding structure MS2 can be formed on a first molding structure MS1. The second molding structure MS2 may include a plurality of second gate electrodes (WL21 to WL2n and SSL) and a plurality of second insulating patterns 112, and the second gate electrodes (WL21 to WL2n and SSL) and the second insulating patterns 112 are alternately stacked on the first molding structure MS1. For example, the second gate electrodes (WL21 to WL2n and SSL) and the second insulating patterns 112 may be in the shape of layers extending in a first direction X and a second direction Y. The second gate electrodes (WL21 to WL2n and SSL) and the second insulating patterns 112 may be alternately stacked in a third direction Z.

[0048] In some embodiments, the second gate electrode (WL21 to WL2n and SSL) may include multiple second word lines WL21 to WL2n and a serial select line SSL, and the second word lines WL21 to WL2n and the serial select line SSL are sequentially stacked on the first molded structure MS1. In some embodiments, the serial select line SSL may be the uppermost gate electrode among the second gate electrodes (WL21 to WL2n and SSL).

[0049] The first gate electrode (GSL and WL11 to WL1n) and the second gate electrode (WL21 to WL2n and SSL) may comprise a conductive material. For example, the first gate electrode (GSL and WL11 to WL1n) and the second gate electrode (WL21 to WL2n and SSL) may comprise a metal such as tungsten (W), cobalt (Co) or nickel (Ni) or a semiconductor material such as silicon, but this disclosure is not limited thereto.

[0050] The first insulating pattern 110 and the second insulating pattern 112 may include insulating material. For example, the first insulating pattern 110 and the second insulating pattern 112 may include silicon oxide, but this disclosure is not limited thereto.

[0051] The channel structure CS can penetrate the first molded structure MS1 and the second molded structure MS2. The channel structure CS can extend in a direction intersecting the gate electrodes (GSL, WL11 to WL1n, WL21 to WL2n and SSL). For example, the channel structure CS can be in the form of a column extending in the third direction Z. Each of the channel structures CS can include a semiconductor pattern 130 and an information storage film 132.

[0052] Semiconductor pattern 130 may penetrate the first molding structure MS1 and the second molding structure MS2. For example, semiconductor pattern 130 may extend in the third direction Z. Semiconductor pattern 130 is shown as cup-shaped, but this disclosure is not limited thereto. For example, semiconductor pattern 130 may be various shapes such as cylindrical, rectangular, or non-hollow cylindrical shapes.

[0053] Semiconductor pattern 130 may include semiconductor materials, such as monocrystalline silicon, polycrystalline silicon, organic semiconductor materials or carbon nanostructures, but this disclosure is not limited thereto.

[0054] The information storage film 132 can be disposed between the semiconductor pattern 130 and the gate electrodes (GSL, WL11 to WL1n, WL21 to WL2n and SSL). For example, the information storage film 132 can extend along the side of the semiconductor pattern 130.

[0055] The information storage film 132 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a high-k material whose dielectric constant is greater than that of silicon oxide. The high-k material may include at least one of, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0056] In some embodiments, the information storage film 132 may include multiple films. For example, such as Figure 4 As shown, the information storage film 132 may include a tunnel insulating film 132a, a charge storage film 132b, and a barrier insulating film 132c sequentially stacked on the semiconductor pattern 130.

[0057] The tunnel insulating film 132a may include, for example, silicon oxide and a high-k material (such as aluminum oxide (Al2O3) or hafnium oxide (HfO2)) with a dielectric constant greater than that of silicon oxide. The charge storage film 132b may include, for example, silicon nitride. The barrier insulating film 132c may include, for example, silicon oxide and a high-k material (such as aluminum oxide (Al2O3) or hafnium oxide (HfO2)) with a dielectric constant greater than that of silicon oxide.

[0058] In some embodiments, each of the channel structures CS may further include a first fill pattern 134. The first fill pattern 134 may be formed to fill the interior of the cup-shaped semiconductor pattern 130. For example, the semiconductor pattern 130 may extend along the side and bottom surfaces of the first fill pattern 134. The first fill pattern 134 may include, for example, silicon oxide, but this disclosure is not limited thereto.

[0059] In some embodiments, each of the channel structures CS may further include a channel pad (or solder pad) 136. The channel pad 136 may be formed to be attached to the upper portion of the semiconductor pattern 130. For example, the channel pad 136 may be formed in a first interlayer insulating film 140 formed on a first molding structure MS1 and a second molding structure MS2.

[0060] Figure 3 The diagram shows a channel pad 136 formed on the top surface of a semiconductor pattern 130, but the disclosure is not limited thereto. Optionally, the upper portion of the semiconductor pattern 130 may be formed to extend along the side of the channel pad 136. The channel pad 136 may comprise, for example, polysilicon doped with impurities, but the disclosure is not limited thereto.

[0061] In some embodiments, the channel structure CS can be arranged in a zigzag pattern. For example, as Figure 2 As shown, the channel structure CS can be arranged in an alternating manner in the first direction X and the second direction Y. Because the channel structure CS is arranged in a zigzag pattern, the integration density of the non-volatile memory device according to some embodiments of this disclosure can be further improved.

[0062] In some embodiments, due to the characteristics of the etching used to form the channel structure CS, the width of the channel structure CS penetrating the first molding structure MS1 can be reduced by approaching the top surface of the substrate 100. Furthermore, due to the characteristics of the etching used to form the channel structure CS, the width of the channel structure CS penetrating the second molding structure MS2 can be reduced by approaching the top surface of the substrate 100.

[0063] In some embodiments, since the etching for penetrating the first molding structure MS1 and the etching for penetrating the second molding structure MS2 are performed separately, the width of the portion of the channel structure CS penetrating the uppermost surface of the first molding structure MS1 can be greater than the width of the portion of the channel structure CS penetrating the lowermost surface of the second molding structure MS2.

[0064] Optionally, in some embodiments, the width of the channel structure CS can gradually decrease from the uppermost surface of the second molding structure MS2 to the lowermost surface of the first molding structure MS1. For example, etching for penetrating the first molding structure MS1 and etching for penetrating the second molding structure MS2 can be performed simultaneously.

[0065] Bit lines BL can be spaced apart from each other and can extend parallel to each other. For example, bit lines BL can extend in a first direction X. In some embodiments, bit lines BL can be formed on a second molding structure MS2.

[0066] The bit line BL can be connected to the channel structure CS. For example, as... Figure 3 and Figure 5 As shown, bit line BL can be connected to channel structure CS via bit line contact 170. Bit line contact 170 can electrically connect bit line BL and channel structure CS via, for example, a second interlayer insulating film 165.

[0067] The first molded structure MS1 and the second molded structure MS2 can be cut by the first word line groove WLC1 and the second word line groove WLC2. The first word line groove WLC1 and the second word line groove WLC2 can extend in a direction intersecting the bit line BL. For example, the first word line groove WLC1 can extend in the second direction Y to cut the first molded structure MS1 and the second molded structure MS2, and the second word line groove WLC2 can be spaced apart from the first word line groove WLC1 in the first direction X and can extend in the second direction Y to cut the first molded structure MS1 and the second molded structure MS2.

[0068] Therefore, the first gate electrode (GSL and WL11 to WL1n) and the second gate electrode (WL21 to WL2n and SSL) can be cut by the first word line trench WLC1 and the second word line trench WLC2.

[0069] The portions of the first molded structure MS1 and the second molded structure MS2 that are cut by the first word line groove WLC1 and the second word line groove WLC2 can form a single block region BLK. For example, as Figure 2 As shown, the block region BLK can be defined between the first word line groove WLC1 and the second word line groove WLC2.

[0070] In some embodiments, the first word line groove WLC1 can completely cut the first molding structure MS1 and the second molding structure MS2, and the second word line groove WLC2 can completely cut the first molding structure MS1 and the second molding structure MS2.

[0071] In some embodiments, such as Figure 2 As shown, the first word line groove WLC1 and the second word line groove WLC2 can be formed in the cell array region CAR and the contact region CTR and span across the cell array region CAR and the contact region CTR.

[0072] In some embodiments, such as Figure 3 and Figure 5 As shown, due to the etching characteristics used to form the first word line trench WLC1 and the second word line trench WLC2, the width of the portion of the first word line trench WLC1 and the second word line trench WLC2 that cuts the first molding structure MS1 can be reduced by approaching the top surface of the substrate 100, and the width of the portion of the first word line trench WLC1 and the second word line trench WLC2 that cuts the second molding structure MS2 can be reduced by approaching the top surface of the substrate 100.

[0073] In some embodiments, since the etching for cutting the first molded structure MS1 and the etching for cutting the second molded structure MS2 are performed separately, the width of the portion of the first word line groove WLC1 and the second word line groove WLC2 that cuts the uppermost surface of the first molded structure MS1 can be greater than the width of the portion of the first word line groove WLC1 and the second word line groove WLC2 that cuts the lowermost surface of the second molded structure MS2.

[0074] The first molded structure MS1 can also be cut by the first groove BC11 and the second groove BC12. The first groove BC11 and the second groove BC12 can be placed between the first word line groove WLC1 and the second word line groove WLC2. That is, the first groove BC11 and the second groove BC12 can cut the first molded structure MS1 in the block area BLK.

[0075] The first trench BC11 and the second trench BC12 can define multiple blocks (I, II, and III) within the block region BLK. For example, as shown... Figure 2As shown, the first trench BC11 can define the first block I and the second block II, and the second trench BC12 can define the second block II and the third block III.

[0076] In some embodiments, the first trench BC11 and the second trench BC12 may be formed in the cell array region CAR and the contact region CTR and span across the cell array region CAR and the contact region CTR.

[0077] In some embodiments, such as Figure 3 and Figure 5 As shown, due to the characteristics of the etching used to form the first trench BC11 and the second trench BC12, the width of the first trench BC11 and the second trench BC12 can be reduced by approaching the top surface of the substrate 100.

[0078] Optionally, in some embodiments, the first groove BC11 and the second groove BC12 can completely cut through the first molded structure MS1, as will be discussed later. Figure 8 This will be described in detail.

[0079] The second molded structure MS2 can also be cut by the third groove BC21 and the fourth groove BC22. The third groove BC21 and the fourth groove BC22 can be placed between the first word line groove WLC1 and the second word line groove WLC2. That is, the third groove BC21 and the fourth groove BC22 can cut the second molded structure MS2 in the block area BLK.

[0080] In some embodiments, such as Figure 2 As shown, the third trench BC21 and the fourth trench BC22 can be formed in the cell array region CAR and the contact region CTR and span across the cell array region CAR and the contact region CTR.

[0081] In some embodiments, such as Figure 3 and Figure 5 As shown, due to the characteristics of the etching used to form the third trench BC21 and the fourth trench BC22, the width of the third trench BC21 and the fourth trench BC22 can be reduced by being close to the top surface of the substrate 100.

[0082] In some embodiments, since the etching for cutting the first molded structure MS1 and the etching for cutting the second molded structure MS2 are performed separately, the width of the uppermost portion of the first trench BC11 and the second trench BC12 can be greater than the width of the lowermost portion of the third trench BC21 and the fourth trench BC22.

[0083] In some embodiments, the third groove BC21 and the fourth groove BC22 may only partially cut the second molded structure MS2, as will be discussed later. Figure 8 This will be described in detail.

[0084] In some embodiments, the spacer 154 and the second filling pattern 152 may be formed in the first letter groove WLC1 and the second letter groove WLC2, as well as the first groove BC11, the second groove BC12, the third groove BC21 and the fourth groove BC22.

[0085] The spacer 154 may extend along the contours of the first letter groove WLC1 and the second letter groove WLC2, as well as the contours of the first groove BC11, the second groove BC12, the third groove BC21, and the fourth groove BC22. The second filling pattern 152 may be formed to fill the portions of the first letter groove WLC1 and the second letter groove WLC2, as well as the portions of the first groove BC11, the second groove BC12, the third groove BC21, and the fourth groove BC22 that are not filled by the spacer 154.

[0086] In some embodiments, the second filling pattern 152 filling the first word line trench WLC1 and the second word line trench WLC2 can be configured as a common source line of a non-volatile memory device according to some embodiments of the present disclosure. Figure 1 (CSL). For example, the second fill pattern 152 may include a conductive material. The second fill pattern 152, which fills the first word line trench WLC1 and the second word line trench WLC2, may be connected to the substrate 100 through the first molding structure MS1 and the second molding structure MS2.

[0087] In some embodiments, the second fill pattern 152 may be connected to the impurity region 105 in the substrate 100. The impurity region 105 may extend, for example, in a second direction Y.

[0088] The spacer 154 may include an insulating material. Therefore, the second fill pattern 152 can be electrically decoupled from the first gate electrode (GSL and WL11 to WL1n) and the second gate electrode (WL21 to WL2n and SSL).

[0089] In some embodiments, the second filling pattern 152 filling the first trench BC11, the second trench BC12, the third trench BC21, and the fourth trench BC22 may not be connected to the substrate 100. For example, as Figure 3 and Figure 5 As shown, spacer 154 can extend along the bottom of the first groove BC11 and the second groove BC12.

[0090] However, this disclosure is not limited thereto. Optionally, only insulating material may be formed in the first alphanumeric groove WLC1, the second alphanumeric groove WLC2, and the first groove BC11, the second groove BC12, the third groove BC21, and the fourth groove BC22.

[0091] In some embodiments, the second molding structure MS2 may further include a first cutting line CL1 and a second cutting line CL2. The first cutting line CL1 and the second cutting line CL2 may be positioned between the first letter groove WLC1 and the second letter groove WLC2.

[0092] The first cutting line CL1 and the second cutting line CL2 can cut the string selection line SSL. For example, as... Figure 3 As shown, a first cutting line CL1 may extend in the second direction Y to cut the string selection line SSL. A second cutting line CL2 may be spaced apart from the first cutting line CL1 in the first direction X, and may extend in the second direction Y to cut the string selection line SSL.

[0093] In some embodiments, such as Figure 2 As shown, the first cutting line CL1 can be placed between the first block I and the second block II, and the second cutting line CL2 can be placed between the second block II and the third block III. Therefore, the channel structure CS in the first block I and the channel structure CS in the second block II can be selectively selected and controlled by the portion of the string selection line SSL cut by the first cutting line CL1. Similarly, the channel structure CS in the second block II and the channel structure CS in the third block III can be selectively selected and controlled by the portion of the string selection line SSL cut by the second cutting line CL2.

[0094] The following will refer to Figures 2 to 8 The present disclosure describes a first molding structure MS1 and a second molding structure SM2 for a non-volatile memory device according to some embodiments thereof.

[0095] Figure 8 It is shown Figures 2 to 7 Partially exploded perspective view of the first molded structure MS1 and the second molded structure MS2. For convenience, Figure 8 Only shown Figure 2 The cell array region CAR, and in Figure 8 The second filling pattern 152 and the spacer 154 are not shown in the diagram.

[0096] Reference Figure 8 The first molded structure MS1 may include a first groove BC11 and a second groove BC12 that cut the first molded structure MS1.

[0097] In some embodiments, the first groove BC11 and the second groove BC12 can completely cut the first molded structure MS1. For example, the first groove BC11 can extend in the second direction Y to completely cut the first molded structure MS1, and the second groove BC12 can be spaced apart from the first groove BC11 in the first direction X and can extend in the second direction Y to completely cut the first molded structure MS1.

[0098] Therefore, the first molded structure MS1 between the first letter groove WLC1 and the second letter groove WLC2 may further include a plurality of first stack members S11, second stack members S12, and third stack members S13 spaced apart from each other by a first groove BC11 and a second groove BC12. For example, the first stack members S11 and the second stack members S12 can be separated from each other by the first groove BC11, and the second stack members S12 and the third stack members S13 can be separated from each other by the second groove BC12.

[0099] The second molded structure MS2 may include multiple third grooves BC21 and multiple fourth grooves BC22, and the third grooves BC21 and fourth grooves BC22 cut the second molded structure MS2.

[0100] In some embodiments, the third groove BC21 and the fourth groove BC22 may partially cut the second molded structure MS2. For example, the third groove BC21 may be spaced apart from each other and may be arranged in the second direction Y, and the fourth groove BC22 may be spaced apart from the third groove BC21 in the first direction X, may be spaced apart from each other, and may be arranged in the second direction Y.

[0101] Therefore, the second molding structure MS2 between the first word line groove WLC1 and the second word line groove WLC2 may include a plurality of fourth stack members S21, fifth stack members S22, and sixth stack members S23 that are at least partially connected by a plurality of first connecting portions CP1 and a plurality of second connecting portions CP2. For example, the fourth stack members S21 and the fifth stack members S22 may be connected to each other by the first connecting portions CP1, and the fifth stack members S22 and the sixth stack members S23 may be connected to each other by the second connecting portions CP2.

[0102] The fourth stack S21 can be stacked on the first stack S11, the fifth stack S22 can be stacked on the second stack S12, and the sixth stack S23 can be stacked on the third stack S13.

[0103] The first connecting parts CP1 can be spaced apart from each other and can be arranged in the second direction Y. That is, the third groove BC21 and the first connecting parts CP1 can be arranged alternately in the second direction Y. The second connecting parts CP2 can be spaced apart from each other and can be arranged in the second direction Y. That is, the fourth groove BC22 and the second connecting parts CP2 can be arranged alternately in the second direction Y.

[0104] Therefore, the bottom surface of the first connecting portion CP1 and the bottom surface of the second connecting portion CP2 can be spaced apart from the top surface of the substrate 100. In some embodiments, the third trench BC21 and the first connecting portion CP1 can be stacked with the first trench BC11 in the third direction Z, and the fourth trench BC22 and the second connecting portion CP2 can be stacked with the second trench BC12 in the third direction Z.

[0105] The third trench BC21 can expose a portion of the first trench BC11, and the fourth trench BC22 can expose a portion of the second trench BC12. That is, the third trench BC21 can be connected to the first trench BC11, and the fourth trench BC22 can be connected to the second trench BC12.

[0106] In some embodiments, a first cutting line CL1 may be formed in a first connecting portion CP1, and a second cutting line CL2 may be formed in a second connecting portion CP2. In some embodiments, the width of the first cutting line CL1 may be less than the width of the third groove BC21, and the width of the second cutting line CL2 may be less than the width of the fourth groove BC22. As used herein, the term "width" refers to the width in the first direction X. Therefore, portions of the string select line SSL may be provided in the first connecting portion CP1 and the second connecting portion CP2.

[0107] As the integration density of non-volatile memory devices according to some embodiments of this disclosure increases, the number of channel structures CS disposed in each molded structure cut by word line trenches (e.g., in a block region BLK) increases. In order to individually control a considerable number of channel structures CS in the block region BLK, each molded structure cut by word line trenches can be further cut into multiple blocks (e.g., a first block I, a second block II, and a third block III).

[0108] However, as the aspect ratio (AR) of the non-volatile memory device according to some embodiments of this disclosure increases, tilting phenomena may occur, such as the first block I, the second block II, and the third block III collapsing or tilting in one direction. To reduce or prevent this, the block region BLK can be patterned into an "H" shape, allowing the formation of connecting portions that support and connect the first block I, the second block II, and the third block III. However, these connecting portions may degrade the dispersion at the lower part of the molded structure and thus potentially reduce product reliability. For example, during the patterning of the block region BLK into an "H" shape, the etchant may not be uniformly injected into the lower part of the molded structure spaced apart from the connecting portions, as well as into the lower part of the molded structure adjacent to the connecting portions.

[0109] In a non-volatile memory device according to some embodiments of the present disclosure, the first molding structure MS1 can be completely cut by the first trench BC11 and the second trench BC12. That is, since no connecting portion is formed in the first molding structure MS1, the dispersion at the lower part of the first molding structure MS1 can be improved.

[0110] Furthermore, the second molding structure MS2 disposed on the first molding structure MS1 may include a first connecting portion CP1 and a second connecting portion CP2 that support and connect the first block I, the second block II, and the third block III. Therefore, tilting of the first block I, the second block II, and the third block III can be reduced or prevented, and a non-volatile memory device with improved product reliability can be provided.

[0111] Figure 9 This is a layout diagram of a non-volatile memory device according to some embodiments of the present disclosure. Figure 10 It is along Figure 9 The sectional view taken by the line EE. Figure 11 yes Figure 9 A partially exploded perspective view of a non-volatile memory device. The following discussion will focus primarily on... Figures 1 to 8 To describe the differences in non-volatile memory devices Figure 9 Non-volatile memory devices.

[0112] Reference Figures 9 to 11 The first letter groove WLC1 and the second letter groove WLC2 can cut a portion of the second molded structure MS2.

[0113] Therefore, the second molding structure MS2 may include a seventh stack S24, which is at least partially connected to the fourth stack S21 via a plurality of third connecting portions CP3. Furthermore, the second molding structure MS2 may include an eighth stack S25, which is at least partially connected to the sixth stack S23 via a plurality of fourth connecting portions CP4. For example, the fourth stack S21 and the seventh stack S24 may be connected via the third connecting portions CP3, and the sixth stack S23 and the eighth stack S25 may be connected via the fourth connecting portions CP4.

[0114] The third connecting parts CP3 can be spaced apart from each other and can be arranged in the second direction Y. That is, the first letter groove WLC1 and the third connecting part CP3 can be arranged alternately in the second direction Y. The fourth connecting parts CP4 can be spaced apart from each other and can be arranged in the second direction Y. That is, the second letter groove WLC2 and the fourth connecting part CP4 can be arranged alternately in the second direction Y.

[0115] In some embodiments, the bottom surfaces of the third connecting portion CP3 and the fourth connecting portion CP4 may be spaced apart from the top surface of the substrate 100.

[0116] In some embodiments, the second molding structure MS2 may further include a third dicing line CL3 and a fourth dicing line CL4. The third dicing line CL3 and the fourth dicing line CL4 may dicing the second gate electrodes (WL21 to WL2n and SSL). For example, as... Figure 10 As shown, the third cleaving line CL3 and the fourth cleaving line CL4 can cut the second gate electrode (WL21 to WL2n and SSL).

[0117] In some embodiments, a third cleaving line CL3 may be formed in a third connecting portion CP3, and a fourth cleaving line CL4 may be formed in a fourth connecting portion CP4. In some embodiments, the width of the third cleaving line CL3 may be smaller than the width of the first word line trench WLC1, and the width of the fourth cleaving line CL4 may be smaller than the width of the second word line trench WLC2. As used herein, the term "width" refers to the width in the first direction X. Therefore, portions of the second gate electrodes (WL21 to WL2n and SSL) may be disposed in the third connecting portion CP3 and the fourth connecting portion CP4.

[0118] Figure 12 This is a partially exploded perspective view of a non-volatile memory device according to some embodiments of the present disclosure. The focus hereafter will be primarily on... Figures 1 to 8 To describe the differences in non-volatile memory devices Figure 12 Non-volatile memory devices.

[0119] Reference Figure 12The non-volatile memory device according to some embodiments of the present disclosure also includes a third molding structure MS3.

[0120] A third molding structure MS3 may be formed on a second molding structure MS2. The third molding structure MS3 may include a plurality of third gate electrodes (WL31 to WL3n and SSL) and a plurality of third insulating patterns 114 alternately stacked on the second molding structure MS2. A plurality of channel structures CS may penetrate the first molding structure MS1, the second molding structure MS2 and the third molding structure MS3.

[0121] In some embodiments, the third gate electrode (WL31 to WL3n and SSL) may include multiple third word lines WL31 to WL3n and a serial select line SSL, and the third word lines WL31 to WL3n and the serial select line SSL are sequentially stacked on the second molded structure MS2. In some embodiments, the serial select line SSL may be the uppermost gate electrode among the third gate electrodes (WL31 to WL3n and SSL).

[0122] In some embodiments, the second molding structure MS2 may not include the serial select line SSL. For example, the second molding structure MS2 may include a plurality of second gate electrodes sequentially stacked on the first molding structure MS1, specifically, a plurality of second word lines WL21 to WL2n. In some embodiments, the second molding structure MS2 may not include the first cut line CL1 and the second cut line CL2.

[0123] In some embodiments, the first letter groove WLC1 and the second letter groove WLC2 can completely cut the third molding structure MS3.

[0124] The third molding structure MS3 can also be cut by the fifth groove BC31 and the sixth groove BC32. The fifth groove BC31 and the sixth groove BC32 can be placed between the first letter groove WLC1 and the second letter groove WLC2.

[0125] In some embodiments, the third molding structure MS3 may include a plurality of fifth grooves BC31 and a plurality of sixth grooves BC32, and the fifth grooves BC31 and sixth grooves BC32 cut the third molding structure MS3. The fifth grooves BC31 and sixth grooves BC32 may partially cut the third molding structure MS3.

[0126] Therefore, the third molding structure MS3 between the first word line groove WLC1 and the second word line groove WLC2 may further include a plurality of ninth stack members S31, tenth stack members S32, and eleventh stack members S33, which are at least partially connected by a plurality of fifth connecting portions CP5 and a plurality of sixth connecting portions CP6. For example, the ninth stack members S31 and the tenth stack members S32 may be connected by the fifth connecting portion CP5, and the tenth stack members S32 and the eleventh stack members S33 may be connected by the sixth connecting portion CP6.

[0127] The fifth connecting part CP5 may be superimposed on the first connecting part CP1 in the third direction Z, and the sixth connecting part CP6 may be superimposed on the second connecting part CP2 in the third direction Z. However, this disclosure is not limited thereto. Optionally, the fifth connecting part CP5 may not be superimposed on the first connecting part CP1 in the third direction Z, and the sixth connecting part CP6 may not be superimposed on the second connecting part CP2 in the third direction Z.

[0128] In some embodiments, the third molding structure MS3 may further include a fifth cutting line CL5 and a sixth cutting line CL6. The fifth cutting line CL5 and the sixth cutting line CL6 may be positioned between the first word line groove WLC1 and the second word line groove WLC2. The fifth cutting line CL5 and the sixth cutting line CL6 may extend in the second direction Y to cut the string select line SSL.

[0129] In some embodiments, a fifth cutting line CL5 may be formed in a fifth connecting portion CP5, and a sixth cutting line CL6 may be formed in a sixth connecting portion CP6.

[0130] Figure 13 This is a partially exploded perspective view of a non-volatile memory device according to some embodiments of the present disclosure. The focus hereafter will be primarily on... Figures 1 to 12 To describe the differences in non-volatile memory devices Figure 13 Non-volatile memory devices.

[0131] Reference Figure 13 The third groove BC21 and the fourth groove BC22 completely cut the second molded structure MS2.

[0132] For example, the third groove BC21 can extend in the second direction Y to completely cut the second molded structure MS2, and the fourth groove BC22 can be spaced apart from the third groove BC21 in the first direction X and can extend in the second direction Y to completely cut the second molded structure MS2.

[0133] Therefore, the fourth stack S21 and the fifth stack S22 can be separated from each other by the third trench BC21, and the fifth stack S22 and the sixth stack S23 can be separated from each other by the fourth trench BC22.

[0134] Figure 14 This is a partially exploded perspective view of a non-volatile memory device according to some embodiments of the present disclosure. The focus hereafter will be primarily on... Figures 1 to 12 To describe the differences in non-volatile memory devices Figure 14 Non-volatile memory devices.

[0135] Reference Figure 14 The fifth groove BC31 and the sixth groove BC32 completely cut the third molded structure MS3.

[0136] For example, the fifth groove BC31 can extend in the second direction Y to completely cut the third molding structure MS3, and the sixth groove BC32 can be spaced apart from the fifth groove BC31 in the first direction X and can extend in the second direction Y to completely cut the third molding structure MS3.

[0137] Therefore, the ninth stack S31 and the tenth stack S32 can be separated from each other by the fifth trench BC31, and the tenth stack S32 and the eleventh stack S33 can be separated from each other by the sixth trench BC32.

[0138] Figure 15 This is a partially exploded perspective view of a non-volatile memory device according to some embodiments of the present disclosure. The focus hereafter will be primarily on... Figures 1 to 8 To describe the differences in non-volatile memory devices Figure 15 Non-volatile memory devices. Specifically, Figure 15 It is along Figure 2 The sectional view taken by line AA.

[0139] Reference Figure 15 The non-volatile memory device according to some embodiments of the present disclosure also includes a substrate 10 and a peripheral circuit structure PS.

[0140] The substrate 10 may include a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate, or may include an SOI substrate or a GOI substrate.

[0141] The peripheral circuit structure PS can be formed on the substrate 10. The peripheral circuit structure PS can form the peripheral circuitry controlling the operation of each memory cell. For example, the peripheral circuit structure PS may include a row decoder, a column decoder, a page buffer, and control circuitry. For example, as... Figure 15As shown, the peripheral circuit structure PS may include peripheral circuit elements PT and wiring structure PW.

[0142] In some embodiments, the peripheral circuit element PT may include a transistor. For example, the peripheral circuit element PT may include a peripheral circuit gate electrode 12, a peripheral circuit gate insulating film 14, a gate spacer 16, and / or a source / drain region 18.

[0143] In some embodiments, the peripheral circuit element PT may be a high-voltage transistor, but this disclosure is not limited thereto. Examples of the peripheral circuit element PT may include various active elements such as transistors and various passive elements such as capacitors, resistors, or inductors.

[0144] In some embodiments, a third interlayer insulating film 20 may be formed on a substrate 10. The third interlayer insulating film 20 may be formed to cover peripheral circuit elements PT on the substrate 10. The third interlayer insulating film 20 is shown as a single layer, but this disclosure is not limited thereto. Optionally, the third interlayer insulating film 20 may also be a multilayer film consisting of multiple stacked insulating films. The third interlayer insulating film 20 may include, for example, silicon oxide, but this disclosure is not limited thereto.

[0145] The wiring structure PW may include peripheral circuit wiring 22 and peripheral circuit contacts 24. The peripheral circuit wiring 22 and peripheral circuit contacts 24 may be formed in, for example, a third interlayer insulating film 20. The peripheral circuit wiring 22 may be connected to the peripheral circuit element PT via the peripheral circuit contacts 24.

[0146] Peripheral circuit wiring 22 may include, for example, metal (e.g., copper (Cu) or aluminum (Al)), but this disclosure is not limited thereto. Peripheral circuit contacts 24 may include, for example, silicon (e.g., polysilicon) or metal (e.g., W or Cu), but this disclosure is not limited thereto.

[0147] Figure 16 This is a cross-sectional view of a non-volatile memory device according to some embodiments of the present disclosure. Figure 17 It is shown Figure 16 A magnified sectional view of part R2. The following text will focus primarily on... Figures 1 to 15 To describe the differences in non-volatile memory devices Figure 16 and Figure 17 Non-volatile memory devices. Specifically, Figure 16 It is along Figure 2 The sectional view taken by line AA.

[0148] Reference Figure 16 and Figure 17 The non-volatile memory device according to some embodiments of the present disclosure also includes a source structure 200.

[0149] The source structure 200 may be formed on the substrate 100. In some embodiments, the source structure 200 may be disposed between the substrate 100 and the first molded structure MS1. The source structure 200 may include a conductive material. For example, the source structure 200 may include a metal or polysilicon doped with impurities.

[0150] In some embodiments, the channel structure CS can be connected to the substrate 100 via the source structure 200. For example, as Figure 17 As shown, the substrate 100 may include a substrate trench ST. The lower portion of the channel structure CS may fill the substrate trench ST. In some embodiments, the information storage film 132 of the channel structure CS may extend along the sides and bottom of the substrate trench ST.

[0151] In some embodiments, the source structure 200 may be formed as a semiconductor pattern 130 connected to the channel structure CS. For example, the source structure 200 may be connected to the semiconductor pattern 130 via a portion of the information storage film 132.

[0152] In some embodiments, the portion of the source structure 200 adjacent to the semiconductor pattern 130 may protrude toward the information storage film 132. For example, due to the characteristics of the etching used to remove a portion of the information storage film 132 to form the source structure 200, the length of the source structure 200 extending in the third direction Z may be larger in the region adjacent to the semiconductor pattern 130.

[0153] The following will refer to Figures 1 to 30 Methods for manufacturing a non-volatile memory device according to some embodiments of the present disclosure are described.

[0154] Figures 18 to 26 Steps of a method for manufacturing a non-volatile memory device according to some embodiments of the present disclosure are illustrated. For convenience, the steps already referred to above will be omitted or at least simplified. Figures 1 to 8 The description describes the features of a method for manufacturing a non-volatile memory device according to some embodiments of the present disclosure. Specifically, Figures 18 to 26 This is a partial exploded perspective view illustrating a method of manufacturing a non-volatile memory device according to some embodiments of the present disclosure.

[0155] Reference Figure 18 This forms multiple first sacrificial patterns 210 and multiple first insulating patterns 110.

[0156] The first sacrificial pattern 210 and the first insulating pattern 110 may be stacked alternately in the third direction Z. The first sacrificial pattern 210 may include a material that is etch-selective relative to the first insulating pattern 110. For example, if the first insulating pattern 110 includes silicon oxide, the first sacrificial pattern 210 may include polysilicon.

[0157] Reference Figure 19 Multiple sacrificial channels 220 are formed that penetrate the first sacrificial pattern 210 and the first insulating pattern 110.

[0158] For example, a plurality of first vias can be formed extending in the third direction Z through the first sacrificial pattern 210 and the first insulating pattern 110. Subsequently, a plurality of sacrificial channels 220 can be formed to fill the first vias. The sacrificial channels 220 may include a material having etch selectivity relative to the first sacrificial pattern 210 and the first insulating pattern 110.

[0159] Reference Figure 20 The first word line groove WLC1 and the second word line groove WLC2, as well as the first groove BC11 and the second groove BC12, are formed to cut the first sacrificial pattern 210 and the first insulating pattern 110.

[0160] The first letter groove WLC1 and the second letter groove WLC2, as well as the first groove BC11 and the second groove BC12, can cut the first sacrificial pattern 210 and the first insulating pattern 110. In some embodiments, the first letter groove WLC1 and the second letter groove WLC2, as well as the first groove BC11 and the second groove BC12, can extend in the second direction Y to completely cut the first sacrificial pattern 210 and the first insulating pattern 110.

[0161] Therefore, the first sacrificial pattern 210 and the first insulating pattern 110 can form a first stack S11, a second stack S12 and a third stack S13 separated from each other by the first trench BC11 and the second trench BC12.

[0162] Reference Figure 21 Multiple sacrificial fill patterns 230 are formed in the first letter groove WLC1, the second letter groove WLC2, the first groove BC11, and the second groove BC12.

[0163] The sacrificial fill pattern 230 can be formed to fill the first word line trench WLC1 and the second word line trench WLC2, as well as the first trench BC11 and the second trench BC12. The sacrificial fill pattern 230 may include a material that has etch selectivity relative to the first sacrificial pattern 210 and the first insulating pattern 110.

[0164] Reference Figure 22Multiple second sacrificial patterns 212 and multiple second insulating patterns 112 are formed on the first sacrificial pattern 210 and the first insulating pattern 110.

[0165] The second sacrificial pattern 212 and the second insulating pattern 112 may be stacked alternately in the third direction Z. The second sacrificial pattern 212 may include a material that has etch selectivity relative to the second insulating pattern 112. For example, if the second insulating pattern 112 includes silicon oxide, the second sacrificial pattern 212 may include polysilicon.

[0166] In some embodiments, the second sacrificial pattern 212 may include the same material as the first sacrificial pattern 210, and the second insulating pattern 112 may include the same material as the first insulating pattern 110.

[0167] In some embodiments, a first cutting line CL1 and a second cutting line CL2 may be further formed.

[0168] The first cutting line CL1 and the second cutting line CL2 can cut the uppermost second sacrificial pattern 212 among the second sacrificial patterns 212. For example, the first cutting line CL1 can extend in the second direction Y to cut the uppermost second sacrificial pattern 212, and the second cutting line CL2 can be spaced apart from the first cutting line CL1 in the first direction X and can extend in the second direction Y to cut the uppermost second sacrificial pattern 212.

[0169] In some embodiments, the first cutting line CL1 may be formed to overlap with the first groove BC11 in the third direction Z, and the second cutting line CL2 may be formed to overlap with the second groove BC12 in the third direction Z.

[0170] Reference Figure 23 Multiple channel structures CS are formed that penetrate the first sacrificial pattern 210, the first insulating pattern 110, the second sacrificial pattern 212, and the second insulating pattern 112.

[0171] For example, a plurality of second through-holes can be formed extending in the third direction Z through the second sacrificial pattern 212 and the second insulating pattern 112. The second through-holes can be formed such that... Figure 21 The sacrificial channel 220 is exposed. Thereafter, the sacrificial channel 220 exposed by the second through-hole can be removed. Thereafter, a channel structure CS filling the first and second through-holes can be formed.

[0172] The first and second through holes are described above as being formed separately, but this disclosure is not limited thereto. In some embodiments, the formation of the sacrificial channel 220 may not be performed. Obviously, through holes penetrating the first sacrificial pattern 210, the first insulating pattern 110, the second sacrificial pattern 212, and the second insulating pattern 112 may also be formed.

[0173] Reference Figure 24 The first letter groove WLC1 and the second letter groove WLC2, a plurality of third grooves BC21 and a plurality of fourth grooves BC22 are formed to cut the second sacrificial pattern 212 and the second insulating pattern 112.

[0174] In some embodiments, the first word line groove WLC1 and the second word line groove WLC2 may extend in the second direction Y to completely cut the second sacrificial pattern 212 and the second insulating pattern 112.

[0175] In some embodiments, the third trench BC21 and the fourth trench BC22 may partially cut the second sacrificial pattern 212 and the second insulating pattern 112. For example, the third trench BC21 may be spaced apart from each other and may be arranged in the second direction Y, and the fourth trench BC22 may be spaced apart from the third trench BC21 in the first direction X and spaced apart from each other, and may be arranged in the second direction Y.

[0176] Therefore, the second sacrificial pattern 212 and the second insulating pattern 112 can form a fourth stack S21, a fifth stack S22 and a sixth stack S23 that are at least partially connected by the first connecting portion CP1 and the second connecting portion CP2.

[0177] In some embodiments, the third groove BC21 and the first connecting portion CP1 may be superimposed on the first groove BC11 in the third direction Z, and the fourth groove BC22 and the second connecting portion CP2 may be superimposed on the second groove BC12 in the third direction Z. Therefore, the first cutting line CL1 may be formed in the first connecting portion CP1, and the second cutting line CL2 may be formed in the second connecting portion CP2.

[0178] Reference Figure 25 Remove the sacrificial fill pattern 230.

[0179] As a result, the first word line groove WLC1 and the second word line groove WLC2, the first groove BC11 and the second groove BC12 can partially expose the first sacrificial pattern 210.

[0180] Reference Figure 26 This forms multiple first gate electrodes (GSL and WL11 to WL1n) and multiple second gate electrodes (WL21 to WL2n and SSL).

[0181] The first gate electrode (GSL and WL11 to WL1n) can be formed in the region where the first sacrificial pattern 210 has been removed. That is, the first gate electrode (GSL and WL11 to WL1n) can replace the first sacrificial pattern 210.

[0182] The second gate electrode (WL21 to WL2n and SSL) can be formed in the region where the second sacrificial pattern 212 has been removed. That is, the second gate electrode (WL21 to WL2n and SSL) can replace the second sacrificial pattern 212.

[0183] Therefore, it can form Figure 8 The first molding structure MS1 and the second molding structure MS2.

[0184] Figures 27 to 30 Steps of a method for manufacturing a non-volatile memory device according to some embodiments of the present disclosure are illustrated. For convenience, the steps already referred to above will be omitted or at least simplified. Figures 18 to 26 The description describes the features of a method for manufacturing a non-volatile memory device according to some embodiments of the present disclosure. Specifically, Figures 27 to 30 This illustrates a method for manufacturing a non-volatile memory device according to some embodiments of the present disclosure (specifically, in...). Figure 23 A partial exploded perspective view of the steps following the steps shown in the figure.

[0185] Reference Figure 27 This forms the third cutting line CL3 and the fourth cutting line CL4.

[0186] The third cutting line CL3 and the fourth cutting line CL4 can cut multiple second sacrificial patterns 212. For example, the third cutting line CL3 and the fourth cutting line CL4 can extend in the second direction Y to cut the second sacrificial pattern 212.

[0187] In some embodiments, the third cutting line CL3 may be formed to overlap with the first word line groove WLC1 in the third direction Z, and the fourth cutting line CL4 may be formed to overlap with the second word line groove WLC2 in the third direction Z.

[0188] Reference Figure 28 Multiple channel structures CS are formed that penetrate the first sacrificial pattern 210, the first insulating pattern 110, the second sacrificial pattern 212, and the second insulating pattern 112.

[0189] The formation of the channel structure CS is related to the above reference. Figure 23 The descriptions are almost identical, therefore, their detailed descriptions will be omitted.

[0190] Subsequently, a first letter groove WLC1 and a second letter groove WLC2, a plurality of third grooves BC21 and a plurality of fourth grooves BC22 are formed to cut the second sacrificial pattern 212 and the second insulating pattern 112.

[0191] In some embodiments, the first letter groove WLC1 and the second letter groove WLC2 may partially cut the second molded structure MS2. Therefore, the second sacrificial pattern 212 and the second insulating pattern 112 may form a seventh stack S24 that is at least partially connected to the fourth stack S21 via the third connection CP3. Furthermore, the second sacrificial pattern 212 and the second insulating pattern 112 may form an eighth stack S25 that is at least partially connected to the sixth stack S23 via the fourth connection CP4.

[0192] In some embodiments, a third cutting line CL3 may be formed in the third connecting portion CP3, and a fourth cutting line CL4 may be formed in the fourth connecting portion CP4.

[0193] Reference Figure 29 Remove multiple sacrifice fill patterns 230.

[0194] As a result, the first word line groove WLC1 and the second word line groove WLC2, the first groove BC11 and the second groove BC12 can partially expose the first sacrificial pattern 210.

[0195] Reference Figure 30 This forms multiple first gate electrodes (GSL and WL11 to WL1n) and multiple second gate electrodes (WL21 to WL2n and SSL).

[0196] The formation of the first gate electrode (GSL and WL11 to WL1n) and the second gate electrode (WL21 to WL2n and SSL) are as described above. Figure 26 The descriptions are almost identical, therefore, their detailed descriptions will be omitted.

[0197] Therefore, a first molding structure MS1 and a second molding structure MS2 can be formed.

[0198] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without departing from the principles of the inventive concept. Therefore, the disclosed embodiments of the inventive concept are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A non-volatile memory device, the non-volatile memory device comprising: Base; A first molded structure is located on a substrate and includes a plurality of first gate electrodes extending in a first direction; A second molding structure is located on the first molding structure and includes a plurality of second gate electrodes extending in a first direction; as well as Multiple channel structures intersect with the multiple first gate electrodes and the multiple second gate electrodes by penetrating the first molding structure and the second molding structure. The first molded structure includes a first stack and a second stack separated from each other by a first groove, the first groove extending in a first direction. The second molded structure includes a third stacked component stacked on a first stacked component, a fourth stacked component stacked on a second stacked component, and a first connecting portion connecting the third stacked component and the fourth stacked component. The first connection allows the remaining second gate electrodes, except for the topmost second gate electrode, to remain continuous between the third and fourth stacks, and The second molding structure also includes a plurality of second trenches, each of which is alternately arranged with each of the first connection portions in a first direction and penetrates each of the plurality of second gate electrodes in a second direction perpendicular to the first direction to expose a portion of the first trench.

2. The non-volatile memory device according to claim 1, wherein, The first connecting portion overlaps with the first groove in the second direction, and the first connecting portion is not arranged in the area that does not overlap with the first groove in the second direction.

3. The non-volatile memory device according to claim 1, wherein, The bottom surface of the first connecting part is spaced apart from the top surface of the base.

4. The non-volatile memory device according to claim 1, further comprising: The third molding structure, located on the second molding structure, includes multiple third gate electrodes. The plurality of channel structures intersect with the plurality of third gate electrodes by penetrating the third molding structure.

5. The non-volatile memory device according to claim 4, wherein, The third molding structure includes a fifth stacked component stacked on a third stacked component, a sixth stacked component stacked on a fourth stacked component, and a second connecting portion connecting the fifth stacked component and the sixth stacked component.

6. The non-volatile memory device according to claim 4, wherein, The third molding structure includes a fifth stacked component stacked on top of a third stacked component and a sixth stacked component stacked on top of a fourth stacked component, and The fifth and sixth stacks are spaced apart from each other.

7. The non-volatile memory device according to claim 1, further comprising: The third molding structure, located between the first molding structure and the second molding structure, includes multiple third gate electrodes. The plurality of channel structures intersect with the plurality of third gate electrodes by penetrating the third molding structure.

8. The non-volatile memory device according to claim 7, wherein, The third molding structure includes a fifth stack stacked between the first stack and the third stack, a sixth stack stacked between the second stack and the fourth stack, and a second connecting portion connecting the fifth stack and the sixth stack.

9. The non-volatile memory device according to claim 7, wherein, The third molding structure includes a fifth stacked component stacked between the first and third stacked components and a sixth stacked component stacked between the second and fourth stacked components. The fifth and sixth stacks are spaced apart from each other.

10. The non-volatile memory device according to claim 1, wherein, The second molding structure includes a cutting line located in the first connecting portion, and The cutting line cuts the uppermost second gate electrode among the plurality of second gate electrodes.

11. A non-volatile memory device, the non-volatile memory device comprising: Base; A first molded structure is located on a substrate and includes a plurality of first gate electrodes; The second molding structure is located on the first molding structure and includes a plurality of second gate electrodes; Multiple channel structures intersect with the multiple first gate electrodes and the multiple second gate electrodes by penetrating the first molding structure and the second molding structure; as well as Bit lines extend in a first direction and connect to the plurality of channel structures. The first molding structure includes a first groove that extends in a second direction intersecting the first direction to completely cut through the first molding structure. The second molding structure includes a plurality of second grooves that expose a portion of the first groove, and The plurality of second trenches are spaced apart from each other and arranged in a second direction to penetrate each of the plurality of second gate electrodes in a third direction perpendicular to the first and second directions.

12. The non-volatile memory device according to claim 11, wherein, The first molding structure also includes a third groove, which is spaced apart from the first groove in a first direction and extends in a second direction to completely cut through the first molding structure. The second molding structure includes multiple fourth grooves that expose a portion of the third groove, and The fourth groove is spaced apart from each other and arranged in the second direction.

13. The non-volatile memory device of claim 11, further comprising: The peripheral circuit structure is located below the substrate.

14. The non-volatile memory device according to claim 11, wherein, The plurality of channel structures include a semiconductor pattern and an information storage film, wherein the semiconductor pattern penetrates a first molding structure and a second molding structure, and the information storage film is located between each of the plurality of first gate electrodes and the plurality of second gate electrodes and the semiconductor pattern.

15. The non-volatile memory device of claim 14, further comprising: The source structure is located between the substrate and the first molded structure. The plurality of channel structures are connected to the substrate via source structures, and The source structure is connected to the semiconductor pattern through an information storage film.

16. A non-volatile memory device, the non-volatile memory device comprising: Base; A first molded structure is located on a substrate and includes a plurality of first gate electrodes; The second molding structure is located on the first molding structure and includes a plurality of second gate electrodes; Multiple channel structures intersect with the multiple first gate electrodes and the multiple second gate electrodes by penetrating the first molding structure and the second molding structure; Bit lines extend in a first direction and are connected to the plurality of channel structures; A first word line groove extends in a second direction intersecting the first direction, and the first word line groove cuts the plurality of first gate electrodes and the plurality of second gate electrodes; The second word line groove extends in the second direction and cuts the plurality of first gate electrodes and the plurality of second gate electrodes; as well as A first trench extends along a second direction between the first word line trench and the second word line trench, and the first trench cuts through the plurality of first gate electrodes. The first molded structure includes a first stack and a second stack separated by a first groove. The second molded structure includes a third stacked component stacked on a first stacked component, a fourth stacked component stacked on a second stacked component, and a plurality of first connecting portions connecting the third stacked component and the fourth stacked component. The first connection allows the remaining second gate electrodes, except for the topmost second gate electrode, to remain continuous between the third and fourth stacks, and The second molding structure also includes a plurality of second trenches, each of which is alternately arranged with each of the plurality of first connections in a second direction and extends through each of the plurality of second gate electrodes in a third direction perpendicular to the first and second directions to expose a portion of the first trench.

17. The non-volatile memory device according to claim 16, wherein, The second molding structure includes multiple cutting lines extending in a second direction in the plurality of first connecting portions, and The multiple cutting lines cut the uppermost second gate electrode among the multiple second gate electrodes.

18. The non-volatile memory device according to claim 16, wherein, The second molding structure includes a fifth stacked member spaced apart from the third stacked member by a first letter groove, and a plurality of second connecting portions connecting the third stacked member and the fifth stacked member.

19. The non-volatile memory device according to claim 18, wherein, The plurality of second gate electrodes are partially located in the plurality of second connection portions.

20. The non-volatile memory device according to claim 18, wherein, The second molding structure also includes cutting lines located in the plurality of second connecting portions and cutting the plurality of second gate electrodes.

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