RISC-V instruction set shift instruction implementation circuit

Abstract

This invention relates to the field of integrated circuit technology, specifically to a RISC-V instruction set shift instruction implementation circuit. The circuit integrates a shift module, which consists of a left shifter, a right shifter, and a subtractor. When an instruction is emitted from the instruction buffer, it enters the decoding module for instruction decoding. At this time, the decoded information and operands enter the shift module. The left shifter performs a left shift instruction, and the right shifter performs a right shift instruction. The subtractor provides the shift distance for the left and right shifters. After the operand operations are completed, the result is output and the instruction is committed, thus completing the instruction execution. This circuit supports all shift operation instructions included in the RISC-V instruction set, and its timing is easily converged, allowing for higher clock frequencies. It is particularly suitable for architecture designs that pursue high-performance CPUs.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a RISC-V instruction set shift instruction implementation circuit. Background Technology

[0002] Processors have been around for over 50 years. In their development, to meet diverse processing needs and pursue higher performance, various processor architectures have continuously expanded their instruction sets. For example, the Ricsv instruction set, in addition to the basic shift instructions in the base instruction set, adds shift types such as circular shift, carry-over shift, funnel shift, and single-bit operations to the Bitmainip extension. After compilation, the number of instructions executed by the program can be greatly reduced, thus allowing the processor to achieve even higher computational performance.

[0003] The RISC-V64 instruction set contains numerous shift instructions, including the RV BaseInteger and RV Btmainip instruction sets, both of which involve shift instructions. Currently, there are no suitable logic circuit units in the design products that support all of the above shift instructions.

[0004] For high-performance CPU designs, existing barrel shifter modules can easily cause timing issues, limit core frequency, and cannot support all shift instructions of all RISCV architectures. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention discloses a RISC-V instruction set shift instruction implementation circuit, which solves the problems in existing products where, for high-performance CPU designs, existing barrel shifter modules easily cause timing constraints, limit core frequency, and cannot support all shift instructions of all RISC-V architectures.

[0006] This invention is achieved through the following technical solution:

[0007] This invention discloses a RISC-V instruction set shift instruction implementation circuit. The circuit integrates a shift module, which consists of a left shifter, a right shifter, and a subtractor. When an instruction is emitted from the instruction buffer, it enters the decoding module to complete instruction decoding. At this time, the decoded information and operands enter the shift module. The left shifter completes the left shift instruction, and the right shifter completes the right shift instruction. The subtractor is responsible for providing the shift distance for the left and right shifters. After the operand operations are completed, the result is output and the instruction is submitted, and the instruction is executed.

[0008] Furthermore, after determining the operands, the shift distance operands include shift_amt and XLEN-shift_amt. When the instruction is a single shift operation, the shifter selects the initial shift distance data. When the instruction is a cyclic shift or funnel shift, the shift operation can be decomposed into left shift and right shift operations, and the results of the left shifter and right shifter are logically ORed.

[0009] Furthermore, the left shifter uses a logic expansion gating circuit to shape the shifted data A, generating a data array tb consisting of 64 data vectors tb[i], where the data length of each vector tb[i] is i. The generation process is as follows:

[0010] S11 sets variable i, with an initial value of 0;

[0011] S12 takes the shifted data A[i:0] bits and assigns them the value tb[i];

[0012] S13 performs an inverted operation on the data tb[i];

[0013] S14 Increment variable i by 1. If variable i is less than 64, then repeat step 2; otherwise, execute S15.

[0014] S15 outputs the data array tb[i].

[0015] Furthermore, the left shifter uses a logical expansion method to cut the shifted data shift_decode_amt, generating a data array sh consisting of 64 vectors sh[i], where the data width of vector sh[i] is i. The specific steps are as follows:

[0016] S21 sets variable j, with the initial value of j being 0;

[0017] S22 takes the bits that are considered as data [j:0] as sh[j];

[0018] S23 Increment variable j by 1. If variable j is less than 64, then repeat step 2; otherwise, repeat step 5.

[0019] S24 outputs sh[j]

[0020] S25 generates a data array sh consisting of 64 vectors sh[j].

[0021] Furthermore, the left shifter performs a bitwise AND operation on the nth row vector of the tb and sh data matrices, respectively, where n is the row index of the tb[i] and sh[j] data arrays. At this time, index i and index j are the same. The bitwise AND result is then logically ORed bit by bit to obtain a 1-bit result tmp[n]. Since both the data matrices tb and sh have 64 row vectors, the width of the final vector tmp is also 64. The process is as follows:

[0022] S31 sets the variable n, with an initial value of 0;

[0023] S32 takes tb[n] and sh[n], and performs a bitwise AND operation on tb[n] and sh[n] to obtain the vector tb_sh;

[0024] S33 performs a bitwise OR operation on the vector tb_sh to obtain a single-bit result tmp[n];

[0025] S34 Increment variable n by 1. If variable n is less than 64, repeat step 2; otherwise, execute S35.

[0026] S35 outputs tmp[n];

[0027] The nth row vector in the sh data array is subjected to a bitwise logical OR operation to obtain the sin_select[n] vector. The corresponding tmp[n] value or sin value is selected as the final shift result out[n] based on the sin_select[n] bit value. The output data out is also 64 bits wide.

[0028] Furthermore, the method by which the right shifter completes the right shift instruction is the same as that of the left shifter in completing the left shift instruction. It also uses a logic expansion gating circuit to implement the shift function. It is the same as the shift processing unit of the left shifter, except that it adds an inversion operation on the input and output data. When the logic left shift is carried forward by 1, the result of the single-bit operation instruction is calculated and output by the left shifter. When the logic right shift is carried forward by 1, the result of the right shift instruction is calculated and output by the right shifter. Finally, the result of the shift module selects the corresponding shifter data result according to the shift control signal.

[0029] Furthermore, when the shift instruction is a BFP instruction, a segment of data from operand B replaces a bit region of operand A. After extracting the OFF and LEN fields from the instruction code, the mask and the replacement data are simultaneously shifted left. Finally, a logical AND-OR operation is performed on the shift results of the mask and the replacement data. The specific process is as follows:

[0030] S41 selects OFF and LEN data based on the SEL field;

[0031] S42 calculates the mask based on the LEN data.

[0032] S43 uses a left shifter to shift the mask by a distance equal to the OFF data. It uses a right shifter to shift the data inb_A by a distance equal to the OFF data. However, this right shifter needs to be used as a left shifter, and the shifted data inb_A and the output result rishift_outb are reversed respectively.

[0033] S44 performs a logical AND-OR operation on the result;

[0034] The BFP instruction performs a logical left shift on the mask data and data B[31:0], using the right shifter as a left shifter. The shifted data B is inverted before entering the right shift data and after the result is output. The left and right shifters have the same shift distance, which is OFF data. The left shifter data input is the mask data, and the right shifter data input is inb_A[31:0]. The result is ORed to obtain the BFP instruction operation result.

[0035] Furthermore, when the shift instruction is a circular shift or a funnel shift, the outputs of the left shifter and the right shifter are called simultaneously, and the results of the two shifters are ORed.

[0036] When the shift type is circular left shift, the data to be shifted is shifted left by n bits in the left shift module with a shift-in value of zero, resulting in l_res. The data to be shifted right by 64-n bits in the right shift module with a shift-in value of zero, resulting in r_res. Performing a bitwise OR operation on l_res and r_res yields the circular left shift result. The circular right shift is the reverse: the left shift module shifts left by 64-n bits, and the right shift module shifts right by n bits. Performing a bitwise OR operation on the shift results of the two shifters yields the circular right shift result.

[0037] Furthermore, when the shift type is funnel shift, its operation is the same as the circular shift operation. In the circular shift operation, the data shifted to the left and right is the same data, while in the funnel shift operation, the data shifted to the left and right are different data, and the data selector is responsible for selecting the data.

[0038] When the shift type is a single-bit operation, the number of bits to be shifted is 64'b1. A mask is generated using a left shifter. The data to be operated on is then subjected to corresponding logical operations with the mask to complete the single-bit operation. The single-bit operation includes a logical OR operation. Its cyclic shift and funnel shift multiplex the operation logic in the single-bit operation.

[0039] Furthermore, the system includes a processor and a memory storing execution instructions. When the RISC-V instruction set shift instruction implementation circuit is operating, the processor executes the execution instructions stored in the memory.

[0040] The beneficial effects of this invention are as follows:

[0041] This invention supports all shift operation instructions included in the RISCV architecture instruction set, and the timing is easily converged, allowing for higher clock speeds. It is particularly suitable for architecture designs that pursue high-performance CPUs. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a block diagram illustrating the principle of instruction execution completion in an embodiment of the present invention;

[0044] Figure 2 This is a block diagram illustrating the principle of the shifting module according to an embodiment of the present invention;

[0045] Figure 3 This is a flowchart illustrating the specific process of outputting data (out) with a width of 64 bits in this embodiment of the invention.

[0046] Figure 4 This is a schematic diagram of the principle of outputting the shift result value OUT in an embodiment of the present invention;

[0047] Figure 5 This is a block diagram illustrating the principle of the reversal operation in an embodiment of the present invention;

[0048] Figure 6 This is a diagram of the BFP instruction format according to an embodiment of the present invention;

[0049] Figure 7 This is a schematic diagram of the principle when the shift instruction is a cyclic shift and a funnel shift according to an embodiment of the present invention;

[0050] Figure 8 This is a schematic diagram illustrating the principle of selecting the output of the calculation result in an embodiment of the present invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] Example 1

[0053] This embodiment discloses a Ricsv instruction set that, in addition to the basic shift instructions in the base instruction set, adds shift type instructions such as circular shift, carry-over shift, funnel shift, and single-bit operation to the Bitmainip extension instructions. After compilation, the number of instructions executed by the program can be greatly reduced, thus enabling the processor to achieve higher computing performance.

[0054] The Riscv architecture supports the following shift instructions:

[0055]

[0056]

[0057] Shift instructions require the decoding unit to provide the control signals necessary for instruction execution, such as... Figure 1 As shown, the instruction is emitted from the instruction buffer, enters the decoding module to complete the instruction decoding, and then the decoding information and operands enter the shift module. After the operation is completed, the output result is submitted to the instruction, and the execution of this instruction is completed.

[0058] The shift control signals required by the shift module in this embodiment are shown in the table below.

[0059] Control signal active high

[0060]

[0061]

[0062] If a traditional barrel shifter is used, the shift width is 128 bits to meet the shift requirements of the Risc64 instruction set. This requires cascading through 7 selectors, which can easily cause timing problems.

[0063] This embodiment differs from traditional barrel shifters. The shifter is implemented using a logical loop unrolling method. The entire shift module mainly consists of a left shifter, a right shifter, and a 6-bit subtractor, as follows: Figure 2As shown in the diagram. The left shifter is responsible for executing left shift instructions, and the right shifter is responsible for executing right shift instructions. The left and right shifters respectively perform the shift operations required by the instruction, and the subtractor is responsible for providing the shift distance operands for the left and right shifters.

[0064] With the operands fixed, the shift distance operand has only two possibilities: shift_amt and XLEN-shift_amt (using the rv64 instruction set as an example, so XLEN is 64). Different shift operations will require different shift distance operands for the shifter. The relationship between the shift distance operands for left and right shifters is shown in the following code:

[0065] assignshift_amt_sub=(is_funnel_32|is_rolw|is_rwshift|is_bfp)? XLEN / 2:XLEN)–shift_amt;

[0066] assign lshift_sel_amt=is_setbit|~is_rshift;

[0067] assign rshift_sel_amt=is_rshift;

[0068] assign lshift_amt=(lshift_sel_amt|is_bfp)? shift_amt:shift_amt_sub;

[0069] assign rshift_amt=(rshift_sel_amt|is_bfp)? shift_amt:shift_amt_sub;

[0070] When the instruction is a single shift operation, the shifter selects the initial shift distance data, i.e., shift_amt. When the instruction is a cyclic shift or funnel shift, the shift operation can be decomposed into left and right shift operations, and a logical OR operation is performed on the results of the left and right shifters. Note that the shift distance data selected for the left and right shifters are different, as shown in the table below:

[0071]

[0072] Example 2

[0073] This embodiment discloses a method for implementing a left shift unit, which is a logic expansion gating circuit. The logic expansion is to shape the data to be shifted, A, to generate a data array tb consisting of 64 data vectors tb[i], where the data length of each vector tb[i] is i. The generation process is as follows:

[0074] Set variable i, and initialize it to 0;

[0075] Take the shifted data A[i:0] bits and assign the value tb[i];

[0076] Invert the data tb[i].

[0077] Increment variable i by 1. If variable i is less than 64, repeat step 2; otherwise, repeat step 5.

[0078] Output data array tb[i]

[0079] The code is as follows:

[0080]

[0081]

[0082] Then, the shift_amt data is decoded into hotcode encoding. That is, if lshift_amt = i, then lshift_decode_amt[i+1] = 1, and the remaining bits are all 0. Subsequently, the lshift_decode_amt signal is used as the strobe signal for the logic expansion circuit. The shift_amt is hotcode encoded according to the following code.

[0083]

[0084] The shifted data shift_decode_amt is split using a logical expansion method to generate a data array sh consisting of 64 vectors sh[i], where the data width of vector sh[i] is i. The specific steps are as follows:

[0085] Set variable j, and initialize j to 0;

[0086] Take the bits that are considered as data [j:0] as sh[j];

[0087] Increment variable j by 1. If variable j is less than 64, repeat step 2; otherwise, repeat step 5.

[0088] Output result: sh[j]

[0089] Generate a data array sh consisting of 64 vectors sh[j]. Then, perform a bitwise AND operation on the nth row vector of the data matrix tb and the data matrix sh, where n is the row index of the data arrays tb[i] and sh[j]. At this time, index i and index j are the same. Perform a bitwise logical OR operation on the result of the bitwise AND operation to obtain a 1-bit result tmp[n]. Since both data matrices tb and sh have 64 row vectors, the width of the final vector tmp is also 64. The process is as follows:

[0090] Set a variable n, and initialize n to 0;

[0091] Take tb[n] and sh[n], and perform a bitwise AND operation on tb[n] and sh[n] to obtain the vector tb_sh;

[0092] Perform a bitwise OR operation on the vector tb_sh to obtain a single-bit result tmp[n];

[0093] Increment variable n by 1. If variable n is less than 64, repeat step 2; otherwise, repeat step 5.

[0094] Output the result tmp[n];

[0095] Perform a bitwise logical OR operation on the nth row vector in the sh data array to obtain the sin_select[n] vector. Select the corresponding tmp[n] value or sin value as the final shift result out[n] based on the bit value of sin_select[n]. The output data out is also 64 bits wide. The specific process is as follows: Figure 3 As shown. This method is applicable to data shifting of arbitrary width. For ease of illustration, let's take 16-bit data as an example. Assume the number of bits to be shifted is 0x8fe8, and the shift distance is 0x4. The data and the distance value are cut to generate a data matrix consisting of 16 vectors, as shown. Figure 4 As shown, the final output shift result value is out. Here, sin is the value to be shifted into the shift operation. The sin value is an external input signal from the shift unit. In the Riscv instruction set, the shift value in the shift operation is divided into zero, one, and signedbit. Different instructions have different shift values, which are selected using a selector. The selection rules are shown in the table below.

[0096]

[0097] Example 3

[0098] This embodiment discusses a right-hand shifter, which also uses a logic expansion gating circuit to implement the shift function. Its shift processing unit is the same as that of the left-hand shifter, except that it additionally performs a reversal operation on the input and output data, such as... Figure 5As shown. In hardware circuits, the inversion operation does not consume any logic resources.

[0099] Logical shift instructions, arithmetic shift instructions, carry-over instructions, and single-bit operation instructions all use a single shifter to obtain the shift result. For logical left shift, carry-over left shift, and single-bit operation instructions, the result is calculated and output by a left shifter. For logical right shift, arithmetic shift, and carry-over right shift instructions, the result is calculated and output by a right shifter. The final result of the shift module is determined by selecting the corresponding shifter data result based on the shift control signal.

[0100] When the shift instruction is a BFP instruction, it replaces a bit range of operand A with a segment of data from operand B. The BFP instruction format is as follows: Figure 6 As shown. After extracting the OFF and LEN fields from the instruction code, both the mask and the replacement data need to be shifted left simultaneously. Finally, a logical AND-OR operation is performed on the shifted results of the mask and the replacement data. The specific process is as follows:

[0101] 1. Based on the SEL field, select the OFF and LEN data;

[0102] 2. Calculate the mask based on the LEN data. The calculation code is as follows:

[0103]

[0104] 3. Use a left shifter to shift the mask by a distance equal to the OFF data. Use a right shifter to shift the data inb_A by a distance equal to the OFF data. However, the right shifter here needs to be used as a left shifter, and the shifted data inb_A and the output result rishift_outb are reversed respectively.

[0105] 4. Perform a logical AND / OR operation on the result, as shown in the following code:

[0106] assign bfp_res=(rshift_outb_rev&lshift_outb)|(inb_B&~lshift_outb);

[0107] The BFP instruction requires a logical left shift using the mask data and data B[31:0]. To satisfy the two left shift requirements, the right shifter needs to be used as the left shifter. This can be achieved by reversing the shift data B before it enters the right shift data and after the result is output. The left and right shifters have the same shift distance, which is OFF data. The left shifter input is the mask data, and the right shifter input is inb_A[31:0]. The result is then ORed to obtain the BFP instruction operation result.

[0108] When the shift instruction is a circular shift or a funnel shift, it is necessary to simultaneously call the outputs of the left shifter and the right shifter, and then OR the results of the two shifters, such as... Figure 7 As shown. When the shift type is circular left shift, the data to be shifted is shifted left by n bits in the left shift module, with a shift-in value of zero, resulting in l_res. The data to be shifted is then shifted right by 64-n bits in the right shift module, with a shift-in value of zero, resulting in r_res. Performing a bitwise OR operation between l_res and r_res yields the circular left shift result. The circular right shift is the reverse: the left shift module shifts left by 64-n bits, and the right shift module shifts right by n bits. Performing a bitwise OR operation between the two shifter results yields the circular right shift result.

[0109] Example 4

[0110] This embodiment discloses a RISC-V instruction set shift instruction implementation circuit. The shift type is funnel shift, which operates the same as cyclic shift, except that the shifted data is different. In cyclic shift, the shifted data for left and right shifts is the same data, while in funnel shift, the shifted data for left and right shifts are different data. A data selector is responsible for data selection.

[0111]

[0112] Example 5

[0113] This embodiment discloses a RISC-V instruction set shift instruction implementation circuit. The shift instructions are cyclic shift and funnel shift, which require simultaneously calling the outputs of the left shifter and the right shifter, and then performing an OR operation on the results of the two shifters, such as... Figure 7 As shown. When the shift type is circular left shift, the shifted data is shifted n bits to the left in the left-hand module, and the shifted-in value is zero, resulting in l_res.

[0114] The data to be shifted is shifted 64-n bits to the right in the right shift module, with the shift-in value being zero, to obtain the shift result r_res. The left shift result is obtained by performing a bitwise OR operation between l_res and r_res.

[0115] The circular right shift works in reverse order. The left shift module shifts the left by 64-n bits, and the right shift module shifts the right by n bits. The shift results of the two shifters are bitwise ORed to obtain the circular right shift result.

[0116] Example 6

[0117] This embodiment discloses a RISC-V instruction set shift instruction implementation circuit. When the shift type is a single-bit operation, the number of bits to be shifted is 64'b1. A left shifter is used to generate a mask. The data to be operated on is then subjected to corresponding logical operations with the mask to complete the single-bit operation. The single-bit operation includes a logical OR operation, so circular shifts and funnel shifts reuse the operational logic from the single-bit operation. The logical operations for the single-bit operation are shown in the table below. The operation result requires output selection, such as... Figure 8 As shown.

[0118] Instruction type Logical operation types sbset / sbseti / sbsetw / sbsetiw OR operation sbclr / sbclri / sbclrw / sbclriw AND operation, NOT operation sbinv / sbinvi / sbinvwsbinviw XOR operation sbext / sbexti / sbextw AND operation

[0119] Example 7

[0120] This embodiment discloses a RISC-V instruction set shift instruction implementation circuit. Since the final output positions of different shift instructions are not the same, it is necessary to select the output of each shift result. The shift operation has three outputs: a left shift unit, a right shift unit, and a logic operation unit. The relationship between the result output selection and the instruction is shown in the following table:

[0121]

[0122] The code is as follows:

[0123] assign shift_out=is_logic_sel? shift_outb:is_rshift? rshift_outb:lshift_outb.

[0124] In summary, this invention uses two shift units to support all shift instructions across all RISCV architectures. It proposes a logical loop unrolling gating method to complete the shift unit operation. This invention can also be applied to other instruction set architectures. Left and right shifters are used to perform cyclic shift instructions. Left and right shifters are also used to perform funnel shift instructions. Logical loop unrolling is used to implement the left shifter function. A right shifter nested within a left shifter implements the right shifter function. This invention is applicable to shift instruction operations in other instruction sets.

[0125] It supports all shift operation instructions included in the RISCV architecture instruction set, and its timing is easily converged, allowing for higher clock speeds. It is especially suitable for architecture designs that pursue high-performance CPUs.

[0126] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A RISC-V instruction set shift instruction implementation circuit, characterized in that, The circuit integrates a shift module, which consists of a left shifter composed of a logic expansion gating circuit, a right shifter composed of a logic expansion gating circuit, and a subtractor, wherein: The left shifter is used to cut the shifted data A to generate tb[i] array and sh[i] array, and output the left shift result through bitwise AND-OR operation; The right shifter is used to invert the input data, call the left shifter logic, and invert it again to output the right shift result; The subtractor is used to calculate the shift distance shift_amt or XLEN-shift_amt according to the instruction type. After the instruction is issued from the instruction buffer, it enters the decoding module to complete the instruction decoding. At this time, the decoded information and operands enter the shift module. The left shifter is used to complete the left shift instruction, and the right shifter is used to complete the right shift instruction. The subtractor is responsible for providing the shift distance for the left and right shifters. After the operand calculation is completed, the result is output and the instruction is submitted. The execution of this instruction is complete.

2. The RISC-V instruction set shift instruction implementation circuit according to claim 1, characterized in that, After determining the operands, the shift distance operands include shift_amt and XLEN-shift_amt. When the instruction is a single shift operation, the shifter selects the initial shift distance data. When the instruction is a cyclic shift or funnel shift, the shift operation is decomposed into left shift and right shift operations, and the results of the left shifter and right shifter are logically ORed.

3. The RISC-V instruction set shift instruction implementation circuit according to claim 1, characterized in that, The left shifter uses a logic expansion gating circuit to shape the shifted data A, generating a data array tb consisting of 64 data vectors tb[i]. The data length of each vector tb[i] is i. The generation process is as follows: S11 sets variable i, with an initial value of 0; S12 takes the shifted data A[i:0] bits and assigns them the value tb[i]; S13 performs a negation operation on the data tb[i]; S14 Increment variable i by 1. If variable i is less than 64, then repeat step 2; otherwise, execute S15. S15 outputs the data array tb[i].

4. The RISC-V instruction set shift instruction implementation circuit according to claim 3, characterized in that, The left shifter uses a logical expansion method to cut the shifted data, generating a data array sh consisting of 64 vectors sh[i], where the data width of vector sh[i] is i. The specific steps are as follows: S21 sets variable j, with the initial value of j being 0; S22 takes the [j:0] bits of the shifted data A as sh[j]; S23 Increment variable j by 1. If variable j is less than 64, then repeat step 2; otherwise, repeat step 5. S24 outputs sh[j] S25 generates a data array sh consisting of 64 vectors sh[j].

5. The RISC-V instruction set shift instruction implementation circuit according to claim 4, characterized in that, The left shifter performs a bitwise AND operation on the nth row vector of the data matrix tb and the data matrix sh, respectively, where n is the row index of the data arrays tb[i] and sh[j]. At this time, index i and index j are the same. The bitwise AND result is then processed bitwise by bitwise OR to obtain the 1-bit result tmp[n]. Since both data matrices tb and sh have 64 row vectors, the width of the final vector tmp is also 64. The process is as follows: S31 Set variable n, with an initial value of 0; S32 Take tb[n] and sh[n], and perform a bitwise AND operation on tb[n] and sh[n] to obtain vector tb_sh; S33 Perform bitwise OR operation on vector tb_sh to obtain single-bit result tmp[n]; S34 Increment variable n by 1. If variable n is less than 64, repeat step 2; otherwise, execute S35; S35 Output result tmp[n]; where the nth row vector in the sh data array is subjected to a bitwise logical OR operation to obtain the sin_select[n] vector. The corresponding tmp[n] value is selected as the final shift result out[n] according to the bit value of sin_select[n]. The output data out is also 64 bits wide.

6. The RISC-V instruction set shift instruction implementation circuit according to claim 1, characterized in that, The method by which the right shifter completes the right shift instruction is the same as that of the left shifter in completing the left shift instruction. It also uses a logic expansion gating circuit to implement the shift function. It is the same as the shift processing unit of the left shifter, except that it adds an inversion operation on the input and output data. When the logical and arithmetic left shifts are shifted in by 1, the result of the single-bit operation instruction is calculated and output by the left shifter. The shift results of the three types of instructions, namely logical right shift, arithmetic right shift, and right shift in by 1, are all calculated and output by the right shifter. Finally, the result of the shift module selects the corresponding shifter data result according to the shift control signal.

7. The RISC-V instruction set shift instruction implementation circuit according to claim 1, characterized in that, When the shift instruction is a BFP instruction, a bit region of operand A is replaced with a segment of data from operand B. After extracting the OFF and LEN fields from the instruction code, the mask and operand B are simultaneously shifted left. Finally, logical operations are performed on the shift results of the mask and operand B. The specific process is as follows: S41 selects OFF and LEN data based on the SEL field; S42 calculates the mask based on the LEN data; S43 uses a left shifter to shift the mask by a distance equal to the OFF data, and a right shifter to shift the data inb_A by a distance equal to the OFF data. However, the right shifter here needs to be used as a left shifter, and the shifted data inb_A and the output result rishift_outb are reversed respectively. S44 performs a logical AND-OR operation on the result; The BFP instruction performs a logical left shift on the mask data and data B[31:0], using the right shifter as a left shifter. Operand B is inverted before entering the right shift data and after the result is output. The left and right shifters have the same shift distance, both being OFF data. The left shifter input is the mask data, and the right shifter input is inb_A[31:0]. The operation on the result yields the BFP instruction's calculation result. Data B[31:0] is the low-order word of operand B; The data inb_A is the low-order word inb_A[31:0] of operand A.

8. The RISC-V instruction set shift instruction implementation circuit according to claim 1, characterized in that, When the shift instruction is a circular shift or a funnel shift, the outputs of the left shifter and the right shifter are called simultaneously, and the results of the two shifters are ORed. When the shift type is a circular left shift, the data to be shifted is shifted left by n bits in the left shift module, and the shift-in value is zero, resulting in l_res. The data to be shifted is shifted right by 64-n bits in the right shift module, and the shift-in value is zero, resulting in r_res. The result of the circular left shift is obtained by performing a bitwise OR operation on l_res and r_res. The circular right shift is the reverse: the left shift module shifts left by 64-n bits, and the right shift module shifts right by n bits. The result of the circular right shift is obtained by performing a bitwise OR operation on the shift results of the two shifters.

9. The RISC-V instruction set shift instruction implementation circuit according to claim 1, characterized in that, When the shift type is funnel shift, the left and right shifters work together in the same way as in circular shift, the only difference being that: in circular shift, the shifted data in both shifts is the same data, while in funnel shift, the shifted data in both shifts are different data, switched by the data selector according to the shift_amt size; when the shift type is single-bit operation, the shifted data is fixed as a 64-bit wide binary number 1, that is, the least significant bit is 1 and the remaining bits are 0. The single-bit logic operation is completed after the left shifter generates a mask.

10. The RISC-V instruction set shift instruction implementation circuit according to any one of claims 1-9, characterized in that, The device includes a processor and a memory storing execution instructions. When the RISC-V instruction set shift instruction implementation circuit as described in any one of claims 1 to 9 is operating, the processor executes the execution instructions stored in the memory.

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