Process for the hetero-integration of a semiconductor material of interest on a silicon substrate

Abstract

The invention relates to a process for the hetero-integration of a semiconductor material of interest on a silicon substrate (1), comprising: - a structuring step of the substrate comprising a step of creating a growth mask (2) on the surface of the silicon substrate (1), the growth mask comprising a plurality of mask patterns (20), two mask patterns being separated by a trench (21) in which the silicon substrate (1) is exposed; - a step of forming a two-dimensional buffer layer (5) made of a 2D material, the buffer layer being free of side bonds on its free surface and being formed selectively on a [111] oriented silicon plane (3) in at least one trench (21), the step of forming a buffer layer being performed after the structuring step; - a step of forming at least one layer (61, 62) of a semiconductor material of interest on the buffer layer (5). The semiconductor material of interest is preferably a IV-IV, III-V, II-VI semiconductor material and / or a 2D semiconductor material.

Description

Technical Field

[0001] This invention belongs to the field of heterogeneous integration of semiconductor materials on silicon substrates, and more specifically relates to monolithic heterogeneous integration of semiconductors (IV-IV, III-V, II-VI, 2D materials, etc.) on silicon substrates via epitaxy.

[0002] In the many applications of this invention, references may be made to microelectronics, photonics, sensors, radio frequency related technologies, microsystems (MEMS), Internet of Things components, and more broadly, anything relating to applications or derivative technologies beyond Moore's Law, i.e., technologies that integrate several functions on the same silicon chip. Background Technology

[0003] Silicon (Si) is the most widely used semiconductor in information technology applications and dominates the microelectronics and nanoelectronics industries. Its highly mature integrated circuit (IC) manufacturing technology has made remarkable progress in miniaturization and performance enhancement.

[0004] Furthermore, other semiconductors such as IV-IV, III-V, II-VI semiconductors and 2D materials can have electronic and / or optical properties that complement the electronic and / or optical properties of silicon.

[0005] IV-IV semiconductors are composite semiconductors made from several elements listed in column IV of the periodic table, such as Si, Ge, and C. Examples of IV-IV semiconductors include SiC and SiGe.

[0006] III-V semiconductors are composite semiconductors made of one or more elements from column III of the periodic table (e.g., Al, Ga, In) and one or more elements from column V of the periodic table (e.g., As, Sb, N, P). Examples of III-V semiconductors that may be mentioned include GaAs, GaSb, GaN, AlN, InP, etc.

[0007] II-VI semiconductors are composite semiconductors made of one or more elements from column II of the periodic table (e.g., Cd) and one or more elements from the chalcogen group (column VI) of the periodic table (e.g., S, Se, Te). Examples of II-VI semiconductors that may be mentioned include CdS, CdSe, and CdTe.

[0008] III-V semiconductors are the preferred materials, especially for optoelectronic devices. Most III-V semiconductors have a direct bandgap structure, which means better photon emission and absorption than indirect bandgap semiconductors (such as silicon (Si) and germanium (Ge)). Therefore, light-emitting devices such as LEDs and lasers are primarily based on III-V materials. Similarly, light-absorbing devices (such as photodetectors, sensors, and components) benefit from the optoelectronic properties of III-V materials. Furthermore, a large number of III-V materials exhibit high carrier (electron, hole) mobility, enabling the production of high-performance logic cells and radio frequency (RF) transistors.

[0009] The term "2D material" refers to materials composed of thin sheets a few atoms thick (typically no more than 10 atoms). These materials are electron-saturated. Therefore, the stacking of several of these sheets occurs via van der Waals bonds. Among 2D materials, some are semiconductors. Their extremely low thickness leads to very unusual electronic and optoelectronic properties.

[0010] Monolithic heterogeneous integration of semiconductors of interest (IV-IV, III-V, II-VI, 2D materials, etc.) on silicon substrates via epitaxy is a promising way to add novel functions (electronic, optical, mechanical, sensor, biological, etc.) to CMOS (complementary metal-oxide-semiconductor) integrated circuits based on highly mature silicon technology, thereby opening up a wide range of applications and functional areas.

[0011] Monolithic heterogeneous integration involves the direct deposition of layers of semiconductor materials (IV-IV, III-V, II-VI, 2D materials, etc.) on a silicon substrate via epitaxy.

[0012] However, epitaxy on silicon substrates presents many challenges, the main ones being:

[0013] The difference in the coefficient of thermal expansion between silicon and the semiconductor material to be epitaxially grown can lead to deformation of the epitaxial semiconductor layer, which may cause bending of the substrate or even cracks in the epitaxial layer.

[0014] - The difference in lattice parameters between the semiconductor material to be epitaxially grown and the silicon that causes constraints in the epitaxial layer is relaxed by the generation of crystal defects that form dislocations at the interface between the epitaxial layer and silicon. These dislocations may propagate in the epitaxial layer (exposed dislocations or penetrating dislocations (multiple TDs));

[0015] The difference in polarity between silicon and the epitaxial layer may lead to the formation of planar defects and antiphase walls.

[0016] These crystal defects generated at the interface are the root cause of the severe degradation of the electronic and optical properties of epitaxial materials.

[0017] Of these defects, penetrating dislocations are currently the most difficult to overcome.

[0018] Several solutions for epitaxially growing semiconductor material layers with good crystal quality have been proposed in the literature. These solutions typically involve selectively epitaxially growing the semiconductor layer in a mask comprising a pre-constructed dielectric pattern (typically made of SiO2) on a silicon substrate. These solutions are commonly referred to as “selective region epitaxy” (SAE) or “selective region growth” (SAG). The semiconductor layer is usually deposited using MOCVD. The SAE solution offers the following advantages:

[0019] - Growth occurs only in the open regions (called "trenches") between patterns (exposed on the Si surface); therefore, semiconductor material can be deposited only in the regions of interest, which is important for co-integration with Si-based devices;

[0020] - The deposition of material in very narrow pores leads to a reduction in dislocations, which are then trapped by the walls of the mask pattern.

[0021] The curvature of the substrate and the appearance of cracks in the layer caused by the difference in the coefficient of thermal expansion can be attenuated.

[0022] Several variations of these solutions are given in Kunert B. et al.’s publication, How to control defect formation in monolithic III / V hetero-epitaxy on (100)Si? A critical review on current approaches (2018 Semicond. Sci. Technol. 33 093002).

[0023] The first variant involves growing material in dielectric trenches. This first variant is known by the abbreviation ART, which stands for aspect ratio capture, such as... Figure 1 As shown. If the aspect ratio (AR) corresponding to the mask height (h) divided by the trench width (l) is sufficient, ART includes trapping through-hole dislocations in the III-V semiconductor layer through the walls of the dielectric mask (SiO2). This first variant is relatively simple to implement, but its main limitation is that through-hole dislocations parallel to the trench are not trapped by the walls. Therefore, the density of through-hole dislocations remains high, with the best result being a saturation value of approximately 10. 7 cm -2 .

[0024] For example, patent FR 3010828 relates to a process for fabricating III-V semiconductor material patterns on a silicon-based or germanium-based semiconductor substrate, comprising: a step of generating a growth mask on the substrate surface and a step of growing patterns of III-V material between the mask patterns. For this growth step, optimized parameters are determined to grow III-V material with trapped through dislocations, thereby producing a layer with good crystal quality and low dislocation density.

[0025] The second variant, also known as TASE, is derived from the term "growth in a dielectric tube," which signifies template-assisted selective epitaxy, such as... Figure 2A and Figure 2B As shown.

[0026] The third variant is called CELO, which is similar in principle to TASE, meaning finite extensional lateral overgrowth, such as... Figure 3 As shown. It involves first growing material in a trench (in the same manner as the ART), then forcing the layer to grow laterally through a second constraint (this time in the height direction), thereby encapsulating the layer. Thus, a horizontal ART is added to the vertical ART. This second constraint allows residual TD not blocked by the trench walls to be captured.

[0027] Although the second and third variants can capture more (or even the vast majority) of penetrating dislocations, thus reducing the density of penetrating dislocations, they still have drawbacks:

[0028] - The technology used to construct the substrate is very laborious to implement, especially since it involves a large number of steps; - Because the contact area between the epitaxial material and the dielectric is very large, the dielectric must have very high quality to avoid defects;

[0029] Epitaxy in dielectric tubes is difficult to control, especially for ternary and quaternary alloys in which fluctuations in alloy composition are observed.

[0030] The present invention aims to provide a process for monolithic heterogeneous integration of semiconductors of interest (IV-IV, III-V, II-VI, 2D materials, etc.) on a silicon substrate by selective epitaxy, without the aforementioned disadvantages of the prior art.

[0031] More specifically, the present invention aims to provide a process for monolithic heterogeneous integration of semiconductors of interest (IV-IV, III-V, II-VI, 2D materials, etc.) on a silicon substrate by selective epitaxy, which enables the reduction of defects, particularly dislocations, at the interface between silicon and the epitaxial layer, and the process is relatively simple to perform. Summary of the Invention

[0032] The first subject of the present invention, which overcomes these drawbacks, is a process for heterogeneous integration of semiconductor materials of interest on a silicon substrate, characterized in that the process comprises:

[0033] - A step of structuring a substrate, which includes the step of generating a growth mask on the surface of a silicon substrate, the growth mask comprising a plurality of mask patterns, two mask patterns being separated by trenches therein exposing the silicon substrate;

[0034] - The step of forming a two-dimensional buffer layer made of 2D material, the buffer layer having no side bonds on its free surface and selectively formed on a

[111] oriented silicon plane in at least one trench, is performed after the structuring step and is performed by metal-organic vapor deposition (MOCVD) technique;

[0035] - The step of forming at least one layer of semiconductor material of interest on a buffer layer.

[0036] The semiconductor materials of interest are preferably IV-IV, III-V, II-VI semiconductor materials and / or 2D semiconductor materials.

[0037] According to one embodiment, the buffer layer is selectively formed on the

[111] -oriented silicon plane in each trench.

[0038] According to the present invention, the terms “selective,” “selectively,” and similarly “selective growth” and “selective passivation” are defined in the SAG sense, that is, in the trenches of the growth mask.

[0039] According to the present invention, a "2D material" refers to a material composed of thin sheets a few atoms thick (typically a maximum thickness of 10 atoms), with strong bonds between atoms in the plane of the sheet and weak van der Waals bonds outside the plane. It can also be called a "two-dimensional material" or a "layered material." Similarly, a "two-dimensional layer" refers to a layer made of 2D material, thus the material is composed of atomic sheets containing strong bonds in the plane of the sheet and weak van der Waals bonds outside the plane, for example, between two sheets or on the surface of a free sheet. Materials not structured as sheets but having ionic or covalent bonds throughout their entire volume can also be referred to as "3D materials," such as conventional semiconductor materials.

[0040] The present invention is a process for selectively growing a two-dimensional buffer layer without covalent or side bonds in the trenches of a growth mask (preferably made of dielectric) on a silicon substrate by MOCVD. The silicon substrate can be a standard Si(001) (also known as Si(100)) silicon substrate or a Si(111) silicon substrate.

[0041] The two-dimensional buffer layer is made of a two-dimensional material with suitable operating conditions. It can then be used as a universal substrate for the localized growth of any type of semiconductor of interest with reduced defect content (especially reduced through-dislocation density), resulting in optimal physicochemical properties. Specifically, growth on a two-dimensional buffer layer, in contrast to direct growth on a silicon substrate, allows overcoming differences in lattice parameters. It has no or very few covalent bonds or side bonds at the interface. The formation of this two-dimensional buffer layer is actually performed by promoting van der Waals epitaxial growth, enabling the formation of unconstrained materials that avoid relaxation processes caused by the generation of through dislocations. Therefore, this allows for the formation of a layer of semiconductor material of interest, which has a density of less than 10... 6 / cm 2 Crystal materials with penetrating dislocation density.

[0042] Among the advantages of the method of the present invention, it can be mentioned that:

[0043] - Semiconductor layers are generated on a standard silicon substrate by heteroepitaxial growth, such as Si(100)300mm used in the microelectronics industry, which has a low crystal defect density;

[0044] - The simplicity and low cost of the process, which requires only a few steps and can be performed in a standard manner;

[0045] - The technology is versatile: it can be envisioned to grow all types of semiconductors and heterostructures (IV-IV, III-V, II-VI, heterostructures of 2D materials, etc.), regardless of the differences in crystal structure and lattice parameters of silicon.

[0046] Furthermore, the growth of 3D semiconductor materials (GaAs, GaN, etc.) on 2D materials is typically very difficult on silicon substrates not structured as dielectric mask patterns due to the low nucleation rate of adsorbed atoms reaching the surface (due to the lack of side bonds in the 2D material). The term "adsorbed atoms" refers to atoms adsorbed on the substrate surface. This results in the growth of sparse islands on the surface. The selective growth process according to the invention, performed in trenches of the growth mask, allows nucleation to be concentrated in a very limited area of ​​the substrate: this significantly enhances the nucleation density and, in particular, allows for the growth of continuous layers of 3D material on 2D material.

[0047] The very low density of penetrating dislocations thus allows efficient integration of electronic components, optoelectronic components, sensors and imaging components, and generally any “beyond Moore’s Law” components, on silicon substrates with

[001] orientation or even

[111] orientation, which is especially compatible with CMOS technology.

[0048] Preferably, the mask pattern is made of a dielectric material.

[0049] According to one embodiment, the silicon substrate is a

[001] oriented silicon substrate. In this case, the structuring step further includes forming

[111] oriented silicon facets in the silicon substrate to form at least one

[111] oriented silicon plane. Each facet is formed via a trench, i.e., in the silicon substrate exposed at the bottom of the trench.

[0050] The facets may have a tilted surface with an angle of less than 90° relative to the surface of the silicon substrate in which the facets are formed.

[0051] According to a particular embodiment, two

[111] oriented silicon facets are formed in the trench, each facet having an inclined surface at an angle of less than 90° relative to the surface of the silicon substrate in which the facets are formed. Thus, the two facets can in particular form a V, with a first segment forming an angle of +54.7° relative to the substrate surface and a second segment forming an angle of -54.7° relative to the substrate surface.

[0052] The process of forming facets may include a process of chemically etching a silicon substrate, such as chemical etching based on tetramethylammonium hydroxide, tetraethylammonium hydroxide, ammonia, potassium hydroxide, or sodium hydroxide.

[0053] According to one embodiment, the silicon substrate is a

[111] oriented silicon substrate, and the surface of the substrate forms a

[111] oriented silicon plane.

[0054] According to one embodiment, the process further includes a passivation step comprising depositing an atomic biplane of gallium and selenium onto a

[111] -oriented silicon plane to form a silicon-gallium-selenium passivated surface on the silicon plane. The passivated surface may also be referred to as a "passivation layer".

[0055] According to a particular embodiment, the passivation step is performed between the structuring step and the step of forming the buffer layer.

[0056] The passivation process may include a metal-organic precursor vapor deposition (MOCVD) step.

[0057] Organometallic precursors can be trimethylgallium (TMGa) and diisopropylselenium (DiPSe).

[0058] According to one embodiment, the step of forming at least one buffer layer includes a van der Waals epitaxy and further includes:

[0059] - The first nucleation step of 2D materials on a passivated surface; and

[0060] - The first growth step performed on the nuclei obtained at the end of the first nucleation step.

[0061] The first nucleation step may include a metal-organic precursor vapor deposition (MOCVD) step.

[0062] Organometallic precursors can be trimethylgallium (TMGa) and diisopropylselenium (DiPSe).

[0063] According to one embodiment, the step of preparing at least one layer of the semiconductor material of interest includes an additional epitaxial step, which includes:

[0064] - A second nucleation step on the semiconductor of interest in the buffer layer; and

[0065] - A second growth step for the nucleated layer obtained at the end of the second nucleation step.

[0066] The second nucleation step may include a metal-organic precursor vapor deposition (MOCVD) step.

[0067] According to one embodiment, the process further includes at least one step prior to the step of forming a buffer layer or the passivation step, such as removing the natural oxide by chemical etching with hydrofluoric acid.

[0068] The width of the trench is typically less than or equal to 20 micrometers, and preferably less than or equal to 2 micrometers.

[0069] The 2D material of the buffer layer can be selected from GaSe, GaS, GaTe, MoS2, MoSe2, WS2, WSe2, InSe, or a combination of the aforementioned materials.

[0070] Semiconductor materials of interest can be selected from GaAs, GaSb, GaN, and AlN.

[0071] The second subject of the present invention is a structure obtained via a heterogeneous integration process according to the first subject of the present invention, the structure comprising:

[0072] -Silicon substrate;

[0073] - Multiple mask patterns located on a silicon substrate, with two mask patterns separated by trenches;

[0074] - A two-dimensional buffer layer located in each trench;

[0075] - A semiconductor material layer of interest located on a two-dimensional buffer layer and at least in each trench, the semiconductor material layer of interest having a density of less than 10 6 / cm 2 The density of penetrating dislocations.

[0076] Preferably, the semiconductor material of interest is IV-IV, III-V, II-VI semiconductor material and / or 2D semiconductor material.

[0077] Preferably, the mask pattern is made of a dielectric material.

[0078] Advantageously, the structure also includes a passivation layer made of silicon-gallium-selenium between the silicon substrate and the two-dimensional buffer layer. Attached Figure Description

[0079] Referring to the accompanying drawings, other features and advantages of the invention will become apparent from the following description, which is given for illustrative purposes, without any implied limitation, in the drawings:

[0080] Figure 1 This represents the first variant of selective epitaxial growth based on existing technology;

[0081] Figure 2A and Figure 2B This represents a second variant of selective epitaxial growth based on existing technology;

[0082] Figure 3 This represents the third variant of selective epitaxial growth based on existing technology;

[0083] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4L , Figure 4M , Figure 4N Examples and variations of the heterogeneous integration process according to the present invention are shown. Detailed Implementation

[0084] Figure 1 , Figure 2A , Figure 2B and Figure 3 The prior art has already been described above and will not be repeated here.

[0085] Figures 4A to 4N Examples and variations of the heterogeneous integration process according to the present invention are shown. In this example, the initial silicon substrate 1 has a

[001] crystal orientation and can therefore be represented as Si(001).

[0086] The process includes a step of structuring a

[001] oriented silicon substrate, which includes a step of fabricating a growth mask 2 on the surface of the substrate. Figure 4AThe growth mask 2 includes a mask pattern 20. The growth mask is preferably made of a dielectric material, typically SiO2 or SiN, which exhibits selectivity for etching relative to the silicon substrate. Two consecutive (or adjacent) mask patterns are separated from each other by a distance l. In this example, this distance l corresponds to the width of the trench 21. The trench corresponds to the area of ​​the substrate 1 that is not covered by the dielectric material (or "exposed area").

[0087] A mask pattern can be created by starting with a silicon substrate, performing thermal oxidation on the substrate to deposit an upper layer of silicon oxide (SiO2 layer), and then defining trenches by photolithography and etching into the SiO2 layer to expose the silicon surface at the bottom of each trench.

[0088] At this stage of the process, the trench has a depth h and a width l (the distance between the two patterns). The trench width l can be between tens of nanometers and 20 micrometers. Preferably, the trench width l is less than 2 micrometers. The length L of the mask pattern can be greater than tens of micrometers.

[0089] according to Figure 4B The example shown includes a structuring step that involves chemically etching the silicon substrate 1 in each trench 21 to form silicon facets 31, 32 with a

[111] orientation, which can be represented as Si(111). The Si(111) facets form V-shaped grooves in the silicon substrate 1.

[0090] Chemical etching can be anisotropic and can be performed using solutions based on tetramethylammonium or tetraethylammonium hydroxide diluted in water, or with ammonia, potassium hydroxide, or sodium hydroxide. The temperature of the solution during the etching step is typically between 20°C and 100°C.

[0091] Prior to chemical etching, a first step of removing native oxides (not shown) may be required, depending on the chemical etching solution used. This first step of removing native oxides is typically performed by chemical etching with hydrofluoric acid (HF), usually by exposing the substrate to a dilute hydrofluoric acid solution (e.g., a volume concentration of 0.2% to 1%) for 30 to 90 seconds.

[0092] Following the chemical etching step, the structuring step includes a second step of removing the native oxide from the silicon to obtain deoxidized Si(111) facets 31', 32', as follows: Figure 4C As shown. The second step in removing natural oxides is typically performed by chemical etching with hydrofluoric acid (HF), typically with a dilute hydrofluoric acid solution (e.g., a volume concentration of 0.5%) for 30 to 60 seconds.

[0093] If a

[111] oriented silicon substrate is used instead of a Si(001) substrate, a chemical etching step is not required to form a Si(111) plane.

[0094] If the available silicon substrate already has at least one

[111] oriented silicon plane, then a chemical etching step is not required: this may mean that the surface of the substrate is made of Si(111), or that the Si(001) substrate already includes Si(111) facets.

[0095] In the case of a Si(111) substrate, a growth mask can be designed on the silicon substrate such that the mask pattern exposes a portion of the Si(111) substrate. The steps described below can then be performed.

[0096] More generally, regardless of the orientation of the silicon substrate, the mask pattern must expose the silicon plane oriented

[111] .

[0097] In the case of a Si(001) substrate, the

[111] oriented plane will typically form a V, with the first segment forming an angle of +54.74° relative to the substrate and the second segment forming an angle of -54.74° relative to the substrate.

[0098] In the case of a Si(111) substrate, the exposed Si(111) plane will be essentially 0° relative to the substrate surface.

[0099] The process then includes a step of selectively passivating the Si(111) facets, which involves depositing atomic planes of gallium on the facets, followed by depositing atomic planes of selenium. Figure 4D This allows for the formation of a passivated silicon surface (also known as a "passivation layer") made of Si-Ga-Se, such as... Figure 4E As shown. This surface is electron-saturated and stable at high temperatures (up to approximately 650-700°C). This passivation layer 4 then enables the growth of 2D materials via van der Waals epitaxy, as described below.

[0100] The atomic plane of Ga bonded to the atomic plane of Se in this way can be called an "atomic biplane" and can be regarded as a half-sheet of "2D GaSe" material. Specifically, 2D GaSe refers to two-dimensional gallium selenide (as a sheet) composed of four atomic planes of the Se-Ga-Ga-Se sequence.

[0101] The terms “electron passivated surface” or “passivation layer” or “electron saturated surface” mean a surface without side bonds: all the valence electrons of the gallium and selenium atoms that make up the passivation layer are paired.

[0102] To perform this passivation step, a silicon substrate is typically introduced into a growth chamber, and GaSe atomic biplanes are deposited via metal-organic chemical vapor deposition (MOCVD). MOCVD is performed by transporting Ga and Se precursors introduced into the growth chamber via a carrier gas to form a passivation layer on the Si (111) facets exposed in the trenches of the growth mask.

[0103] To obtain the Si-Ga-Se passivation layer via MOCVD, organometallic precursors, typically trimethylgallium (TMGa) and diisopropylselenium (DiPSe), are simultaneously introduced into the chamber, both in a gaseous state at the operating temperature of the process. Alternatively, it can be any other gallium precursor and / or any other selenium precursor.

[0104] The carrier gas is usually hydrogen. Alternatively, it can be nitrogen or argon, or any other inert gas in column VIII of the periodic table.

[0105] The passivation process is typically performed between 400°C and 650°C.

[0106] The total pressure is adjusted according to the geometry of the chamber, but typical values ​​are between 5 Torr and 200 Torr.

[0107] The voltage division of gallium precursors is typically between 1 mTorr and 200 mTorr.

[0108] The III / VI molar flow ratio (Group III precursor / Group VI precursor) is typically between 1 and 10.

[0109] According to a specific embodiment, the conditions for the passivation step are:

[0110] - Total pressure in the chamber: 10-20 Torr;

[0111] - The voltage drop across TMGa is approximately 10 mTorr;

[0112] -Se / Ga(VI / III) molar flow ratio: approximately 3-4;

[0113] -Temperature: 530-550℃;

[0114] -Growth time t: between 2 and 5 seconds.

[0115] MOCVD technology is advantageous because it enables good reproducibility and high crystal growth rates. Furthermore, it is industrially applicable.

[0116] Alternatively, other chemical vapor deposition (CVD) techniques, such as atomic layer deposition (ALD), can be used.

[0117] As previously mentioned, following the passivation step, the process includes a van der Waals epitaxial step, which involves epitaxially growing a 2D material on the passivation layer 4 to form a two-dimensional buffer layer 5. Figure 4K As can be seen in the diagram. This epitaxial step typically includes a first nucleation step and a first nucleation step or a lateral growth step. These steps will be described in detail below.

[0118] The term "lateral growth" refers to the growth of each nucleus by extending primarily within the plane of the passivation layer, and more generally within the plane in which it is deposited.

[0119] In the example shown, buffer layer 5 is made of gallium selenide (2D GaSe) structured into a thin sheet. In other words, buffer layer 5 comprises at least one 2D GaSe sheet.

[0120] The first nucleation step is the GaSe nucleation step. The GaSe nucleation step is performed by depositing GaSe grains 51 onto the passivation layer 4. Figure 4F and Figure 4G As can be seen, the initial width of the GaSe core is equal to tens of nanometers.

[0121] To perform nucleation, the substrate is held in a growth chamber and MOCVD technology is used. The precursors that can be used are the same as those used in the passivation step. The partial pressure of the precursor used is less than that of the passivation step.

[0122] The carrier gas is usually hydrogen. Alternatively, it can be nitrogen, argon, or any other inert gas from column VIII of the periodic table.

[0123] The first nucleation step is usually performed between 400°C and 650°C.

[0124] The total pressure in the chamber is typically between 5 Torr and 80 Torr.

[0125] The partial pressure of Ga precursors is typically between 1 mTorr and 50 mTorr.

[0126] The VI / III molar flow ratio depends on the type of precursor. Typical values ​​are between 3 and 4.

[0127] According to a specific embodiment, the conditions for the first nucleation step are as follows:

[0128] - Total pressure in the chamber: 5-20 Torr;

[0129] - The voltage drop across TMGa is approximately 2-3 mTorr;

[0130] -Se / Ga(VI / III) molar flow ratio: approximately 3-4;

[0131] -Temperature: 530-550℃.

[0132] For a growth time t1 between 2 and 3 seconds, the core thickness reaches approximately

[0133] After nucleation, such as Figure 4H and Figure 4I As shown, the GaSe core is grown laterally for several micrometers until at least one continuous sheet is obtained on the

[111] oriented facet 52. Each 2D GaSe sheet is crystallographically oriented relative to the Si(111) surface, as shown... Figure 4J and Figure 4K As shown.

[0134] Figure 4K The buffer layer 5 is formed by two GaSe sheets located on the passivation layer 4: a lower sheet 52 and an upper sheet 53. The bond 54 between the lower sheet 52 and the passivation layer 4, and the bond 55 between the two sheets 52 and 53, are weak van der Waals bonds. The outer surface 56 of the upper sheet 53 has no side bonds.

[0135] Compared to the first nucleation step, this first growth step, or lateral growth step, of the GaSe grains is performed at a lower partial pressure and a higher temperature.

[0136] The substrate is held in the growth chamber.

[0137] The first growth step, or lateral growth step, is usually performed between 570°C and 650°C.

[0138] The total pressure in the chamber is typically between 5 Torr and 80 Torr.

[0139] The partial pressure of Ga precursors is typically between 0.5 mTorr and 5 mTorr.

[0140] The VI / III molar flow ratio depends on the type of precursor. Typical values ​​are between 3 and 4.

[0141] According to a specific embodiment, the conditions for the first growth step are as follows:

[0142] - Total pressure in the chamber: 5-20 Torr;

[0143] - The voltage drop across TMGa is approximately 1 mTorr;

[0144] -Se / Ga(VI / III) molar flow ratio: approximately 3-4;

[0145] -Temperature: 600-640℃.

[0146] The growth time t2 for GaSe grains to completely fuse into a continuous thin sheet is approximately 200 seconds.

[0147] To obtain continuous 2D GaSe sheets (approximately [thickness missing]) This requires a nucleation time t1 and a lateral growth time t2. Since t2 is much longer than t1, t1 can be ignored, and therefore a thin slice requires approximately 200 seconds, and through expansion;

[0148] - It takes about 400 seconds to prepare two thin slices;

[0149] - It takes about 600 seconds to cut three thin slices.

[0150] Therefore, the growth rate is approximately

[0151] The buffer layer is formed from one (or more) thin sheets of 2D material. In the example shown, buffer layer 5 is formed from two thin sheets 52 and 53 of 2D GaSe.

[0152] GaSe buffer layers can be stable up to approximately 950°C. They contain no side bonds. Therefore, they are suitable for epitaxial growth of semiconductor materials of interest (IV-IV, III-V, II-VI, 2D materials, etc.), such as GaAs in the example shown, without mechanical constraints.

[0153] Depending on the type of semiconductor material of interest to be epitaxially grown, the GaSe two-dimensional buffer layer can be replaced with a two-dimensional buffer layer made of a 2D material other than GaSe, while maintaining the passivation step of silicon (111) having atomic planes of gallium (Ga) followed by atomic planes of selenium (Se). Examples that can be mentioned include one of the following materials: GaS, GaTe, MoS2, MoSe2, WS2, WSe2, InSe. Several different layers from the aforementioned material combinations can be combined. Preferably, the 2D material is a material stable at temperatures up to 1000°C.

[0154] The process then includes an additional epitaxial step, which involves epitaxially growing the semiconductor material of interest, typically an IV-IV, III-V, II-VI semiconductor material, or a 2D semiconductor material, on a two-dimensional buffer layer. This additional epitaxial step typically includes a second nucleation step and a second growth step, the second growth step being rapid growth at high temperatures. These steps will be described in detail below.

[0155] In the example shown, the semiconductor material of interest is gallium arsenide (GaAs). Therefore, the second nucleation step is a GaAs nucleation step. However, this example is by no means limiting, and the process is the same for another semiconductor material, such as IV-IV, III-V, II-VI semiconductor materials, or 2D semiconductor materials. The semiconductor material of interest can be selected from GaAs, GaSb, GaN, AlN, or combinations thereof.

[0156] By selectively depositing a nucleation layer 6 made of gallium arsenide (GaAs) on the buffer layer 5, the following can be performed: Figure 4L The GaAs nucleation steps are shown.

[0157] The substrate is held in the growth chamber and MOCVD technology is used.

[0158] To obtain GaAs via MOCVD, organometallic precursors are used, typically TriMethylGallium (TMGa) and Ter-ButylArsine (TBA), which are gaseous at the operating temperature of the process. Alternatively, it can be any other gallium precursor and / or any other arsenic precursor.

[0159] The carrier gas is usually hydrogen. Alternatively, it can be nitrogen or helium, or any other inert gas in column VIII of the periodic table.

[0160] The second nucleation step is usually carried out between 350°C and 450°C.

[0161] Typical values ​​for total pressure in the chamber are between 80 Torr and 600 Torr.

[0162] The voltage divider of gallium precursors is typically between 0.5 Torr and 5 Torr.

[0163] The molar flow ratio is typically between 1.5 and 10.

[0164] According to a specific embodiment, the conditions for the second nucleation step are:

[0165] - Total pressure in the chamber: 200-450 Torr;

[0166] -Time: 200-400 seconds;

[0167] - The voltage drop across TMGa is approximately 1.5 Torr;

[0168] -As / Ga molar flow ratio: approximately 2.5;

[0169] -Temperature: 370-390℃.

[0170] like Figure 4Mor Figure 4N As shown, the second growth step is performed vertically in the trench. The substrate is held in the growth chamber.

[0171] The step of raising the temperature to cause GaAs nuclei to coalesce and to begin the rapid growth of GaAs at high temperature and low pressure makes it possible to obtain localized GaAs layers with excellent crystal quality.

[0172] The second growth step is usually performed between 550°C and 670°C.

[0173] Typical values ​​for total pressure in the chamber are between 5 Torr and 80 Torr.

[0174] The voltage divider of gallium precursors is typically between 10 mTorr and 50 mTorr.

[0175] The molar flow ratio is typically between 2.5 and 15.

[0176] According to a specific embodiment, the conditions for the second growth step are:

[0177] - Total pressure in the room: 20 Torr;

[0178] -Time: 300 seconds;

[0179] - The voltage drop across TMGa is approximately 30 mTorr;

[0180] -As / Ga molar flow ratio: approximately 3.5;

[0181] -Temperature: 570-630℃.

[0182] The resulting structures include:

[0183] -Silicon substrate 1;

[0184] - Multiple mask patterns 20 located on silicon substrate 1, with two mask patterns separated by trenches 21;

[0185] - Passivation layer 4 located in each trench;

[0186] - A two-dimensional buffer layer 5 is located on the passivation layer 4 in each trench;

[0187] - Semiconductor material layers 61 and 62 of interest, located on the two-dimensional buffer layer 5 and filling at least each trench, wherein the through-dislocation density of the semiconductor material layers of interest is less than 10-1. 6 / cm 2 .

[0188] Preferably, the semiconductor material of interest is IV-IV, III-V, II-VI semiconductor material and / or 2D semiconductor material.

[0189] Preferably, the mask pattern is made of a dielectric material.

[0190] In addition, such as Figure 4M As shown, the semiconductor material layer 61 of interest can be confined within the trench. Alternatively, the semiconductor material layer 62 of interest can be widened by lateral growth outside each trench, for example, to form horizontal nanowires with a square cross-section, such as... Figure 4N As shown.

[0191] In addition, the semiconductor material layer of interest preferably has a

[100] orientation.

[0192] Because the buffer layer of a two-dimensional material does not contain any side bonds, it can be used as a general substrate for the localized growth of semiconductors of interest, while reducing defect content (especially reducing the density of through dislocations), thus resulting in optimized physicochemical properties. Specifically, unlike direct growth on a silicon substrate, growth on a buffer layer of a two-dimensional material allows overcoming the problem of lattice parameter differences. By promoting van der Waals growth, there are no covalent bonds (or only a few) at the interface, enabling the formation of unconstrained materials, which avoids relaxation processes caused by the generation of through dislocations. Therefore, this allows for the formation of semiconductor material layers of interest, which have a density of less than 10... 6 / cm 2 Crystal materials with high penetration dislocation density. Semiconductor materials of interest are preferably single-crystal materials.

[0193] In addition, the selective growth of 3D semiconductor materials (GaAs, GaN, etc.) on 2D materials (i.e. without trenches between mask patterns) allows nucleation to be concentrated on a very limited number of regions on the substrate: this significantly increases the nucleation density and, in particular, allows for the growth of continuous layers of 3D materials on 2D materials.

[0194] The present invention is not limited to the embodiments previously described, but extends to any embodiments falling within the scope of the claims.

[0195] In the many applications of this invention, reference may be made to microelectronics, photonics, sensors, radio frequency related technologies, electromechanical microsystems (MEMS), Internet of Things components, battery chargers, high-voltage components, microprocessors, static and dynamic memory, photovoltaics, and any technology that more broadly relates to "beyond Moore's Law" technologies or derivative technologies, i.e., technologies that integrate several functions on the same silicon chip.

Claims

1. A process for heterogeneous integration of a semiconductor material of interest on a silicon substrate (1), characterized in that, The process includes: - The step of structuring the substrate includes the step of generating a growth mask (2) on the surface of the silicon substrate (1), the growth mask including a plurality of mask patterns (20), two mask patterns being separated by trenches (21) in which the silicon substrate (1) is exposed; - The step of forming a two-dimensional buffer layer (5) made of 2D material, the buffer layer having no side bonds on its free surface and selectively formed on a [111] oriented silicon plane (3) in at least one trench (21), the step of forming the buffer layer is performed after the structuring step and is performed by metal-organic vapor deposition (MOCVD) technology; - The step of forming at least one layer (61, 62) of the semiconductor material of interest on the buffer layer (5); - A passivation step, which includes depositing an atomic biplane of gallium and selenium onto the [111] oriented silicon plane (3) to form a silicon-gallium-selenium passivated surface (4) on the plane.

2. The process according to claim 1, wherein the semiconductor material of interest is IV-IV, III-V, II-VI semiconductor material and / or 2D semiconductor material.

3. The process according to any one of claims 1 and 2, wherein the mask pattern is made of a dielectric material.

4. The process according to any one of claims 1-2, wherein the silicon substrate (1) is a [001] oriented silicon (Si(001)) substrate, and the structuring step further comprises forming at least one [111] oriented silicon facet (31, 32) in the silicon substrate (1) to form at least a [111] oriented silicon plane (3), the facet being formed by trench (21).

5. The process according to claim 4, wherein the facet has an inclined surface having an angle of less than 90° relative to the substrate of the surface in which the facet is formed.

6. The process according to claim 5, wherein two silicon facets (31, 32) oriented in [111] are formed in the trench (21), each facet having an inclined surface having an angle of less than 90° relative to the substrate of the surface in which the facet is formed.

7. The process according to any one of claims 1-2, wherein the passivation step is performed between the structuring step and the step of forming the buffer layer (5).

8. The process according to any one of claims 1-2, wherein, The step of forming at least one buffer layer (5) includes a van der Waals epitaxy and includes: - The first nucleation step of the 2D material on the passivated surface (4); and - A first growth step performed on the nucleus (51) obtained at the end of the first nucleation step.

9. The process according to any one of claims 1-2, wherein the step of preparing at least one layer (61, 62) of the semiconductor material of interest includes an additional epitaxial step, said epitaxial step comprising: - A second nucleation step performed on the semiconductor of interest on the buffer layer (5); as well as - A second growth step is performed on the nucleated layer (6) obtained at the end of the second nucleation step.

10. The process according to any one of claims 1-2, wherein, The width of the groove (21) is less than or equal to 20 μm.

11. The process according to claim 10, wherein, The width of the groove (21) is less than or equal to 2 μm.

12. The process according to any one of claims 1-2, wherein the 2D material of the buffer layer (5) is selected from GaSe, GaS, GaTe, MoS2, MoSe2, WS2, WSe2, InSe or a combination of said materials.

13. The process according to any one of claims 1-2, wherein the semiconductor material of interest is selected from GaAs, GaSb, GaN and AlN.

14. A structure obtained via a heterogeneous integration process according to any one of claims 1 to 13, wherein the structure comprises: - Silicon substrate (1); - Multiple mask patterns (20) located on the silicon substrate (1), with two mask patterns separated by trenches (21); - A two-dimensional buffer layer (5) located in each trench (21); - A layer (61, 62) of semiconductor material of interest located on the two-dimensional buffer layer (5) and at least in each trench (21), the layer of semiconductor material of interest having a density of less than 10 6 / cm 2 Line dislocation density; A passivation layer (4) made of silicon-gallium-selenium is placed between the silicon substrate (1) and the two-dimensional buffer layer (5).

15. The structure according to claim 14, wherein the semiconductor material of interest is IV-IV, III-V, II-VI semiconductor material and / or 2D semiconductor material.

16. The structure according to any one of claims 14 to 15, wherein the layer (62) of the semiconductor material of interest fills each trench (21) and also extends to the outside of each trench to form a horizontal nanowire.

17. The structure according to any one of claims 14 to 15, wherein the layer of the semiconductor material of interest is a single-crystal material.

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