A battery pack open cell protection circuit

Abstract

The present invention provides a cell short - circuit protection circuit for a battery pack, which includes an upper - grouped battery Batt up , a lower - grouped battery Batt dn and a bidirectional power DCDC. A shunt resistor R up and a shunt resistor R dn are successively connected in series between the upper - grouped battery Batt up and the lower - grouped battery Batt dn . The bidirectional power DCDC includes a capacitor C1, a capacitor C2, an inductor L, a MOS transistor Q1, a MOS transistor Q2 and a shunt resistor Rm. It can detect the voltage and current of the battery pack in real time. When any group of batteries in the battery pack has a cell short - circuit, by managing the charging of the non - short - circuited grouped batteries, the non - short - circuited grouped batteries are used to provide uninterrupted power supply for the electrical equipment, ensuring the normal operation of the equipment.

Description

Technical Field

[0001] The present invention relates to the technical field of battery power supplies, and particularly to a disconnection protection circuit for a battery pack. Background Art

[0002] With the development of battery technology, backup battery power systems are widely used in various fields. Generally, the backup battery power is connected in parallel across the two ends of the main power supply device. When the main power supply is normal, it can charge the battery pack of the energy storage device of the backup power system to ensure sufficient energy of the backup power system during emergency use. In the case of a failure of the main power supply device, it can seamlessly switch to supply power to the electrical equipment by the backup battery power system to ensure the normal operation of the electrical equipment. Since the voltage of a single battery is relatively low (the nominal voltage of a single lead-acid battery is 2V, and the nominal voltage of a single lithium iron phosphate battery is 3.2V), multiple or even hundreds of single batteries need to be connected in series to provide sufficient voltage for the system. During the use of the series-connected batteries, the power supply energy of the power system may be insufficient or the entire group may not be able to output power supply due to the disconnection (open circuit) of individual single batteries. Moreover, it is difficult to detect this kind of failure when the main power supply is normal because the backup battery power system is not enabled.

[0003] Therefore, it is necessary to provide a battery disconnection detection and protection circuit that can detect the voltage and current of the battery pack in real time, accurately identify the disconnected battery in a timely manner, and ensure the continuous backup power supply and normal charging after the battery is disconnected through the control circuit. Summary of the Invention

[0004] In response to the needs in the prior art, the present invention provides a disconnection protection circuit for a battery pack, which can detect the voltage and current of the battery pack in real time. After any group of batteries in the battery pack is disconnected, by managing the charging of the non-disconnected grouped batteries, the non-disconnected grouped batteries are used to provide uninterrupted power supply for the electrical equipment to ensure the normal operation of the equipment.

[0005] A disconnection protection circuit for a battery pack includes an upper grouped battery Batt up and a lower grouped battery Batt dn and a bidirectional power DCDC. A shunt resistor R up is sequentially connected in series between the upper grouped battery Batt dn and the lower grouped battery Batt up and a shunt resistor R dn, the bidirectional power DCDC includes MOS transistor Q1, MOS transistor Q2, a controller, and capacitors C1 and C2 connected in series. The source electrode of MOS transistor Q1 is electrically connected to the drain electrode of MOS transistor Q2. The common terminal of MOS transistor Q1 and MOS transistor Q2 is electrically connected to the common terminal of capacitors C1 and C2 through an inductor L and a shunt resistor Rm in sequence. The drain electrode of MOS transistor Q1 is electrically connected to the other end of capacitor C1, and the source electrode of MOS transistor Q2 is electrically connected to the other end of capacitor C2. Denote the common terminal of capacitors C1 and C2 as connection terminal M and electrically connect it to the common terminal of shunt resistor Rup and shunt resistor Rdn. Denote the common terminal of the drain electrode of MOS transistor Q1 and capacitor C1 as connection terminal H and electrically connect it to the positive terminal of the upper battery pack Battup. Denote the common terminal of the source electrode of MOS transistor Q2 and capacitor C2 as connection terminal L and electrically connect it to the negative terminal of the lower battery pack Battdn;

[0006] The controller collects the voltages of connection terminal H and connection terminal L, collects the currents of shunt resistor Rup and shunt resistor Rdn, collects the peak current of shunt resistor Rm, calculates the limit value IRm of the peak current based on the voltages of connection terminal H and connection terminal L and the currents of shunt resistor Rup and shunt resistor Rdn, and controls MOS transistor Q1 and MOS transistor Q2 to perform switching inversion or synchronous rectification respectively according to the peak current and the limit value IRm.

[0007] Further: The controller includes STM32F334, a comparator, and a counter. STM32F334 generates and controls a PWM signal, and the PWM signal outputs two isolated PWM signals through an isolation drive circuit to drive MOS transistor Q1 and MOS transistor Q2 respectively.

[0008] Further: The controller is connected with an alarm.

[0009] Advantages of the present invention: 1. When a cell in either the upper or lower battery pack is short-circuited, the DCDC circuit can perform charging management on the battery pack without short-circuited cells, use the battery pack without short-circuited cells to provide uninterrupted power supply for electrical equipment, and ensure the normal operation of the equipment.

[0010] 2. It can detect the voltage and current of the battery pack in real time, understand the state of the backup battery power system in a timely and accurate manner, and avoid incalculable losses to the power station caused by the failure to detect battery system faults in time.

[0011] 3. When the battery pack is normal, it can balance the upper and lower battery packs.

[0012] 4. The circuit design is reasonable, the use effect is good, and on the basis of ensuring reliability, the production cost can be effectively reduced. Description of the Drawings

[0013] Figure 1 is the circuit diagram of the present invention;

[0014] Figure 2 Schematic diagram of inductor charging when the input is high and the output is low;

[0015] Figure 3 Schematic diagram of inductor discharging when the input is high and the output is low;

[0016] Figure 4 Curve graph of inductor current change when the input is high and the output is low;

[0017] Figure 5 Input-output curve graph;

[0018] Figure 6 Schematic diagram of the system floating charge when the battery does not fail;

[0019] Figure 7 Schematic diagram of the system charging when the battery does not fail;

[0020] Figure 8 Schematic diagram of the system discharging when the battery does not fail;

[0021] Figure 9 Schematic diagram of charging inside the system when Battup fails;

[0022] Figure 10 Schematic diagram of discharging inside the system when Battup fails. Specific implementation manner

[0023] The present invention will be described in detail below with reference to the accompanying drawings. The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described by referring to the accompanying drawings are exemplary and are only used to explain the present invention and should not be construed as limiting the present invention. The orientation terms such as left, middle, right, up, and down in the examples of the present invention are only relative concepts to each other or are referred to the normal use state of the product and should not be considered as restrictive.

[0024] A battery pack open cell protection circuit, as Figure 1 shown, includes an upper group of batteries Batt up and a lower group of batteries Batt dn and a bidirectional power supply DCDC. A shunt resistor R up is sequentially connected in series between the upper group of batteries Batt dn and the lower group of batteries Batt up and a shunt resistor R dn, the bidirectional power DCDC includes MOS transistor Q1, MOS transistor Q2, a controller, and capacitors C1 and C2 connected in series. The source electrode of MOS transistor Q1 is electrically connected to the drain electrode of MOS transistor Q2. The common terminal of MOS transistor Q1 and MOS transistor Q2 is sequentially electrically connected to the common terminal of capacitors C1 and C2 through inductor L and shunt resistor Rm. The drain electrode of MOS transistor Q1 is electrically connected to the other end of capacitor C1, and the source electrode of MOS transistor Q2 is electrically connected to the other end of capacitor C2. Denote the common terminal of capacitors C1 and C2 as connection terminal M and electrically connect it to the common terminal of shunt resistor Rup and shunt resistor Rdn. Denote the common terminal of the drain electrode of MOS transistor Q1 and capacitor C1 as connection terminal H and electrically connect it to the positive terminal of the upper battery pack Battup. Denote the common terminal of the source electrode of MOS transistor Q2 and capacitor C2 as connection terminal L and electrically connect it to the negative terminal of the lower battery pack Battdn;

[0025] The controller collects the voltages of connection terminals H and L, that is, the voltages of battery packs Battup and Battdn, collects the currents of shunt resistors Rup and Rdn, that is, the currents of battery packs Battup and Battdn, and collects the peak current of shunt resistor Rm. Calculate the limit value IRm of the peak current according to the voltages of connection terminals H and L and the currents of shunt resistors Rup and Rdn. Control MOS transistor Q1 and MOS transistor Q2 to perform switching inversion or synchronous rectification respectively according to the peak current and the limit value IRm. The controller is connected with an alarm.

[0026] When the upper end of the DCDC inputs and the lower end outputs, Q1 serves as the input switching transistor and Q2 serves as the synchronous rectification output transistor. When the lower end inputs and the upper end outputs, Q2 serves as the input switching transistor and Q1 serves as the synchronous rectification output transistor. The DCDC adopts a current-mode working mode to control the maximum value of the current on the inductor to achieve the control of the input and output voltage and current. Collect the current of shunt resistor Rm, that is, the current on the inductor. When the current peak reaches the controlled value or the maximum duty cycle moment, the switching transistor turns off. Control the turn-off of the synchronous rectification transistor according to the zero value of the inductor current or the maximum duty cycle moment.

[0027] Among them, the controller includes STM32F334, a comparator, and a counter. STM32F334 generates and controls the PWM signal. The PWM signal outputs two isolated PWM signals through the isolation drive circuit to drive MOS transistor Q1 and MOS transistor Q2 respectively. The isolation drive circuit is a drive circuit with drive transformer T1 as the core.

[0028] The working principle of the present invention:

[0029] When the DCDC has high - end input voltages H+ and M-, the low - end outputs are voltages M+ and L-. During the working process, when there is high - end input, Q1 is used as a switching device and Q2 is used as a synchronous rectification device. From time T0 to T1, Q1 conducts and Q2 turns off. The high - end power source charges the inductor, and the inductor stores energy. The schematic diagram of the working mode is shown in Figure 2 . From time T1 to T2, Q2 conducts and Q1 turns off. The high - end power source discharges through the inductor, releasing energy and outputting at the low - end. The schematic diagram of the working process is shown in Figure 3 . The above is the working process of one cycle of high - end input and low - end output. The inductor current has three working modes: continuous conduction mode (CM), discontinuous conduction mode (DCM), and diode - emulation mode (DM), as shown in Figure 4 . Among them, the high - end voltage, low - end voltage, high - end current, and low - end current, after being converted by the ADC, together with the corresponding set values, perform PID feedback calculations to give the limit value of the peak current. The peak current limit value and the peak current are compared by the peripheral comparator of the STM32F334 to generate a comparison result. The result, together with the peripheral HRtrim counter of the STM32F334, controls the generation of the PWM signal to control Q1 and Q2 to play the role of switching inversion or synchronous rectification, and controls the duty cycle of the PWM signal to control the input (output) voltage and current of the DCDC.

[0030] Conversely, when there is low - end input with voltages M+ and L-, Q1 acts as a synchronous rectifier and Q2 acts as a switching tube, and the high - end outputs voltages H+ and M-, realizing bidirectional controllable energy flow. Both the high - end and low - end can be at constant voltage and constant current at the set voltage and current values. When at constant voltage, the current can be negative (when the input is negative).

[0031] The input - output curve of the system is shown in Figure 5 . In the figure, Iset and Vset are the set voltage or current values at one end (high - end or low - end). The high - end values are Vhset and Ihset, and the low - end values are Vlset and Ilset. Imax and Vmax are the protection values of the DCDC module. They form the output curve Output_curve, input curve Input_curve, output area Output_area, and input area Input_area. When both the high - end or low - end voltage and current are positive, it is output in the first quadrant; when the voltage is positive and the current is negative, in the fourth quadrant, it is input.

[0032] When the DCDC is working, one end (high - end or low - end) must work on the input or output curve, that is, in the state of constant - current input, constant - voltage input, constant - current output, or constant - voltage output. The other end works on the output or input curve or within the area. If one end works in the first quadrant, the other end must work in the fourth quadrant.

[0033] When Vl > Vlset and Vh < Vhset: The DCDC works in the low - end input constant - current or high - end output constant - current mode.

[0034] When Vl > Vlset and Vh = Vhset: The DCDC operates in the high - end output constant - voltage mode.

[0035] When Vl > Vlset and Vh > Vhset: The DCDC operates in the standby mode.

[0036] When Vl = Vlset and Vh < Vhset: The DCDC operates in the low - end input constant - voltage mode.

[0037] When Vl = Vlset and Vh = Vhset: The DCDC operates in the low - end output constant - voltage mode or the low - end input constant - voltage mode or the high - end input constant - voltage mode or the high - end output constant - voltage mode.

[0038] When Vl = Vlset and Vh > Vhset: The DCDC operates in the low - end output constant - voltage mode.

[0039] When Vl < Vlset and Vh < Vhset: The DCDC operates in the standby mode.

[0040] When Vl < Vlset and Vh = Vhset: The DCDC operates in the high - end input constant - voltage mode.

[0041] When Vl < Vlset and Vh > Vhset: The DCDC operates in the low - end output constant - current mode or the high - end input constant - current mode.

[0042] The above - mentioned operating modes change with the changes of the set value and the battery voltage, and the switching is continuous in the middle. The input constant - current mode is only an overload protection mode and should not appear during normal use, so it will no longer appear in the following introduction.

[0043] In this application, if the number of battery cells in the Battup and Battdn two groups is exactly the same, then Vhset and Vlset at both ends (high - end and low - end) are both the maximum value of the average voltage of the upper and lower two groups of batteries (that is, half of the voltage of the entire battery pack) and half of the battery - pack voltage alarm value, which are hereinafter collectively referred to as Vset. In this application, Vset changes in real - time with the change of the battery voltage. Ihset and Ilset are the set charging current values of the battery, which are hereinafter collectively referred to as Iset.

[0044] System operating scenario analysis:

[0045] 1. When the battery does not fail

[0046] During the charging and discharging process of the DCDC, it plays a role in balancing the voltages of the Battup and Battdn two groups, and finally makes the voltages of the two groups of batteries the same.

[0047] a) Static or floating charge

[0048] When Vh > Vl, Vset = (Vh + Vl) / 2, then Vh > Vset and Vl < Vset. The DCDC operates in the state of high - end input and low - end output. The schematic diagram of the system floating charge is shown in Figure 6 shown. The DCDC operates in the high - end input constant voltage or low - end output constant current or low - end output constant voltage mode until the two grouped voltages of Vh and Vl are equal, and then enters the input constant voltage or output constant voltage mode.

[0049] The analysis for Vh < Vl is the same as that for Vh > Vl.

[0050] When Vh = Vl, the DCDC operates in the state of high - end input constant voltage or high - end output constant voltage or low - end input constant voltage or low - end output constant voltage. Which specific working state is random. At this time, the DCDC has no output current and the power consumption is the smallest.

[0051] b) Charging

[0052] 1) The charging current is equal to Iset

[0053] When Vh > Vl, since Vset = (Vh + Vl) / 2, then Vh > Vset and Vl < Vset. The DCDC operates in the high - end input and low - end output constant current mode. Because the DCDC current sampling is in the main circuit, the low - end charging current Il sampled by the DCDC is already equal to Iset, so the DCDC actually operates in a no - output state. In fact, both the upper and lower grouped batteries are charged with the current Iset.

[0054] The analysis for Vh < Vl is the same as that for Vh > Vl.

[0055] When Vh = Vl, the DCDC randomly operates in the state of high - end input constant voltage or high - end output constant voltage (constant current) or low - end input constant voltage or low - end output constant voltage (constant current). Which specific working state is random. At this time, the DCDC has no output current and the power consumption is the smallest.

[0056] 2) The charging current is less than Iset

[0057] Assume Vh > Vl. Since Vhet = (Vh + Vl) / 2, then Vh > Vset and Vl < Vset. The DCDC operates in the high - end input and low - end output constant current mode. Because the DCDC current sampling is in the main circuit, the actual charging current of the low - end battery Il already includes Ichg. The actual low - end output current is Iset - Ichg. That is to say, Battdn is still charged with a constant current of Iset. Battup is charged with a current less than the charging current or even in a discharging state until the two grouped voltages are the same. The schematic diagram of the system charging is shown in Figure 7 shown.

[0058] The analysis for Vh < Vl can be deduced by analogy.

[0059] When Vh = Vl, the DCDC randomly operates in the state of high - end input constant voltage, high - end output constant voltage, low - end input constant voltage, or low - end output constant voltage. Which specific operating state is random. At this time, the DCDC has no output current and the power consumption is the smallest.

[0060] c) Discharging

[0061] When Vh > Vl, the DCDC operates in the low - end output constant - current mode until the voltages of the two groups are the same. When operating in the output constant - current mode, since the low - end sampling current includes Idcg, the actual low - end output current of the DCDC is Idcg + Iset. The schematic diagram of the system discharging is shown in Figure 8 shown.

[0062] 2. When the battery fails

[0063] a) Charging

[0064] Assume that Battup has a cell open - circuit. The overall battery pack is in an open - circuit state. The voltage of the battery pack is equal to the output voltage of the charger and is greater than twice the voltage Vl of Battdn. So, Vl < Vset, Vh > Vset. At this time, the DCDC operates in the low - end output constant - current mode to perform constant - current charging on Battdn. Until the voltage Vl reaches 1 / 2 of the charger voltage. At this time, Vl = Vset, Vh = Vset, and then perform constant - voltage charging on Battdn. Therefore, normal charging management of Battdn can be achieved after Battup has a cell open - circuit. The schematic diagram of the charging in the system when Battup fails is shown in Figure 9 shown.

[0065] After Battdn has a cell open - circuit, the analysis is similar by analogy.

[0066] b) Discharging

[0067] Assume that Battup has a broken cell, the entire battery pack is in an open circuit state, and the charger loses power. The voltage of the battery pack is 0. At this time, take half of the battery low voltage warning value Vllmt as Vset. It is less than twice the voltage Vl of Battdn. So there is Vl > Vset, Vh < Vset. Because Battup has a broken cell, the high-end output current is always 0. At this time, DCDC works at constant voltage for high-end output. After being connected in series with Battdn and the voltage is boosted, it supplies power to the load. At this time, Vset is 1 / 2Vllmt, and the voltage output of the battery pack is Vl + Vh = Vl + Vset = Vl + (1 / 2Vllmt), which is greater than Vllmt. Since Vset is the maximum value of the average voltage of the upper and lower two groups of batteries (that is, half of the voltage of the entire battery pack) and half of the battery pack Vllmt, Vset will be increased to (Vl + 1 / 2Vllmt) / 2. As Vset increases, Vh also increases accordingly until Vh = Vl, enabling the battery pack to supply power to the load at twice the voltage of Battdn. In actual use, when Battup suddenly has a broken cell, or the charger suddenly loses power after the broken cell occurs, since Vset always exists, during the voltage drop process of the battery pack, the state conversion to high-end output has been completed and the voltage will not drop. Whether taking half of Vllmt as Vset or taking half of the original battery pack voltage as Vset, the power supply to the load will not be interrupted. Therefore, uninterrupted power supply to the load can be achieved when Battup has a broken cell. The schematic diagram of the internal discharge of the system during Battup failure is shown in Figure 10 as shown

[0068] After Battdn has a broken cell, the analysis is similar by analogy.

[0069] 3. Battery Fault Detection

[0070] Although DCDC can meet the demand for re-discharge after a broken cell in the battery, since the battery capacity is reduced by half and the power supply time is greatly shortened, it is necessary to give a fault alarm for the broken cell in time. In the above analysis, during the charging and discharging process, it can be judged that the battery has a broken cell. Only during floating charge, when Vl = Vh, it is impossible to accurately judge the situation of the broken cell in the battery. At this time, DCDC will regularly and automatically increase a Δ value to Vhset and decrease a Δ value to Vlset, start the low-end input and high-end output mode, and detect the battery current. Then decrease a Δ value to Vhset and increase a Δ value to Vlset. Start the low-end output and high-end input mode to detect the battery current. To judge whether the battery has a broken cell and give an alarm

[0071] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. What is described in the above embodiments and the specification only illustrates the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of the present invention claimed is defined by the appended claims and their equivalents.

Claims

1. A battery pack open cell protection circuit, characterized in that: Including an upper grouped battery Batt up and a lower grouped battery Batt dn and a bidirectional power supply DCDC. A shunt resistor R up is sequentially connected in series between the upper grouped battery Batt dn and the lower grouped battery Batt up and a shunt resistor R dn . The bidirectional power supply DCDC includes an MOS transistor Q1, an MOS transistor Q2, a controller, and capacitors C1 and C2 connected in series. The source electrode of the MOS transistor Q1 is electrically connected to the drain electrode of the MOS transistor Q2. The common terminal of the MOS transistor Q1 and the MOS transistor Q2 is sequentially electrically connected to the common terminal of the capacitors C1 and C2 through an inductor L and a shunt resistor Rm. The drain electrode of the MOS transistor Q1 is electrically connected to the other end of the capacitor C1. The source electrode of the MOS transistor Q2 is electrically connected to the other end of the capacitor C2. The common terminal of the capacitors C1 and C2 is denoted as connection terminal M and is electrically connected to the common terminal of the shunt resistors Rup and Rdn. The common terminal of the drain electrode of the MOS transistor Q1 and the capacitor C1 is denoted as connection terminal H and is electrically connected to the positive electrode end of the upper grouped battery Battup. The common terminal of the source electrode of the MOS transistor Q2 and the capacitor C2 is denoted as connection terminal L and is electrically connected to the negative electrode end of the lower grouped battery Battdn. The controller collects the voltages of connection terminal H and connection terminal L, collects the currents of the shunt resistors Rup and Rdn, and collects the peak current of the shunt resistor Rm. The limit value IRm of the peak current is calculated according to the voltages of connection terminal H and connection terminal L and the currents of the shunt resistors Rup and Rdn. The MOS transistor Q1 and the MOS transistor Q2 are respectively controlled to perform switching inversion or synchronous rectification according to the peak current and the limit value IRm. The controller includes an STM32F334, a comparator, and a counter. The STM32F334 generates and controls a PWM signal. The PWM signal outputs two isolated PWM signals through an isolation drive circuit to respectively drive the MOS transistor Q1 and the MOS transistor Q2; When the DCDC has high-end input H+ and M- voltages, it outputs low-end M+ and L- voltages; during the working process, when there is high-end input, Q1 is used as a switching device and Q2 is used as a synchronous rectification device; from time T0 to T1, Q1 conducts and Q2 turns off, and the high-end power source charges the inductor, and the inductor stores energy; from time T1 to T2, Q2 conducts and Q1 turns off, and the high-end power source discharges through the inductor, releasing energy and outputting at the low end. The above is the working process of one cycle of high-end input and low-end output; among them, the high-end voltage, low-end voltage, high-end current and low-end current, after being converted by the ADC, together with the corresponding set values, perform PID feedback calculation to give the limit value of the peak current. The peak current limit value and the peak current are compared by the peripheral comparator of STM32F334 to generate a comparison result. The result, together with the peripheral HRtrim counter of STM32F334, controls the generation of the PWM signal to control Q1 and Q2 to play the role of switching inversion or synchronous rectification, and controls the duty cycle of the PWM signal to control the input voltage and current of the DCDC; conversely, when there is low-end input of M+ and L- voltages, Q1 is used as a synchronous rectification tube and Q2 is used as a switching tube, and high-end H+ and M- voltages are output to achieve bidirectional controllable flow of energy; both the high and low ends can be constant voltage and constant current at the set voltage and current values. When in constant voltage, the current is negative.

2. A battery pack open cell protection circuit according to claim 1, characterized in that: The controller is connected with an alarm.

Images