A New High Voltage Transmission Gate Circuit

Abstract

The present invention relates to the technical field of high-voltage analog integrated circuit design, and specifically discloses a new type of high-voltage transmission gate circuit, including a gate drive circuit and a high-voltage switch tube circuit; wherein the gate drive circuit is used to provide a high-voltage gate control signal to the high-voltage switch tube circuit under the control of a switch current signal; and the high-voltage switch tube circuit is used to isolate or transmit a high-voltage input signal according to the high-voltage gate control signal. The new type of high-voltage transmission gate circuit provided by the present invention has the advantages of high isolation, low interference, and can be directly cascaded, and can especially overcome the shortcomings of the transmission gate in the prior art that interferes with the signal source and the output node cannot be cascaded.

Description

Technical Field

[0001] The present invention relates to the technical field of high-voltage analog integrated circuit design, and more specifically, to a novel high-voltage transmission gate circuit. Background Art

[0002] High-voltage transmission gate circuits are used in various systems and are key circuits in high-voltage multiplexers, especially in battery management systems, where they are used to select different battery signals.

[0003] In the high-voltage BCD process, DMOS devices can achieve high-voltage resistance between the drain and source, but due to process limitations, the gate and source generally cannot withstand high voltage. Therefore, the gate control signal of the high-voltage transmission gate needs to be carefully designed.

[0004] Traditional high voltage transmission gate circuits such as Figure 1 As shown, the gate control signal size of the high-voltage switch tubes P1 and P2 of the circuit is determined by the voltage drop of the first resistor R1, and VS is the switch control signal; since the resistors R1 and R2 are directly connected to the high-voltage input signal node A, when the switch is in the on state, the current signal flowing through the resistors R1 and R2 will interfere with the input signal, and will introduce a large error in some high-precision occasions; in addition, the high-voltage transmission gate of this structure may have the possibility of the switch tubes P1 and P2 substrate diodes being turned on, so the output node B cannot be cascaded when applied. Summary of the invention

[0005] In order to solve the deficiencies in the prior art, the present invention provides a novel high-voltage transmission gate circuit, which can overcome the shortcomings of the prior art that the gate control signal interferes with the input signal and the output node cannot be cascaded.

[0006] As a first aspect of the present invention, a novel high-voltage transmission gate circuit is provided, comprising a gate drive circuit and a high-voltage switch tube circuit; wherein:

[0007] The gate drive circuit is used to provide a high-voltage gate control signal for the high-voltage switch tube circuit under the control of a switch current signal;

[0008] The high-voltage switch tube circuit is used to isolate or transmit a high-voltage input signal according to the high-voltage gate control signal.

[0009] Further, the gate drive circuit includes a first NMOS tube N1, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, and a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; the high-voltage switch tube circuit includes a second NMOS tube N2 and a third NMOS tube N3; wherein,

[0010] The gate of the first NMOS transistor N1 is respectively connected to the high voltage input signal A terminal and the cathode of the third diode D3, the drain is connected to one end of the first resistor R1, and the source is respectively connected to the anode of the third diode D3, the drain of the fifth NMOS transistor N5, one end of the third resistor R3 and the anode of the first diode D1;

[0011] The gate of the fifth NMOS transistor N5 is connected to the bias signal VB2, the drain is respectively connected to the anode of the third diode D3, the source of the first NMOS transistor N1, one end of the third resistor R3 and the anode of the first diode D1, and the source is connected to the drain of the seventh NMOS transistor N7;

[0012] The gate of the seventh NMOS transistor N7 is connected to the bias signal VB1, the drain is connected to the source of the fifth NMOS transistor N5, and the source is connected to the ground;

[0013] The gate of the fourth NMOS transistor N4 is respectively connected to the high voltage output signal B terminal and the cathode of the fourth diode D4, the drain is connected to one end of the second resistor R2, and the source is respectively connected to the anode of the fourth diode D4, the drain of the sixth NMOS transistor N6, one end of the fourth resistor R4 and the anode of the second diode D2;

[0014] The gate of the sixth NMOS transistor N6 is connected to the bias signal VB2, the drain is respectively connected to the anode of the fourth diode D4, the source of the fourth NMOS transistor N4, one end of the fourth resistor R4 and the anode of the second diode D2, and the source is connected to the drain of the eighth NMOS transistor N8;

[0015] The gate of the eighth NMOS transistor N8 is connected to the bias signal VB1, the drain is connected to the source of the sixth NMOS transistor N6, and the source is connected to the ground;

[0016] The gate of the first PMOS transistor P1 is connected to its own drain, and its gate and drain are also respectively connected to the gate of the second PMOS transistor P2, the gate of the third PMOS transistor P3, and the source of the fourth PMOS transistor P4, and its source is connected to the power supply terminal VDD;

[0017] The gate of the second PMOS transistor P2 is respectively connected to the gate and source of the first PMOS transistor P1, the source of the fourth PMOS transistor P4 and the gate of the third PMOS transistor P3, the drain is connected to the source of the fifth PMOS transistor P5, and the source is connected to the power supply terminal VDD;

[0018] The gate of the third PMOS transistor P3 is respectively connected to the gate and source of the first PMOS transistor P1, the source of the fourth PMOS transistor P4 and the gate of the second PMOS transistor P2, the drain is connected to the source of the sixth PMOS transistor P6, and the source is connected to the power supply terminal VDD;

[0019] The gate of the fourth PMOS transistor P4 is connected to its own drain, and its gate and drain are also respectively connected to the switch current signal IS terminal, the gate of the fifth PMOS transistor P5 and the gate of the sixth PMOS transistor P6, and the source is respectively connected to the drain and gate of the first PMOS transistor P1, the gate of the second PMOS transistor P2 and the gate of the third PMOS transistor P3;

[0020] The gate of the fifth PMOS transistor P5 is respectively connected to the gate and drain of the fourth PMOS transistor P4, the gate of the sixth PMOS transistor P6, and the switch current signal IS terminal, the drain is respectively connected to the other end of the third resistor R3, the gate of the second NMOS transistor N2, and the cathode of the first diode D1, and the source is connected to the drain of the second PMOS transistor P2;

[0021] The gate of the sixth PMOS transistor P6 is respectively connected to the gate and drain of the fourth PMOS transistor P4, the gate of the fifth PMOS transistor P5, and the switch current signal IS terminal, the drain is respectively connected to the other end of the fourth resistor R4, the gate of the third NMOS transistor N3, and the cathode of the second diode D2, and the source is connected to the drain of the third PMOS transistor P3;

[0022] The cathode of the first diode D1 is respectively connected to one end of the third resistor R3, the drain of the fifth PMOS transistor P5 and the gate of the second NMOS transistor N2, and the anode is respectively connected to the other end of the third resistor R3, the anode of the third diode D3, the source of the first NMOS transistor N1 and the drain of the fifth NMOS transistor N5;

[0023] The cathode of the second diode D2 is respectively connected to one end of the fourth resistor R4, the drain of the sixth PMOS transistor P6 and the gate of the third NMOS transistor N3, and the anode is respectively connected to the other end of the fourth resistor R4, the anode of the fourth diode D4, the source of the fourth NMOS transistor N4 and the drain of the sixth NMOS transistor N6;

[0024] The cathode of the third diode D3 is respectively connected to the high voltage input signal A terminal and the gate of the first NMOS transistor N1, and the anode is respectively connected to the source of the first NMOS transistor N1, the drain of the fifth NMOS transistor N5, one end of the third resistor R3 and the anode of the first diode D1;

[0025] The cathode of the fourth diode D4 is respectively connected to the high voltage output signal B terminal and the gate of the fourth NMOS transistor N4, and the anode is respectively connected to the source of the fourth NMOS transistor N4, the drain of the sixth NMOS transistor N6, one end of the fourth resistor R4 and the anode of the second diode D2;

[0026] One end of the first resistor R1 is connected to the power supply terminal VDD, and the other end is connected to the drain of the first NMOS transistor N1;

[0027] One end of the second resistor R2 is connected to the power supply terminal VDD, and the other end is connected to the drain of the fourth NMOS transistor N4;

[0028] One end of the third resistor R3 is respectively connected to the cathode of the first diode D1, the drain of the fifth PMOS transistor P5 and the gate of the second NMOS transistor N2, and the other end is respectively connected to the anode of the first diode D1, the anode of the third diode D3, the source of the first NMOS transistor N1 and the drain of the fifth NMOS transistor N5;

[0029] One end of the fourth resistor R4 is respectively connected to the cathode of the second diode D2, the drain of the sixth PMOS transistor P6 and the gate of the third NMOS transistor N3, and the other end is respectively connected to the anode of the second diode D2, the anode of the fourth diode D4, the source of the fourth NMOS transistor N4 and the drain of the sixth NMOS transistor N6;

[0030] The gate of the second NMOS transistor N2 is respectively connected to one end of the third resistor R3, the drain of the fifth PMOS transistor P5 and the cathode of the first diode D1, the drain is connected to the drain of the third NMOS transistor N3, and the source is connected to the high voltage input signal A terminal;

[0031] The gate of the third NMOS transistor N3 is respectively connected to one end of the fourth resistor R4, the drain of the sixth PMOS transistor P6 and the cathode of the second diode D2, the drain is connected to the drain of the second NMOS transistor N2, and the source is connected to the high voltage output signal B terminal.

[0032] Furthermore, the first NMOS transistor N1 is a source follower.

[0033] Furthermore, the fourth NMOS transistor N4 is a source follower.

[0034] The novel high-voltage transmission gate circuit provided by the present invention has the following advantages: the circuit adopts two source followers N1 and N4 to isolate the high-voltage input signal A end from the high-voltage output signal B end, so the high-voltage gate control signal provided by the gate drive circuit will not interfere with the high-voltage input signal A end and the high-voltage output signal B end, which can overcome the shortcomings of the prior art that the gate control signal interferes with the high-voltage input signal and the output node cannot be cascaded, so as to achieve the advantages of high isolation, low interference and cascadability. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation of the present invention.

[0036] Figure 1 The figure is a schematic diagram of the working principle of a conventional high voltage transmission gate circuit in the prior art.

[0037] Figure 2 A schematic diagram of the working principle of the novel high-voltage transmission gate circuit provided by the present invention. DETAILED DESCRIPTION

[0038] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the specific implementation method, structure, characteristics and effects of the new high-voltage transmission gate circuit proposed by the present invention are described in detail below in combination with the accompanying drawings and preferred embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the present invention.

[0039] In this embodiment, a new type of high voltage transmission gate circuit is provided, such as Figure 2 As shown, the novel high-voltage transmission gate circuit includes a gate drive circuit 21 and a high-voltage switch tube circuit 22; wherein,

[0040] The gate drive circuit 21 is used to provide a high-voltage gate control signal to the high-voltage switch tube circuit 22 under the control of a switch current signal;

[0041] The high-voltage switch tube circuit 22 is used to isolate or transmit a high-voltage input signal according to the high-voltage gate control signal.

[0042] Preferably, if Figure 2As shown, the gate drive circuit 21 includes a first NMOS tube N1, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, and a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; the high-voltage switch tube circuit 22 includes a second NMOS tube N2 and a third NMOS tube N3; wherein,

[0043] The gate of the first NMOS transistor N1 is respectively connected to the high voltage input signal A terminal and the cathode of the third diode D3, the drain is connected to one end of the first resistor R1, and the source is respectively connected to the anode of the third diode D3, the drain of the fifth NMOS transistor N5, one end of the third resistor R3 and the anode of the first diode D1;

[0044] The gate of the fifth NMOS transistor N5 is connected to the bias signal VB2, the drain is respectively connected to the anode of the third diode D3, the source of the first NMOS transistor N1, one end of the third resistor R3 and the anode of the first diode D1, and the source is connected to the drain of the seventh NMOS transistor N7;

[0045] The gate of the seventh NMOS transistor N7 is connected to the bias signal VB1, the drain is connected to the source of the fifth NMOS transistor N5, and the source is connected to the ground;

[0046] The gate of the fourth NMOS transistor N4 is respectively connected to the high voltage output signal B terminal and the cathode of the fourth diode D4, the drain is connected to one end of the second resistor R2, and the source is respectively connected to the anode of the fourth diode D4, the drain of the sixth NMOS transistor N6, one end of the fourth resistor R4 and the anode of the second diode D2;

[0047] The gate of the sixth NMOS transistor N6 is connected to the bias signal VB2, the drain is respectively connected to the anode of the fourth diode D4, the source of the fourth NMOS transistor N4, one end of the fourth resistor R4 and the anode of the second diode D2, and the source is connected to the drain of the eighth NMOS transistor N8;

[0048] The gate of the eighth NMOS transistor N8 is connected to the bias signal VB1, the drain is connected to the source of the sixth NMOS transistor N6, and the source is connected to the ground;

[0049] The gate of the first PMOS transistor P1 is connected to its own drain, and its gate and drain are also respectively connected to the gate of the second PMOS transistor P2, the gate of the third PMOS transistor P3, and the source of the fourth PMOS transistor P4, and its source is connected to the power supply terminal VDD;

[0050] The gate of the second PMOS transistor P2 is respectively connected to the gate and source of the first PMOS transistor P1, the source of the fourth PMOS transistor P4 and the gate of the third PMOS transistor P3, the drain is connected to the source of the fifth PMOS transistor P5, and the source is connected to the power supply terminal VDD;

[0051] The gate of the third PMOS transistor P3 is respectively connected to the gate and source of the first PMOS transistor P1, the source of the fourth PMOS transistor P4 and the gate of the second PMOS transistor P2, the drain is connected to the source of the sixth PMOS transistor P6, and the source is connected to the power supply terminal VDD;

[0052] The gate of the fourth PMOS transistor P4 is connected to its own drain, and its gate and drain are also respectively connected to the switch current signal IS terminal, the gate of the fifth PMOS transistor P5 and the gate of the sixth PMOS transistor P6, and the source is respectively connected to the drain and gate of the first PMOS transistor P1, the gate of the second PMOS transistor P2 and the gate of the third PMOS transistor P3;

[0053] The gate of the fifth PMOS transistor P5 is respectively connected to the gate and drain of the fourth PMOS transistor P4, the gate of the sixth PMOS transistor P6, and the switch current signal IS terminal, the drain is respectively connected to the other end of the third resistor R3, the gate of the second NMOS transistor N2, and the cathode of the first diode D1, and the source is connected to the drain of the second PMOS transistor P2;

[0054] The gate of the sixth PMOS transistor P6 is respectively connected to the gate and drain of the fourth PMOS transistor P4, the gate of the fifth PMOS transistor P5, and the switch current signal IS terminal, the drain is respectively connected to the other end of the fourth resistor R4, the gate of the third NMOS transistor N3, and the cathode of the second diode D2, and the source is connected to the drain of the third PMOS transistor P3;

[0055] The cathode of the first diode D1 is respectively connected to one end of the third resistor R3, the drain of the fifth PMOS transistor P5 and the gate of the second NMOS transistor N2, and the anode is respectively connected to the other end of the third resistor R3, the anode of the third diode D3, the source of the first NMOS transistor N1 and the drain of the fifth NMOS transistor N5;

[0056] The cathode of the second diode D2 is respectively connected to one end of the fourth resistor R4, the drain of the sixth PMOS transistor P6 and the gate of the third NMOS transistor N3, and the anode is respectively connected to the other end of the fourth resistor R4, the anode of the fourth diode D4, the source of the fourth NMOS transistor N4 and the drain of the sixth NMOS transistor N6;

[0057] The cathode of the third diode D3 is respectively connected to the high voltage input signal A terminal and the gate of the first NMOS transistor N1, and the anode is respectively connected to the source of the first NMOS transistor N1, the drain of the fifth NMOS transistor N5, one end of the third resistor R3 and the anode of the first diode D1;

[0058] The cathode of the fourth diode D4 is respectively connected to the high voltage output signal B terminal and the gate of the fourth NMOS transistor N4, and the anode is respectively connected to the source of the fourth NMOS transistor N4, the drain of the sixth NMOS transistor N6, one end of the fourth resistor R4 and the anode of the second diode D2;

[0059] One end of the first resistor R1 is connected to the power supply terminal VDD, and the other end is connected to the drain of the first NMOS transistor N1;

[0060] One end of the second resistor R2 is connected to the power supply terminal VDD, and the other end is connected to the drain of the fourth NMOS transistor N4;

[0061] One end of the third resistor R3 is respectively connected to the cathode of the first diode D1, the drain of the fifth PMOS transistor P5 and the gate of the second NMOS transistor N2, and the other end is respectively connected to the anode of the first diode D1, the anode of the third diode D3, the source of the first NMOS transistor N1 and the drain of the fifth NMOS transistor N5;

[0062] One end of the fourth resistor R4 is respectively connected to the cathode of the second diode D2, the drain of the sixth PMOS transistor P6 and the gate of the third NMOS transistor N3, and the other end is respectively connected to the anode of the second diode D2, the anode of the fourth diode D4, the source of the fourth NMOS transistor N4 and the drain of the sixth NMOS transistor N6;

[0063] The gate of the second NMOS transistor N2 is respectively connected to one end of the third resistor R3, the drain of the fifth PMOS transistor P5 and the cathode of the first diode D1, the drain is connected to the drain of the third NMOS transistor N3, and the source is connected to the high voltage input signal A terminal;

[0064] The gate of the third NMOS transistor N3 is respectively connected to one end of the fourth resistor R4, the drain of the sixth PMOS transistor P6 and the cathode of the second diode D2, the drain is connected to the drain of the second NMOS transistor N2, and the source is connected to the high voltage output signal B terminal.

[0065] Preferably, the first NMOS transistor N1 is a source follower.

[0066] Preferably, the fourth NMOS transistor N4 is a source follower.

[0067] The working principle of the novel high-voltage transmission gate circuit provided by the present invention is as follows: when the switch current signal IS is turned on, the PMOS tubes P1, P2, P3, P4, P5, and P6 enter the working state, and a resistance voltage drop is generated in the third resistor R3 and the fourth resistor R4. By reasonably selecting the size of the current I and the size of the third resistor R3 and the fourth resistor R4, the V of the second NMOS tube N2 and the third NMOS tube N3 can be guaranteed. GS Greater than the turn-on voltage V TH At the same time, the voltage of the second NMOS tube N2 is less than 5V, and the high-voltage switch tube circuit 22 is in the on state, transmitting the high-voltage input signal from the A terminal to the B terminal. At this time, the V GSN2 and the V of the third NMOS tube N3 GSN3 The calculation formula is as follows:

[0068] V GSN2 =I·R3-V THN1

[0069] V GSN3 =I·R3-V THN4

[0070] When the switch current signal IS is turned off, the PMOS tubes P1, P2, P3, P4, P5, and P6 enter the cut-off state, and no voltage drop occurs across the third resistor R3 and the fourth resistor R4. At this time, the V GS Less than the turn-on voltage V TH , the high-voltage switch circuit 22 is in the off state. At this time, the V GSN2 and the V of the third NMOS tube N3 GSN3 The calculation formula is as follows:

[0071] V GSN2 =-V THN1

[0072] V GSN3 =-V THN4

[0073] Since source followers N1 and N4 are used to isolate the high-voltage input signal A from the high-voltage output signal B, the high-voltage gate control signal provided by the gate drive circuit 21 will not interfere with the high-voltage input signal A and the high-voltage output signal B. This can overcome the shortcomings of the prior art that the gate control signal interferes with the high-voltage input signal and the output node cannot be cascaded, so as to achieve the advantages of high isolation, low interference and cascadability.

[0074] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A novel high voltage transmission gate circuit, characterized in that: It comprises a gate drive circuit (21) and a high-voltage switch tube circuit (22); wherein: The gate drive circuit (21) is used to provide a high-voltage gate control signal for the high-voltage switch tube circuit (22) under the control of a switch current signal; The high-voltage switch tube circuit (22) is used to isolate or transmit a high-voltage input signal according to the high-voltage gate control signal; The gate drive circuit (21) includes a first NMOS tube N1, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, and a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; the high-voltage switch tube circuit (22) includes a second NMOS tube N2 and a third NMOS tube N3; The gate of the first NMOS transistor N1 is respectively connected to the high voltage input signal A terminal and the cathode of the third diode D3, the drain is connected to one end of the first resistor R1, and the source is respectively connected to the anode of the third diode D3, the drain of the fifth NMOS transistor N5, one end of the third resistor R3 and the anode of the first diode D1; The gate of the fifth NMOS transistor N5 is connected to the bias signal VB2, the drain is respectively connected to the anode of the third diode D3, the source of the first NMOS transistor N1, one end of the third resistor R3 and the anode of the first diode D1, and the source is connected to the drain of the seventh NMOS transistor N7; The gate of the seventh NMOS transistor N7 is connected to the bias signal VB1, the drain is connected to the source of the fifth NMOS transistor N5, and the source is connected to the ground; The gate of the fourth NMOS transistor N4 is respectively connected to the high voltage output signal B terminal and the cathode of the fourth diode D4, the drain is connected to one end of the second resistor R2, and the source is respectively connected to the anode of the fourth diode D4, the drain of the sixth NMOS transistor N6, one end of the fourth resistor R4 and the anode of the second diode D2; The gate of the sixth NMOS transistor N6 is connected to the bias signal VB2, the drain is respectively connected to the anode of the fourth diode D4, the source of the fourth NMOS transistor N4, one end of the fourth resistor R4 and the anode of the second diode D2, and the source is connected to the drain of the eighth NMOS transistor N8; The gate of the eighth NMOS transistor N8 is connected to the bias signal VB1, the drain is connected to the source of the sixth NMOS transistor N6, and the source is connected to the ground; The gate of the first PMOS transistor P1 is connected to its own drain, and its gate and drain are also respectively connected to the gate of the second PMOS transistor P2, the gate of the third PMOS transistor P3, and the source of the fourth PMOS transistor P4, and its source is connected to the power supply terminal VDD; The gate of the second PMOS transistor P2 is respectively connected to the gate and source of the first PMOS transistor P1, the source of the fourth PMOS transistor P4 and the gate of the third PMOS transistor P3, the drain is connected to the source of the fifth PMOS transistor P5, and the source is connected to the power supply terminal VDD; The gate of the third PMOS transistor P3 is respectively connected to the gate and source of the first PMOS transistor P1, the source of the fourth PMOS transistor P4 and the gate of the second PMOS transistor P2, the drain is connected to the source of the sixth PMOS transistor P6, and the source is connected to the power supply terminal VDD; The gate of the fourth PMOS transistor P4 is connected to its own drain, and its gate and drain are also respectively connected to the switch current signal IS terminal, the gate of the fifth PMOS transistor P5 and the gate of the sixth PMOS transistor P6, and the source is respectively connected to the drain and gate of the first PMOS transistor P1, the gate of the second PMOS transistor P2 and the gate of the third PMOS transistor P3; The gate of the fifth PMOS transistor P5 is respectively connected to the gate and drain of the fourth PMOS transistor P4, the gate of the sixth PMOS transistor P6, and the switch current signal IS terminal, the drain is respectively connected to the other end of the third resistor R3, the gate of the second NMOS transistor N2, and the cathode of the first diode D1, and the source is connected to the drain of the second PMOS transistor P2; The gate of the sixth PMOS transistor P6 is respectively connected to the gate and drain of the fourth PMOS transistor P4, the gate of the fifth PMOS transistor P5, and the switch current signal IS terminal, the drain is respectively connected to the other end of the fourth resistor R4, the gate of the third NMOS transistor N3, and the cathode of the second diode D2, and the source is connected to the drain of the third PMOS transistor P3; The cathode of the first diode D1 is respectively connected to one end of the third resistor R3, the drain of the fifth PMOS transistor P5 and the gate of the second NMOS transistor N2, and the anode is respectively connected to the other end of the third resistor R3, the anode of the third diode D3, the source of the first NMOS transistor N1 and the drain of the fifth NMOS transistor N5; The cathode of the second diode D2 is respectively connected to one end of the fourth resistor R4, the drain of the sixth PMOS transistor P6 and the gate of the third NMOS transistor N3, and the anode is respectively connected to the other end of the fourth resistor R4, the anode of the fourth diode D4, the source of the fourth NMOS transistor N4 and the drain of the sixth NMOS transistor N6; The cathode of the third diode D3 is respectively connected to the high voltage input signal A terminal and the gate of the first NMOS transistor N1, and the anode is respectively connected to the source of the first NMOS transistor N1, the drain of the fifth NMOS transistor N5, one end of the third resistor R3 and the anode of the first diode D1; The cathode of the fourth diode D4 is respectively connected to the high voltage output signal B terminal and the gate of the fourth NMOS transistor N4, and the anode is respectively connected to the source of the fourth NMOS transistor N4, the drain of the sixth NMOS transistor N6, one end of the fourth resistor R4 and the anode of the second diode D2; One end of the first resistor R1 is connected to the power supply terminal VDD, and the other end is connected to the drain of the first NMOS transistor N1; One end of the second resistor R2 is connected to the power supply terminal VDD, and the other end is connected to the drain of the fourth NMOS transistor N4; One end of the third resistor R3 is respectively connected to the cathode of the first diode D1, the drain of the fifth PMOS transistor P5 and the gate of the second NMOS transistor N2, and the other end is respectively connected to the anode of the first diode D1, the anode of the third diode D3, the source of the first NMOS transistor N1 and the drain of the fifth NMOS transistor N5; One end of the fourth resistor R4 is respectively connected to the cathode of the second diode D2, the drain of the sixth PMOS transistor P6 and the gate of the third NMOS transistor N3, and the other end is respectively connected to the anode of the second diode D2, the anode of the fourth diode D4, the source of the fourth NMOS transistor N4 and the drain of the sixth NMOS transistor N6; The gate of the second NMOS transistor N2 is respectively connected to one end of the third resistor R3, the drain of the fifth PMOS transistor P5 and the cathode of the first diode D1, the drain is connected to the drain of the third NMOS transistor N3, and the source is connected to the high voltage input signal A terminal; The gate of the third NMOS transistor N3 is respectively connected to one end of the fourth resistor R4, the drain of the sixth PMOS transistor P6 and the cathode of the second diode D2, the drain is connected to the drain of the second NMOS transistor N2, and the source is connected to the high voltage output signal B terminal; Wherein, the first NMOS tube N1 is a source follower; Wherein, the fourth NMOS transistor N4 is a source follower.

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