Pattern layout design method, pattern forming method, and semiconductor device manufacturing method

Abstract

The present invention relates to a method for designing a pattern layout, a method for forming a pattern using the same, and a method for manufacturing a semiconductor device. The layout of an original pattern is rotated in a rotational direction to form a layout of a rotated pattern. The vertices and division points of the layout of the rotated pattern are matched with the reference points closest to them among the reference points, and the matched reference points are connected to form a layout of a first modified pattern. An area of ​​the layout of the first modified pattern is enlarged to form a layout of a second modified pattern. A layout of a reference pattern having the same direction as the layout of the rotated pattern is formed. A layout of a target pattern is formed based on the area where the reference pattern and the layout of the second modified pattern overlap. Optical proximity correction is performed on the layout of the target pattern to form a layout of a third modified pattern, and the layout of the third modified pattern is rotated in the opposite rotational direction to form a layout of a final pattern.

Description

Technical Field

[0001] Embodiments relate to a method of designing a layout of a pattern, a method of forming a pattern using the method of designing a layout of a pattern, and a method of manufacturing a semiconductor device using the method of designing a layout of a pattern. Background Art

[0002] When a material pattern is formed on a material layer through a photolithography process using a mask having a pattern layout drawn thereon, the material pattern may be formed to have a shape different from the pattern layout on the mask. This is because when the pattern layout is transferred to a photoresist layer on the material layer through an exposure process using the mask, the pattern layout may be deformed due to optical effects. Summary of the Invention

[0003] An embodiment is directed to a method for designing a layout of a pattern, which includes: rotating the layout of an original pattern designed on a mask by a rotation angle in a first rotation direction to form a layout of a rotated pattern, the mask including a reference point; matching the vertices and division points of the layout of the rotated pattern with corresponding reference points among the reference points of the mask, and connecting the matched reference points to form a layout of a first modified pattern, wherein the corresponding reference points among the reference points of the mask are respectively closest to the vertices and division points of the layout of the rotated pattern; expanding the area of ​​the layout of the first modified pattern to form a layout of a second modified pattern; forming a layout of a reference pattern having the same direction as the layout of the rotated pattern; forming a layout of a target pattern based on an area where the layout of the reference pattern and the layout of the second modified pattern overlap with each other; performing optical proximity correction on the layout of the target pattern to form a layout of a third modified pattern; and rotating the layout of the third modified pattern by the rotation angle in a second rotation direction to form a layout of a final pattern, wherein the second rotation direction is opposite to the first rotation direction.

[0004] An embodiment is also directed to a method for designing a layout of a pattern, comprising: rotating a layout of an original pattern designed on a mask by a rotation angle in a first rotation direction to form a layout of a rotated pattern, the mask comprising reference points arranged in a grid and reference lines extending in the first direction to pass through reference points among the reference points, the layout of the original pattern having a polygonal shape including edges intersecting each other at vertices, each edge having an angle with respect to the reference line, the angle being not any one of 0 degrees, 45 degrees, and 90 degrees, and the vertices respectively overlapping with reference points among the reference points; matching the vertices and segmentation points of the layout of the rotated pattern with corresponding reference points among the reference points of the mask, and connecting the matching vertices and segmentation points. The method comprises the steps of: adjusting the reference points of the mask to form a layout of a first modified pattern, wherein the corresponding reference points among the reference points of the mask are respectively closest to the vertices and the division points of the layout of the rotated pattern; expanding the area of ​​the layout of the first modified pattern to form a layout of a second modified pattern; forming a layout of the reference pattern having the same direction as the layout of the rotated pattern; forming a layout of the target pattern based on the area where the layout of the reference pattern and the layout of the second modified pattern overlap with each other; performing optical proximity correction on the layout of the target pattern to form a layout of a third modified pattern; and rotating the layout of the third modified pattern by the rotation angle in a second rotation direction to form a layout of a final pattern, wherein the second rotation direction is opposite to the first rotation direction.

[0005] An embodiment also provides a method for forming a pattern, which includes designing a layout of a final pattern on a mask and forming a pattern on a substrate using the mask on which the layout of the final pattern is designed, wherein designing the layout of the final pattern on the mask includes: rotating the layout of the original pattern designed on the mask by a rotation angle in a first rotation direction to form a layout of the rotated pattern, the mask including reference points; matching the vertices and division points of the layout of the rotated pattern with corresponding reference points in the reference points of the mask, respectively, and connecting the matched reference points to form a layout of a first modified pattern, wherein the corresponding reference points among the reference points of the mask are respectively closest to the vertices and division points of the layout of the rotated pattern; expanding the area of ​​the layout of the first modified pattern to form a layout of a second modified pattern; forming a layout of the reference pattern having the same direction as the layout of the rotated pattern; forming a layout of a target pattern based on an area where the layout of the reference pattern and the layout of the second modified pattern overlap with each other; performing optical proximity correction on the layout of the target pattern to form a layout of a third modified pattern; and rotating the layout of the third modified pattern by the rotation angle in a second rotation direction to form a layout of the final pattern, wherein the second rotation direction is opposite to the first rotation direction.

[0006] An embodiment is also directed to a method for manufacturing a semiconductor device, comprising designing a layout of a final pattern on a mask, forming an active pattern on a substrate using the mask on which the layout of the final pattern is designed, forming a gate structure on an upper portion of the active pattern, forming a bit line structure on a portion of the active pattern, forming a contact plug structure on a portion of the active pattern, and forming a capacitor on the contact plug structure, wherein designing the layout of the final pattern on the mask comprises: rotating the layout of an original pattern designed on the mask by a rotation angle in a first rotation direction to form a layout of a rotated pattern, the mask including reference points; matching vertices and division points of the layout of the rotated pattern with corresponding reference points among the reference points of the mask, and Connecting matching reference points to form a layout of a first modified pattern, wherein the corresponding reference points among the reference points of the mask are respectively closest to the vertices and the division points of the layout of the rotated pattern; expanding the area of ​​the layout of the first modified pattern to form a layout of a second modified pattern; forming a layout of the reference pattern having the same direction as the layout of the rotated pattern; forming a layout of a target pattern based on an area where the layout of the reference pattern and the layout of the second modified pattern overlap with each other; performing optical proximity correction on the layout of the target pattern to form a layout of a third modified pattern; and rotating the layout of the third modified pattern by the rotation angle in a second rotation direction to form a layout of a final pattern, wherein the second rotation direction is opposite to the first rotation direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a flowchart illustrating a method of designing a layout of a pattern according to an example embodiment.

[0008] Figures 2 to 7 is a plan view illustrating a method of forming a layout of a final pattern by modifying the layout of an original pattern.

[0009] Figure 8 and Figure 9 is a plan view illustrating a method of forming a pattern according to an example embodiment.

[0010] Figures 10 to 29 are a plan view and a cross-sectional view illustrating a semiconductor device according to an example embodiment. DETAILED DESCRIPTION

[0011] Figure 1 is a flowchart illustrating a method of designing a layout of a pattern according to an example embodiment, Figures 2 to 7 is a plan view illustrating a method of forming a layout of a final pattern by modifying the layout of an original pattern.

[0012] Reference Figure 1 and Figure 2In a first operation S110 , the layout of the original pattern 20 designed on the mask 10 may be rotated in a first rotation direction by a rotation angle θ to form a layout of a rotated pattern 30 .

[0013] Mask 10 may include reference points 2 arranged in a grid. Imaginary reference line 4 may extend in a first direction to pass through some of reference points 2. Mask 10 may define a second direction perpendicular to the first direction, a third direction having an acute angle with respect to the first direction or the second direction, and a fourth direction perpendicular to the third direction.

[0014] In an example embodiment, the layout of the primitive pattern 20 may have a polygonal shape, and a first vertex 21 where first to fourth edges 25 , 26 , 27 , and 28 of the polygon intersect with each other may overlap with some reference points 2 .

[0015] In one example embodiment, the polygon may be a rectangle including first and second edges 25 and 26, each of which may extend in the fourth direction and are opposed to each other, and third and fourth edges 27 and 28, each of which may extend in the third direction and are opposed to each other. The length of the rectangle in the third direction may be greater than the width of the rectangle in the fourth direction. Thus, the rectangle may extend in the third direction and may be said to have a direction parallel to the third direction.

[0016] Each of the edges 25, 26, 27, and 28 of the rectangle may be divided into several sections by the first partition points 24. Some of the first partition points 24 may overlap with corresponding reference points 2, and other of the first partition points 24 may not overlap with the reference points 2.

[0017] The layout of the original pattern 20 can be rotated in a first rotation direction about a reference vertex 5 among the first vertices 21 of the polygon to form a layout of the rotated pattern 30, and the reference line 4 can pass through the reference vertex 5. The first rotation direction can be clockwise or counterclockwise, and is shown as counterclockwise in the figure.

[0018] The sum of the rotation angle θ and the angle of one of the edges of the polygon relative to the reference line 4 may be 90 degrees. Therefore, the sum of the rotation angle θ and the angle of the third edge 27 of the rectangle relative to the reference line 4 may be 90 degrees. In an example embodiment, at least one of the edges of the polygon may have an angle other than 0 degrees, 45 degrees, and 90 degrees relative to the reference line 4. In the rectangle, each edge may have an angle other than 0 degrees, 45 degrees, and 90 degrees relative to the reference line 4.

[0019] The layout of the rotated pattern 30 can have the same polygonal shape as the layout of the original pattern 20, however, the orientation of the polygon can be changed. Therefore, if the layout of the original pattern 20 is a rectangular shape having a third orientation, the layout of the rotated pattern 30 formed by rotating the original pattern 20 by a first rotation angle θ can be a rectangular shape having a second orientation, and the length in the second direction can be greater than the width in the first direction. The rectangle can have fifth and sixth edges 35 and 36, each of which can extend in the first direction, and seventh and eighth edges 37 and 38, each of which can extend in the second direction, and can include a second vertex 31 at which the fifth to eighth edges 35, 36, 37, and 38 can intersect.

[0020] In the rectangular layout of rotated pattern 30, each of fifth to eighth edges 35, 36, 37, and 38 can be divided into several segments by second and third segmentation points 33 and 34. Second segmentation point 33 may overlap with corresponding reference points 2, and third segmentation point 34 may not overlap with reference point 2. Furthermore, some of the second vertices 31 of the rectangle may not overlap with reference point 2. However, reference vertex 5 of rotated pattern 30 may be the same as reference vertex 5 of original pattern 20 and therefore may overlap with reference point 2. Each of fifth edge 35 and seventh edge 37, which intersect at reference vertex 5, may have an angle of 0 or 90 degrees relative to reference line 4.

[0021] Reference Figure 1 and Figure 3 In the second operation S120, the second vertex 31 and each of the second and third division points 33 and 34 of the layout of the rotation pattern 30 may be matched with the nearest reference point among the reference points 2, and the matched reference points 2 may be connected to each other to form the layout of the first modified pattern 40.

[0022] The operation of matching the second vertex 31 and each of the second and third division points 33 and 34 of the layout of the rotation pattern 30 with the nearest reference point in the reference point 2 may be referred to as grid snapping, thereby forming the third vertex 41 and the fourth division point 43 overlapping with the reference point 2.

[0023] As described above, the second division points 33 of the layout of the rotated pattern 30 may overlap with corresponding reference points in reference point 2, respectively, and therefore no additional matching operation is required. However, the third division point 34 may not overlap with reference point 2, and therefore an additional matching operation may be performed to match corresponding reference points closest to the third division point 34. Furthermore, some of the second vertices 31 of the layout of the rotated pattern 30 may not overlap with reference point 2, in which case an additional matching operation may be performed.

[0024] In the drawing, the third vertex 41 and the fourth dividing point 43 that can be formed by mesh snapping are shown by inverted triangles, compared to the second vertex 31 and the second and third dividing points 33 and 34 shown by triangles.

[0025] The third vertex 41 and the fourth dividing point 43 may be connected to each other to form a layout of the first modified pattern 40. In the figure, the layout of the first modified pattern 40 has a rectangular shape having a second direction, wherein the reference vertex 5 is one of the vertices of the rectangle. The rectangle may have a ninth edge 45 and a tenth edge 46, each of which may extend in the first direction, and an eleventh edge 47 and a twelfth edge 48, each of which may extend in the second direction, and which may extend in the second direction.

[0026] In an example embodiment, the length of the first modified pattern 40 in the second direction may be greater than the length of the rotated pattern 30 in the second direction, and the width of the first modified pattern 40 in the first direction may be less than the width of the rotated pattern 30 in the first direction.

[0027] Reference Figure 1 and Figure 4 In the third operation S130, the area of ​​the layout of the first modified pattern 40 may be expanded to form the layout of the second modified pattern 50. Therefore, a plus bias may be imparted to the layout of the first modified pattern 40.

[0028] In one exemplary embodiment, the width of the first modified pattern 40 in the first direction can be increased, thereby expanding its area. Thus, the lengths of the ninth and tenth edges 45, 46, each of which can extend in the first direction, can be extended in opposite directions in the first direction to form a thirteenth and fourteenth edges 55, 56, respectively. The eleventh and twelfth edges 47, 48, each of which can extend in the second direction, can be shifted in the first direction to form a fifteenth and sixteenth edges 57, 58, respectively. The fifteenth and sixteenth edges 57, 58 can intersect with the ends of the thirteenth and fourteenth edges 55, 56, 56. Thus, a second modified pattern 50 having a rectangular shape can be formed, including the thirteenth to sixteenth edges 55, 56, 57, and 58, and having an area larger than that of the first modified pattern 40. The thirteenth to sixteenth edges 55, 56, 57, and 58 can intersect with each other at the fourth vertex 51.

[0029] In another embodiment, the area of ​​the layout of the first modified pattern 40 may be expanded, for example, in the second direction, to form the layout of the second modified pattern 50 .

[0030] Reference Figure 1 and Figure 5In a fourth operation S140 , a layout of the reference pattern 60 having the same direction as the layout of the rotated pattern 30 may be formed.

[0031] In an example embodiment, the layout of the reference pattern 60 may include: a first line 67 extending in the second direction to pass through the reference vertex 5 of the layout of the original pattern 20; and a second line 68 extending in the second direction to pass through the reference point 2 and spaced apart from the first line 67 in the first direction by a distance close to the width of the layout of the original pattern 20 in the fourth direction.

[0032] In an example embodiment, the first line 67 and the second line 68 of the layout of the reference pattern 60 may correspond to lines elongated in the second direction from the eleventh edge 47 and the twelfth edge 48 of the layout of the first modified pattern 40 .

[0033] Reference Figure 1 and Figure 6 In a fifth operation S150, a layout of the target pattern 70 may be formed based on a region in which the layouts of the reference pattern 60 and the second modified pattern 50 overlap with each other.

[0034] Therefore, the target pattern 70 may be formed using a logical AND among Boolean operators on the layout of the reference pattern 60 and the second modified pattern 50 .

[0035] In an example embodiment, the layout of the target pattern 70 may have a rectangular shape including a portion of the first line 67 and the second line 68 of the layout of the reference pattern 60 between the thirteenth edge 55 and the fourteenth edge 56 of the layout of the second modified pattern 50, and a portion of the thirteenth edge 55 and the fourteenth edge 56 of the layout of the second modified pattern 50 between the first line 67 and the second line 68 of the layout of the reference pattern 60.

[0036] Therefore, the layout of the target pattern 70 can have a rectangular shape, which includes a seventeenth edge 75 extending from the reference vertex 5 in the first direction, an eighteenth edge 76 extending in the first direction to face the seventeenth edge 75, a nineteenth edge 77 extending from the reference vertex 5 in the second direction, and a twentieth edge 78 extending in the second direction to face the nineteenth edge 77, and the seventeenth edge 75, the eighteenth edge 76, the nineteenth edge 77 and the twentieth edge 78 can intersect each other at the fifth vertex 71.

[0037] The layout of the target pattern 70 may include a fifth dividing point 73 that divides each of the seventeenth to twentieth edges 75, 76, 77, and 78 into a plurality of sections. In an example embodiment, the fifth dividing point 73 may overlap with the fourth dividing point 43, respectively.

[0038] In a sixth operation S160, optical proximity correction (OPC) may be performed on the layout of the target pattern 70 to form a layout of a third modified pattern.

[0039] In an example embodiment, OPC may be performed based on data regarding the fifth vertex 71 and the fifth division point 73 included in the layout of the target pattern 70. Data for performing OPC may be stored in a database in units of reference point 2 included in the mask 10, and the fifth vertex 71 and the fifth division point 73 may overlap with the reference point 2, so that OPC may be performed based on the data regarding the fifth vertex 71 and the fifth division point 73.

[0040] In one example embodiment, OPC may include corner rounding correction. For example, each corner of the rectangle of the target pattern 70 layout (that is, the portion of each of the seventeenth to twentieth edges 75, 76, 77, and 78 near the fifth vertex 71) may be expanded outward, so that the layout of the third modified pattern may have a rectangular shape with a first corner 79 expanded outward.

[0041] Reference Figure 7 In a seventh operation S170 , the layout of the third modified pattern may be rotated by a rotation angle θ in a second rotation direction that may be opposite to the first rotation direction to form a layout of a final pattern 80 .

[0042] In one exemplary embodiment, the layout of the third modified pattern can be rotated in a second rotational direction about the reference vertex 5, which is shown as a clockwise direction in the figure. The layout of the final pattern 80 can have the same shape as the third modified pattern, but can have a different orientation. Thus, the layout of the final pattern 80 can have a rectangular shape with a second corner 89 that extends outward, and the rectangle can have a third orientation.

[0043] Through the above operations, OPC can be performed on the layout of the original pattern 20 to form the layout of the final pattern 80. Therefore, the layout of the original pattern 20 may include first to fourth edges 25, 26, 27, and 28 having angles other than any one of 0 degrees, 45 degrees, and 90 degrees relative to the reference line 4 of the mask 10, and therefore, at least one of the first division points 24 that divide each of the first to fourth edges 25, 26, 27, and 28 into a plurality of segments may not overlap with the reference point 2 of the mask 10. Therefore, the data stored at the reference point 2 for performing OPC cannot be used, so that OPC cannot be automatically performed using a computer program, and the layout of the original pattern 20 must be manually divided and the optimal deviation must be found through simulation.

[0044] However, in example embodiments, even if each of the first to fourth edges 25, 26, 27, and 28 of the layout of the original pattern 20 has an angle other than one of 0 degrees, 45 degrees, and 90 degrees relative to the reference line 4, each of the fifth to eighth edges 35, 36, 37, and 38 of the layout of the rotated pattern 30 formed by rotating the layout of the original pattern 20 about the reference vertex 5 may also have an angle of 0 degrees or 90 degrees relative to the reference line 4, and the third vertex 41 and the fourth dividing point 43 of the layout of the first modified pattern 40 formed by grid capture may overlap with the reference point 2, so that the data stored at the reference point 2 may be used, and OPC may be automatically performed by a computer processor using a computer program.

[0045] In addition, a deviation can be imparted to the layout of the first modified pattern 40 to form a layout of the second modified pattern 50, a layout of the reference pattern 60 having dimensions similar to those of the layout of the original pattern 20 and including a first line 67 and a second line 68 passing through the reference point 2 can be formed, and a logical AND operator can be applied to the second modified pattern 50 and the reference pattern 60, so that a layout of a target pattern 70 that is very similar to the layout of the original pattern 20 can be formed, wherein the layout of the target pattern 70 can include a fifth vertex 71 and a fifth dividing point 73 that overlap with the reference point 2, and data for OPC from the second reference point 2 can be used.

[0046] In the above, a single pattern designed on the mask 10 has been described, but the embodiments may also be applied to a plurality of patterns provided on the mask 10. For example, when a layout of a plurality of original patterns 20 is designed to be spaced apart from each other by a given distance along a first direction on the mask 10, a layout of a plurality of rotated patterns 30, a layout of a plurality of first modified patterns 40 and a plurality of second modified patterns 50, a layout of a plurality of third modified patterns, a layout of a plurality of reference patterns 60, a layout of a plurality of target patterns 70, and a layout of a plurality of final patterns 80 may be formed accordingly.

[0047] In an example embodiment, the layout of the reference pattern 60 may be formed to correspond to the layout of the second modified pattern 50 to be spaced apart from each other by a given distance in the first direction.

[0048] Figure 8 and Figure 9 1 is a plan view illustrating a method of forming a pattern according to an exemplary embodiment. This method can be performed using a method of designing a layout of a pattern, and thus repeated descriptions may be omitted here.

[0049] Reference Figure 7 and Figure 8, a mask 10 in which the layout of the final pattern 80 is designed can be used for a substrate 12 on which an etching target layer and a photoresist layer 16 are sequentially stacked (refer to Figure 9 ) performs an exposure process.

[0050] The layout of the final pattern 80 designed on the mask 10 can be transferred to the photoresist layer 16, however, the second corner 89 expanded by the OPC can be reduced. Therefore, a layout that is similar to the original pattern 20 (refer to Figure 2 ) is a very similar layout of the transfer pattern 90.

[0051] The layout of the transfer pattern 90 may have a rectangular shape having a third direction, and the rectangle may include a twenty-first edge 95 and a twenty-second edge 96, each of which may extend in the fourth direction and are opposite to each other, and a twenty-third edge 97 and a twenty-fourth edge 98, each of which may extend in the third direction and are opposite to each other. The rectangle may also include a sixth vertex 91 at which the twenty-first to twenty-fourth edges 95, 96, 97, and 98 intersect with each other.

[0052] Reference Figure 9 A developing process may be performed on the photoresist layer 16 to form a photoresist pattern (not shown) having substantially the same shape as the layout of the transfer pattern 90 .

[0053] The etching target layer may be etched using the photoresist pattern as an etching mask to form a pattern 14 having a desired shape on the substrate 12 , and the photoresist pattern may be removed by, for example, an ashing process and / or a stripping process.

[0054] In another embodiment, an etching mask layer (not shown) may be further formed on the substrate 12 between the etching target layer and the photoresist layer 16, the etching mask layer may be etched using the photoresist pattern to form an etching mask, and the etching target layer may be etched using the etching mask to form a pattern 14.

[0055] As explained above, a pattern 14 having a shape very similar to the layout of the original pattern 20 can be formed, and the pattern 14 can be obtained by referring to Figures 1 to 7 The method is formed by the layout of the final pattern 80.

[0056] Figures 10 to 29 are a plan view and a cross-sectional view illustrating a semiconductor device according to an example embodiment. Figure 10 、 Figure 11 、 Figure 13 、 Figure 15 、 Figure 18 、 Figure 22 and Figure 28 It's a floor plan. Figure 12 、 Figure 14 、 Figure 16 、 Figure 17 、 Figure 19-21 、 Figure 23-27 and Figure 29 It is a cross-sectional view. Figure 13 、 Figure 15 、 Figure 18 、 Figure 22 and Figure 28 yes Figure 11 An enlarged plan view of region X, Figure 12 、 Figure 14 、 Figure 16 、 Figure 17 、 Figure 19-21 、 Figure 23-27 and Figure 29 They respectively include cross sections taken along lines AA' and BB' of the corresponding plan views.

[0057] This method can use the reference Figures 1 to 7 Described method of designing pattern layout and reference Figure 8 and Figure 9 The method of forming a pattern is described and thus repeated description may be omitted here.

[0058] Hereinafter, two directions substantially parallel to the upper surface of the substrate 100 and substantially perpendicular to each other may be referred to as a first direction and a second direction, respectively, and a direction substantially parallel to the upper surface of the substrate 100 and having an acute angle other than 45 degrees relative to each of the first direction and the second direction may be referred to as a third direction.

[0059] Reference Figure 10 , can be executed and referenced Figures 1 to 8 The processes described are essentially the same or similar processes.

[0060] Therefore, it is possible to Figure 11 and Figure 12 ), and an exposure process is performed on the photoresist layer 16 using the mask 10 on which the layout of the final pattern 80 is designed, so that a layout similar to the original pattern 20 (refer to Figure 2 ) A layout of very similar transfer patterns 90. For example, a layout of a plurality of transfer patterns 90 spaced apart from each other in each of the third direction and a direction substantially perpendicular to the third direction may be formed on the photoresist layer 16.

[0061] In an example embodiment, the layout of each transfer pattern 90 may have a rectangular shape having a third direction.

[0062] The substrate 100 may include semiconductor materials such as silicon, germanium, silicon germanium, etc., or III-V semiconductor compounds such as GaP, GaAs, GaSb, etc. In an example embodiment, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0063] Reference Figure 11 , a development process may be performed on the photoresist layer 16 to form photoresist patterns (not shown), each of which may have a shape substantially the same as the layout of one of the transfer patterns 90, and the upper portion of the substrate 100 may be etched using the photoresist patterns as an etching mask to form the active patterns 105.

[0064] In an example embodiment, each active pattern 105 may have a rectangular shape similar to the layout of each transfer pattern 90. However, due to characteristics of an etching process, ends of the rectangle in the third direction may be rounded.

[0065] Isolation patterns 110 may be formed on the substrate 100 to cover sidewalls of the active patterns 105 .

[0066] Reference Figure 13 and Figure 14 An ion implantation process may be performed on the substrate 100 to form an impurity region (not shown), and the active pattern 105 and the isolation pattern 110 may be partially etched to form a first recess extending in the first direction.

[0067] A gate structure 160 may be formed in the first recess. The gate structure 160 may include a gate insulating layer 130 on the surface of the active pattern 105 exposed by the first recess, a gate electrode 140 filling a lower portion of the first recess on the gate insulating layer 130, and a gate mask 150 filling an upper portion of the first recess on the gate electrode 140. The gate structure 160 may extend in a first direction, and a plurality of gate structures 160 may be formed in a second direction.

[0068] In an example embodiment, the gate insulating layer 130 may be formed on the surface of the active pattern 105 exposed by the first recess through a thermal oxidation process, and thus may include an oxide such as silicon oxide.

[0069] Reference Figure 15 and Figure 16 , an insulating layer structure 200 may be formed on the active patterns 105 and the isolation patterns 110 .

[0070] In an exemplary embodiment, the insulating layer structure 200 may include a first insulating layer 170, a second insulating layer 180, and a third insulating layer 190 stacked sequentially. Each of the first insulating layer 170 and the third insulating layer 190 may include an oxide such as silicon oxide, and the second insulating layer 180 may include a nitride such as silicon nitride.

[0071] A first conductive layer 210 and a first mask 220 may be sequentially formed on the insulating layer structure 200 , and the first conductive layer 210 and the insulating layer structure 200 may be etched using the first mask 220 as an etching mask to form a first opening 230 exposing the active pattern 105 .

[0072] The first conductive layer 210 may include, for example, doped polysilicon, and the first mask 220 may include nitride, for example, silicon nitride.

[0073] During the etching process, the upper portion of the active pattern 105 exposed by the first opening 230 and the upper portion of the isolation pattern 110 adjacent thereto may also be etched, and the upper portion of the gate mask 150 may also be etched to form a second recess. Therefore, the bottom of the first opening 230 may be referred to as a second recess.

[0074] In an example embodiment, the first opening 230 may expose a central upper surface of each of the active patterns 105 extending in the third direction, and thus a plurality of first openings 230 may be formed in each of the first and second directions.

[0075] A second conductive layer 240 may be formed to fill the first opening 230 .

[0076] In an exemplary embodiment, the second conductive layer 240 may be formed by forming a preliminary second conductive layer on the active pattern 105, the isolation pattern 110, the gate mask 150, and the first mask 220 to fill the first opening 230; and removing an upper portion of the preliminary second conductive layer by a CMP process and / or an etch-back process. The second conductive layer 240 may be formed to have an upper surface substantially coplanar with an upper surface of the first conductive layer 210.

[0077] In an example embodiment, a plurality of second conductive layers 240 may be formed to be spaced apart from each other in each of the first direction and the second direction. The second conductive layer 240 may include, for example, doped polysilicon and thus may be merged with the first conductive layer 210.

[0078] Reference Figure 17 After removing the first mask 220 , a third conductive layer 250 , a barrier layer 270 and a first metal layer 280 may be sequentially formed on the first conductive layer 210 and the second conductive layer 240 .

[0079] In an exemplary embodiment, the third conductive layer 250 may include a material substantially the same as that of the first conductive layer 210 and the second conductive layer 240. Thus, the third conductive layer 250 may include doped polysilicon and thus may be merged with the first conductive layer 210 and the second conductive layer 240. The barrier layer 270 may include a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, etc. The first metal layer 280 may include a metal such as tungsten, titanium, tantalum, etc.

[0080] A capping layer 290 may be formed on the first metal layer 280. The capping layer 290 may include nitride, eg, silicon nitride.

[0081] Reference Figure 18 and Figure 19 , the capping layer 290 can be partially etched to form a first capping pattern 295, and the first metal layer 280, the barrier layer 270, the third conductive layer 250, the first conductive layer 210 and the second conductive layer 240, and the third insulating layer 190 can be sequentially etched using the first capping pattern 295 as an etching mask.

[0082] The first capping pattern 295 may extend in the second direction, and the plurality of first capping patterns 295 may be spaced apart from each other in the first direction. Through the etching process, the second conductive pattern 245, the third conductive pattern 255, the barrier pattern 275, the metal pattern 285, and the first capping pattern 295 may be sequentially stacked on the active pattern 105, the isolation pattern 110, and the gate mask 150 in the first opening 230, and the third insulating pattern 195, the first conductive pattern 215, the third conductive pattern 255, the barrier pattern 275, the metal pattern 285, and the first capping pattern 295 may be sequentially stacked on the second insulating layer 180 of the insulating layer structure 200 outside the first opening 230.

[0083] As described above, the first to third conductive layers 210, 240, and 250 may be merged with each other, and thus, the sequentially stacked second conductive pattern 245 and the third conductive pattern 255, and the sequentially stacked first conductive pattern 215 and the third conductive pattern 255 may each form a conductive pattern structure 265. Hereinafter, the sequentially stacked conductive pattern structure 265, the barrier pattern 275, the metal pattern 285, and the first capping pattern 295 may be referred to as a bit line structure 305.

[0084] In an example embodiment, the bit line structure 305 may extend in the second direction, and a plurality of bit line structures 305 may be formed in the first direction.

[0085] The second opening 705 may be formed between adjacent bit line structures in the first direction among the bit line structures 305 to expose the upper surface of the second insulating layer 180 and be connected to the first opening 230 .

[0086] Reference Figure 20 A first spacer layer can be formed on the exposed upper surfaces of the active pattern 105, the isolation pattern 110 and the gate mask 150, the sidewalls of the first opening 230, and the second insulating layer 180 to cover the bit line structure 305, and a fourth insulating layer and a fifth insulating layer can be sequentially formed on the first spacer layer.

[0087] The first spacer layer may cover sidewalls of the third insulation pattern 195 below the bit line structure 305 on the second insulation layer 180 , and the fifth insulation layer may completely fill the first opening 230 .

[0088] The fourth and fifth insulating layers may be etched through an etching process. In one exemplary embodiment, the etching process may include a wet etching process, and all portions of the fourth and fifth insulating layers except for portions thereof within the first opening 230 may be removed. Thus, substantially the entire surface of the first spacer layer may be exposed, that is, all portions of the first spacer layer except for portions thereof within the first opening 230. The portions of the fourth and fifth insulating layers remaining within the first opening 230 may form a fifth insulating pattern 320 and a sixth insulating pattern 330, respectively.

[0089] A second spacer layer can be formed on the exposed surface of the first spacer layer and the portions of the fourth insulation pattern 320 and the fifth insulation pattern 330 in the first opening 230, and can be anisotropically etched to form a second spacer 340 on the surface of the first spacer layer and the fifth insulation pattern 320 and the sixth insulation pattern 330, thereby covering the sidewalls of the bit line structure 305.

[0090] A dry etching process may be performed using the first capping pattern 295 and the second spacer 340 as an etching mask to form a third opening 350 exposing the upper surface of the active pattern 105 . Upper surfaces of the isolation pattern 110 and the gate mask 150 may also be exposed by the third opening 350 .

[0091] Through a dry etching process, portions of the first spacer layer on the upper surface of the first capping pattern 295 and the upper surface of the second insulating layer 180 may be removed, thereby forming first spacers 315 to cover the sidewalls of the bitline structure 305. The first spacers 315 may include a nitride, such as silicon nitride. During the dry etching process, the first insulating layer 170 and the second insulating layer 180 may be partially removed to form a first insulating pattern 175 and a second insulating pattern 185, respectively, below the bitline structure 305. The first to third insulating patterns 175, 185, and 195 stacked sequentially below the bitline structure 305 may form an insulating pattern structure.

[0092] Reference Figure 21A third spacer layer may be formed on the upper surface of the first capping pattern 295, the outer sidewalls of the second spacer 340, portions of the upper surfaces of the fifth and sixth insulating patterns 320 and 330, and the upper surfaces of the active pattern 105, the isolation pattern 110, and the gate mask 150 exposed by the third opening 350, and anisotropically etched to form third spacers 375 covering the sidewalls of the bit line structure 305. The third spacers 375 may include a nitride, such as silicon nitride. The third spacers 375 may include a nitride, such as silicon nitride.

[0093] The first to third spacers 315 , 340 , and 375 sequentially stacked on the sidewalls of the bit line structure 305 in a horizontal direction substantially parallel to the upper surface of the substrate 100 may be referred to as a preliminary spacer structure.

[0094] An upper portion of the active pattern 105 may be etched to form a third recess 390 connected to the third opening 350 .

[0095] A lower contact plug layer may be formed to fill the third opening 350 and the third recess 390. The lower contact plug layer may include, for example, doped polysilicon.

[0096] The lower contact plug layer may be planarized until an upper surface of the first capping pattern 295 may be exposed to form a lower contact plug 405 between the bit line structures 305 .

[0097] In an example embodiment, the lower contact plug 405 may extend in the second direction, and a plurality of lower contact plugs 405 may be formed in the first direction.

[0098] Reference Figure 22 and Figure 23 , a second mask (not shown) can be formed on the first cover pattern 295 and the lower contact plug 405, the second mask including a plurality of fourth openings arranged in the second direction, each of which can extend in the first direction, and the lower contact plug 405 can be etched using the fourth mask as an etching mask.

[0099] In an example embodiment, each fourth opening may overlap the gate structure 160 in a vertical direction substantially perpendicular to the upper surface of the substrate 100. Through an etching process, a fifth opening may be formed to expose the upper surface of the gate mask 150 of the gate structure 160 between the bit line structures 305.

[0100] After removing the second mask, a second capping pattern 410 may be formed to fill the fifth opening. The second capping pattern 410 may include a nitride, such as silicon nitride. In an example embodiment, the second capping pattern 410 may extend in the first direction between the bit line structures 305, and a plurality of second capping patterns 410 may be formed in the second direction.

[0101] Therefore, the lower contact plugs 405 extending in the second direction between the bit line structures 305 may be divided into a plurality of segments spaced apart from each other in the second direction by the second capping patterns 410 .

[0102] Reference Figure 24 , the upper portion of the lower contact plug 405 may be removed.

[0103] In one example embodiment, an upper portion of the lower contact plug 405 may be removed by an etch-back process. As the upper portion of the lower contact plug 405 is removed, an upper portion of the preliminary spacer structure on the sidewall of the bit line structure 305 may be exposed, and upper portions of the second spacer 340 and the third spacer 375 of the exposed preliminary spacer structure may be removed.

[0104] The upper portion of the lower contact plug 405 may be further removed by, for example, an etch-back process. Therefore, the upper surface of the lower contact plug 405 may be lower than the upper surfaces of the second spacer 340 and the third spacer 375 .

[0105] A fourth spacer layer may be formed on the bit line structure 305, the preliminary spacer structure, the second cap pattern 410, and the lower contact plug 405 and anisotropically etched to form a fourth spacer 425 covering the first to third spacers 315, 340, and 375 on each of opposite side walls of the bit line structure 305 along the first direction, thereby exposing the upper surface of the lower contact plug 405.

[0106] A metal silicide pattern 435 may be formed on the exposed upper surface of the lower contact plug 405. In one exemplary embodiment, the metal silicide pattern 435 may be formed by forming a second metal layer on the first and second capping patterns 295 and 410, the fourth spacer 425, and the lower contact plug 405; performing a heat treatment thereon; and removing unreacted portions of the second metal layer. The metal silicide pattern 435 may include, for example, cobalt silicide, nickel silicide, titanium silicide, or the like.

[0107] Reference Figure 25 , an upper contact plug layer 450 may be formed on the first and second capping patterns 295 and 410 , the first to fourth spacers 315 , 340 , 375 , and 425 , the metal silicide pattern 435 , and the lower contact plug 405 .

[0108] In an example embodiment, the upper contact plug layer 450 may include a metal such as tungsten.

[0109] Reference Figure 26 , the upper contact plug layer 450 may be planarized by, for example, a CMP process.

[0110] A portion of the upper contact plug layer 450 may be partially removed to form a hole 470 .

[0111] The hole 470 may be formed by removing a portion of the upper contact plug layer 450 , a portion of an upper portion of the first capping pattern 295 , and a portion of upper portions of the first, third, and fourth spacers 315 , 375 , and 425 , thereby exposing an upper surface of the second spacer 340 .

[0112] As the holes 470 are formed, the upper contact plug layer 450 may be transformed into upper contact plugs 455. In an exemplary embodiment, a plurality of upper contact plugs 455 may be formed in each of the first and second directions and may be arranged in a honeycomb pattern. In a plan view, each upper contact plug 455 may have a circular, elliptical, or polygonal shape.

[0113] The lower contact plug 405 , the metal silicide pattern 435 , and the upper contact plug 455 , which are sequentially stacked, may form a first contact plug structure.

[0114] Reference Figure 27 , the exposed second spacers 340 may be removed to form air gaps 345 connected to the holes 470. The second spacers 340 may be removed by, for example, a wet etching process.

[0115] In one example embodiment, in the second spacer 340 on the sidewall of the bit line structure 305 extending in the second direction, not only the portion of the second spacer 340 exposed by the hole 470 but also the portion of the second spacer 340 parallel to the exposed portion thereof may be removed. Therefore, not only the portion of the second spacer 340 exposed by the hole 470 and not covered by the upper contact plug 455 may be removed, but also the portion of the second spacer 340 adjacent thereto in the second direction and covered by the second capping pattern 410 and the portion of the second spacer 340 adjacent thereto in the second direction and covered by the upper contact plug 455 may be removed.

[0116] A first insulating interlayer 480 and a second insulating interlayer 490 stacked sequentially may be formed to fill the hole 470. The first insulating interlayer 480 and the second insulating interlayer 490 may also be sequentially stacked on the second capping pattern 410.

[0117] The first insulating interlayer 480 may include a material having poor gap-filling properties, and thus the air gap 345 below the hole 470 may not be filled by the first insulating interlayer 480 but may remain. The air gap 345 may also be referred to as an air spacer and may form a spacer structure together with the first spacer 315, the third spacer 375, and the fourth spacer 425. Therefore, the air gap 345 may be a spacer including air. The second insulating interlayer 490 may include a nitride, such as silicon nitride.

[0118] Reference Figure 28 and Figure 29 , a capacitor 540 may be formed to contact an upper surface of the upper contact plug 455 .

[0119] Therefore, the etch stop layer 500 and the mold layer (not shown) may be sequentially formed on the upper contact plug 455 and the first and second insulating interlayers 480 and 490 and partially etched to form a sixth opening exposing the upper surface of the upper contact plug 455 .

[0120] A lower electrode layer may be formed on the sidewalls of the sixth opening, the exposed upper surface of the upper contact plug 455, and the mold layer. A sacrificial layer may be formed on the lower electrode layer to fully fill the remaining portion of the sixth opening, and the upper portions of the lower electrode layer and the sacrificial layer may be planarized until the upper surface of the mold layer is exposed to divide the lower electrode layer. The remaining second sacrificial layer and the mold layer may be removed by, for example, a wet etching process, thereby forming a cylindrical lower electrode 510 on the exposed upper surface of the upper contact plug 455. In another embodiment, a pillar-shaped lower electrode may be formed to fill the sixth opening.

[0121] A dielectric layer 520 may be formed on the lower electrode 510 and the etch stop layer 500 , and an upper electrode 530 may be formed on the dielectric layer 520 to form a capacitor 540 including the lower electrode 510 , the dielectric layer 520 , and the upper electrode 530 .

[0122] A third insulating interlayer 550 may be formed to cover the capacitor 540. The third insulating interlayer 550 may include an oxide such as silicon oxide. An upper wiring (not shown) may be further formed on the third insulating interlayer 550 to complete the manufacture of the semiconductor device.

[0123] The method of designing a pattern layout, the method of forming a pattern, and the method of manufacturing a semiconductor device can be applied to methods of manufacturing logic devices (such as CPUs, MPUs, APs, etc.), volatile memory devices (such as DRAM devices, SRAM devices, etc.), or non-volatile memory devices (such as PRAM devices, MRAM devices, RRAM devices, etc.).

[0124] In summary and review, considering the distortion of the pattern layout during the exposure process, optical proximity correction (OPC) may be performed before designing the pattern layout and manufacturing the mask. However, when the pattern layout has an edge having an angle other than 0 degrees, 45 degrees, or 90 degrees relative to the reference line, OPC may not be automatically performed.

[0125] As described above, example embodiments may provide a method for designing a pattern layout. Example embodiments may also provide a method for forming a pattern using the method for designing a pattern layout. Example embodiments may also provide a method for manufacturing a semiconductor device using the method for designing a pattern layout.

[0126] As described above, in a method of designing a layout of a pattern according to an example embodiment, OPC may be automatically performed by a computer or processor using a computer program even if the layout of the original pattern includes edges having angles other than 0, 45, or 90 degrees relative to a reference line.

[0127] The various operations of the above methods may be performed as appropriate, such as by various hardware and / or software components, modules, and / or circuits. When implemented in software, the operations may be implemented using, for example, an ordered list of executable instructions for implementing logical functions, and may be embodied in a processor-readable medium for use with or in connection with an instruction execution system, apparatus, or device (such as a single-core or multi-core processor or a system containing a processor).

[0128] In some embodiments, the blocks or steps and functions of the methods or algorithms described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of software and hardware. If implemented in software, the functions may be stored or transmitted as one or more instructions or codes on a tangible, non-transitory computer-readable medium. The software module may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD ROM, or any other suitable form of storage medium.

[0129] Example embodiments have been disclosed herein, and although specific terms are employed, they are to be used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art at the time of filing this application, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly indicated otherwise. Accordingly, those skilled in the art will understand that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.

[0130] Korean Patent Application No. 10-2019-0128844, filed on October 17, 2019, in the Korean Intellectual Property Office and entitled “Method of designing a layout of a pattern, method of forming a pattern using the same, and method of manufacturing a semiconductor device using the same,” is hereby incorporated by reference in its entirety.

Claims

1. A method for designing a layout of a pattern, the method comprising: rotating a layout of an original pattern designed on a mask by a rotation angle in a first rotation direction to form a layout of a rotated pattern, wherein the mask includes a reference point; matching vertices and division points of the layout of the rotated pattern with corresponding reference points among the reference points of the mask, respectively, and connecting the matched reference points to form a layout of a first modified pattern, the corresponding reference points among the reference points of the mask being closest to the vertices and division points of the layout of the rotated pattern, respectively; expanding an area of ​​the layout of the first modified pattern to form a layout of a second modified pattern; forming a layout of a reference pattern having the same orientation as the layout of the rotated pattern; forming a layout of a target pattern based on an area where the layout of the reference pattern and the layout of the second modified pattern overlap each other; performing optical proximity correction on the layout of the target pattern to form a layout of a third modified pattern; as well as The layout of the third modified pattern is rotated by the rotation angle in a second rotation direction opposite to the first rotation direction to form a layout of a final pattern. 2 . The method of claim 1 , wherein the reference points are arranged in a grid in the mask, and the layout of the original pattern has a polygonal shape, vertices of the polygon respectively overlapping with reference points among the reference points.

3. The method of claim 2, wherein: The mask includes a reference line extending in a first direction to pass through a reference point among the reference points and a reference vertex among the vertices of the layout of the original pattern, and At least one of the edges of the layout of the primitive pattern has an angle with respect to the reference line, and the angle is not any one of 0 degrees, 45 degrees, and 90 degrees.

4. The method of claim 3, wherein: The layout of the rotated pattern is formed by rotating the original pattern about the reference vertex in the first rotation direction, and Some of the edges of the layout of the rotation pattern each have an angle of 0 degrees or 90 degrees with respect to the reference line, and the some of the edges of the layout of the rotation pattern intersect each other at the reference vertex.

5. The method of claim 3, wherein: each of the edges of the layout of the original pattern is divided into a plurality of segments by a dividing point, When forming the layout of the rotated pattern, some of the vertices and division points of the layout of the rotated pattern that respectively correspond to the vertices and division points of the layout of the original pattern do not overlap with the reference point, and The layout of the first modified pattern is formed by respectively matching the ones of the vertices and the division points of the layout of the rotated pattern that do not overlap with the reference points with corresponding reference points closest to the ones of the reference points. 6 . The method of claim 3 , wherein the layout of the second modified pattern is formed by stretching or moving each of edges of the layout of the first modified pattern in the first direction.

7. The method of claim 3, wherein the layout of the reference pattern comprises: a first line extending in a second direction perpendicular to the first direction to pass through the reference vertex of the layout of the original pattern; as well as Second lines extending in the second direction to pass through some of the reference points are spaced apart from the first lines in the first direction by a width of the layout of the primitive pattern in the first direction.

8. The method of claim 7, wherein the layout of the target pattern has a rectangular shape, the rectangle comprising: portions of the first and second lines of the layout of the reference pattern, each of the portions extending in the second direction between edges of the layout of the second modified pattern; as well as The portions of the edge of the layout of the second modified pattern, each of the portions extending in the first direction between the first line and the second line of the layout of the reference pattern.

9. The method of claim 1, wherein the optical proximity correction comprises corner rounding correction of the layout of the target pattern.

10. The method of claim 9, wherein: The layout of the target pattern includes edges, vertices, and division points, the edges intersecting each other at the vertices, the division points respectively overlapping corresponding reference points among the reference points and dividing each of the edges into a plurality of segments, and The corner rounding correction of the layout of the target pattern is performed based on data on the vertices and the division points of the layout of the target pattern.

11. The method of claim 1 , wherein: The plurality of layouts of the original pattern are designed to be spaced apart from each other by a distance along a first direction on the mask, and A plurality of layouts of the rotated pattern, a plurality of layouts of the first modified pattern, a plurality of layouts of the second modified pattern, a plurality of layouts of the third modified pattern, a plurality of layouts of the reference pattern, a plurality of layouts of the target pattern, and a plurality of layouts of the final pattern are formed. 12 . The method of claim 11 , wherein the plurality of layouts of the reference patterns are formed to correspond to the plurality of layouts of the second modification patterns, respectively, and are spaced apart from each other by a distance in the first direction.

13. The method of claim 1 , wherein the rotation of the layout of the original pattern, the matching of the vertices and division points of the layout of the rotated pattern with corresponding reference points among the reference points, the expansion of the area of ​​the layout of the first modified pattern, the formation of the layout of the reference pattern, the formation of the layout of the target pattern, the execution of the optical proximity correction, and the rotation of the layout of the third modified pattern are automatically performed by a computer processor.

14. A method for designing a layout of a pattern, the method comprising: rotating a layout of an original pattern designed on a mask by a rotation angle in a first rotation direction to form a layout of a rotated pattern, the mask including reference points arranged in a grid and reference lines extending in the first direction to pass through reference points among the reference points, the layout of the original pattern having a polygonal shape including edges intersecting each other at vertices, each of the edges having an angle with respect to the reference line, the angle being not any one of 0 degrees, 45 degrees, and 90 degrees, and the vertices respectively overlapping with reference points among the reference points; matching vertices and division points of the layout of the rotated pattern with corresponding reference points among the reference points of the mask, respectively, and connecting the matched reference points to form a layout of a first modified pattern, the corresponding reference points among the reference points of the mask being closest to the vertices and division points of the layout of the rotated pattern, respectively; expanding an area of ​​the layout of the first modified pattern to form a layout of a second modified pattern; forming a layout of a reference pattern having the same orientation as the layout of the rotated pattern; forming a layout of a target pattern based on an area where the layout of the reference pattern and the layout of the second modified pattern overlap each other; performing optical proximity correction on the layout of the target pattern to form a layout of a third modified pattern; as well as The layout of the third modified pattern is rotated by the rotation angle in a second rotation direction opposite to the first rotation direction to form a layout of a final pattern.

15. The method of claim 14, wherein: The layout of the rotated pattern is formed by rotating the original pattern in the first rotation direction about a reference vertex among the vertices of the layout of the original pattern, the reference vertex being passed through by the reference line, and Some of the edges of the layout of the rotation pattern each have an angle of 0 degrees or 90 degrees with respect to the reference line, and the some of the edges of the layout of the rotation pattern intersect each other at the reference vertex.

16. The method of claim 15, wherein the layout of the reference pattern comprises: a first line extending in a second direction perpendicular to the first direction to pass through the reference vertex of the layout of the original pattern; as well as A second line extending in the second direction to pass through a reference point among the reference points, the second line being spaced apart from the first line in the first direction by a distance of the width of the layout of the primitive pattern in the first direction.

17. The method of claim 14, wherein: each of the edges of the layout of the original pattern is divided into a plurality of segments by a dividing point, When forming the layout of the rotated pattern, some of the vertices and division points of the layout of the rotated pattern that respectively correspond to the vertices and division points of the layout of the original pattern do not overlap with the reference point, and The layout of the first modified pattern is formed by matching the ones of the vertices and the division points of the layout of the rotated pattern that do not overlap with the reference points with corresponding reference points among the reference points that are respectively closest to the ones of the vertices and the division points. 18 . The method of claim 14 , wherein the layout of the second modified pattern is formed by stretching or moving each of edges of the layout of the first modified pattern in the first direction.

19. A method for forming a pattern, the method comprising: Design the layout of the final pattern on the mask, including: rotating a layout of an original pattern designed on the mask by a rotation angle in a first rotation direction to form a layout of a rotated pattern, wherein the mask includes a reference point; matching the vertices and the division points of the layout of the rotated pattern with corresponding reference points among the reference points of the mask, respectively, and connecting the matched reference points to form a layout of a first modified pattern, wherein the corresponding reference points among the reference points of the mask are respectively closest to the vertices and the division points of the layout of the rotated pattern; expanding an area of ​​the layout of the first modified pattern to form a layout of a second modified pattern; forming a layout of a reference pattern having the same orientation as the layout of the rotated pattern; forming a layout of a target pattern based on an area where the layout of the reference pattern and the layout of the second modified pattern overlap each other; performing optical proximity correction on the layout of the target pattern to form a layout of a third modified pattern; and rotating the layout of the third modified pattern by the rotation angle in a second rotation direction opposite to the first rotation direction to form the layout of the final pattern; and The pattern is formed on a substrate using the mask on which the layout of the final pattern is designed.

20. The method of claim 19, wherein an etching target layer and a photoresist layer are sequentially stacked on the substrate, and forming the pattern on the substrate comprises: performing an exposure process using the mask on which the layout of the final pattern is designed, thereby transferring the layout of the final pattern to the photoresist layer, the photoresist layer having the layout of the pattern; performing a developing process to transform the photoresist layer into a photoresist pattern having the layout of the pattern; as well as The etching target layer is etched using the photoresist pattern as an etching mask.

21. The method of claim 20, wherein the layout of the pattern of the photoresist layer is similar to the layout of the original pattern designed on the mask.

22. The method of claim 20, wherein an etching mask layer is further formed on the substrate between the etching target layer and the photoresist layer, and etching the etching target layer using the photoresist pattern comprises: etching the etch mask layer using the photoresist pattern to form an additional etch mask; as well as The etching target layer is etched using the additional etching mask.

23. The method of claim 19, wherein: The reference points are arranged in a grid in the mask, and Vertices of the layout of the original pattern respectively overlap with reference points among the reference points.

24. The method of claim 23, wherein: The mask includes a reference line extending in a first direction to pass through a reference point among the reference points and a reference vertex among the vertices of the layout of the original pattern, and At least one of the edges of the layout of the primitive pattern has an angle with respect to the reference line, and the angle is not any one of 0 degrees, 45 degrees, and 90 degrees.

25. A method for manufacturing a semiconductor device, the method comprising: Design the layout of the final pattern on the mask, including: rotating a layout of an original pattern designed on the mask by a rotation angle in a first rotation direction to form a layout of a rotated pattern, wherein the mask includes a reference point; matching the vertices and the division points of the layout of the rotated pattern with corresponding reference points among the reference points of the mask, respectively, and connecting the matched reference points to form a layout of a first modified pattern, wherein the corresponding reference points among the reference points of the mask are respectively closest to the vertices and the division points of the layout of the rotated pattern; expanding an area of ​​the layout of the first modified pattern to form a layout of a second modified pattern; forming a layout of a reference pattern having the same orientation as the layout of the rotated pattern; forming a layout of a target pattern based on an area where the layout of the reference pattern and the layout of the second modified pattern overlap each other; performing optical proximity correction on the layout of the target pattern to form a layout of a third modified pattern; and rotating the layout of the third modified pattern by the rotation angle in a second rotation direction opposite to the first rotation direction to form the layout of the final pattern; forming an active pattern on a substrate using the mask on which the layout of the final pattern is designed; forming a gate structure on an upper portion of the active pattern; forming a bit line structure on a portion of the active pattern; forming a contact plug structure on a portion of the active pattern; and A capacitor is formed on the contact plug structure.

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