Ceramic electronic device and manufacturing method thereof
By adding Zr to the ceramic protective part and adjusting the A/B ratio, the problem of insufficient sintering of ceramic electronic devices at high heating rates is solved, achieving ceramic electronic devices with hardness and crack resistance suitable for automotive use.
Patent Information
- Application Number
- CN202011108116.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2019-10-17
- Filing Date
- 2020-10-16
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2040-10-16
AI Technical Summary
During the manufacturing process of ceramic electronic devices, although increasing the heating rate can improve the continuity of the internal electrode layer, the high heating rate causes the ceramic protective part to not be fully sintered, resulting in insufficient surface hardness of the device, which may cause cracks and electrical short circuits; while reducing the heating rate or increasing the firing temperature may cause excessive sintering of the internal electrode layer.
By adding Zr to the ceramic protective part and adjusting the A/B ratio to 0.990 or less, controlling the Zr/Ti ratio between 0.010 and 0.25, using a perovskite structured ceramic material, ensuring that the ceramic protective part is fully sintered at a high heating rate, and promoting sintering by adding sintering aids such as oxides or glass compositions of Mn, V, Si, and B, controlling grain growth, and improving hardness.
This ensures that the ceramic protective portion is fully sintered and has sufficient hardness at a high heating rate, avoiding cracks and electrical short circuits, making it suitable for applications requiring resistance to mechanical stress, such as automotive applications.
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Figure CN112687468B_ABST
Abstract
Description
Technical Field
[0001] One aspect of the present invention relates to a ceramic electronic device and a method for manufacturing the same. Background Art
[0002] It is known that internal electrode layers and dielectric layers are alternately stacked in ceramic electronic devices such as laminated ceramic capacitors. A technique has been disclosed in which the continuity of the internal electrode layers is improved by increasing the heating rate to 3000°C / h when manufacturing the ceramic electronic device by firing (for example, see "J. Am. Ceram. Soc., 90
[12] 3811-3817 (2007)"). Summary of the Invention
[0003] The inventors have discovered that even by further increasing the heating rate, the continuity of the internal electrode layers can be improved. However, when the heating rate is high, the ceramic protector, which protects the internal electrode layers, is not fully sintered. If the ceramic protector is not fully sintered, the surface hardness of the ceramic electronic device is insufficient, potentially causing cracks. If cracks caused by these cracks reach the internal electrode layers through the ceramic protector, an electrical short circuit may occur. However, if the heating rate is reduced or the firing temperature is increased to fully sinter the ceramic protector, the internal electrode layers may be over-sintered.
[0004] An object of the present invention is to provide a ceramic electronic device and a method for manufacturing the ceramic electronic device, which can ensure sufficient mechanical hardness of the ceramic protective portion even when the firing temperature rise rate is high.
[0005] According to one aspect of the present invention, a ceramic electronic device is provided, comprising a stacked structure in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked, the dielectric layers being mainly composed of ceramic, the stacked structure having a rectangular parallelepiped shape, the plurality of internal electrode layers being alternately exposed to a first end face and a second end face of the stacked structure, the first end face being opposite to the second end face, wherein a ceramic protective portion comprises a cover layer and a side edge, wherein the cover layer is provided on at least one of upper and lower faces of the stacked structure in a stacking direction, wherein in the stacked structure, the side edge is a region covering edge portions of the plurality of internal electrode layers extending toward two side faces other than the first and second end faces, wherein a main component of the ceramic protective portion is a ceramic material having a perovskite structure represented by the general formula ABO3, wherein the A site of the perovskite structure contains at least Ba, wherein the B site of the perovskite structure contains at least Ti and Zr, wherein the Zr / Ti ratio, which is the molar ratio of Zr to Ti, is 0.010 or greater and 0.25 or less, and wherein the A / B ratio, which is the molar ratio of the A site to the B site, is 0.990 or less.
[0006] According to another aspect of the present invention, a method for manufacturing a ceramic electronic device is provided, comprising: preparing a ceramic stacking structure including a stacking portion, a covering sheet and a side edge portion; firing the ceramic stacking structure, wherein, in the stacking portion, a plurality of sheets including particles whose main component is ceramic and a plurality of metal conductive paste patterns are alternately stacked, and the above-mentioned plurality of metal conductive paste patterns are alternately exposed to a first end face and a second end face of the ceramic stacking structure, the first end face being opposite to the second end face, wherein the covering sheet is arranged on at least one of the upper and lower surfaces in the stacking direction of the stacking portion, wherein the side edge portion is arranged on a side surface of the stacking portion, wherein the main component ceramic of the covering sheet and the side edge portion before firing is a ceramic material having a perovskite structure represented by the general formula ABO3, wherein the A site of the perovskite structure contains at least Ba, wherein the B site of the perovskite structure contains at least Ti and Zr, wherein the Zr / Ti ratio as the molar ratio of Zr and Ti is 0.010 or greater and 0.25 or less, and wherein the A / B ratio as the molar ratio of the A site and the B site is 0.990 or less. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 A partial perspective view showing a stacked ceramic capacitor;
[0008] Figure 2 Shown along Figure 1 The cross-sectional view taken along line AA;
[0009] Figure 3 Shown along Figure 1 The cross-sectional view taken along line BB;
[0010] Figure 4A an enlarged view showing a cross section of the side edge;
[0011] Figure 4B an enlarged view showing a cross section of the end edge;
[0012] Figure 5 The relationship between the grain size of the surface of the ceramic protection portion and the Vickers hardness HV of the surface is shown;
[0013] Figure 6 A flowchart showing a method for manufacturing a laminated ceramic capacitor;
[0014] Figure 7A and Figure 7B The lamination process is shown;
[0015] Figure 8 The lamination process is shown;
[0016] Figure 9 The lamination process is shown;
[0017] Figure 10AThe Vickers hardness HV of the surface of the ceramic protective portion in each of Examples 1 to 4 and Comparative Examples 1 and 2 is shown;
[0018] Figure 10B shows the Vickers hardness HV of the surface of the ceramic protection portion when the firing temperature is 1190° C.; and
[0019] Figure 11 The Vickers hardness HV of the surface of the ceramic protective portion in each of Examples 3 and 5 to 7 and Comparative Example 3 is shown. DETAILED DESCRIPTION
[0020] The embodiments will be described with reference to the accompanying drawings.
[0021] [Implementation Method]
[0022] Figure 1 A partial perspective view of a stacked ceramic capacitor 100 according to an embodiment is shown. Figure 2 Shown along Figure 1 Cross-sectional view taken along line AA. Figure 3 Shown along Figure 1 The cross-sectional view taken along line BB. Figures 1 to 3 As shown, a multilayer ceramic capacitor 100 includes a rectangular parallelepiped multilayer chip 10 and a pair of external electrodes 20a and 20b, respectively, disposed on two opposing end surfaces of the multilayer chip 10. Of the four surfaces, excluding the two end surfaces, the two surfaces other than the upper and lower surfaces in the stacking direction are referred to as side surfaces. External electrodes 20a and 20b extend to the upper and lower surfaces and both side surfaces. However, external electrodes 20a and 20b are spaced apart from each other.
[0023] The laminated chip 10 has a structure designed to have alternating dielectric layers 11 and internal electrode layers 12. The dielectric layers 11 comprise a ceramic material serving as the dielectric material. The internal electrode layers 12 comprise a base metal. The end edges of the internal electrode layers 12 alternately expose a first end face of the laminated chip 10 and a second end face of the laminated chip 10 that is different from the first end face. In the embodiment, the first face and the second face are opposite each other. External electrodes 20a are provided on the first end face. External electrodes 20b are provided on the second end face. Thus, the internal electrode layers 12 alternately connect to the external electrodes 20a and 20b. Thus, the laminated ceramic capacitor 100 has a structure in which multiple dielectric layers 11 are stacked, with each pair of dielectric layers 11 sandwiching an internal electrode layer 12. In the laminated structure of the dielectric layers 11 and the internal electrode layers 12, the two internal electrode layers 12 are the outermost layers. The upper and lower faces of the laminated structure in the stacking direction are covered with cover layers 13. The main component of the cover layer 13 is a ceramic material. For example, the main component of the cover layer 13 is the same as the main component of the dielectric layer 11 .
[0024] For example, the laminated ceramic capacitor 100 may have a length of 0.25 mm, a width of 0.125 mm, and a height of 0.125 mm. The laminated ceramic capacitor 100 may have a length of 0.4 mm, a width of 0.2 mm, and a height of 0.2 mm. The laminated ceramic capacitor 100 may have a length of 0.6 mm, a width of 0.3 mm, and a height of 0.3 mm. The laminated ceramic capacitor 100 may have a length of 1.0 mm, a width of 0.5 mm, and a height of 0.5 mm. The laminated ceramic capacitor 100 may have a length of 3.2 mm, a width of 1.6 mm, and a height of 1.6 mm. The laminated ceramic capacitor 100 may have a length of 4.5 mm, a width of 3.2 mm, and a height of 2.5 mm. However, the size of the laminated ceramic capacitor 100 is not limited.
[0025] The main component of the internal electrode layer 12 is a base metal such as nickel (Ni), copper (Cu), tin (Sn), etc. The internal electrode layer 12 can be made of a precious metal such as platinum (Pt), palladium (Pd), silver (Ag), gold (Au), or an alloy thereof. The average thickness of the internal electrode layer 12 is, for example, 1 μm or less. The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3. The perovskite structure includes ABO with a non-stoichiometric composition. 3-α。 In an embodiment, the A site of the ceramic material contains at least Ba (barium), and the B site of the ceramic material contains at least Ti (titanium).
[0026] like Figure 2 As shown, the region where one group of internal electrode layers 12 connected to external electrode 20 a faces another group of internal electrode layers 12 connected to external electrode 20 b is a region where capacitance is generated in multilayer ceramic capacitor 100. Therefore, this region is referred to as capacitance region 14. That is, capacitance region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.
[0027] The region where internal electrode layers 12 connected to external electrode 20a face each other without sandwiching internal electrode layer 12 connected to external electrode 20b is referred to as edge 15. The region where internal electrode layers 12 connected to external electrode 20b face each other without sandwiching internal electrode layer 12 connected to external electrode 20a is another edge 15. In other words, edge 15 is a region where a group of internal electrode layers 12 connected to one external electrode face each other without sandwiching internal electrode layer 12 connected to the other external electrode. Edge 15 is a region in which no capacitance is generated in multilayer ceramic capacitor 100.
[0028] like Figure 3As shown, the region of the laminated chip 10 extending from both sides thereof to the internal electrode layer 12 is referred to as a side edge 16. That is, the side edge 16 is a region covering the edges of the laminated internal electrode layer 12 in the direction extending toward both side surfaces.
[0029] The cover layer 13 and the side edge 16 surround the outer periphery of the capacitor region 14, thereby protecting the capacitor region 14. Therefore, the cover layer 13 and the side edge 16 are referred to as a ceramic protection portion 50 hereinafter.
[0030] Figure 4A An enlarged view of a cross section of side edge 16 is shown. Side edge 16 has a structure in which dielectric layers 11 and reverse pattern layers 17 are alternately stacked in the stacking direction of dielectric layers 11 and internal electrode layers 12 in capacitor region 14. Each dielectric layer 11 in capacitor region 14 is formed continuously with each dielectric layer 11 in side edge 16. This structure suppresses the height difference between capacitor region 14 and side edge 16.
[0031] Figure 4B An enlarged view of a cross section of edge 15 is shown. In edge 15, every other internal electrode layer 12 extends to the edge surface of edge 15, compared to side edge 16. In the layers where internal electrode layers 12 extend to the edge surface of edge 15, no reverse pattern layer 17 is provided. Each dielectric layer 11 in capacitor region 14 is formed continuously with each dielectric layer 11 in edge 15. This structure minimizes the height difference between capacitor region 14 and edge 15.
[0032] Internal electrode layers 12 are formed by firing a metallic conductive paste containing metal powder. Dielectric layers 11 and cover layers 13 are formed by firing dielectric green sheets containing ceramic powder. However, sintering conditions vary depending on the material. For example, a slow temperature increase during firing reduces the continuity of internal electrode layers 12. However, it is known that a temperature increase of 3000°C / h or greater during firing improves the continuity of internal electrode layers 12.
[0033] The present inventors have confirmed that even if the heating rate is further increased, the continuity of the internal electrode layer 12 can be improved. However, when the heating rate is too high (for example, 6000°C / h or higher), the sintering of the ceramic protection portion 50 is insufficient. When the ceramic protection portion 50 is not sufficiently sintered, the hardness of the surface of the stacked ceramic capacitor 100 is not large enough, and defects may occur. When cracks caused by defects reach the internal electrode layer 12 through the ceramic protection portion 50, an electrical short circuit may occur. However, when the heating rate is reduced or the firing temperature is increased to sufficiently promote the sintering of the ceramic protection portion 50, the internal electrode layer 12 may be over-sintered.
[0034] Therefore, it is considered to add oxides of Mn (manganese), V (vanadium), Si (silicon), B (boron), etc., or a glass composition containing these oxides as a sintering aid to the ceramic protective portion 50 to promote the sintering of the ceramic protective portion 50. The sintering aid becomes a liquid phase during sintering and helps densify the surface of the main component ceramic through dissolution and reprecipitation. However, at high heating rates such as 6000°C / h or higher, the effect of improving densification is limited because sufficient time for dissolution and reprecipitation cannot be fully ensured.
[0035] Therefore, it is considered to add Zr (zirconium) to the ceramic protective portion 50 to promote sintering. For example, it is considered to add Zr in an amount approximately equal to that of Ba to adjust the sintering characteristics. This is because the A / B ratio, which is the molar ratio of A sites to B sites in the perovskite sintered structure, is important, and maintaining a constant A / B ratio is crucial for sintering characteristics. For example, Zr can be added in the form of BaZrO3, CaZrO3, SrZrO3, etc.
[0036] However, the present inventors have found that when Zr is added at a high heating rate, such as 6000°C / h or higher, sintering may be delayed. This is because when the A / B ratio is 1.000 or greater, the grain growth of perovskite is suppressed and the A-site element present at a high concentration at the grain boundary hinders diffusion between perovskite grains.
[0037] Therefore, the present inventors have discovered that when the A / B ratio is greatly shifted toward the B-rich side and the perovskite has a Zr-rich composition, the ceramic protection portion 50 is sufficiently sintered at a high heating rate.
[0038] When the amount of Zr is too small, the ceramic protection portion 50 may not obtain the necessary sintering at a high temperature rise rate. Therefore, in the present embodiment, the amount of Zr in the ceramic protection portion 50 has a lower limit. Specifically, the Zr / Ti ratio, which is the molar ratio of Zr to Ti in the main component ceramic of the ceramic protection portion 50, is 0.010 or greater. The Zr / Ti ratio is preferably 0.015 or greater. The Zr / Ti ratio is more preferably 0.020 or greater. On the other hand, when the amount of Zr is too large, abnormal grain growth may occur on the surface of the ceramic protection portion 50 and sufficient hardness may not be obtained. Therefore, in the present embodiment, the amount of Zr in the ceramic protection portion 50 has an upper limit. Specifically, the Zr / Ti ratio is 0.25 or less. The Zr / Ti ratio is preferably 0.20 or less. The Zr / Ti ratio is more preferably 0.16 or less.
[0039] Next, even if a sufficient amount of Zr is added to the ceramic protection portion 50, when the A / B ratio is large, it may not necessarily promote the sintering of the ceramic protection portion 50. Therefore, in this embodiment, the A / B ratio has an upper limit. Specifically, the A / B ratio of the main component ceramic of the ceramic protection portion 50 is 0.990 or less. The "A" of the A / B ratio is the total molar amount of elements that can be dissolved in the A site. For example, when the ceramic protection portion 50 includes a ceramic material having a perovskite structure represented by the general formula ABO3, which contains at least Ba in the A site and contains Ti and Zr in the B site, "A" means the total amount of Ba and elements that can be dissolved in the A site, such as Ca, Sr or rare earth elements. The "B" of the A / B ratio is the total molar amount of elements that can be dissolved in the B site. For example, "B" means the total amount of Ti and Zr. The A / B ratio is preferably 0.985 or less. The A / B ratio is more preferably 0.982 or less. On the other hand, if the A / B ratio is too low, abnormal appearance or insufficient densification due to localized abnormal grain growth may occur, or large pores may form. Therefore, the A / B ratio preferably has a lower limit. For example, the A / B ratio is preferably 0.900 or greater. The A / B ratio is more preferably 0.920 or greater. The A / B ratio is more preferably 0.940 or greater.
[0040] Figure 5 The figure shows the relationship between the grain size of the surface of the ceramic protection portion 50 and the Vickers hardness HV of the surface after firing when the ceramic protection portion 50 is fired using ceramic powder having an average particle size of 0.5 μm. Figure 5 As shown, as the densification of the ceramic protection portion 50 is promoted, the Vickers hardness HV becomes larger. However, if sintering is continued and the grain diameter becomes larger due to grain growth, the Vickers hardness HV becomes lower. The Vickers hardness HV of the surface of the ceramic protection portion 50 is preferably 600 or greater. Therefore, it is preferred that the average grain diameter of the surface of the ceramic protection portion 50 has an upper limit. Figure 5 In the present invention, there is a case where HV ≥ 600 is satisfied even if the average grain diameter is about 3 μm. However, from the viewpoint of the distribution of grain diameters or contamination of abnormally grown grains, the average grain diameter on the surface of the ceramic protection portion 50 is preferably 2.0 μm or less. The average grain diameter is more preferably 1.5 μm or less. The average grain diameter is more preferably 1.2 μm or less. The average grain diameter can be calculated as the average value of the maximum diameters of grains in a direction parallel to the internal electrode layer in one field of view in an SEM (scanning electron microscope) image obtained at a magnification such that 100 or more grains are included in one field of view.
[0041] It is preferable that the main component ceramic of the region other than the ceramic protection portion 50 (at least one of the capacitor region 14 and the edge 15) has the same composition as that of the ceramic protection portion 50. In this case, even when firing a large-sized product at a rapid temperature increase rate, internal deformation caused by the difference between internal and external sintering can be suppressed. This product is suitable for applications requiring resistance to mechanical stress, such as automotive applications.
[0042] Next, a method of manufacturing the laminated ceramic capacitor 100 will be described. Figure 6 A method for manufacturing the multilayer ceramic capacitor 100 is shown.
[0043] (Process for producing raw material powder) A dielectric material for forming the dielectric layer 11 is prepared. The dielectric material includes a ceramic which is a main component of the dielectric layer 11. Generally, the A-site element and the B-site element are contained in the dielectric layer 11 in the form of a sintered phase of ABO3 grains. For example, BaTiO3 is a tetragonal compound having a perovskite structure and a high dielectric constant. Generally, BaTiO3 is obtained by reacting a titanium material such as titanium dioxide with a barium material such as barium carbonate to synthesize barium titanate. Various methods can be used as a method for synthesizing the ceramic for obtaining the dielectric layer 11. For example, a solid phase method, a sol-gel method, a hydrothermal method, etc. can be used. This embodiment can use any of these methods.
[0044] An additive compound may be added to the obtained ceramic powder according to the purpose. The additive compound may be an oxide or glass of Zr, Ca, Sr, Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), or a rare earth element (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), and Yb (ytterbium)), or Co (cobalt), Ni, Li (lithium), B, Na (sodium), K (potassium), and Si.
[0045] Next, a reverse pattern material for forming the end edge 15 and the side edge 16 is prepared. The reverse pattern material includes a main component ceramic of the end edge 15 and the side edge 16. For example, BaTiO3 powder is made into a main component ceramic. BaTiO3 powder can be manufactured by the same method as the dielectric material. An additive compound can be added to the obtained BaTiO3 powder according to the purpose. The additive compound can be an oxide or glass of Zr, Ca, Sr, Mg, Mn, V, Cr or a rare earth element (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm and Yb), or Co, Ni, Li, B, Na, K and Si. The dielectric material can be used as the reverse pattern material.
[0046] Next, a covering material for forming the covering layer 13 is prepared. The covering material includes a ceramic as the main component of the covering layer 13. For example, BaTiO3 powder is made into a ceramic as the main component. BaTiO3 powder can be produced by the same method as the dielectric material. An additive compound can be added to the obtained BaTiO3 powder according to the purpose. The additive compound can be an oxide or glass of Zr, Ca, Sr, Mg, Mn, V, Cr or a rare earth element (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm and Yb), or Co, Ni, Li, B, Na, K and Si. The dielectric material can be used as the covering material.
[0047] (Lamination Process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the resulting dielectric material and wet-mixed. Using the resulting slurry, a strip-shaped dielectric green sheet 51 having a thickness of 0.8 μm or less is applied to a substrate by, for example, a die coater method or a doctor blade method, and then dried.
[0048] Next, if Figure 7A As shown, a metal conductive paste for forming internal electrodes is applied to the surface of a dielectric green sheet 51 by screen printing or gravure printing. The metal conductive paste includes an organic binder. Thus, a first pattern 52 for forming an internal electrode layer is provided. Ceramic particles are added to the metal conductive paste as an auxiliary material. The main component of the ceramic particles is not limited. However, it is preferred that the main component of the ceramic particles be the same as that of the dielectric layer 11.
[0049] Next, a binder and an organic solvent are added to the reverse pattern material produced in the raw material powder production process. The binder is, for example, ethyl cellulose. The organic solvent is, for example, terpineol. The reverse pattern material is then kneaded with the binder and the organic solvent. Thus, a reverse pattern paste for forming a reverse pattern layer is obtained. Figure 7A As shown, a reverse pattern paste is printed on the peripheral area of the dielectric green sheet 51. This peripheral area is a portion of the dielectric green sheet 51 where the first pattern 52 is not printed. Thus, the second pattern 53 is provided. Thus, the height difference caused by the first pattern 52 is masked.
[0050] Then, if Figure 7B As shown, each of the dielectric green sheets 51, each of the first patterns 52, and each of the second patterns 53 are alternately stacked so that the internal electrode layers 12 and the dielectric layers 11 alternate with each other. The end edges of the internal electrode layers 12 are alternately exposed to the end surfaces along the length direction of the dielectric layers 11, thereby alternately leading to a pair of external electrodes 20a and 20b with different polarizations. For example, the total number of stacked dielectric green sheets 51 is 100 to 500.
[0051] Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the covering material produced in the raw material production process and wet-mixed. Using the resulting slurry, a strip-shaped covering sheet 54 having a thickness of 10 μm or less is applied to the substrate by, for example, a die coater method or a doctor blade method, and then dried. Figure 8 As shown, a predetermined number of cover sheets 54 (e.g., 2 to 10 layers) are stacked on the upper surface of the stacked dielectric green sheets 51 and clamped. Another predetermined number of cover sheets 54 (e.g., 2 to 10 layers) are stacked on the lower surface of the stacked dielectric green sheets 51 and clamped. The resulting stacked structure is punched into a predetermined size (e.g., 1.0 mm x 0.5 mm). A metallic conductive paste, to become the external electrodes 20 a and 20 b, is then applied to both edge surfaces of the cut stacked structure by dipping or the like and dried. This results in a ceramic stacked structure. A predetermined number of stacked cover sheets 54 can be placed on both the upper and lower surfaces of the stacked dielectric green sheets 51.
[0052] exist Figures 7A to 8 In the method, the portion of the dielectric green sheet 51 corresponding to the first pattern 52 is laminated with the first pattern 52 to serve as a laminated portion, in which a plurality of sheets containing BaTiO3 particles, whose main component is ceramic, and a plurality of metal conductive paste patterns are alternately laminated. The remaining portion of the dielectric green sheet 51, in which the region extending beyond the first pattern 52 is laminated with the second pattern 53, serves as a side edge portion provided on the side of the laminated portion.
[0053] The side edge portion may be attached to the side of the laminate portion, or may be applied to the side of the laminate portion. Figure 9 As shown, dielectric green sheets 51 and first patterns 52 having the same width as the dielectric green sheets 51 are alternately stacked. This forms a stacked portion. Next, a sheet formed from a reverse pattern paste is attached to the side of the stacked portion. Alternatively, the side edges can be formed by applying a reverse pattern paste to the side surfaces.
[0054] exist Figures 7A to 9 In the method, the amount of additives added in the raw material manufacturing process is adjusted so that in the region corresponding to the ceramic protective portion 50, the Zr / Ti ratio is 0.02 or more and 0.16 or less, and the A / B ratio is 0.982 or less.
[0055] (Firing process) The binder is removed under N2 atmosphere. Thereafter, Ni paste to be used as the ground layer of the external electrodes 20a and 20b is applied to the obtained ceramic laminate structure. -5 to 10 -8The obtained ceramic laminate structure is fired in a reducing atmosphere of 500 Å at 100° C. to 1300° C. for 10 minutes to 2 hours. In this way, the ceramic capacitor 100 is obtained.
[0056] (Reoxidation Process) After that, a reoxidation process is performed in a N2 atmosphere at a temperature range of 600°C to 1000°C.
[0057] (Plating Process) After that, metals such as Cu, Ni, and Sn are applied to the external electrodes 20a and 20b by electroplating or the like.
[0058] With this manufacturing method, the Zr / Ti ratio of the region corresponding to the ceramic protection portion 50 is 0.010 or greater. Consequently, the ceramic protection portion 50 is sufficiently sintered. On the other hand, a Zr / Ti ratio of 0.25 or less suppresses abnormal grain growth, achieving sufficient hardness on the surface of the ceramic protection portion 50. Furthermore, the A / B ratio of the region corresponding to the ceramic protection portion 50 is 0.990 or less. Therefore, the A / B ratio is sufficiently low. Furthermore, the ceramic protection portion 50 is sufficiently sintered.
[0059] The Zr / Ti ratio is preferably 0.015 or greater. The Zr / Ti ratio is more preferably 0.020 or greater. The Zr / Ti ratio is preferably 0.20 or less. The Zr / Ti ratio is more preferably 0.16 or less. The A / B ratio is preferably 0.985 or less. The A / B ratio is more preferably 0.982 or less. The A / B ratio is preferably 0.920 or greater. The A / B ratio is more preferably 0.940 or greater. It is preferred that the firing conditions such as the firing temperature or the firing time are adjusted so that the average grain diameter on the surface of the ceramic protection portion 50 after firing is 2.0 μm or less. More preferably, the firing conditions are adjusted so that the average grain diameter is 1.5 μm or less. More preferably, the firing conditions are adjusted so that the average grain diameter is 1.2 μm or less.
[0060] As mentioned above Figure 5As described above, as grain growth is promoted, the Vickers hardness HV becomes lower. Therefore, it is preferred that grain growth has an upper limit. For example, it is preferred to adjust the firing conditions so that the average grain diameter on the surface of the ceramic protection portion 50 after firing is 10 times or less of the average particle size of the main component ceramic powder in the area corresponding to the ceramic protection portion 50 in the ceramic laminate structure before firing. More preferably, the firing conditions are adjusted so that the average grain diameter on the surface of the ceramic protection portion 50 after firing is 4 times or less of the average particle size of the main component ceramic powder in the area corresponding to the ceramic protection portion 50 in the ceramic laminate structure before firing. More preferably, the firing conditions are adjusted so that the average grain diameter on the surface of the ceramic protection portion 50 after firing is 2.5 times or less of the average particle size of the main component ceramic powder in the area corresponding to the ceramic protection portion 50 in the ceramic laminate structure before firing.
[0061] From the viewpoint of improving the continuity of the internal electrode layer 12, the maximum temperature increase rate in the firing step is preferably greater than 3000°C / h. More preferably, the maximum temperature increase rate is 6000°C / h or greater. Even more preferably, the maximum temperature increase rate is 9000°C / h or greater.
[0062] The firing temperature (the maximum temperature of the firing process) is preferably 860°C or higher. The firing temperature is more preferably 1000°C or higher. The firing temperature is even more preferably 1100°C or higher. This is because increasing the firing temperature promotes densification. The firing temperature is preferably 1250°C or lower. The firing temperature is more preferably 1200°C or lower. The firing temperature is even more preferably 1150°C or lower. This is because when the firing temperature is low, the thermal energy applied to the internal electrode layer 12 is small, thereby suppressing cracking of the internal electrode layer 12.
[0063] In the embodiments, the stacked ceramic capacitor is described as an example of a ceramic electronic device. However, the embodiments are not limited to the stacked ceramic capacitor. For example, the embodiments may be applied to another electronic device such as a varistor or a thermistor.
[0064] [Example]
[0065] (Example 1) An additive compound was added to barium titanate powder. The barium titanate powder and the additive compound were wet-mixed and pulverized in a ball mill. Thus, a dielectric material was obtained. An additive compound was added to barium titanate powder. The barium titanate powder and the additive compound were wet-mixed and pulverized in a ball mill. Thus, a reverse pattern material was obtained. An additive compound was added to barium titanate powder. The barium titanate powder and the additive compound were wet-mixed and pulverized in a ball mill. Thus, a covering material was obtained.
[0066] A butyral-based material as an organic binder is added to the dielectric material. Toluene and ethanol as solvents are added to the dielectric material. A dielectric green sheet 51 is manufactured by a doctor blade method. A metal conductive paste as the first pattern 52 is printed on the resulting dielectric green sheet 51. A binder such as ethyl cellulose and an organic solvent such as terpineol are added to the reverse pattern material. The reverse pattern material is then kneaded with the binder and the organic solvent by a roller mill. A reverse pattern paste is thus manufactured. The resulting reverse pattern paste as the second pattern 53 is printed on the portion of the dielectric green sheet 51 where the first pattern 52 is not printed. 250 dielectric green sheets 51 printed with the first pattern 52 and the second pattern 53 are stacked.
[0067] A butyral-based material was added to the cover material as an organic binder. Toluene and ethanol were added to the cover material as solvents. The cover sheet was produced using a doctor blade method. The cover sheet was laminated on both the upper and lower surfaces of the laminated dielectric green sheets and heat-clamped. The cover sheet had a thickness of 30 μm.
[0068] In the region corresponding to the ceramic protection portion 50 , the Zr / Ti ratio was 0.020 and the A / B ratio was 0.960.
[0069] After that, the binder was removed in N2 atmosphere. Ni external electrodes were formed on the formed laminated structure by dipping. In a reducing atmosphere (O2 partial pressure: 10 -5 to 10 -8 The resulting laminated structure is fired in a molten-crystal sieve (1000 nm) at 400 nm. This forms a sintered structure. The sintered structure has a length of 1.0 mm, a width of 0.5 mm, and a height of 0.5 mm. The sintered structure is subjected to a reoxidation process at 800°C in an N2 atmosphere. Thereafter, metal layers of Cu, Ni, and Sn are plated on the surfaces of the external electrodes by plating. Thus, a laminated ceramic capacitor 100 is formed. After firing, each of the dielectric layers 11 has a thickness of 2.5 μm. Each of the internal electrode layers 12 has a thickness of 2.0 μm.
[0070] (Example 2) In Example 2, the Zr / Ti ratio was 0.040 in the region corresponding to the ceramic protection portion 50. Other conditions were the same as those in Example 1.
[0071] (Example 3) In Example 3, the Zr / Ti ratio was 0.080 in the region corresponding to the ceramic protection portion 50. Other conditions were the same as those in Example 1.
[0072] (Example 4) In Example 4, the Zr / Ti ratio was 0.16 in the region corresponding to the ceramic protection portion 50. Other conditions were the same as those in Example 1.
[0073] (Comparative Example 1) In Comparative Example 1, the Zr / Ti ratio in the region corresponding to the ceramic protection portion 50 was 0.0020. Other conditions were the same as those in Example 1.
[0074] (Comparative Example 2) In Comparative Example 2, the Zr / Ti ratio was 0.32 in the region corresponding to the ceramic protection portion 50. Other conditions were the same as those in Example 1.
[0075] Figure 10A The Vickers hardness HV of the surface of the ceramic protection portion 50 in each of the cases where the firing temperatures were 1170° C., 1190° C., 1210° C., 1230° C., 1250° C., and 1270° C. in Examples 1 to 4 and Comparative Examples 1 and 2, respectively, is shown. Figure 10B The Vickers hardness HV of the surface of the ceramic protection portion 50 of Examples 1 to 4 and Comparative Examples 1 and 2 at a firing temperature of 1190° C. is shown. The Vickers hardness HV is a value measured under the conditions of a Vickers hardness tester with a load of 100 gf and a load holding time of 15 seconds.
[0076] like Figure 10A and Figure 10B As shown, in Examples 1 to 4, the Vickers hardness HV is sufficiently high. Specifically, at a temperature greater than 1180°C (at which the internal electrode layer 12 is sufficiently dense), the Vickers hardness HV is 600 or higher and sufficiently high. This is believed to be because the Zr / Ti ratio in the region corresponding to the ceramic protection portion 50 is 0.010 or higher and 0.25 or lower, and the A / B ratio in the region corresponding to the ceramic protection portion 50 is 0.990 or lower, suppressing abnormal grain growth and sufficiently promoting sintering of the ceramic protection portion 50.
[0077] On the other hand, in Comparative Example 1, the Vickers hardness HV was low. This is believed to be because the Zr / Ti ratio was less than 0.010, which did not sufficiently promote the sintering of the ceramic protective portion 50. In Comparative Example 2, the Vickers hardness was high at temperatures of 1210°C and 1230°C. However, in Comparative Example 2, the Vickers hardness was not high enough at temperatures of 1250°C and 1270°C. This is believed to be because the Zr / Ti ratio was greater than 0.25, causing abnormal grain growth.
[0078] (Example 5) In Example 5, the A / B ratio was 0.922 in the region corresponding to the ceramic protection portion 50. Other conditions were the same as those in Example 3.
[0079] (Example 6) In Example 6, the A / B ratio was 0.942 in the region corresponding to the ceramic protection portion 50. Other conditions were the same as those in Example 3.
[0080] (Example 7) In Example 7, the A / B ratio was 0.982 in the region corresponding to the ceramic protection portion 50. Other conditions were the same as those in Example 3.
[0081] (Comparative Example 3) In Comparative Example 3, the A / B ratio was 1.002 in the region corresponding to the ceramic protection portion 50. Other conditions were the same as those in Example 3.
[0082] Figure 11 The Vickers hardness HV of the surface of the ceramic protection portion 50 of each of Examples 3, 5 to 7 and Comparative Example 3 at a firing temperature of 1190° C. is shown. The Vickers hardness HV is a value measured under a load of 100 gf and a load holding time of 15 seconds in a Vickers hardness tester. Figure 11 As shown, the Vickers hardness HV is greater than 600 and is sufficiently high in Examples 3 and 5 to 7. This is considered to be because the Zr / Ti ratio in the region corresponding to the ceramic protection portion 50 is 0.010 or more and 0.25 or less, and the A / B ratio in the region corresponding to the ceramic protection portion 50 is 0.990 or less, abnormal grain growth is suppressed, and sintering of the ceramic protection portion 50 is sufficiently promoted.
[0083] On the other hand, the Vickers hardness was low in Comparative Example 3. This is probably because the A / B ratio was large and the sintering of the ceramic protection portion 50 was not sufficiently promoted.
[0084] Although the embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions, and modifications may be made thereto without departing from the spirit and scope of the invention. The amount of each element in the dielectric layer 11 can be confirmed by performing ICP analysis or La-ICP-MS (laser ablation inductively coupled plasma mass spectrometry). It has been confirmed that the amount of each element in the product determined by the analysis is consistent with the amount of each element added as the raw material.
Claims
1. A ceramic electronic device comprising: A stacked structure in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked, the main component of the dielectric layers being ceramic, the stacked structure having a rectangular parallelepiped shape, the plurality of internal electrode layers alternately exposed at a first end face and a second end face of the stacked structure, the first end face being opposite to the second end face, The ceramic protection part includes a cover layer and a side edge. The covering layer is provided on at least one of the upper and lower surfaces of the stacking structure in the stacking direction. In the stacked structure, the side edge is a region covering edge portions of the plurality of internal electrode layers extending toward two side surfaces other than the first end surface and the second end surface. The main component ceramic of the ceramic protection portion is a ceramic material having a perovskite structure represented by the general formula ABO3. Wherein, the A site of the perovskite structure contains at least Ba, Wherein, the B site of the perovskite structure contains at least Ti and Zr, wherein the Zr / Ti ratio as the Zr / Ti molar ratio is 0.020, 0.040, 0.080 or 0.16, Here, an A / B ratio, which is a molar ratio of the A site to the B site, is 0.922 or more and 0.982 or less.
2. The ceramic electronic device according to claim 1, wherein The surface of the ceramic protection portion has a Vickers hardness HV of 600 or greater.
3. The ceramic electronic device according to claim 1 or 2, wherein: The average grain diameter of the surface of the ceramic protection portion is 2.0 μm or less.
4. The ceramic electronic device according to claim 1 or 2, wherein: The main component of the internal electrode layer is Ni or Cu.
5. The ceramic electronic device according to claim 1 or 2, wherein: The main component ceramic of the capacitor region is the same as the main component ceramic of the ceramic protection portion. The capacitor region is a region where a group of internal electrode layers exposed to a first edge surface of the stacked structure is opposite to another group of internal electrode layers exposed to a second edge surface of the stacked structure.
6. A method for manufacturing a ceramic electronic device, comprising the following steps: preparing a ceramic laminate structure including a laminate portion, a cover sheet, and a skirt portion; firing the ceramic laminate structure, In the stacked portion, a plurality of sheets including particles whose main component is ceramic and a plurality of metal conductive paste patterns are alternately stacked, and the plurality of metal conductive paste patterns are alternately exposed to a first end surface and a second end surface of the ceramic stacked structure, the first end surface being opposite to the second end surface. The cover sheet is provided on at least one of the upper and lower surfaces of the stacking portion in the stacking direction. wherein the side edge portion is arranged on the side of the stacking portion, wherein the main component ceramics of the cover sheet before firing and the side edge portion before firing are ceramic materials having a perovskite structure represented by the general formula ABO3, Wherein, the A site of the perovskite structure contains at least Ba, Wherein, the B site of the perovskite structure contains at least Ti and Zr, wherein the Zr / Ti ratio as the Zr / Ti molar ratio is 0.020, 0.040, 0.080 or 0.16, Among them, the A / B ratio, which is a molar ratio of the A site to the B site, is 0.922 or more and 0.982 or less.
7. The method according to claim 6, wherein: The maximum value of the temperature increase rate during the firing is 6000° C. / h or greater.
8. The method according to claim 6 or 7, wherein: The firing conditions are adjusted so that the average grain diameter of the surfaces of the cover sheet and the side edge portion is 2.0 μm or less.
9. The method according to claim 6 or 7, wherein: The firing conditions are adjusted so that the average grain diameter of the surfaces of the cover sheet and the skirt portion after the firing is 10 times or less the average grain diameter of the main component ceramic in the cover sheet and the skirt portion.
Citation Information
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