Semiconductor element and method for measuring temperature of semiconductor element

Abstract

An apparatus for monitoring the temperature of a semiconductor device includes a plurality of active area structures. One or more active devices include portions of the plurality of active area structures. A metal layer is formed on the plurality of active area structures and is separated from the one or more active devices by one or more dummy gate layers. The metal layer is used to measure the temperature of the plurality of active area structures caused by a change in resistance in the metal layer.

Description

Technical Field

[0001] This case is about a device for monitoring semiconductor components, especially a device for monitoring the temperature of semiconductor components. Background Art

[0002] A method for monitoring the temperature of semiconductor components includes using the junction of a diode or bipolar junction transistor (BJT) in a region of a substrate near the transistor structure to be measured. Another method for monitoring the temperature of semiconductor components includes using the gate of a transistor structure to sense the temperature. Summary of the Invention

[0003] According to an embodiment of this case, there is a semiconductor component, including a plurality of active region structures, one or more active components, and a metal layer. The one or more active components include parts of the active region structures. The metal layer covers the active region structures and is separated from the one or more active components by one or more virtual gate layers, where the metal layer is used to measure the temperature of the active region structures due to resistance changes in the metal layer.

[0004] According to an embodiment of this case, there is a semiconductor component, including a first virtual gate layer, a second virtual gate layer, a plurality of active region structures, a first metal layer, a first active component, and a second active component. The active region structures extend between the first virtual gate layer and the second virtual gate layer. The first metal layer is on the active region structures. The first active component includes a part of the active region structures between the first virtual gate layer and the first metal layer. The first active component includes a drain metal layer and a first active gate layer. The drain metal layer is on the active region structures and between the first virtual gate layer and the first metal layer. The first active gate layer covers the active region structures between the drain metal layer and the first metal layer. The second active component includes a part of the active region structures between the first metal layer and the second virtual gate layer. The second active component includes a source metal layer and a second active gate layer. The source metal layer is on the active region structures between the first metal layer and the second virtual gate layer. The second active gate layer covers the active region structures between the first metal layer and the source metal layer, where the first active component and the second active component are serially coupled, and the first active gate layer of the first active component is used to sense the temperature of the active region structures.

[0005] According to an embodiment of this case, there is a method for measuring the temperature of a semiconductor component, including: applying a first current from a first position of a first gate structure of a first component to a second position of the first gate structure of the first component, where the first component is serially connected to a second component; switching a second gate structure of the second component to control the flow of a second current between the second component and the first component; and measuring the voltage drop from the first position of the first gate structure of the first component to the second position of the first gate structure of the first component.

[0006] According to an embodiment of the present case, it is about a semiconductor device, including a first dummy gate layer, a second dummy gate layer, a plurality of active region structures, a first metal layer, a first active device, a second active device, and a second active gate layer. The active region structures extend between the first dummy gate layer and the second dummy gate layer. The first metal layer is on the active region structures. The first active device includes a first active gate layer and a part of the active region structures between the first dummy gate layer and the first metal layer. The second active device includes a part of the active region structures between the first metal layer and the second dummy gate layer. The second active gate layer covers the active region structures between the first metal layer and the second dummy gate layer, wherein the first active device and the second active device are serially coupled, and the first active gate layer of the first active device is used to sense the temperature of the active region structures.

[0007] According to an embodiment of the present case, it is about a semiconductor device, including a plurality of active region structures, one or more active devices, a first dummy gate layer, a second dummy gate layer, and a metal layer. The one or more active devices include parts of the active region structures. The metal layer covers the active region structures and is positioned between the first dummy gate layer and the second dummy gate layer to electrically isolate the metal layer from the one or more active devices, wherein the metal layer is used to measure the temperature of the active region structures due to the change in resistance in the metal layer.

[0008] According to an embodiment of the present case, it is about a semiconductor device, including a plurality of active region structures, a first active device, and a second active device, a first dummy gate layer, a second dummy gate layer, and a metal layer. The first active device and the second active device include parts of the active region structures, wherein the first active device and the second active device are arranged in a series configuration. The first dummy gate layer and the second dummy gate layer are positioned between the first active device and the second active device. The metal layer covers the active region structures and is positioned between the first dummy gate layer and the second dummy gate layer, wherein the metal layer is used to measure the temperature of the active region structures due to the change in resistance in the metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] When read in conjunction with the accompanying drawings, various aspects of an embodiment of the present case can be best understood from the following detailed description. It should be noted that, according to standard practices in the industry, the various features are not drawn to scale. In fact, for the clarity of discussion, the sizes of the various features can be arbitrarily increased or decreased.

[0010] Figure 1A is a schematic diagram of a semiconductor device using a sensing metal resistor to measure temperature according to an embodiment;

[0011] Figure 1B is according to an embodiment ofFigure 1A Schematic diagram of an equivalent circuit of a semiconductor device;

[0012] Figure 1C Graph showing the relationship between the temperature and resistance of a sensing metal resistor according to an embodiment;

[0013] Figure 1D and Figure 1E is a cross-sectional schematic diagram of a semiconductor device according to an embodiment; Figure 1A of a semiconductor device;

[0014] Figures 2A to 2B Schematic diagram of a semiconductor device for measuring temperature using a sensing gate according to an embodiment;

[0015] Figure 3 Schematic diagram of a semiconductor device for measuring transient temperature changes according to an embodiment;

[0016] Figure 4 Flowchart of a method for measuring temperature according to one or more embodiments.

[0017]

Symbol description

[0018] 100, 200, 300... semiconductor devices

[0019] 102, 103, 104, 105, 106, 202, 203, 204, 205, 206, 302, 304, 306, 308, 310... active region structures

[0020] 102SD~106SD... S / D electrode structures

[0021] 108, 110, 126... gate layers

[0022] 112... first source metal layer

[0023] 114... first active gate layer

[0024] 116... first drain metal layer

[0025] 118... third dummy gate layer

[0026] 120... sensing metal resistor

[0027] 122... fourth dummy gate layer

[0028] 124... second source metal layer

[0029] 128... second drain metal layer

[0030] 130... active region structure channel

[0031] 132, 134, 136, 138, 140, 142, 144, 146, 226, 228, 230, 232, 234… Through holes

[0032] 102E~106E… Extension parts

[0033] MA1, M1… First active elements

[0034] MA2, M2… Second active elements

[0035] 150… Circuit model

[0036] 152… Nodes

[0037] 156… Readout circuit

[0038] 158… Curve graph

[0039] Vc… Power voltage source

[0040] Vr… Voltage

[0041] Iref… Current source

[0042] I_ac… AC current

[0043] X, Y… Directions

[0044] A - A’… Section line

[0045] R… Resistor

[0046] 160… Dielectric layer

[0047] 170… Substrate

[0048] 208… First virtual gate layer

[0049] 210… Second virtual gate layer

[0050] 212, 322… Drain metal layer

[0051] 214… Sensing gate layer

[0052] 216… First metal layer

[0053] 218… Switching gate layer

[0054] 220, 318… Source metal layer

[0055] 242, 244, 246… Equivalent circuit

[0056] 248… AC switch

[0057] 249… AC signal

[0058] 314… Temperature monitor element

[0059] 320… Active gate layer

[0060] 324… Virtual gate layer

[0061] 400… Method

[0062] 402, 404, 406, 408, 410… Steps Detailed implementation

[0063] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components, values, steps, materials, arrangements, etc. are described below to simplify the content of an embodiment of this case. Of course, these are only examples and are not intended to be restrictive. Other components, values, operations, materials, arrangements, etc. can be envisioned. For example, in the following description, forming a first feature above or on top of a second feature can include embodiments where the first feature and the second feature are formed in direct contact, and can also include embodiments where additional features can be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, an embodiment of this case may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0064] Furthermore, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to simplify the description of the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device / element during use or operation. The device can be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive terms used herein can be interpreted accordingly.

[0065] One or more embodiments of this disclosure include methods for on-wafer temperature measurement / monitoring of three-dimensional (3D) active devices, such as 3D metal oxide semiconductor field effect transistors (MOSFETs), fin field-effect transistors (FinFETs), gate-all-around (GAA) FETs, etc. A method for on-wafer temperature measurement / monitoring includes a source metal resistor for detecting the temperature of a 3D active device. Another method utilizes a dual polysilicon gate arrangement or a cascode configuration to detect the temperature of a 3D active device.

[0066] Figure 1A FIG. 2 is a schematic diagram of a semiconductor element 100 that can be used to measure the temperature of an active element. In at least some embodiments, the semiconductor element 100 is used to measure the temperature of a 3D active element. According to various embodiments, Figure 1B FIG. 3 is a schematic diagram of an equivalent circuit of the semiconductor device 100, Figure 1C FIG. 4 is a graph showing the relationship between the temperature and resistance of the sensing metal resistor 120 of the semiconductor element 100, and Figure 1D and Figure 1E FIG. 5 is a schematic diagram of a cross-section of the semiconductor element 100 along the Figure 1A section line A-A' of FIG. 2.

[0067] The semiconductor element 100 includes active region structures 102, 103, 104, 105, and 106 arranged in substantially parallel rows extending in a first direction (Y-axis), and a plurality of gate layers 108, 110, 114, 118, 122, and 126 arranged in substantially parallel columns and extending in a second direction (X-axis) substantially perpendicular to the first direction.

[0068] The active region structures 102-106 are continuous segments among or on substrates (e.g., substrate 170) depicted in, for example, Figure 1D and Figure 1E and have n-type or p-type doping and include various semiconductor structures, including source-drain (S / D) structures, such as the S / D structures 102SD-106SD shown in Figure 1D and Figure 1E FIGS. 5 and 6. In some embodiments, the active region structures 102-106 are located in wells (not shown) (i.e., n-wells or p-wells) within the substrate.

[0069] In some embodiments, the active region structures 102-106 are electrically isolated from other elements in the substrate by one or more isolation structures (not shown) (e.g., one or more shallow trench isolation (STI) structures).

[0070] The S / D structure is a semiconductor structure having a doping type opposite to that of the other parts of the active region structures 102-106. In some embodiments, the S / D structure is configured to have a lower resistivity than the other parts of the active region structures 102-106. In some embodiments, the S / D structure includes one or more portions having a doping concentration greater than one or more doping concentrations otherwise present throughout the active region structures 102-106. In various embodiments, the S / D structure includes an epitaxial region of semiconductor material (e.g., silicon, silicon germanium (SiGe), and / or silicon carbide (SiC)).

[0071] Each gate layer includes a conductive material (e.g., metal or polysilicon), covers each of the active region structures 102-106, at least partially surrounds each of the active region structures 102-106 in some embodiments, and is electrically isolated from each of the active region structures 102-106 by one or more dielectric layers. Thus, the plurality of gate layers are used to form a gate structure component capable of controlling the conductive channels in the underlying active region structures 102-106 based on an applied voltage. The plurality of gate layers include dummy gate layers 108, 110, 118, and 122, and active gate layers 114 and 126.

[0072] The active region structures 102-106 extend at least between the first dummy gate layer 108 and the second dummy gate layer 110, and include source / drain (S / D) structures (not shown in Figure 1A ), which will be discussed further below with respect to Figure 1D and Figure 1E The first source metal layer 112 covers and contacts the S / D structures of the active region structures 102-106 and extends in a second direction. The first source metal layer 112 is between the first dummy gate layer 108 and the first active gate layer 114. The first drain metal layer 116 covers and contacts the S / D structures of the active region structures 102-106 and extends in a second direction that is substantially parallel to the first dummy gate layer 108. The first drain metal layer 116 is between the first active gate layer 114 and the third dummy gate layer 118. Thus, the first source metal layer 112, the first active gate layer 114, the first drain metal layer 116, the channel portion of each of the active region structures 102-106 located below the first active gate layer 114, and the adjacent S / D structures are used to form the first active element MA1.

[0073] The sense metal resistor 120 covers and contacts the S / D structures of the active region structures 102-106 between the third dummy gate layer 118 and the fourth dummy gate layer 122. The sense metal resistor 120 extends in a second direction (X) that is substantially parallel to the first dummy gate layer 108.

[0074] The second source metal layer 124 covers and contacts the S / D structures of the active region structures 102-106 between the fourth dummy gate layer 122 and the second active gate layer 126. The second source metal layer 124 extends in the second direction (X) and is substantially parallel to the first dummy gate layer 108. The second drain metal layer 128 covers and contacts the S / D structures of the active region structures 102-106 between the second active gate layer 126 and the second dummy gate layer 110. The second drain metal layer 128 extends in the second direction (X) and is substantially parallel to the first dummy gate layer 108. Thus, the second source metal layer 124, the second active gate layer 126, the second drain metal layer 128, the channel portions of each of the active region structures 102-106 located below the second active gate layer 126, and the adjacent S / D structures are used to form the second active element MA2.

[0075] Thus, the active region structures 102-106 are arranged to form the active region structure channel 130 including the first active element MA1 and the second active element MA2. Since the active region structures 102-106 have a relatively high thermal conductivity with respect to the surrounding dielectric layer (not shown), the temperatures of the active gate layers 114 and 126, the drain metal layers 116 and 128, the source metal layers 112 and 124, the active region structures 102-106 below the sense metal resistor 120, and the sense metal resistor itself are substantially the same.

[0076] The vias 132, 134, and 136 electrically connect the first source metal layer 112, the first active gate layer 114, and the first drain metal layer 116 to their respective overlying metal segments (not shown), e.g., the first metal layer segment, such that one active element MA1 is configured to be included in an integrated circuit (IC). The vias 138, 140, and 142 electrically connect the second source metal layer 124, the second active gate layer 126, and the second drain metal layer 128 to their respective overlying metal segments (not shown), e.g., the first metal layer segment, such that the active element MA2 is configured to be included in the IC.

[0077] The vias 144 and 146 electrically connect the opposite ends of the sense metal resistor 120 to the overlying metal segment (not shown), e.g., the first metal layer segment, such that the sense metal resistor 120 is configured to be included in a test circuit arrangement such that, as described below, the resistance value of the sense metal resistor 120 can be measured.

[0078] In operation, the third virtual gate layer 118 and the fourth virtual gate layer 122 electrically isolate the sense metal resistor 120 from the first active element MA1 and the second active element MA2 during the resistance measurement. The electrical isolation between the sense metal resistor 120, the first active element MA1, and the second active element MA2 enables accurate resistance measurement by substantially preventing the current from the first active element MA1 and the second active element MA2 from affecting the measurement result at the sense metal resistor 120 via the vias 144 and 146.

[0079] In the measurement operation, the vias 144 and 146 are electrically coupled to one or more measurement instruments (not shown), a voltage drop is generated across the sense metal resistor 120 based on the current applied via the sense metal resistor 120, and the resistance value of the sense metal resistor 120 is calculated. In some embodiments, the resistance of the sense metal resistor 120 has a linear relationship with temperature, and the temperature of the active region structures 102-106 distributed on the active region structure channel 130 is determined by finding the resistance of the sense metal resistor 120.

[0080] In some embodiments, the active region structures 102-106 are configured for PMOS technology, NMOS technology, CMOS technology, FinFET technology, etc.

[0081] In some embodiments, the sense metal resistor 120 includes a resistive metal material such as nichrome or carbon. In some embodiments, the sense metal resistor 120 is a metal oxide film. In some embodiments, the sense metal resistor 120 contains copper (Cu).

[0082] In some embodiments, the vias 132, 134, 136, 138, 140, 142, 144, and 146 correspond to holes etched in the interlayer dielectric and filled with one or more metals. In various embodiments, the vias 132, 134, 136, 138, 140, 142, 144, and 146 are via structures of similar or different forms relative to each other.

[0083] Figure 1B is a schematic diagram of a circuit model 150 of a semiconductor element 100 according to an embodiment. The circuit model 150 includes a current source Iref in series with a resistor R. The current source Iref is connected between the power voltage source Vc and the node 152. The resistor R is connected between the node 152 and the ground. The voltage Vr is the voltage drop across the resistor R. The current source Iref corresponds to the current applied to the sense metal resistor 120. The voltage Vr corresponds to the voltage across the sense metal resistor 120. The resistor R is the resistance of the sense metal resistor 120 being measured. The readout circuit 156 is connected to the node 152 and measures the voltage Vr at the node 152. Equation (1):

[0084] The equation (1): R = Vr / Iref

[0085] It is used to calculate the resistance value of the sensing metal resistor 120.

[0086] Figure 1C A graph 158 including the linear relationship between the resistance R of the sensing metal resistor 120 and the temperature. The graph 158 includes a temperature axis (X-axis) and a resistance axis (Y-axis). After calculating the resistance R using the above equation (1), the temperature of the sensing metal resistor 120 is determined based on the relationship between the resistance R of the sensing metal resistor and the temperature (e.g., the linear relationship shown in the graph 158). Different materials have different temperatures corresponding to specific resistance values. Standard tools (such as MATLAB, etc.) can be used to calculate the temperature at different resistances.

[0087] The readout circuit 156 measures the voltage Vr at the node 152. In some embodiments, the readout circuit 156 displays the measured voltage. In some embodiments, the readout circuit 156 only displays the resistance value R. In some embodiments, the readout circuit 156 only displays the temperature value based on the calculated resistance value. In some embodiments, the readout circuit 156 includes an analog-to-digital converter (ADC), which allows the readout circuit 156 to convert the analog reading of the voltage Vr into a digital value for operation with other digital systems. In some embodiments, the readout circuit 156 includes an amplifier arrangement, such as an operational amplifier, to amplify the voltage Vr for detection and measurement.

[0088] In Figure 1D In a non-limiting example depicted in the cross-section of

[0089] In Figure 1EIn the non-limiting example depicted in the cross-section, semiconductor element 100 corresponds to GAA technology, in which S / D structures 102SD to 106SD are the only parts of active region structures 102 to 106 in the transverse plane. S / D structures 102SD to 106SD are in contact with and electrically connected to sense metal resistor 120, and are separated from extensions 102E to 106E of substrate 170 by dielectric layer 160. Extensions 102E to 106E correspond to the manufacturing method for forming active region structures 102 to 106 and are not active components of semiconductor element 100.

[0090] In Figure 1D and Figure 1E each non-limiting example of, the channel regions (not shown) of active region structures 102 to 106 are adjacent to S / D structures 102SD to 106SD that are in contact with sense metal resistor 120. In various embodiments, semiconductor element 100 includes configurations other than those depicted in Figure 1D and Figure 1E such that sense metal resistor 120 is in contact with an S / D structure adjacent to the channel region of active region structures 102 to 106.

[0091] Because sense metal resistor 120 is in contact with S / D structures 102SD to 106SD adjacent to the channel regions of active region structures 102 to 106, the temperature of sense metal resistor 120 is substantially the same as the temperature of the channel regions. Accordingly, the temperature value calculated based on the resistance measurement value of sense metal resistor 120 is more accurate than the temperature value obtained by a method that is not based on the resistance measurement value of a sense metal resistor (e.g., a method based on substrate diode characteristics).

[0092] Figure 2ASchematic diagram of a semiconductor element 200 having a dual gate layer arrangement as part of a cascode transistor configuration, which can be used to measure the temperature of a 3D active element. The semiconductor element 200 includes active region structures 202, 203, 204, 205, and 206, which are arranged in rows substantially parallel to each other and extend along a first direction (Y). The active region structures 202, 203, 204, 205, and 206 extend between a first gate layer 208 and a second virtual gate layer 210. The first virtual gate layer 208 and the second virtual gate layer 210 are arranged in columns substantially parallel to each other and extend in a second direction (X) substantially perpendicular to the first direction (Y). A drain metal layer 212 is formed on the active region structures 202, 203, 204, 205, and 206 and extends in the second direction (X). The drain metal layer 212 is located between the first virtual gate layer 208 and a sense gate layer 214. The sense gate layer 214 extends in the second direction and is substantially parallel to the first virtual gate layer 208. A first metal layer 216 is formed on the active region structures 202, 203, 204, 205, and 206 and extends in the second direction and is substantially parallel to the first virtual gate layer 208. The first metal layer 216 is located between the sense gate layer 214 and a switching gate layer 218. The switching gate layer 218 extends in the second direction and is substantially parallel to the first virtual gate layer 208. Thus, the first metal layer 216, the sense gate layer 214, the drain metal layer 212, the channel portions of each of the active region structures 202-206 located below the sense gate layer 214, and the adjacent S / D structures (not shown) in the active region structures 202-206 are used to form a first active element M1.

[0093] A source metal layer 220 is formed on the active region structures 202, 203, 204, 205, and 206 and extends in the second direction and is substantially parallel to the first virtual gate layer 208. The source metal layer 220 is located between the switching gate layer 218 and the second virtual gate layer 210. Thus, the source metal layer 220, the switching gate layer 218, the first metal layer 216, the channel portions of each of the active region structures 202-206 located below the switching gate layer 218, and the adjacent S / D structures (not shown) in the active region structures 202-206 are used to form a second active element M2. The first metal layer 216 is used as the source of the first active element M1 and the drain of the second active element M2, whereby the active elements M1 and M2 are arranged in a cascode configuration. The first metal layer 216 couples the source of the first active element M1 to the drain of the second active element M2. Moreover, the first metal layer 216 allows current to flow between the source of the first active element M1 and the drain of the second active element M2.

[0094] The through-holes 226, 228, 230, 232 and 234 electrically connect the first active element M1 and the second active element M2 to an overlying metal section (not shown), such as a first metal layer section, such that the active elements M1 and M2 are configured to be included in a test circuit arrangement.

[0095] The through-holes 228 and 230 located at opposite ends of the sense gate layer 214 of the first active element M1 enable the resistance of the switching gate layer 218 to be measured during a measurement operation. Since the sense gate layer 214 is close to the channel regions of the active region structures 202, 203, 204, 205 and 206, the measured temperature value of the sense gate layer 214 indicates the channel region temperature.

[0096] During a measurement operation, the second active element M2 is configured to receive an AC signal and thus operate as a switch under AC operation. The second active element M2 is coupled to an AC signal source that is configured to cause the AC operation to simulate the operation of one or more active elements of an IC circuit. In some embodiments, the second active element M2 turns on when the AC signal of the AC signal source is positive and turns off when the AC signal is negative. In the above cascode configuration, the first active element M1 operates in a saturation region with a high output resistance. The second active element M2 operates in a linear region with a low output resistance. As Figure 2A shown, the first active element M1 and the second active element M2 are connected in series via the first metal layer 216, where an AC current I_ac flows through the source of the first active element M1 and the drain of the second active element M2 when the second active element is turned on. Since, based on the cascode configuration, the channel resistance of the first active element M1 is substantially greater than the channel resistance of the second active element M2, most of the power is dissipated in the first active element M1.

[0097] The channel resistance of the sense gate layer 214 is linearly proportional to the temperature of the channel regions of the active region structures 202, 203, 204, 205 and 206 below the sense gate layer 214. Once the resistance of the sense gate layer 214 is calculated, the linear relationship is used to determine the temperature of the channel regions of the active region structures 202, 203, 204, 205 and 206.

[0098] In operation, in some embodiments, the resistance of the sensing gate layer 214 of the first active element M1 is measured by applying an AC signal to the switching gate layer 218 while biasing the sensing gate layer 214 with a DC voltage higher than the threshold voltage of the first active element M1, thereby switching the first active element M1 on. When a current I_ac is thus induced via a cascode configuration, a test current is applied and the voltage drop across the sensing gate layer 214 is measured via vias 228 and 230. The resistance value of the sensing gate layer 214 is calculated using the measured voltage drop across the sensing gate layer 214 and the test current. Using the resistance value of the sensing gate layer 214, the temperature of the channel regions of the active region structures 202, 203, 204, 205, and 206 is determined using the linear relationship between the resistance of the gate layer and temperature discussed herein. Since the first active element M1 is thus operating in the saturation region in response to the AC signal, the determined temperature corresponds to the temperature of one or more active elements of the IC circuit simulated by the AC signal.

[0099] The via 232 of the switching gate layer 218 is used to allow triggering of the second active element M2 under AC operation or in response to a step function. In operation, in some embodiments, an AC or step signal is applied to the gate of the second active element M2 for triggering, such that the second active element M2 is turned on or off depending on the value of the AC or step signal for testing. Using this method, transient temperature values can be measured under AC operation or in response to a step signal. In some embodiments, the gate of the second active element M2 is kept on for testing under DC operating conditions.

[0100] In some embodiments, the semiconductor element 200 allows the formation of other active elements or repeating structures on the active region structures 202 - 206 based on the first virtual gate layer 208 and the second virtual gate layer 210. If new active elements are formed on the active region structures 202 - 206, the first virtual gate layer 208 and the second virtual gate layer 210 provide sufficient electrical isolation.

[0101] In various embodiments, the first active element M1 and the second active element M2 are configured for PMOS technology, NMOS technology, CMOS technology, FinFET technology, etc.

[0102] In some embodiments, the vias 226, 228, 230, 232, 234, and 236 correspond to holes etched in the interlayer dielectric, which are filled with one or more metals. In various embodiments, the vias 226, 228, 230, 232, 234, and 236 are via structures of similar or different forms to each other.

[0103] Figure 2BSchematic diagrams of equivalent circuits 242, 244, and 246 of a semiconductor element 200 according to one embodiment. Figure 2B Includes a first equivalent circuit 242 of semiconductor element 200. The equivalent circuit 242 includes a first active element M1 coupled to an AC switch 248, and the AC switch 248 indicates a second active element M2 under AC operation. As discussed herein, under AC operation, an AC signal 249 is used to switch the switching gate layer 218 of the second active element M2 on and off to indicate the switch 248.

[0104] When the AC switch 248 is on, the second equivalent circuit 244 models when the first active element M1 operates in the saturation region and the second active element M2 operates in the linear region. The second equivalent circuit 244 includes a resistor Ron M1 that corresponds to the output channel resistance of the first active element M1 in the saturation region. The resistor Ron M1 is coupled between the drain of the first active element M1 and a second resistor Ron M2 that corresponds to the output channel resistance of the second active element M2 in the linear region. Based on a cascode arrangement, the resistor Ron M1 is greater than the resistor Ron M2. In some embodiments, the size of the first active element M1 matches the size of one or more active elements simulated by the semiconductor element 200, whereby the resistor Ron M1 matches the output channel resistance of the one or more active elements.

[0105] The third equivalent circuit 246 models the semiconductor element 200 as a resistor Ron M1 based on the cascode arrangement of the semiconductor element 200 because Ron M1 >> Ron M2.

[0106] In some embodiments, the readout circuit measures the voltage on the sense gate layer 214 and displays the result. In some embodiments, the readout circuit is the readout circuit as described in connection with Figure 1B In some embodiments, the readout circuit is programmed to display only the value of the temperature based on the calculated value of the resistance of the sense gate layer 214. In some embodiments, the readout circuit includes an analog-to-digital converter (ADC) to measure the voltage on the sense gate layer 214. In some embodiments, the readout circuit includes an opAmp arrangement to measure the voltage across the sense gate layer 214.

[0107] Figure 3FIG. 0 is a schematic diagram of a semiconductor element 300 that can be used to measure temperature under AC or transient operation. The semiconductor element 300 includes active region structures 302, 304, 306, 308, and 310, which are arranged in rows substantially parallel to each other and extend along a first direction (Y). The semiconductor element 300 includes temperature monitor elements 314 and active element M0, each disposed on the active region structures 302, 304, 306, 308, and 310. The temperature monitor element 314 is equivalent to the semiconductor element 200 described above inverted with respect to the first direction (Y). Figure 2A The active element M0 includes a source metal layer 318 between the second virtual gate layer 210 of the temperature monitor element 314 and the active gate layer 320. A drain metal layer 322 is located between the active gate layer 320 and the third virtual gate layer 324.

[0108] As described above with respect to the semiconductor element 200, the temperature monitor element 314 is used to measure the temperature of the channel regions of the active region structures 302, 304, 306, 308, and 310 located below the sense gate layer 214 under transient and / or AC operating conditions. In operation, based on the common-source common-gate arrangement of the temperature monitor element 314 and the active elements M0 and M1 with a matching configuration, by switching the active element M2 to on and applying the same AC and / or transient signal to the active gate layer 320 of the active element M0 and the switching gate layer 218 of the second active element M1, the same current I_ac is induced in each of the active elements M0 and M2. Therefore, the same temperature is generated in each channel region of the active region structures 302, 304, 306, 308, and 310 corresponding to the active elements M0 and M2, and the temperature judged by measuring the sense gate layer 214 corresponds to the temperature of the active element M0.

[0109] In some embodiments, during operation, all the active elements in the semiconductor element 300 are not in operation, and the temperature monitor element 314 is used to measure the temperature of the substrate.

[0110] The virtual gate layers 208, 210, and 324 provide electrical isolation between the temperature monitor element 314 and other active elements including the active element M0. In some embodiments, in addition to the active element M0, there are also many active elements (not shown) that share the active region structures 302 - 310 with the temperature monitor element 314, and in addition to the virtual gate layers 208, 210, and 324, there is also one or more virtual gate layers (not shown) that electrically isolate the additional active elements from the temperature monitor element 314.

[0111] In various embodiments, the active device M0 is configured for PMOS technology, NMOS technology, CMOS technology, GAA FET technology, FinFET technology, etc.

[0112] Figure 4 FIG. 400 is a flow chart of a method 400 for measuring the temperature of a measurement channel region according to one or more embodiments. In various embodiments, the method 400 can be used to measure the temperature of the channel region of an active region structure shared by one or more active devices or to simulate the operation of one or more active devices.

[0113] In step 402, in some embodiments, a metal layer, such as sense metal resistor 120 Figure 1A (), active region structure 202, 203, 204, 205, and 206 Figure 2A () or active region structure 302, 304, 306, 308, and 310), is formed on an active region structure, such as active region structures 102, 103, 104, 105, and 106 Figure 1A () or sense gate layer 214 Figure 2A (). In some embodiments, the metal layer is a covering metal layer. In some embodiments, the metal layer is polysilicon or a metal gate layer. In some embodiments, the metal layer is a drain metal layer. In some embodiments, the metal layer is a source metal layer.

[0114] In step 404, a current is applied to the metal layer, such as sense metal resistor 120 Figure 1A () or sense gate layer 214 Figure 2A (). In some embodiments, applying the current to the metal layer includes providing the current to the metal layer via a pair of vias, such as vias 144 and 146 Figure 1A () or vias 228 and 230 Figure 2A ().

[0115] Applying the current includes applying a DC current, as discussed above with respect to Figures 1A to 3 . In some embodiments, applying the current includes applying a DC current to the first gate layer of a first active device in a cascode arrangement and applying an AC and / or transient signal to the second gate layer of a second active device in the cascode arrangement, as discussed above with respect to Figures 2A to 3 .

[0116] In step 406, the metal layer, such as sense metal resistor 120 Figure 1A () or sense gate layer 214 Figure 1A (), is measured, such as by a readout circuit Figure 2A)) the voltage across. In some embodiments, the readout circuit is used to measure the voltage across the metal layer. In some embodiments, the readout circuit is a resistive readout circuit. In some embodiments, the readout circuit is a 4-point Kelvin structure with a double-bridge configuration to measure resistance levels below 1 ohm. In some embodiments, the readout circuit includes an analog-to-digital converter. In some embodiments, the readout circuit includes an operational amplifier.

[0117] In some embodiments, measuring the voltage across the metal layer includes measuring the voltage via a pair of vias (such as via 144 and 146( Figure 1A )) or via 228 and 230( Figure 2A ).

[0118] In step 408, the measured voltage across the metal layer and the current applied to the metal layer are used to determine the resistance of the metal layer (such as the sense metal resistor 120( Figure 1A ) or the sense gate layer 214( Figure 2A )) as discussed above with respect to Figures 1A to 3 .

[0119] In step 410, the linear relationship between the temperature and resistance of the above metal layer is used to calculate the temperature of the channel region of the active region structure located under the metal layer (such as the sense metal resistor 120( Figure 1A ) or the sense polysilicon gate layer 214( Figure 2A )) as discussed above with respect to Figures 1A to 3 . In some embodiments, calculating the temperature of the channel region includes calculating the channel region of the active region structure shared by multiple active components. In some embodiments, calculating the temperature includes calculating the transient temperature change of the active component under AC or DC operation. In some embodiments, calculating the temperature includes calculating the temperature of the substrate when all the active components arranged on the active region structure are turned off.

[0120] One aspect of this specification relates to a device for monitoring the temperature of semiconductor components including multiple active region structures. One or more active components include parts of the multiple active region structures. A metal layer covers the multiple active region structures and is separated from the one or more active components by one or more virtual gate layers, where the metal layer is used to measure the temperature of the multiple active region structures due to resistance changes in the metal layer.

[0121] In some embodiments, the device for monitoring the temperature of semiconductor components, wherein the multiple active region structures include fins of a fin field-effect transistor (FinFET).

[0122] In some embodiments, a device for monitoring the temperature of a semiconductor element, wherein the plurality of active region structures includes a channel of a gate-all-around (GAA) field-effect transistor (FET).

[0123] In some embodiments, a device for monitoring the temperature of a semiconductor element, wherein the metal layer includes nickel-chromium alloy, carbon, metal oxide, or copper (Cu).

[0124] In some embodiments, a device for monitoring the temperature of a semiconductor element also includes a pair of vias at opposite ends of the metal layer, whereby the metal layer is used to receive a current.

[0125] In some embodiments, a device for monitoring the temperature of a semiconductor element, wherein the metal layer is thereby used to have a voltage drop between the pair of vias in response to the current.

[0126] In some embodiments, a device for monitoring the temperature of a semiconductor element, wherein a resistance of the metal layer is linearly proportional to the temperature of the plurality of active region structures.

[0127] In some embodiments, a device for monitoring the temperature of a semiconductor element, wherein at least one of the one or more active elements is a three-dimensional (3D) active element.

[0128] In some embodiments, a device for monitoring the temperature of a semiconductor element, wherein the metal layer includes a drain metal layer formed on the plurality of active region structures.

[0129] In some embodiments, a device for monitoring the temperature of a semiconductor element, wherein the one or more active elements are used to be turned off when measuring a temperature of a substrate including the plurality of active region structures.

[0130] Another aspect of the present specification relates to a semiconductor element including a first virtual gate layer and a second virtual gate layer. A plurality of active region structures extend between the first virtual gate layer and the second virtual gate layer. A first metal layer covers the plurality of active region structures. A first active element includes portions of the plurality of active region structures between the first virtual gate layer and the first metal layer. The first active element includes a drain metal layer on the plurality of active region structures and between the first virtual gate layer and the first metal layer, and a first active gate layer covering the plurality of active region structures between the drain metal layer and the first metal layer. A second active element includes portions of the plurality of active region structures between the first metal layer and the second virtual gate layer. The second active element includes a source metal layer on the plurality of active region structures between the first metal layer and the second virtual gate layer; and a second active gate layer covering the plurality of active region structures between the first metal layer and the source metal layer. The first active element and the second active element are coupled in series. The first active gate layer of the first active element is used to sense the temperature of the plurality of active region structures.

[0131] In some embodiments, the semiconductor device, wherein the first active device includes a fin field-effect transistor (FinFET).

[0132] In some embodiments, the semiconductor device, wherein the first active device includes a gate-all-around (GAA) field-effect transistor (FET).

[0133] In some embodiments, the semiconductor device, wherein based on the series-coupled arrangement, the operating channel resistance of the first active device is greater than the operating channel resistance of the second active device.

[0134] In some embodiments, the semiconductor device, wherein the first active device is thereby configured to operate in a saturation region.

[0135] In some embodiments, the semiconductor device, wherein the second active device is thereby configured to operate in a linear region.

[0136] In some embodiments, the semiconductor device, wherein a resistance of the first active gate layer is linearly proportional to the temperature of the plurality of active region structures.

[0137] Another aspect of the specification includes a method of measuring the temperature of a semiconductor device. The method includes: applying a current to a gate layer of a first device serially connected to a second device; switching a gate structure of the second device to control current flow between the second device and the first device; and measuring a voltage drop across the gate structure of the first device.

[0138] In some embodiments, wherein switching the gate structure of the second device includes applying an AC signal to the gate structure of the second device.

[0139] In some embodiments, wherein switching the gate structure of the second device includes applying a step function signal to the gate structure of the second device.

[0140] The features of several embodiments have been outlined above so that those skilled in the art may better understand the aspects of an embodiment of the present disclosure. Those skilled in the art should understand that they can readily use an embodiment of the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of an embodiment of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of an embodiment of the present disclosure.

Claims

1. A semiconductor element, characterized in that: include: a first dummy gate layer; a second dummy gate layer; a plurality of active area structures extending between the first dummy gate layer and the second dummy gate layer; a first metal layer, the first metal layer being on the active area structures; A first active device, including a plurality of portions of the active region structures between the first dummy gate layer and the first metal layer, the first active device comprising: a drain metal layer on the active region structures and between the first dummy gate layer and the first metal layer; and a first active gate layer, the first active gate layer covering the active region structures between the drain metal layer and the first metal layer; and a second active device, including a plurality of portions of the active region structures between the first metal layer and the second dummy gate layer, the second active device comprising: a source metal layer, the source metal layer being on the active region structures between the first metal layer and the second dummy gate layer; and A second active gate layer covers the active area structures between the first metal layer and the source metal layer, wherein the first active element and the second active element are coupled in series, and the first active gate layer of the first active element is used to sense a temperature of the active area structures.

2. The semiconductor device according to claim 1, wherein: The first active element includes a fin field effect transistor.

3. The semiconductor device according to claim 1, wherein: The first active element includes a surrounding gate field effect transistor.

4. The semiconductor device according to claim 1, wherein: A first operating channel resistance of the first active element is greater than a second operating channel resistance of the second active element.

5. The semiconductor device according to claim 4, wherein: The first active element is thereby configured to operate in a saturation region.

6. The semiconductor device according to claim 4, wherein: The second active element is thereby configured to operate in a linear region.

7. The semiconductor device according to claim 1, wherein: A resistance of the first active gate layer is linearly proportional to the temperature of the active region structures.

8. A method for measuring the temperature of a semiconductor device, characterized in that: include: Applying a first current from a first position of a first gate structure of a first element to a second position of the first gate structure of the first element, the first element being connected in series with a second element, wherein the first gate structure covers a first plurality of active region structures among a plurality of active region structures, and the first plurality of active region structures are disposed between a drain metal layer and a metal layer of the first element; switching a second gate structure of the second element to control the flow of a second current between the second element and the first element, wherein the second gate structure covers a second plurality of active region structures among the active region structures, and the second plurality of active region structures are disposed between the metal layer and a source metal layer of the second element; as well as A voltage drop from the first location of the first gate structure of the first device to the second location of the first gate structure of the first device is measured to sense a temperature of the active region structures.

9. The method according to claim 8, characterized in that The switching of the second gate structure of the second element includes applying an AC signal to the second gate structure of the second element.

10. The method according to claim 8, characterized in that The switching of the second gate structure of the second element includes applying a step function signal to the second gate structure of the second element.

11. A semiconductor element, characterized in that: include: a first dummy gate layer; a second dummy gate layer; a plurality of active area structures extending between the first dummy gate layer and the second dummy gate layer; a first metal layer, the first metal layer being on the active area structures; a first active device, including a first active gate layer and a plurality of portions of the active region structures between the first dummy gate layer and the first metal layer; a second active device including portions of the active region structures between the first metal layer and the second dummy gate layer; as well as A second active gate layer covers the active area structures between the first metal layer and the second virtual gate layer, wherein the first active element and the second active element are coupled in series, and the first active gate layer of the first active element is used to sense a temperature of the active area structures.

12. The semiconductor device according to claim 11, wherein The first active element includes a drain metal layer, which is on the active region structures and between the first virtual gate layer and the first metal layer.

13. The semiconductor device according to claim 12, wherein: The first active element includes a first active gate layer, and the first active gate layer covers the active region structures between the drain metal layer and the first metal layer.

14. The semiconductor device according to claim 11, wherein The second active element further includes a source metal layer, and the source metal layer is on the active region structures between the first metal layer and the second virtual gate layer.

15. The semiconductor device according to claim 14, wherein: The second active element further includes a second active gate layer, and the second active gate layer covers the active region structures between the first metal layer and the source metal layer.

16. The semiconductor device according to claim 11, wherein The first active element includes a fin field effect transistor.

17. The semiconductor device according to claim 11, wherein: The first active element includes a surrounding gate field effect transistor.

18. The semiconductor device according to claim 11, wherein in, Based on the series coupling of the first active element and the second active element, a first operating channel resistance of the first active element is greater than a second operating channel resistance of the second active element.

19. The semiconductor device according to claim 18, wherein: The first active element is thereby configured to operate in a saturation region.

20. The semiconductor device according to claim 18, wherein The second active element is thereby configured to operate in a linear region.

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