Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package includes a first tube die and a second tube die. The first tube die includes a first spiral section of an inductor and a first bonding metal. The first bonding metal is connected to the first spiral section. The second tube die is bonded to the first tube die. The second tube die includes a second spiral section of the inductor and a second bonding metal. The second bonding metal is connected to the second spiral section. The inductor extends from the first tube die to the second tube die.

Description

Technical Field

[0001] The disclosed embodiments relate to a semiconductor package and a method for manufacturing the same. Background Art

[0002] Semiconductor devices and integrated circuits used in various electronic devices (such as mobile phones and other mobile electronic devices) are usually manufactured on a single semiconductor wafer. The die of the wafer can be processed and packaged with other semiconductor devices or dies at the wafer level, and various technologies and applications have been developed for wafer-level packaging. The integration of multiple semiconductor devices has become a challenge in the field. Summary of the invention

[0003] According to some embodiments of the present disclosure, a semiconductor package includes a first tube die and a second tube die. The first tube die includes a first spiral segment of an inductor and a first bonding metal. The first bonding metal is connected to the first spiral segment. The second tube die is bonded to the first tube die. The second tube die includes a second spiral segment of the inductor and a second bonding metal. The second bonding metal is connected to the second spiral segment. The inductor extends from the first tube die to the second tube die. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The various aspects of the present disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0005] Figures 1A to 1F is a schematic cross-sectional view illustrating a manufacturing process of a semiconductor die according to some embodiments of the present disclosure.

[0006] Figures 2A to 2F is a schematic cross-sectional view illustrating a manufacturing process of another semiconductor die according to some embodiments of the present disclosure.

[0007] FIG. 3A to FIG. 3J is a schematic cross-sectional view illustrating a manufacturing process of a semiconductor package according to some embodiments of the present disclosure.

[0008] Figure 3K is a schematic cross-sectional view illustrating an electronic device according to some embodiments of the present disclosure.

[0009] Figure 4A yes Figure 3K Schematic perspective view of an inductor of a semiconductor package shown in FIG.

[0010] Figure 4B yes Figure 4A Schematic exploded view of the inductor shown in .

[0011] Figure 5 are schematic cross-sectional views of semiconductor packages according to some alternative embodiments of the present disclosure.

[0012] Fig. 6A are schematic cross-sectional views of semiconductor packages according to some alternative embodiments of the present disclosure.

[0013] Figure 6B yes Fig. 6A Schematic exploded view of an inductor of a semiconductor package shown in .

[0014] Fig. 7A are schematic cross-sectional views of semiconductor packages according to some alternative embodiments of the present disclosure.

[0015] Figure 7B yes Fig. 7A Schematic exploded view of an inductor of a semiconductor package shown in .

[0016] Fig. 8A are schematic cross-sectional views of semiconductor packages according to some alternative embodiments of the present disclosure.

[0017] Figure 8B yes Fig. 8A Schematic exploded view of an inductor of a semiconductor package shown in .

[0018] [Explanation of Symbols]

[0019] 10, 20, 30, 40, 50: Semiconductor packaging

[0020] 15: Electronic devices

[0021] 100, 102, 104, 106, 108, 200, 202, 204, 206, 208: semiconductor die

[0022] 110, 110a, 210: semiconductor substrate

[0023] 110r, 112b, 302t, 304t: surface

[0024] 112: Semiconductor drilling

[0025] 120, 220: Dielectric interlayer

[0026] 130: Internal conductive pattern / conductive pattern

[0027] 132, 136, 146, 162, 232, 236, 246, 262, 322, 1621, 1622, 2621, 2622: Through hole part

[0028] 134: Groove part / interconnection pattern

[0029] 138, 144, 148, 149, 164, 234, 238, 244, 248, 249, 264, 324: Groove part

[0030] 140, 160, 240, 260: Inductor pattern

[0031] 150, 250: protective layer

[0032] 150a, 250a: Protective material layer

[0033] 170, 270: Conductive pads

[0034] 180, 280: Combined with dielectric layer

[0035] 180a, 280a: Bonding dielectric material layer

[0036] 190, 290: Combined with metallized pattern

[0037] 192, 292: Inductor bonding pad / bonding pad

[0038] 192A, 192B, 292A, 292B: Bonding pads

[0039] 194, 194A, 194B, 294, 294A, 294B: Combined through-hole

[0040] 194t, 194At, 194Bt, 1621t, 1622t: top surface

[0041] 196, 296: Internal connection pads

[0042] 197, 297: Dummy bonding pads

[0043] 198, 298: Conductive vias

[0044] 230: Internal conductive pattern

[0045] 302, 302a: first dielectric layer

[0046] 304: Second dielectric layer

[0047] 306: The third dielectric layer

[0048] 308: First passivation layer

[0049] 310: First redistribution pattern

[0050] 312: Seed layer

[0051] 312a: Seed material layer

[0052] 315: Conductive plug

[0053] 315a: Conductive material

[0054] 320: Second wiring pattern

[0055] 330: Second passivation layer

[0056] 400: Under Bump Metal

[0057] 500: Conductive terminal

[0058] 600: Circuit substrate

[0059] 1010, 1020, 1030, 1040, 3010, 3020, 3030, 3040, 4010, 4020, 4030, 4040, 5010, 5020, 5030, 5040: Winding part

[0060] 1050, 4050: combined part

[0061] 3050A, 5050A: First joint part

[0062] 3050B, 5050B: Second bonding part

[0063] 6010, 6020, 6030, 6040, 6050, 6060, 6110, 6120, 6130, 6140, 6150: Coil

[0064] AS1, AS2: Active Surface

[0065] BS1, BS2: Combination structure

[0066] BI: Combined interface

[0067] C1, C2, SC: Cutting line

[0068] CR1: First current

[0069] CR2: Second current

[0070] C_In, C_Out: Arrows

[0071] CT146, CT162, CT194, CT194A, CT194B, CT246, CT262, CT294, CT1621, CT1622, CT2621, CT2622: Contact area

[0072] D1, D2: Device

[0073] DU1, DU2: Die Unit

[0074] IN1, IN2: internal connection structure

[0075] IND1, IND2, IND3, IND4, IND5: Inductors

[0076] O1, O2, O3, O4: Open

[0077] OP1, OP3: Groove opening

[0078] OP2, OP4: Through hole opening

[0079] PU: Packaging Unit

[0080] RW: Reconstructed Wafer

[0081] T164, T170, T264: thickness

[0082] W1, W2: semiconductor wafer DETAILED DESCRIPTION

[0083] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0084] In addition, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship between one element or feature shown in a figure and another element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0085] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of a three-dimensional (3D) package or a three-dimensional integrated circuit (3DIC) device. The test structure may include, for example, a test pad formed in a redistribution layer or formed on a substrate, so that the 3D package or 3DIC can be tested, probes and / or probe cards can be used, etc. Verification testing can be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein can be used in combination with a test method that includes intermediate verification of a known good die to improve yield and reduce costs.

[0086] Figures 1A to 1F as well as Figures 2A to 2F is a schematic cross-sectional view showing a manufacturing process of the semiconductor die 100 and the semiconductor die 200 according to some embodiments of the present disclosure. Figure 1A and Figure 2A , provide a semiconductor wafer W1 and a semiconductor wafer W2. In some embodiments, the semiconductor wafer W1 includes a plurality of die units DU1 and the semiconductor wafer W2 includes a plurality of die units DU2. In some embodiments, the die unit DU1 corresponds to a portion of the semiconductor wafer W1, and the die unit DU2 corresponds to a portion of the semiconductor wafer W2. For simplicity, Figure 1A A tube core unit DU1 is shown in FIG. Figure 2A However, it should be understood that a plurality of die units DU1 and a plurality of die units DU2 may be arranged in an array form in the corresponding semiconductor wafer W1 and semiconductor wafer W2.

[0087] In some embodiments, each die unit DU1 includes a semiconductor substrate 110a and an interconnect structure IN1 disposed on the semiconductor substrate 110a. In some embodiments, the semiconductor substrate 110a may be made of the following materials: elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, a device D1 is formed in the semiconductor substrate 110a. The device D1 may include active components (such as transistors, etc.) and / or passive components (such as resistors, capacitors, inductors, etc.). The semiconductor substrate 110a may also include a through semiconductor via (TSV) 112. In some embodiments, during processing (in Figure 3DAfter that, the semiconductor via 112 will penetrate through the semiconductor substrate 110a to achieve a dual-side connection. In some alternative embodiments, the semiconductor via 112 is optional and can be omitted. Figure 1A As shown in FIG. 1 , the first end of the semiconductor through-hole 112 is embedded in the interconnect structure IN1 and the second end of the semiconductor through-hole 112 is embedded in the semiconductor substrate 110a. That is, the semiconductor through-hole 112 extends from the interconnect structure IN1 to the semiconductor substrate 110a. It should be understood that Figure 1A One semiconductor through-via 112 is shown in the figure for exemplary description, and the present disclosure is not limited thereto. In some embodiments, the die unit DU1 may include fewer or more semiconductor through-vias 112 .

[0088] In some embodiments, the interconnect structure IN1 includes an inter-dielectric layer 120, an interconnect conductive pattern (also referred to as a conductive pattern) 130, and an inductor pattern 140. In some embodiments, the interconnect conductive pattern 130 and the inductor pattern 140 are embedded in the inter-dielectric layer 120. For simplicity, Figure 1A 1 , the dielectric interlayer 120 is shown as a single dielectric layer and the interconnect conductive pattern 130 and the inductor pattern 140 are shown as being embedded in the single dielectric interlayer 120. However, from the perspective of manufacturing process, the dielectric interlayer 120 may be composed of a plurality of stacked dielectric layers, wherein the interconnect conductive pattern 130 and the inductor pattern 140 are sandwiched between two adjacent dielectric interlayers 120.

[0089] In some embodiments, the interconnected conductive pattern 130 includes trench portions 134, 138 and via portions 132, 136. In some embodiments, the via portions 132, 136 extend vertically through the dielectric interlayer 120 to establish electrical connections with the underlying trench portion (also referred to as an interconnected pattern) 134 or the underlying device D1. For example, the via portion 132 may establish electrical connections between the device D1 in the semiconductor substrate 110 and the overlying trench portion 134, while the via portion 136 may establish electrical connections between the trench portion 134 and the trench portion 138. In some embodiments, the semiconductor through-via 112 directly contacts one of the trench portions 134.

[0090] In some embodiments, the inductor pattern 140 includes trench portions 144, 148, 149, and a via portion 146. In some embodiments, the trench portion 144 may be substantially coplanar with the trench portion 134. Similarly, the trench portion 148, the trench portion 149, and the trench portion 138 are substantially coplanar with each other. In other words, the trench portion 144 and the trench portion 134 may be formed simultaneously by the same process step. Similarly, the trench portion 148, the trench portion 149, and the trench portion 138 may also be formed simultaneously by the same process step.

[0091] In some embodiments, trench portions 134, 138, 144, 148, 149 and via portions 132, 136, 146 may be referred to as metallization layers. For example, trench portions 134, 144 and via portion 132 may be referred to as a first metallization layer of interconnect structure IN1. Similarly, trench portions 138, 148, 149 and via portion 146 may be referred to as a second metallization layer. It should be noted that although Figure 1A In the figure, the interconnect structure IN1 is shown as including only two metallization layers, but the present disclosure is not limited thereto. In some embodiments, more or fewer metallization layers may be included. In some alternative embodiments, the number of the interconnect conductive patterns 130, the number of the inductor patterns 140, and the number of the dielectric interlayers 120 may be adjusted according to the wiring requirements.

[0092] In some embodiments, the material of the dielectric interlayer 120 includes polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), combinations thereof, or other suitable dielectric materials. The dielectric interlayer 120 may be formed by suitable manufacturing techniques such as spin-on coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, the interconnecting conductive pattern 130 and the inductor pattern 140 include the same material. In some embodiments, the materials of the interconnecting conductive pattern 130 and the inductor pattern 140 include aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof. In some embodiments, the interconnecting conductive pattern 130 and the inductor pattern 140 are formed simultaneously. For example, the interconnecting conductive pattern 130 and the inductor pattern 140 may be formed by electroplating, deposition, and / or photolithography and etching. In some embodiments, the conductive pattern 130 and the inductor pattern 140 may be formed according to a single damascene or a dual damascene process.

[0093] refer to Figure 2A, the die unit DU2 in the semiconductor wafer W2 may be similar to the die unit DU1 in the semiconductor wafer W1, and thus will not be described in detail herein. In some embodiments, each die unit DU2 includes a semiconductor substrate 210, in which a device D2 is formed and an interconnect structure IN2 is formed on the semiconductor substrate 210. The interconnect structure IN2 includes a dielectric interlayer 220, in which an interconnect conductive pattern 230 and an inductor pattern 240 are embedded. In some embodiments, the interconnect conductive pattern 230 includes through-hole portions 232, 236 and groove portions 234 and 238. In some embodiments, the inductor pattern 240 includes groove portions 244, 248, 249 and a through-hole portion 246. As Figure 2A As shown in FIG. 1 , the die unit DU2 does not have a semiconductor through hole, but the present disclosure is not limited thereto. In some alternative embodiments, the semiconductor substrate 210 may include a semiconductor substrate having a semiconductor through hole. Figure 1A The semiconductor through via 112 in the die unit DU1 is shown as a semiconductor through via configured similarly.

[0094] For the sake of simplicity, the process performed on the semiconductor wafer W1 and the process performed on the semiconductor wafer W2 will be described below at the same time. It should be noted that this does not mean that the present disclosure is limited to the case where two semiconductor wafers W1 and W2 are processed simultaneously, nor is it limited to the case where similar or corresponding parts between the semiconductor wafer W1 and the semiconductor wafer W2 must use the same material or form the same pattern. For example, in some embodiments, the internal conductive pattern 130 of the semiconductor wafer W1 may include a different material than the material of the internal conductive pattern 230 of the semiconductor wafer W2. As another example, the wiring configuration of the internal conductive pattern 230 of the semiconductor wafer W2 or the wiring configuration of the inductor pattern 240 may be different from the wiring configuration of the internal conductive pattern 130 of the semiconductor wafer W1 or the wiring configuration of the inductor pattern 140.

[0095] refer to Figure 1B and Figure 2B, a protective material layer 150a is formed on the interconnect structure IN1, and a protective material layer 250a is formed on the interconnect structure IN2. In some embodiments, the protective material layer 150a and the protective material layer 250a cover the corresponding underlying interconnect structure IN1 and the interconnect structure IN2. In some embodiments, the protective material layers 150a and 250a may independently include polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO) or any other suitable dielectric material. In some embodiments, the protective material layers 150a and 250a include inorganic materials. The inorganic material may be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), etc. The protective material layers 150a and 250a may be formed by suitable manufacturing techniques such as spin coating and CVD. In some embodiments, the interconnect structure IN1 is sandwiched between the protection material layer 150 a and the semiconductor substrate 110 a , and the interconnect structure IN2 is sandwiched between the protection material layer 250 a and the semiconductor substrate 210 .

[0096] refer to Figure 1C and Figure 2C , the protective material layers 150a, 250a are patterned to form protective layers 150, 250. In some embodiments, the protective layer 150 has a plurality of openings exposing the groove portions 138, 148, and 149. Similarly, the protective layer 250 has a plurality of openings exposing the groove portions 238, 248, and 249. Thereafter, a conductive material may be filled into the openings and on the protective layers 150, 250 by electroplating, deposition, and / or photolithography and etching to form inductor patterns 160, 260 and conductive pads 170, 270. In some embodiments, the inductor pattern 160 is formed on the inductor pattern 140 and is electrically connected to the inductor pattern 140. The inductor pattern 160 may include a through-hole portion 162 extending through the protective layer 150 and a groove portion 164 disposed on the protective layer 150. The via portion 162 electrically connects the trench portion 164 to the trench portions 148, 149 of the inductor pattern 140. In some embodiments, the inductor patterns 140 and 160 are collectively referred to as a first spiral segment (in Figure 3A ).

[0097] In some embodiments, a conductive pad 170 is formed on the protective layer 150 located above the internal conductive pattern 130. In some embodiments, each conductive pad 170 may have a protrusion (through hole) that penetrates the protective layer 150 to establish an electrical connection with the internal conductive pattern 130. In some embodiments, the conductive pad 170 is used to establish an electrical connection with other electronic components (not shown) formed subsequently. In some alternative embodiments, the conductive pad 170 may be a test pad for probing the die unit DU1. In some embodiments, the thickness T164 of the groove portion 164 of the inductor pattern 160 is in the range of 0.6 microns to 2.8 microns. In some embodiments, the thickness T164 of the groove portion 164 is the same as the thickness T170 of the conductive pad 170. In this article, the thickness T170 of the conductive pad 170 refers to the thickness of the conductive pad 170 located above the protective layer 150. That is, the thickness T170 does not include the thickness of the protrusion of the conductive pad 170.

[0098] Similar to the inductor pattern 160, the inductor pattern 260 includes: a groove portion 264 disposed on the protection layer 250; and a via portion 262 extending through the protection layer 250 to establish an electrical connection with the underlying inductor pattern 240. In some embodiments, the inductor patterns 240 and 260 are collectively referred to as the second spiral segment of the inductor IND1 (in Figure 3A ). In some embodiments, a conductive pad 270 is formed on the protective layer 250 and the conductive pad 270 may have a protrusion (through hole) that penetrates the protective layer 250 to establish an electrical connection with the underlying interconnected conductive pattern 230. The thickness T164 of the groove portion 164 may be the same as or different from the thickness T264 of the groove portion 264. In some embodiments, the ratio of the thickness T164 to the thickness T264 is in the range of 0.5 to 5.

[0099] In some embodiments, the materials of the inductor patterns 160, 260 and the conductive pads 170, 270 may include aluminum, titanium, copper, nickel, tungsten, alloys thereof, or other suitable materials. In some embodiments, the material of the inductor pattern 160 is different from the material of the underlying inductor pattern 140, the material of the conductive pad 170 is different from the material of the underlying interconnected conductive pattern 130, the material of the inductor pattern 260 is different from the material of the underlying inductor pattern 240, and the material of the conductive pad 270 is different from the material of the underlying interconnected conductive pattern 230. In some embodiments, the inductor patterns 160, 260 may be formed simultaneously with the corresponding conductive pads 170, 270. That is, the material of the inductor patterns 160, 260 may be the same as the material of the conductive pads 170, 270.

[0100] refer to Figure 1D and Figure 2D, forming a combined dielectric material layer 180a and a combined dielectric material layer 280a on the protective layer 150 and the protective layer 250 to cover the corresponding inductor patterns 160, 260 and the corresponding conductive pads 170, 270, respectively. In some embodiments, the material of the combined dielectric material layers 180a, 280a includes oxide (e.g., silicon dioxide), polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), other suitable polymer dielectric materials or combinations thereof. In some embodiments, the combined dielectric material layers 180a, 280a are formed by spin coating, CVD, plasma enhanced chemical vapor deposition (PECVD), etc.

[0101] refer to Figure 1D to Figure 1E as well as Figure 2D to Figure 2E, the combined dielectric material layer 180a and the combined dielectric material layer 280a are patterned to form the combined dielectric layer 180 and the combined dielectric layer 280. The combined dielectric material layers 180a and 280a may be patterned by a dual damascene process. For example, at least a portion of the combined dielectric material layers 180a, 280a and at least a portion of the protective layers 150, 250 may be removed to form the groove openings OP1, OP3 and the through-hole openings OP2, OP4. In some embodiments, the groove opening OP1 is connected to the through-hole opening OP2, and the groove opening OP3 is connected to the through-hole opening OP4. In some embodiments, the groove opening OP1 and the through-hole opening OP2 expose at least a portion of the groove portion 149 of the interconnect structure IN1. Similarly, the groove opening OP3 and the through-hole opening OP4 expose at least a portion of the groove portion 249 of the interconnect structure IN2. After forming the trench openings OP1, OP3 and the through-hole openings OP2, OP4, conductive material is filled into the trench openings OP1, OP3 and the through-hole openings OP2, OP4 to form inductor bonding pads (also referred to as bonding pads) 192, 292 and bonding vias 194, 294. During the formation of the trench openings OP1, OP3 and the through-hole openings OP2, OP4, other openings may be formed in the bonding dielectric material layers 180a and 280a. In some embodiments, some of these openings expose the conductive pads 170, and the rest of these openings are recesses that do not expose any underlying conductive elements. In some embodiments, conductive material is also filled into these openings to form interconnect bonding pads 196, 296, dummy bonding pads 197, 297, and conductive vias 198, 298. In some embodiments, the inductor bonding pad 192, the bonding via 194, the interconnect bonding pad 196, the dummy bonding pad 197, and the conductive via 198 are collectively referred to as a bonding metallization pattern 190. Similarly, the inductor bonding pad 292, the bonding via 294, the interconnect bonding pad 296, the dummy bonding pad 297, and the conductive via 298 are collectively referred to as a bonding metallization pattern 290. In some embodiments, the material of the bonding metallization pattern 190 and the bonding metallization pattern 290 may include aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof. In some embodiments, the bonding metallization pattern 190 or the bonding metallization pattern 290 may be made of the same material as the corresponding inductor pattern 140 or the inductor pattern 240 and the corresponding interconnect conductive pattern 130 or the interconnect conductive pattern 230. In some embodiments, the material of the bonding metallization pattern 190 or the bonding metallization pattern 290 may be different from the material of the corresponding inductor pattern 160 or the inductor pattern 260.

[0102] like Figure 1EAs shown in , the inductor bonding pad 192 is connected to the groove portion 149 of the inductor pattern 140 through the bonding via 194. In some embodiments, the inductor bonding pad 192 and the bonding via 194 are collectively referred to as inductor bonding metallurgies. In some embodiments, the inductor patterns 140, 160 and the inductor bonding metallurgies (inductor bonding pad 192 and bonding via 194) are collectively referred to as inductor wire fragments. In some embodiments, the internal bonding pad 196 can be connected to the conductive pad 170 through the conductive via 198, and the dummy bonding pad 197 can be electrically floating. That is, the dummy bonding pad 197 can be disposed on the inductor pattern 160 but not electrically connected to the inductor pattern 160. In some embodiments, the top surface of the inductor bonding pad 192, the top surface of the interconnect bonding pad 196, the top surface of the dummy bonding pad 197, and the top surface of the bonding dielectric layer 180 are substantially located at the same level to provide a suitable active surface AS1 to achieve hybrid bonding. The protection layer 150, the inductor pattern 160, the conductive pad 170, the bonding dielectric layer 180, and the bonding metallization pattern 190 are collectively referred to as a bonding structure BS1.

[0103] like Figure 2E As shown in , the inductor bonding pad 292 is connected to the groove portion 249 of the inductor pattern 240 through the bonding via 294. In some embodiments, the inductor bonding pad 292 and the bonding via 294 are collectively referred to as inductor bonding metal. In some embodiments, the inductor patterns 240, 260 and the inductor bonding metal (inductor bonding pad 292 and bonding via 294) are collectively referred to as inductor wire segments. In some embodiments, the internal bonding pad 296 can be connected to the conductive pad 270 through the conductive via 298, and the dummy bonding pad 297 can be electrically floating. That is, the dummy bonding pad 297 can be set on the inductor pattern 260, but not electrically connected to the inductor pattern 260. In some embodiments, the top surface of the inductor bonding pad 292, the top surface of the interconnect bonding pad 296, the top surface of the dummy bonding pad 297, and the top surface of the bonding dielectric layer 280 are substantially located at the same level to provide an appropriate active surface AS2 to achieve hybrid bonding. The protection layer 250, the inductor pattern 260, the conductive pad 270, the bonding dielectric layer 280, and the bonding metallization pattern 290 are collectively referred to as a bonding structure BS2.

[0104] refer to Figure 1E to Figure 1F and Figure 2E to Figure 2F, a singulation process may be performed to form a plurality of semiconductor dies 100 and a plurality of semiconductor dies 200. The singulation process may be performed by, for example, cutting off the semiconductor wafer W1 along a dicing line C1 located between each die unit DU1, and cutting off the semiconductor wafer W2 along a dicing line C2 located between each die unit DU2. In some embodiments, the singulation process typically involves performing a wafer dicing process using a rotating blade and / or a laser beam. In some embodiments, the singulation step is optional and may be skipped. In some embodiments, the semiconductor die 100 and the semiconductor die 200 may be dies capable of performing a storage function. For example, each of the semiconductor die 100 and the semiconductor die 200 may independently be a dynamic random access memory (DRAM), a resistive random access memory (RRAM), a static random access memory (SRAM), etc. However, the present disclosure is not limited thereto. In some alternative embodiments, the semiconductor die 100 and the semiconductor die 200 may independently be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a field-programmable gate array (FPGA), etc. In some embodiments, an inductor wire segment of an inductor is formed in each of the semiconductor die 100 and the semiconductor die 200.

[0105] FIG. 3A to FIG. 3J is a schematic cross-sectional view showing a manufacturing process of a semiconductor package 10 according to some embodiments of the present disclosure. Figure 3A ,jump over Figures 1E to 1F and Figures 2E to 2F The steps of singulating the two semiconductor wafers W1 and W2 shown in FIG. 1 and mixing and combining the semiconductor wafers W1 and W2 to obtain a reconstructed wafer RW. In some embodiments, the reconstructed wafer RW includes a plurality of package units PU. In other words, the exemplary process may be performed at the reconstructed wafer level so that a plurality of package units PU may be processed in the form of the reconstructed wafer RW. Figure 3A In the figure, for the sake of simplicity, one packaging unit PU is shown. However, the present disclosure is not limited thereto. A plurality of packaging units PU may be arranged in an array in the reconstructed wafer RW.

[0106] like Figure 3AAs shown in , the semiconductor die 100 included in the semiconductor wafer W1 can be hybrid-bonded to the semiconductor die 200 included in the semiconductor wafer W2. In some embodiments, the temperature of the hybrid bonding process is in the range of about 200° C. to about 300° C. In some embodiments, the semiconductor wafer W1 is placed so that the active surface AS1 of the semiconductor die 100 contacts the active surface AS2 of the semiconductor die 200 in the semiconductor wafer W2. In addition, the inductor bonding pad 192, the inner connection bonding pad 196, and the dummy bonding pad 197 of the semiconductor die 100 are substantially aligned with and directly contact the corresponding inductor bonding pad 292, the corresponding inner connection bonding pad 296, and the corresponding dummy bonding pad 297 of the semiconductor die 200. That is, the inductor bonding pad 192 is bonded to the inductor bonding pad 292, the inner connection bonding pad 196 is bonded to the inner connection bonding pad 296, and the dummy bonding pad 197 is bonded to the dummy bonding pad 297. In some embodiments, the bonding dielectric layer 180 directly contacts the bonding dielectric layer 280. In some embodiments, to facilitate hybrid bonding between the semiconductor die 100 and the semiconductor die 200, surface preparation may be performed on the bonding surfaces of the semiconductor wafer W1 and the semiconductor wafer W2 (i.e., the active surface AS1 and the active surface AS2). The surface preparation may include, for example, surface cleaning and activation. The active surfaces AS1 and AS2 may be surface cleaned to remove particles on the bonding surfaces of the inductor bonding pads 192 and 292, the bonding surfaces of the interconnect bonding pads 196 and 296, the bonding surfaces of the dummy bonding pads 197 and 297, and the bonding surfaces of the bonding dielectric layers 180 and 280. In some embodiments, for example, the active surfaces AS1 and AS2 may be cleaned by wet cleaning.

[0107] After cleaning the active surfaces AS1 and AS2, activation may be performed on the bonding surfaces of the bonding dielectric layer 180 and the bonding dielectric layer 280 to achieve high bonding strength. For example, plasma activation may be performed to treat the bonding surfaces of the bonding dielectric layer 180 and the bonding dielectric layer 280. When the activated bonding surfaces of the bonding dielectric layer 180 and the bonding dielectric layer 280 are in contact with each other, the bonding dielectric layer 180 and the bonding dielectric layer 280 are pre-bonded. After the semiconductor die 100 is pre-bonded to the semiconductor die 200, a hybrid bonding step is performed. The hybrid bonding step may include a thermal treatment for achieving dielectric bonding and a thermal annealing process for achieving conductor bonding. In some embodiments, a thermal treatment for achieving dielectric bonding is performed to strengthen the bonding between the bonding dielectric layer 180 and the bonding dielectric layer 280. After performing the thermal treatment for achieving dielectric bonding, thermal annealing for conductor bonding is performed to facilitate bonding between the inductor bonding pad 192, the interconnect bonding pad 196, and the dummy bonding pad 197 and the corresponding inductor bonding pad 292, the corresponding interconnect bonding pad 296, and the corresponding dummy bonding pad 297. In some embodiments, the process temperature of the thermal annealing for achieving conductor bonding is higher than the process temperature of the thermal treatment for achieving dielectric bonding. After performing the thermal annealing for conductor bonding, the bonding dielectric layer 180 is bonded to the bonding dielectric layer 280. At the same time, the inductor bonding pad 192, the interconnect bonding pad 196, and the dummy bonding pad 197 are bonded to the corresponding underlying inductor bonding pad 292, the corresponding underlying interconnect bonding pad 296, and the corresponding underlying dummy bonding pad 297. In this way, the upper die (e.g., semiconductor die 100) is hybrid-bonded to the lower die (e.g., semiconductor die 200). In some embodiments, the bonding interface BI is visible at the contact plane between the active surface AS1 of the semiconductor wafer W1 and the active surface AS2 of the semiconductor wafer W2 .

[0108] It should be noted that although Figure 3A The reconstructed wafer RW in is obtained by hybrid bonding of the semiconductor wafer W1 and the semiconductor wafer W2, but the present disclosure is not limited thereto. In some alternative embodiments, one or both of the semiconductor wafer W1 and the semiconductor wafer W2 may be subjected to a singulation process before the hybrid bonding process. In this way, the reconstructed wafer RW may be obtained by hybrid bonding of singulated semiconductor dies (e.g., semiconductor die 100) and semiconductor wafers (e.g., semiconductor wafer W2). For example, the semiconductor die 100 may be picked up and placed on the semiconductor wafer W2 so that the semiconductor die 100 is electrically connected to the semiconductor die 200.

[0109] In some embodiments, when semiconductor die 100 is bonded to semiconductor die 200, inductor patterns 140, 160 and inductor bonding metal (inductor bonding pads 192 and bonding vias 194) of semiconductor die 100 are bonded to inductor patterns 240, 260 and inductor bonding metal (inductor bonding pads 292 and bonding vias 294) of semiconductor die 200 to define a conductive wire surrounding a portion of dielectric material (a portion of bonding dielectric layers 180, 280, a portion of protection layers 150, 250, and dielectric interlayers 120, 220), thereby forming an inductor IND1. In some embodiments, semiconductor die 100 and semiconductor die 200 respectively include wire segments of the conductive wire features of inductor IND1. For example, the inductor patterns 140, 160 and the inductor bonding metal (the inductor bonding pad 192 and the bonding via 194) of the semiconductor die 100 may constitute a first wire segment of the inductor IND1, the inductor patterns 240, 260 and the inductor bonding metal (the inductor bonding pad 292 and the bonding via 294) may constitute a second wire segment of the inductor IND1, and the conductive wire of the inductor IND1 may include a first wire segment and a second wire segment.

[0110] refer to Figure 3A and Figure 3B In some embodiments, the semiconductor substrate 110a is thinned from one side of the surface 110r to form the semiconductor substrate 110. In some embodiments, a portion of the semiconductor substrate 110a may be removed until the semiconductor through hole 112 is exposed. Figure 3B As shown in , after the semiconductor substrate 110a is thinned, the semiconductor through-hole 112 may protrude from the semiconductor substrate 110. That is, the surface 112b of the semiconductor through-hole 112 may be located at a higher level than the surface 110r of the semiconductor substrate 110. In some embodiments, the portion of the semiconductor substrate 110a may be removed by an etching process. The etching process includes, for example, an isotropic etching process and / or an anisotropic etching process. For example, the semiconductor substrate 110a may be thinned by a wet etching process, a dry etching process, or a combination thereof.

[0111] refer to Figure 3C, a first dielectric layer 302a is formed on the surface 110r of the semiconductor substrate 110. In some embodiments, the first dielectric layer 302a is formed to cover the surface 112b of the semiconductor through hole 112. The material of the first dielectric layer 302a includes oxide. In some embodiments, the material of the first dielectric layer 302a includes silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), etc. The first dielectric layer 302a can be formed by a suitable manufacturing technique such as spin coating, lamination, CVD, etc.

[0112] refer to Figure 3D After forming the first dielectric layer 302a, a planarization process is performed to thin the first dielectric layer 302a until the surface 112b of the semiconductor through-hole 112 is exposed to form the first dielectric layer 302. In some embodiments, after the planarization process is completed, the surface 112b of the semiconductor through-hole 112 may be substantially coplanar with the surface 302t of the first dielectric layer 302. In some embodiments, the planarization of the first dielectric layer 302a includes performing a mechanical grinding process and / or a chemical mechanical polishing (CMP) process. In some embodiments, some portions of the semiconductor through-hole 112 may also be removed during the planarization process.

[0113] refer to Figure 3E , a second dielectric layer 304 is formed on the first dielectric layer 302. The second dielectric layer 304 has a plurality of openings O1, and the plurality of openings O1 expose the surface 112b of the semiconductor through-hole 112 and some portions of the first dielectric layer 302. In some embodiments, the material of the second dielectric layer 304 may be similar to that of the first dielectric layer 302. For example, the second dielectric layer 304 may include an oxide, such as silicon oxide. Thereafter, a seed material layer 312a is conformally formed on the second dielectric layer 304. In some embodiments, the seed material layer 312a is blanket formed on the package unit PU. Figure 3E As shown in , the seed material layer 312a extends into the opening O1 to directly contact the semiconductor through hole 112. In some embodiments, the seed material layer 312a may be formed by, for example, a sputtering process, a physical vapor deposition (PVD) process, etc. In some embodiments, the seed material layer 312a may include, for example, copper, tantalum, titanium, a combination thereof, or other suitable materials. In some embodiments, a barrier layer (not shown) may be deposited before forming the seed material layer 312a to prevent undesired diffusion.

[0114] refer to Figure 3F, depositing a conductive material 315a on the seed material layer 312a. In some embodiments, the conductive material 315a may include a metal material, such as copper, aluminum, platinum, nickel, titanium, tantalum, chromium, gold, silver, tungsten, combinations thereof, etc. In some embodiments, the conductive material 315a is formed on the seed material layer 312a by electroplating, electroless plating, physical vapor deposition, chemical vapor deposition, etc.

[0115] refer to Figure 3F and Figure 3G , a planarization process is performed on the conductive material 315a until the second dielectric layer 304 is exposed. That is, some portions of the conductive material 315a disposed on the surface 304t of the second dielectric layer 304 and some portions of the seed material layer 312a may be removed to obtain the first redistribution pattern 310 filling the opening O1. In some embodiments, each first redistribution pattern 310 includes a seed layer 312 and a conductive plug 315 disposed on the seed layer 312. In some embodiments, the conductive plug 315 is laterally surrounded by the seed layer 312. In some embodiments, at least a portion of the first redistribution pattern 310 is electrically and physically connected to the semiconductor through-hole 112.

[0116] refer to Figure 3H , a third dielectric layer 306 is formed on the second dielectric layer 304. The third dielectric layer 306 has an opening O2, and the opening O2 reveals some portions of some first redistribution patterns in the first redistribution pattern 310. In some embodiments, the material of the third dielectric layer 306 may be similar to the material of the first dielectric layer 302 and / or the second dielectric layer 304. For example, the third dielectric layer 306 may include an oxide, such as silicon oxide. A plurality of second redistribution patterns 320 are formed on the third dielectric layer 306. In some embodiments, each second redistribution pattern 320 may be divided into a through-hole portion 322 and a groove portion 324. In some embodiments, the through-hole portion 322 is located in the opening O2 and the groove portion 324 is disposed on the third dielectric layer 306. The through-hole portion 322 allows electrical connection between the second redistribution pattern 320 and the first redistribution pattern 310. For simplicity, Figure 3HThe seed layer 312 is omitted in the following figure. It should be noted that, similar to the first rewiring pattern 310, each of the second rewiring patterns 320 may also include a seed layer and a conductive plug. In some embodiments, the through-hole portion 322 and the groove portion 324 of the second rewiring pattern 320 are formed simultaneously. After forming the second rewiring pattern 320, a first passivation layer 308 is formed on the third dielectric layer 306. The first passivation layer 308 extends beside the second rewiring pattern 320 located on the third dielectric layer 306 and partially covers the groove portion 324 of the second rewiring pattern 320. That is, the first passivation layer 308 includes an opening O3 that exposes a portion of the groove portion 324. In some embodiments, the first passivation layer 308 may be blanket formed on the package unit PU and a patterning process (e.g., deposition, photolithography, and etching) may be performed to form the opening O3. In some embodiments, the material of the first passivation layer 308 includes, for example, polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), combinations thereof, or other suitable dielectric materials.

[0117] refer to Fig. 3I , a second passivation layer 330 is disposed on the first passivation layer 308. In some embodiments, the second passivation layer 330 covers the first passivation layer 308 and partially extends into the opening O3. For example, the second passivation layer 330 extends into the opening O3 to partially cover the groove portion 324 of the second redistribution pattern 320. That is, the second passivation layer 330 may include an opening O4 that exposes a portion of the groove portion 324 revealed by the opening O3. Fig. 3I As shown in , the opening O3 of the first passivation layer 308 is wider than the opening O4 of the second passivation layer 330. In some embodiments, the first passivation layer 308 and the second passivation layer 330 may include different materials. In some alternative embodiments, the material of the second passivation layer 330 may be the same as the material of the first passivation layer 308. For example, the material of the second passivation layer 330 includes polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), a combination thereof, or other suitable dielectric materials.

[0118] In some embodiments, an under-bump metallurgies (UBM) 400 may be conformally formed in the opening O4. In some embodiments, the under-bump metallurgies 400 may also extend over the portion of the second passivation layer 330 surrounding the opening O4. In some embodiments, the material of the under-bump metallurgies 400 includes copper, nickel, tin, palladium, gold, titanium, aluminum, or an alloy thereof. In some embodiments, a plurality of conductive material layers may be stacked to form the under-bump metallurgies 400. In some embodiments, the under-bump metallurgies 400 may be formed by a plating process. The plating process is, for example, electroplating, electroless plating, immersion plating, etc. Thereafter, a plurality of conductive terminals 500 are formed on the under-bump metallurgies 400. In some embodiments, the conductive terminals 500 are electrically connected to the semiconductor die 100 via the first rewiring pattern 310 and the second rewiring pattern 320. The conductive terminals 500 include, for example, solder balls, ball grid array (BGA) connectors, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, combinations thereof (e.g., metal pillars bonded to solder balls), etc.

[0119] refer to Fig. 3I and Figure 3J , performing a singulation process to form a plurality of semiconductor packages 10. The singulation process may be performed, for example, by cutting the reconstructed wafer RW along a cutting line SC between each package unit PU. In some embodiments, the sawing process or singulation process generally involves sawing using a rotating blade or a laser beam. In other words, the sawing or singulation process is, for example, a laser cutting process, a mechanical cutting process, or other suitable processes.

[0120] Figure 3K is a schematic cross-sectional view showing an electronic device 15 according to some embodiments of the present disclosure. Figure 3K , the semiconductor package 10 is stacked on the circuit substrate 600 to form the electronic device 15. In some embodiments, the circuit substrate 600 may be a motherboard, a printed circuit board, etc. In some embodiments, the semiconductor package 10 is connected to the circuit substrate 600 through the conductive terminal 500.

[0121] Figure 4A yes Figure 3KSchematic perspective view of an inductor IND1 of a semiconductor package 10 is shown in FIG. Figure 4B yes Figure 4A Schematic exploded diagram of the inductor IND1 in FIG. Figure 4A and Figure 4B , the conductive wire in the inductor IND1 is shown in FIG. Figure 4A and Figure 4B The dielectric material is omitted (i.e., the dielectric layers 180, 280, the protective layers 150, 250, and the dielectric interlayers 120, 220 are combined). In addition, in the exploded view, the elements are shown as being disposed directly on top of another element to enable a deeper understanding of the structure of the inductor of the present disclosure, rather than focusing only on the manufacturing process of the inductor. For example, for clarity of illustration, the through-hole portion 2621 and the through-hole portion 2622 are shown as being located on the groove portions 248, 249, but from a manufacturing perspective, the through-hole portion 2621 and the through-hole portion 2622 are formed together (formed as a whole) with the groove portion 264 rather than with the groove portions 248, 249. The area marked as "CT" and followed by a reference number in the figure indicates the contact area between the element on which the area CT is drawn and the element indicated by the reference number. For example, in Figure 4B The contact regions CT146 drawn on the trench portion 144 in FIG. 1 indicate the area where the via portion 146 contacts the trench portion 144. The dashed lines provide a visual guide to connecting individual components using the corresponding contact regions.

[0122] refer to Figure 4A and Figure 4BIn some embodiments, the inductor IND1 includes a plurality of winding portions, the winding portions having one or more metallization layers of the interconnect structures IN1, IN2 and one or more metallization layers included in the bonding structures BS1, BS2. In some embodiments, different winding portions may include different conductive materials. For example, the inductor IND1 includes: a winding portion 1010 formed by the inductor pattern 140, a winding portion 1020 formed by the inductor pattern 160, a winding portion 1030 formed by the inductor pattern 260, a winding portion 1040 formed by the inductor pattern 240, and a bonding portion 1050 formed by inductor bonding metal (inductor bonding pad 192, bonding via 194, inductor bonding pad 292, and bonding via 294). In some embodiments, the material of the winding portion 1010 is the same as the material of the winding portion 1040 and the material of the bonding portion 1050. On the other hand, the material of winding portion 1010 is different from the material of winding portion 1020 and winding portion 1030. In some embodiments, the material of winding portion 1020 is the same as the material of winding portion 1030. In some alternative embodiments, winding portion 1020 and winding portion 1030 include different materials. For example, groove portions 144, 148, 149, 244, 248, 249, via portions 146, 246, and bonding metal (inductor bonding pads 192, 292 and bonding vias 194, 294) can be made of copper, and via portions 1621, 1622, 2621, 2622 and groove portions 164, 264 can be made of aluminum. In some embodiments, since the winding portions 1010 to 1040 of the inductor IND1 are distributed between the two semiconductor dies 100 and 200 (i.e., the inductor IND1 extends from the semiconductor die 100 to the semiconductor die 200), the thickness of the individual winding portions 1010 to 1040 can be reduced without sacrificing the performance of the inductor IND1. The reduced thickness of the metallization layer in turn facilitates the planarization of the active surface AS1 and the active surface AS2, thereby improving the bonding between the semiconductor die 100 and the semiconductor die 200. In this way, the overall yield and reliability of the semiconductor package 10 can be improved, thereby reducing the manufacturing cost.

[0123] like Figure 4A and Figure 4BAs shown in , the inductor IND1 includes six vertically stacked coils 6010 to 6060, which are electrically connected in series. In some embodiments, the groove portion 144 of the inductor pattern 140 is in an open loop shape and constitutes the coil 6010 of the inductor IND1. On the other hand, the groove portion 148 of the inductor pattern 140 may constitute the coil 6020 of the inductor IND1. In some embodiments, the groove portion 144 (coil 6010) is connected to the groove portion 148 (coil 6020) through the through-hole portion 146. For example, the through-hole portion 146 electrically contacts and physically contacts both the groove portion 148 and the groove portion 144. In some embodiments, the through-hole portion 146 physically contacts the groove portion 144 at the contact area CT146. In some embodiments, the contact area CT146 is located near one end of the groove portion 144. The other end of the groove portion 144 may be connected to the inductor through an inductor via hole (not shown) or through the interconnect pattern 134 ( Figure 3J ) connected to device D1 ( Figure 3J 16). In the same embodiment, the groove portion 144 and the interconnecting pattern 134 are formed as a whole, that is, no clear interface can be seen between the groove portion 144 and the interconnecting pattern 134. The groove portion 144 and the groove portion 148 can be located at different levels, and the through hole portion 146 can bridge the distance between the two levels. In some embodiments, the through hole portion 146 reaches one end of the groove portion 148. The groove portion 148 also has an open loop shape and contacts the through hole portion 1621 at the contact area CT1621, and the contact area CT1621 is located at the other end of the open loop relative to the through hole portion 146.

[0124] In some embodiments, a through hole portion 1621 is disposed at one end of the groove portion 164. The groove portion 164 may be in an open loop form and constitute a coil 6030 of the inductor IND1. The groove portion 164 and the groove portion 148 are located at different levels, and the through hole portion 1621 may bridge the distance between the two levels. The through hole portion 1622 is disposed at the other end of the groove portion 164 and establishes an electrical connection with the groove portion 149 of the inductor pattern 140 at the contact area CT1622. The groove portion 149 is located at the same level as the groove portion 148. In some embodiments, the groove portion 149 is shorter than the groove portion 148. In this article, when measured along the top surface of the groove portion, the length of the groove portion is the distance between the two ends of the groove portion. In other words, the length of the groove portion is regarded as the length of the trimmed groove portion (rectified trench portion). The groove portion 149 establishes an electrical connection between the through hole portion 1622 at the contact area CT1622 and the bonding through hole 194 at the contact area CT194, and can be referred to as a bridge portion. In some embodiments, the top surfaces 1621t, 1622t of the through hole portions 1621, 1622 and the top surface 194t of the bonding through hole 194 are located at the same horizontal height (substantially coplanar with each other). The bonding through hole 194 reaches the inductor bonding pad 192, and the inductor bonding pad 192 is hybridly bonded to the inductor bonding pad 292. A bonding interface BI can be seen between the inductor bonding pad 192 and the inductor bonding pad 292. The bonding through hole 294 establishes an electrical connection between the inductor bonding pad 292 and the groove portion 249 at the contact area CT294. In some embodiments, the groove portion 249 can also be referred to as a bridge portion. The groove portion 249 connects the inductor bonding metal (inductor bonding pad 192, bonding via 194, inductor bonding pad 292, and bonding via 294) and the via portion 2621. In some embodiments, these bonding metals (inductor bonding pad 192, bonding via 194, inductor bonding pad 292, and bonding via 294) can be regarded as the bonding portion 1050 of the inductor IND1. In some embodiments, the bonding portion 1050 of the inductor IND1 extends across the bonding interface BI between different semiconductor dies 100 and 200.

[0125] In some embodiments, the through-hole portion 2621 establishes an electrical contact between one end of the groove portion 264 and the groove portion 249 at the contact area CT2621. At the other end of the groove portion 264, the through-hole portion 2622 establishes an electrical connection with one end of the groove portion 248 at the contact area CT2622. The groove portion 264 and the groove portion 248 can be regarded as the coil 6040 and the coil 6050 of the inductor IND1, respectively. At the other end of the groove portion 248, the through-hole portion 246 establishes an electrical connection with the groove portion 244 at the contact area CT246. In some embodiments, the groove portion 244 can be referred to as the coil 6060 of the inductor IND1. In some embodiments, the groove portion 244 can be connected to the device D2 through an inductor through hole (not shown), or can be connected to the groove portion 234 ( Figure 3J ). As described above, the materials of some of the winding portions 1010 to 1040 may be different. For example, at the contact areas CT2621 and CT2622 where the through-hole portions 2621, 2622 contact the inductor pattern 240, interfaces between different conductive materials may be observed. In some embodiments, the use of different materials for these several coils of the inductor IND1 allows fine-tuning of the properties (e.g., inductance, resistivity, etc.) of the inductor IND1. In addition, by incorporating a bonding portion 1050 extending across the bonding interface BI of the semiconductor die 100, 200 to connect the winding portions 1010 to 1040, a thinner winding portion may be made. Therefore, the flatness of the upper cover layer may be improved and the reliability of the semiconductor package may be enhanced.

[0126] refer to Figure 4B , the inductor IND1 may be integrated with a larger circuit (not shown). During operation of the semiconductor package 10, current may enter the inductor IND1 from one end (e.g., the groove portion 244 or the groove portion 144) and may travel through the coils 6010 to 6050 to exit from the other end (e.g., the other of the groove portion 244 or the groove portion 144). For example, depending on the configuration of the larger circuit and the applied voltage, the current may enter the inductor from the groove portion 144, such as Figure 4BIndicated by the arrow C_In in the middle. Then, the current can travel through the coil 6010 in a counterclockwise direction to enter the coil 6020 through the through-hole portion 146. Subsequently, the current travels through the coil 6020 in a counterclockwise direction to enter the coil 6030 through the through-hole portion 1621. Then, the current travels through the coil 6030 in a counterclockwise direction to enter the groove portion 149 through the through-hole portion 1622. Thereafter, the current travels through the combination portion 1050 (through the combination through-hole 194, the combination pad 192, the combination pad 292 and the combination through-hole 294 in a sequential order) to enter the groove portion 249. Thereafter, the current enters the coil 6040 through the through-hole portion 2621 and travels through the coil 6040 in a counterclockwise direction. Subsequently, the current enters the coil 6050 through the through-hole portion 2622 and travels through the coil 6050 in a counterclockwise direction to enter the coil 6060 through the through-hole portion 246. Finally, the current leaves the inductor IND1 at one end of the coil 6060, as shown in FIG. Figure 4B That is, the six coils 6010 to 6060 of the inductor IND1 may be connected in series, with the coupling portion 1050 interposed between the coil 6030 and the coil 6040 .

[0127] Figure 5 is a schematic cross-sectional view of a semiconductor package 20 according to some alternative embodiments of the present disclosure. The semiconductor package 20 may be Figure 3J The semiconductor package 20 is similar to the semiconductor package 10 of FIG. 1 , and thus similar elements are designated by the same or similar reference numerals and are not described in detail herein. In the semiconductor package 20, the semiconductor die 202 is used to replace the semiconductor die 200, thereby forming the inductor IND2 when combined with the semiconductor die 102. The difference between the semiconductor die 202 and the semiconductor die 200 (and between the inductor IND2 and the inductor IND1) is the thickness T264 of the groove portion 264 of the inductor pattern 260. Figure 5 , trench portion 264 is thicker than trench portion 164 of semiconductor die 102. In some embodiments, thickness T264 of trench portion 264 may be up to 2 times thickness T164 of trench portion 164. However, the present disclosure is not limited thereto. In some alternative embodiments, trench portion 164 may be thicker than trench portion 264. For example, thickness T164 of trench portion 164 may be up to 5 times thickness T264 of trench portion 264.

[0128] Fig. 6A is a schematic cross-sectional view of a semiconductor package 30 according to some alternative embodiments of the present disclosure. Figure 6B is a schematic exploded view of an inductor IND3 of a semiconductor package 30 according to some alternative embodiments of the present disclosure. Figure 6BFIG. 2 shows a conductive wire in the inductor IND3 included in the semiconductor package 30. The semiconductor package 30 and the inductor IND3 may be respectively connected to Figure 3J and Figure 4B The semiconductor package 10 and the inductor IND1 are similar, so similar elements are marked with the same or similar reference numbers and are not repeated herein. In the semiconductor package 30, the semiconductor die 104 is used to replace the semiconductor die 100, and the semiconductor die 204 is used to replace the semiconductor die 200, so that the inductor IND3 is formed when the semiconductor die 104 and the semiconductor die 204 are combined. Fig. 6A and Figure 6B, the difference between the semiconductor package 30 and the semiconductor package 10 is that the inductor IND3 includes fewer coils than the inductor IND1. In addition, some of the coils of the inductor IND3 may be connected in parallel instead of in series. For example, the coil 6120 and the coil 6130 may be connected in parallel. In some embodiments, the inductor IND3 includes a winding portion 3010, a winding portion 3020, a winding portion 3030, a winding portion 3040, a first combined portion 3050A, and a second combined portion 3050B. The winding portion 3010 includes a groove portion 144 (coil 6110), a through-hole portion 146, a groove portion 148, and a groove portion 149. The winding portion 3020 includes a groove portion 164 (coil 6120) and through-hole portions 1621, 1622. The winding portion 3030 includes the groove portion 264 (coil 6130) and the through-hole portions 2621, 2622. The winding portion 3040 includes the groove portion 244 (coil 6140), the groove portion 248, the groove portion 249 and the through-hole portion 246. The first bonding portion 3050A includes the first portion of the bonding metal (bonding pad 192A, bonding through-hole 194A, bonding pad 292A and bonding through-hole 294A). The second bonding portion 3050B includes the remaining bonding metal (bonding pad 192B, bonding through-hole 194B, bonding pad 292B and bonding through-hole 294B). In some embodiments, the groove portions 148, 149, 248 and 249 are part of the inductor IND3 but do not form the coil of the inductor IND3. Instead, the groove portions 148, 149, 248 and 249 can be used as connectors between different parts of the inductor IND3. For example, the winding portion 3010 is connected to both the winding portion 3020 and the first coupling portion 3050A through the groove portion 148, and is connected to both the winding portion 3020 and the second coupling portion 3050B through the groove portion 149. That is, the groove portion 148 may directly contact the coupling through-hole 194A of the first coupling portion 3050A at the contact region CT194A, and also directly contact the through-hole portion 1621 of the winding portion 3020 at the contact region CT1621, and the groove portion 149 may directly contact the coupling through-hole 194B of the second coupling portion 3050B at the contact region CT194B, and also directly contact the through-hole portion 1622 of the winding portion 3020 at the contact region CT1622. Similarly, the winding portion 3040 is connected to the winding portion 3030 and the second combined portion 3050B via the groove portion 248 , and is connected to the winding portion 3030 and the first combined portion 3050A via the groove portion 249 .That is, the groove portion 248 may directly contact both the coupling through hole 294B of the second coupling portion 3050B and the through hole portion 2622 of the winding portion 3030, and the groove portion 249 may directly contact both the coupling through hole 294A of the first coupling portion 3050A and the through hole portion 2621 of the winding portion 3030. On the other hand, the through hole portion 2621 directly contacts the groove portion 264 at the contact area CT2621, and the through hole portion 2622 directly contacts the groove portion 264 at the contact area CT2622. The winding portion 3010 may be connected to the winding portion 3030 through the first coupling portion 3050A, and the winding portion 3020 may be connected to the winding portion 3040 through the second coupling portion 3050B. In some embodiments, the groove portion 164 (coil 6120) and the groove portion 264 (coil 6130) are electrically connected in parallel on the first side through the bonding via 194A, the bonding pad 192A, the bonding pad 292A and the bonding via 294A, and are electrically connected in parallel on the second side through the bonding via 194B, the bonding pad 192B, the bonding pad 292B and the bonding via 294B.

[0129] During operation of the semiconductor package 30, current may enter the inductor IND3 from one end (e.g., the groove portion 244 or the groove portion 144), and may travel through the coils 6110 to 6140 to exit from the other end (e.g., the other of the groove portion 244 and the groove portion 144). For example, current may enter the inductor from the groove portion 144, as shown in FIG. Figure 6BIND3 in the embodiment of the present invention. The current may then travel in a counterclockwise direction through the coil 6110 (groove portion 144) of the inductor IND3 to enter the groove portion 148 through the through-hole portion 146. In the groove portion 148, the current may be separated into a first current CR1 and a second current CR2. The first current CR1 may enter the coil 6120 (groove portion 164) through the through-hole portion 1621 and travel in a counterclockwise direction through the coil 6120. The first current CR1 then enters the groove portion 149 through the through-hole portion 1622 and travels through the second coupling portion 3050B (through the coupling through-hole 194B, the coupling pad 192B, the coupling pad 292B, and the coupling through-hole 294B in a sequential order) to reach the groove portion 248 from the coupling through-hole 294B. The second current CR2 may travel through the first coupling portion 3050A (through the coupling through-hole 194A, the coupling pad 192A, the coupling pad 292A, and the coupling through-hole 294A in sequential order) to enter the groove portion 249. Then, the second current CR2 enters the coil 6130 (groove portion 264) through the through-hole portion 2621 and travels through the coil 6130 in a counterclockwise direction to reach the groove portion 248 through the through-hole portion 2622. In the groove portion 248, the first current CR1 and the second current CR2 may be recombined and further move toward the coil 6140 (groove portion 244), and the first current CR1 and the second current CR2 enter the coil 6140 (groove portion 244) through the through-hole portion 246. After the current travels through the coil 6140 in the counterclockwise direction, the current may leave the inductor IND3 at one end of the coil 6140, as shown in FIG. Figure 6B In some embodiments, the resistance of the inductor IND3 can be reduced by connecting the coil 6120 in parallel with the coil 6130. In some embodiments, the top surfaces 1621t, 1622t of the through-hole portions 1621, 1622 and the top surfaces 194At, 194Bt of the combined through-holes 194A, 194B are located at the same level (substantially coplanar with each other).

[0130] Fig. 7A is a schematic cross-sectional view of a semiconductor package 40 according to some alternative embodiments of the present disclosure. Figure 7B is a schematic exploded view of an inductor IND4 of a semiconductor package 40 according to some embodiments of the present disclosure. Figure 7B FIG. 4 shows a conductive wire in the inductor IND4 included in the semiconductor package 40. The semiconductor package 40 and the inductor IND4 may be respectively connected to Figure 3J and Figure 4BThe semiconductor package 40 is similar to the semiconductor package 10 and the inductor IND1, so similar elements are marked with the same or similar reference numbers and are not repeated herein. In the semiconductor package 40, the semiconductor die 106 is used to replace the semiconductor die 100, and the semiconductor die 206 is used to replace the semiconductor die 200, so that the inductor IND4 is formed when the semiconductor die 106 and the semiconductor die 206 are combined. Fig. 7A and Figure 7B The difference between the semiconductor package 40 and the semiconductor package 10 is that the inductor IND4 does not include a bridge portion (ie, Figure 4B 149, 249 shown in FIG. 149). That is, the coil 6030 (groove portion 164) of the winding portion 4020 directly contacts the bonding via 194, and the coil 6040 (groove portion 264) of the winding portion 4030 directly contacts the bonding via 294. In some embodiments, making the coils in the inductor directly contact the bonding metal (without inserting the bridge portion) can improve the routing ability of the metallization layer of the interconnect structure and reduce its layout area penalty. In some embodiments, the winding portion 4010 includes the groove portion 144 (coil 6010), the through hole portion 146, and the groove portion 148 (coil 6020). The winding portion 4020 includes the groove portion 164 (coil 6030) and the through hole portion 162. The winding portion 4030 includes the groove portion 264 (coil 6040) and the through hole portion 262. The winding portion 4040 includes the groove portion 248 (coil 6050), the groove portion 244 (coil 6060), and the through-hole portion 246. The bonding portion 4050 includes bonding metal (bonding pad 192, bonding through-hole 194, bonding pad 292, and bonding through-hole 294).

[0131] Fig. 8A is a schematic cross-sectional view of a semiconductor package 50 according to some alternative embodiments of the present disclosure. Figure 8B is a schematic exploded view of an inductor IND5 of a semiconductor package 50 according to some alternative embodiments of the present disclosure. Figure 8B 1 shows the conductive wires of the inductor IND5 included in the semiconductor package 50. The semiconductor package 50 and the inductor IND5 can be respectively connected to Fig. 6A and Figure 6B The semiconductor package 30 and the inductor IND3 are similar, so similar elements are marked with the same or similar reference numbers and are not repeated herein. In the semiconductor package 50, the semiconductor die 108 is used to replace the semiconductor die 104, and the semiconductor die 208 is used to replace the semiconductor die 204, so that the inductor IND5 is formed when the semiconductor die 108 and the semiconductor die 208 are combined. Fig. 8A and Figure 8BThe difference between the semiconductor package 50 and the semiconductor package 30 is that the inductor IND5 further includes the coil 6150. Another difference is that the inductor IND5 does not include a bridge portion (ie, Figure 6B That is, coil 6120 (groove portion 164) of winding portion 5020 directly contacts coupling vias 194A, 194B, while coil 6130 (groove portion 264) of winding portion 5030 directly contacts coupling vias 294A, 294B.

[0132] In some embodiments, winding portion 5010 includes groove portion 148 (coil 6110). Winding portion 5020 includes groove portion 164 (coil 6120) and through-hole portion 162. Winding portion 5030 includes groove portion 264 (coil 6130) and through-hole portion 262. Winding portion 5040 includes groove portion 248 (coil 6140), groove portion 244 (coil 6150) and through-hole portion 246. First bonding portion 5050A includes a first portion of bonding metal (bonding pad 192A, bonding through-hole 194A, bonding pad 292A and bonding through-hole 294A). Second bonding portion 5050B includes the remaining bonding metal (bonding pad 192B, bonding through-hole 194B, bonding pad 292B and bonding through-hole 294B). In some embodiments, the winding portion 5010 is directly connected to the winding portion 5020 through the through hole portion 162 at the contact area CT162. The winding portion 5020 is connected to the first combination portion 5050A at the contact area CT194A and is connected to the second combination portion 5050B at the contact area CT194B. That is, one end of the coil 6120 is connected to the first combination portion 5050A, and the other end of the coil 6120 is connected to the second combination portion 5050B. The first combination portion 5050A and the second combination portion 5050B are sandwiched between the corresponding ends of the coil 6120 and the coil 6130. The coil 6140 is connected to the coil 6130 through the through hole portion 262 at the contact area CT262. The coil 6150 is connected to the coil 6140 through the through hole portion 246 at the contact area CT246.

[0133] During operation of semiconductor package 50, current may enter inductor IND5 from one end (e.g., trench portion 244 or trench portion 148) and may travel through coils 6110 to 6150 to exit from the other end (e.g., the other of trench portion 244 and trench portion 148). For example, current may enter inductor IND5 from trench portion 148, as shown in FIG. Figure 8B, as indicated by the arrow C_In in . Then, the current may travel in a counterclockwise direction through the coil 6110 (groove portion 148) of the inductor IND5 to enter the coil 6120 (groove portion 164) through the through-hole portion 162. When entering the coil 6120, the current may be separated into a first current CR1 and a second current CR2. The first current CR1 may travel in a counterclockwise direction through the coil 6120 and may travel through the second combining portion 5050B (through the combining through-hole 194B, the combining pad 192B, the combining pad 292B, and the combining through-hole 294B in a sequential order) to reach one end of the end coil 6130 (groove portion 264), where the through-hole portion 262 is located. The second current CR2 may travel through the first combining portion 5050A (through the combining through-hole 194A, the combining pad 192A, the combining pad 292A, and the combining through-hole 294A in a sequential order) to enter the coil 6130. Thereafter, the second current CR2 travels in a counterclockwise direction through the coil 6130 to reach the same end where the first current CR1 enters the coil 6130. Subsequently, the first current CR1 and the second current CR2 may be recombined and further move toward the coil 6140 (groove portion 248), where the first current CR1 and the second current CR2 enter the coil 6140 (groove portion 248) through the through-hole portion 262. Then, the current travels in a counterclockwise direction through the coil 6140 and enters the coil 6150 (groove portion 244) through the through-hole portion 246. Finally, the current travels in a counterclockwise direction through the coil 6150 and exits the inductor IND5 at one end of the coil 6150, as shown in FIG. Figure 8B In some embodiments, by connecting the coil 6120 and the coil 6130 in parallel, the resistance of the inductor IND5 can be reduced.

[0134] According to some embodiments of the present disclosure, a semiconductor package includes a first tube die and a second tube die. The first tube die includes a first spiral segment of an inductor and a first bonding metal. The first bonding metal is connected to the first spiral segment. The second tube die is bonded to the first tube die. The second tube die includes a second spiral segment of the inductor and a second bonding metal. The second bonding metal is connected to the second spiral segment. The inductor extends from the first tube die to the second tube die.

[0135] In some embodiments, the first bonding metal includes an inductor bonding via and an inductor bonding pad disposed on the inductor bonding via.

[0136] In some embodiments, the first helical segment includes a first coil and a second coil located at different levels, and the first coil and the second coil are made of different materials.

[0137] In some embodiments, the first spiral segment further includes a groove portion located at the same level as the first coil, and the first coil is connected to the first bonding metal through the second coil and the groove portion.

[0138] In some embodiments, the second coil is connected to the first bonding metal.

[0139] In some embodiments, the second spiral segment includes a third coil and a fourth coil located at different levels, and the first coil, the second coil, the third coil, and the fourth coil are electrically connected together.

[0140] In some embodiments, the first tube core also includes a third bonding metal connected to the first spiral segment, the second tube core also includes a fourth bonding metal connected to the second spiral segment, and the second coil and the third coil are electrically connected in parallel through the first bonding metal and the second bonding metal and through the third bonding metal and the fourth bonding metal.

[0141] In some embodiments, the second coil is connected to the first bonding metal and the third bonding metal, the third coil is connected to the second bonding metal and the fourth bonding metal, the first bonding metal is connected to the second bonding metal, and the third bonding metal is physically connected to the fourth bonding metal.

[0142] According to some embodiments of the present disclosure, a semiconductor package includes a first tube core, a second tube core and an inductor. The first tube core includes a first semiconductor substrate, a first interconnection structure and a first combination structure. The first interconnection structure is arranged on the first semiconductor substrate. The first combination structure is arranged on the first interconnection structure. The second tube core includes a second semiconductor substrate, a second interconnection structure and a second combination structure. The second interconnection structure is arranged on the second semiconductor substrate. The second combination structure is arranged on the second interconnection structure. The first combination structure physically contacts the second combination structure. The inductor includes a first winding part, a second winding part, a third winding part and a fourth winding part connected to each other. The first winding part is embedded in the first interconnection structure, the second winding part is embedded in the first combination structure, the third winding part is embedded in the second combination structure, and the fourth winding part is embedded in the second interconnection structure.

[0143] In some embodiments, the inductor further includes a first coupling portion connected to the first winding portion.

[0144] In some embodiments, the first winding portion includes a coil and a groove portion, and the first coupling portion directly contacts the groove portion.

[0145] In some embodiments, the inductor further includes a first coupling portion connected to the second winding portion.

[0146] In some embodiments, the inductor further includes a first combining portion and a second combining portion sandwiched between the first interconnect structure and the second interconnect structure, wherein the second winding portion and the third winding portion are electrically connected via the first combining portion and the second combining portion.

[0147] In some embodiments, the material of the second winding portion is different from the material of the first winding portion.

[0148] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor package includes at least the following steps. A first tube core is provided. Providing the first tube core includes at least the following steps. A first semiconductor substrate is provided, on which a first interconnect structure is formed. A first coil of an inductor is formed in the first interconnect structure. A second coil of the inductor is formed on the first interconnect structure. The second coil is electrically connected to the first coil. A first inductor bonding via and a first inductor bonding pad are formed on the first interconnect structure. The first inductor bonding via and the first inductor bonding pad are electrically connected to the first coil and the second coil. A second tube core is provided. The second tube core has a third coil of the inductor, a second inductor bonding via and a second inductor bonding pad. The second inductor bonding via and the second inductor bonding pad are connected to the third coil. The first inductor bonding pad is bonded to the second inductor bonding pad to form the inductor.

[0149] In some embodiments, providing the second tube core includes: providing a second semiconductor substrate, on which a second internal connection structure is formed; forming the third coil of the inductor on the second internal connection structure; and forming the second inductor bonding via and the second inductor bonding pad on the second internal connection structure.

[0150] In some embodiments, forming the first inductor bonding via and the first inductor bonding pad includes: forming a dielectric material layer on the first interconnect structure to cover the second coil; removing a portion of the dielectric material layer to form a groove opening and a via opening connected to the groove opening, wherein the groove opening and the via opening expose at least a portion of the first interconnect structure; and filling the groove opening and the via opening with a conductive material.

[0151] In some embodiments, forming the first inductor bonding via and the first inductor bonding pad includes: forming a dielectric material layer on the first interconnect structure to cover the second coil; removing a portion of the dielectric material layer to form a groove opening and a via opening connected to the groove opening, wherein the groove opening and the via opening expose at least a portion of the second coil; and filling the groove opening and the via opening with a conductive material.

[0152] In some embodiments, the first coil and the second coil are formed of different materials.

[0153] In some embodiments, the method for manufacturing the semiconductor package further includes forming a conductive pad on the first interconnect structure, wherein the conductive pad and the second coil are formed simultaneously.

[0154] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, comprising: A first die including a first spiral segment of an inductor and a first bonding metal, wherein the first bonding metal is connected to the first spiral segment, wherein the first spiral segment includes a first coil and a second coil at different levels, and the first coil and the second coil are made of different materials; and A second die, bonded to the first die, includes a second spiral segment of the inductor and a second bonding metal, wherein the second bonding metal is connected to the second spiral segment, and the inductor extends from the first die to the second die. 2 . The semiconductor package according to claim 1 , wherein the first bonding metal comprises an inductor bonding via and an inductor bonding pad disposed on the inductor bonding via. 3 . The semiconductor package according to claim 1 , wherein the first spiral segment further comprises a groove portion located at the same level as the first coil, and the first coil is connected to the first bonding metal through the second coil and the groove portion. The semiconductor package according to claim 1 , wherein the second coil is connected to the first bonding metal. 5 . The semiconductor package according to claim 1 , wherein the second spiral section comprises a third coil and a fourth coil located at different levels, and the first coil, the second coil, the third coil and the fourth coil are electrically connected together.

6. The semiconductor package of claim 5 , wherein the first die further comprises a third bonding metal connected to the first spiral segment, the second die further comprises a fourth bonding metal connected to the second spiral segment, and the second coil and the third coil are electrically connected in parallel through the first bonding metal and the second bonding metal and through the third bonding metal and the fourth bonding metal.

7. The semiconductor package according to claim 6, wherein the second coil is connected to the first bonding metal and the third bonding metal, the third coil is connected to the second bonding metal and the fourth bonding metal, the first bonding metal is connected to the second bonding metal, and the third bonding metal is physically connected to the fourth bonding metal.

8. A semiconductor package, comprising: The first die comprises: a first semiconductor substrate; A first interconnect structure is disposed on the first semiconductor substrate; and A first combining structure, disposed on the first inner connecting structure; The second die comprises: a second semiconductor substrate; A second interconnect structure is disposed on the second semiconductor substrate; and a second bonding structure disposed on the second interconnecting structure, wherein the first bonding structure physically contacts the second bonding structure; and An inductor comprises a first winding portion, a second winding portion, a third winding portion and a fourth winding portion connected to each other, wherein the first winding portion is embedded in the first interconnected structure, the second winding portion is embedded in the first combined structure, the third winding portion is embedded in the second combined structure, and the fourth winding portion is embedded in the second interconnected structure, wherein a material of the second winding portion is different from a material of the first winding portion. 9 . The semiconductor package of claim 8 , wherein the inductor further comprises a first bonding portion connected to the first winding portion. 10 . The semiconductor package according to claim 9 , wherein the first winding portion includes a coil and a groove portion, and the first coupling portion directly contacts the groove portion. 11 . The semiconductor package of claim 9 , wherein the inductor further comprises a first bonding portion connected to the second winding portion.

12. The semiconductor package according to claim 9, wherein the inductor further comprises a first coupling portion and a second coupling portion sandwiched between the first interconnect structure and the second interconnect structure, wherein the second winding portion and the third winding portion are electrically connected via the first coupling portion and the second coupling portion.

13. A method for manufacturing a semiconductor package, comprising: A first die is provided, comprising: Providing a first semiconductor substrate, on which a first interconnect structure is formed, wherein a first coil of an inductor is formed in the first interconnect structure; forming a second coil and a conductive pad of the inductor on the first interconnect structure, the second coil being electrically connected to the first coil, wherein the conductive pad and the second coil are formed simultaneously; and forming a first inductor bonding via and a first inductor bonding pad on the first interconnect structure, wherein the first inductor bonding via and the first inductor bonding pad are electrically connected to the first coil and the second coil; providing a second die having a third coil of the inductor, a second inductor bonding via, and a second inductor bonding pad, wherein the second inductor bonding via and the second inductor bonding pad are connected to the third coil; and The inductor is formed by bonding the first inductor bonding pad to the second inductor bonding pad.

14. The method for manufacturing a semiconductor package according to claim 13, wherein providing the second die comprises: Providing a second semiconductor substrate, on which a second interconnect structure is formed; forming the third coil of the inductor on the second interconnect structure; as well as The second inductor bonding via and the second inductor bonding pad are formed on the second interconnect structure.

15. The method for manufacturing a semiconductor package according to claim 13, wherein forming the first inductor bonding via and the first inductor bonding pad comprises: forming a dielectric material layer on the first interconnect structure to cover the second coil; removing a portion of the dielectric material layer to form a trench opening and a through-hole opening communicating with the trench opening, wherein the trench opening and the through-hole opening expose at least a portion of the first interconnect structure; as well as The trench opening and the via opening are filled with a conductive material.

16. The method for manufacturing a semiconductor package according to claim 13, wherein forming the first inductor bonding via and the first inductor bonding pad comprises: forming a dielectric material layer on the first interconnect structure to cover the second coil; removing a portion of the dielectric material layer to form a groove opening and a through-hole opening communicating with the groove opening, wherein the groove opening and the through-hole opening expose at least a portion of the second coil; as well as The trench opening and the via opening are filled with a conductive material. 17 . The method for manufacturing a semiconductor package according to claim 13 , wherein the first coil and the second coil are formed of different materials.

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