Optical collimator, semiconductor device and method for forming the same

Abstract

The present application discloses an optical collimator, a semiconductor device and a method for forming the same, which is economical and manufactures a multifunctional collimator structure for a contact image sensor to filter ambient infrared light to reduce noise. In one embodiment, the optical collimator includes a dielectric layer; a substrate; a plurality of through holes; and a conductive layer, wherein the dielectric layer is formed above the substrate, wherein the plurality of through holes are configured as an array extending in a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of through holes extends in a vertical direction from the first surface of the dielectric layer through the dielectric layer and the substrate to the second surface of the substrate, and wherein the conductive layer is formed above at least one of the first surface of the dielectric layer and a portion of a sidewall of each of the plurality of through holes, and wherein the conductive layer is configured to allow the optical collimator to filter light of a wavelength range.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor technology, and more particularly to an optical collimator, a semiconductor device and a method for forming the same. Background Art

[0002] In order to prevent noise from ambient infrared (IR) sources, contact image sensors (CIS) (e.g., fingerprint sensors) typically use glass filters. Glass filters in such applications are typically thick (e.g., 400-500 μm) to provide effective filtering of ambient IR noise, especially at large incident angles (>15°). This results in bulky components and high costs. There is a need to develop cost-effective methods to filter ambient IR light to reduce noise in contact image sensors. Summary of the invention

[0003] In some embodiments, an optical collimator is provided, the optical collimator comprising a dielectric layer; a substrate; a plurality of through holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of through holes are configured as an array extending in a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of through holes extends in a vertical direction from the first surface of the dielectric layer through the dielectric layer and the substrate to a second surface of the substrate, and wherein the conductive layer is formed over at least one of the first surface of the dielectric layer and a portion of a sidewall of each of the plurality of through holes, and wherein the conductive layer is configured to allow the optical collimator to filter a range of wavelengths of light.

[0004] In some other embodiments, a semiconductor device is provided, the semiconductor device including at least one optical sensing element; and an optical collimator; wherein the optical collimator includes: a first dielectric layer, a first substrate, a plurality of through holes, and a conductive layer, wherein the first dielectric layer is formed above the first substrate, wherein the plurality of through holes are configured as an array extending in a lateral direction of a first surface of the first dielectric layer, wherein each of the plurality of through holes extends in a vertical direction from the first surface of the first dielectric layer through the first dielectric layer and the first substrate to a second surface of the first substrate, wherein the conductive layer is formed above at least one of the first surface of the first dielectric layer and a portion of a sidewall of each of the plurality of through holes, and wherein the conductive layer is configured to allow the optical collimator to filter light of a wavelength range.

[0005] In some other embodiments, a method for forming a semiconductor device is provided, the method comprising forming a collimator structure on a first substrate having a first dielectric layer, wherein the collimator structure comprises a plurality of through holes, wherein each of the plurality of through holes extends in a vertical direction from a first surface of a second dielectric layer through the second dielectric layer and the second substrate to a second surface of the second substrate; and forming a conductive layer over at least one of the first surface of the second dielectric layer and a portion of a sidewall of each of the plurality of through holes of the collimator structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The embodiments of the present invention can be better understood according to the following detailed description and in conjunction with the drawings of the specification. It should be noted that, according to standard practice in the industry, the various features shown in the figures are not necessarily drawn to scale. In fact, the sizes of various features may be arbitrarily enlarged or reduced to make clear descriptions. It should also be emphasized that the drawings only show typical embodiments of the present invention and therefore should not be regarded as limiting the scope. The present invention can be equally applied to other embodiments.

[0007] Figure 1 A flow chart is shown of an exemplary method of forming a semiconductor device according to some embodiments of the present invention.

[0008] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G and Figure 2H According to some embodiments of the present invention, Figure 1 Schematic cross-sectional views of an exemplary semiconductor device with a collimator during various stages of fabrication in accordance with a method of manufacturing the semiconductor device.

[0009] Figure 3 An exemplary cross-sectional view of a semiconductor device having a collimator according to some embodiments of the present invention is shown.

[0010] Figure 4 Illustrative cross-sectional diagrams showing sidewall profiles of etched openings in a collimator structure according to some embodiments of the present invention.

[0011] Figure 5A An exemplary top view of a semiconductor device with a collimator according to some embodiments of the present invention is shown.

[0012] Figure 5B An exemplary top view of a semiconductor device with a collimator according to some embodiments of the present invention is shown.

[0013] Description of reference numerals:

[0014] 100: Methods

[0015] 102,104,106,108,110,112,114,116,118,120,122: Operation

[0016] 200, 300, 500: Semiconductor devices

[0017] 202: First Base

[0018] 204: First dielectric layer

[0019] 206: Second base

[0020] 208: Second dielectric layer

[0021] 210: Patterned photoresist layer

[0022] 212: Opening

[0023] 214: Conductive parts

[0024] 216: Through hole

[0025] 218: Top surface

[0026] 220: Sidewall

[0027] 220A: Partial

[0028] 222: Sacrificial layer

[0029] 224: Conductive layer

[0030] 302,304,306: Thickness

[0031] 308: Spacing size

[0032] 312: First thickness

[0033] 314: Second thickness

[0034] 318: First width

[0035] 320: Second width

[0036] 400: Sidewall profile

[0037] 402: First Profile

[0038] 404: Second Profile

[0039] 406: The Third Profile

[0040] 408: The Fourth Profile

[0041] 410: The Fifth Profile

[0042] 412: Sixth Profile

[0043] 414: The Seventh Profile

[0044] 416: The Eighth Profile

[0045] 418: Ripple

[0046] 420: Scratches

[0047] 422: Corner

[0048] 424: Undercut

[0049] 502: Square unit

[0050] 504: Diamond Unit DETAILED DESCRIPTION

[0051] It will be appreciated that the following disclosure provides many different embodiments or examples to implement the different components of the subject provided. Specific examples of the various components and their arrangements are described below to simplify the description of the disclosure. Of course, these are merely examples and are not intended to limit the present invention. For example, it will be understood that when an element is described as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or one or more intermediate elements may be present.

[0052] Thick infrared glass can be used to filter the unwanted ambient noise of the contact image sensor. This design results in a bulky structure and increases the cost of such a contact image sensor. The present invention presents various embodiments of methods that integrate the filtering function into the collimator to simultaneously collimate the incident light and filter the ambient noise in a compact design and at low cost.

[0053] Figure 1 A flowchart of a method 100 for forming a multifunctional collimator structure on a semiconductor device according to some embodiments of the present invention is shown. It should be noted that the method 100 is merely an example and is not intended to limit the embodiments of the present invention. Figure 1 Additional operations are provided before, during, and after method 100, and only some other operations are briefly described herein. In some embodiments, the operations of method 100 may be different from those of Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G and Figure 2H The illustrated cross-sectional schematic views of a semiconductor device at various fabrication stages are associated with this disclosure, which will be discussed in further detail below.

[0054] According to some embodiments, please refer to Figure 1, method 100 begins at operation 102, wherein a first substrate is provided. In some embodiments, the first substrate includes at least one optical sensing element. According to some embodiments, method 100 continues to operation 104, wherein a first dielectric layer is deposited on a surface of the first substrate. In some embodiments, the first dielectric layer includes silicon oxide for planarizing a complementary metal-oxide semiconductor (CMOS) back-end surface profile and forming a silicon-to-oxide molten bonding surface. According to some embodiments, method 100 continues to operation 106, wherein a second substrate is bonded over the first dielectric layer on the first substrate. In some embodiments, the second substrate is bonded to the first dielectric layer by a wafer bonding process. In some embodiments, the second substrate is a silicon substrate. According to some embodiments, method 100 continues to operation 108, wherein the second substrate is thinned. In some embodiments, the thinned second substrate has a thickness of 75 μm. According to some embodiments, method 100 continues to operation 110, wherein a second dielectric layer is deposited on a first surface of the second substrate. In some embodiments, the second dielectric layer includes silicon oxide. According to some embodiments, method 100 continues to operation 112 where a photoresist layer is patterned on the second dielectric layer. In some embodiments, the patterned photoresist layer provides a pattern of collimator structures.

[0055] According to some embodiments, method 100 continues to operation 114, wherein a plurality of through holes are formed through the second dielectric layer and the thinned second substrate. In some embodiments, the second dielectric layer is etched using the patterned first photoresist layer as a soft mask, and then the thinned second substrate is etched using the patterned second dielectric layer as a hard mask to form a plurality of through holes. According to some embodiments, method 100 continues to operation 116, wherein at least one conductive component is formed in the first dielectric layer. In some embodiments, the at least one conductive component provides electrical contact with at least one optical sensing element in the first substrate. According to some embodiments, method 100 continues to operation 118, wherein a sacrificial layer (sometimes also referred to as a second photoresist layer) is formed in the plurality of through holes to expose a first surface of the second dielectric layer and a portion of the sidewalls in the plurality of through holes. In some embodiments, the sacrificial layer is applied and etched to expose a portion of the collimator structure. According to some embodiments, method 100 continues to operation 120, wherein at least one conductive layer is deposited. In some embodiments, each of the at least one conductive layer includes a metal layer. According to some embodiments, method 100 continues to operation 122, wherein a portion of the sacrificial layer and at least one conductive layer in contact with the sacrificial layer is removed. In some embodiments, a chemical etching process is performed to remove the sacrificial layer and a portion of the at least one conductive layer in direct contact with the sacrificial layer. In some embodiments, the semiconductor having the collimator structure is wafer cut to form a plurality of dies. In some embodiments, each of the plurality of dies is then wafer bonded to a third substrate and further wire bonded. In some embodiments, each of the plurality of dies is embedded in a molding and packaged.

[0056] As mentioned above, Figure 2A-2H show Figure 1 1 is a schematic cross-sectional view of a portion of a semiconductor device 200 at various stages of manufacturing of the method. The semiconductor device 200 may be included in an integrated circuit (IC). Figure 2A-2H Although the figures show semiconductor device 200, it is understood that the integrated circuit may include many other devices, such as resistors, capacitors, inductors, fuses, etc. For the sake of clarity, Figure 2A-2H Other devices are not shown.

[0057] Figure 2A is one of the various manufacturing stages according to some embodiments of the present invention, corresponding to Figure 1102 and 104, a cross-sectional schematic diagram of a semiconductor device 200 including a first substrate 202 and a first dielectric layer 204. In some embodiments, the first substrate 202 includes at least one optical sensing element (not shown). In some embodiments, each of the at least one optical sensing element is a contact image sensor (CIS). In some embodiments, a contact image sensor is an image sensor that is in direct contact with an object to be imaged or scanned. In some embodiments, the contact image sensor includes a plurality of detectors. In some embodiments, the plurality of detectors detect light emitted from a surface of an object. In some embodiments, each of the plurality of detectors includes one of the following: a charge coupled device (CCD) sensor and a complementary metal oxide semiconductor (CMOS) sensor.

[0058] In some embodiments, the first substrate 202 is a silicon substrate. Alternatively, the first substrate 202 may include other elemental semiconductor materials, such as germanium. The first substrate 202 may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The first substrate 202 may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the first substrate 202 includes an epitaxial layer. For example, the first substrate 202 may have an epitaxial layer covering a bulk semiconductor. Furthermore, the first substrate 202 may include a semiconductor-on-insulator (SOI) structure. For example, the first substrate 202 may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding.

[0059] In some embodiments, the first substrate 202 also includes various p-type doped regions and / or n-type doped regions implemented by, for example, ion implantation and / or diffusion. These doped regions include n-type wells, p-type wells, lightly doped drains (LDDs), heavily doped sources and drains (S / Ds), and various channel doping profiles configured to form various integrated circuit (IC) devices, such as complementary metal oxide semiconductor field-effect transistors (CMOS field-effect transistors, CMOS-FETs), image sensors, and / or light emitting diodes (LEDs). The first substrate 202 may also include other functional components, such as resistors or capacitors formed in or on the substrate. The first substrate 202 also includes lateral isolation components configured to separate various components formed in the first substrate 202, such as shallow trench isolation (STI). The various components in the first substrate 202 also include silicides, gates, and other component components disposed on the source and drain to reduce contact resistance and enhance process compatibility when coupling between devices through local interconnects.

[0060] In some embodiments, the first substrate 202 includes at least one conductive component. In some embodiments, the at least one conductive component may be a source, drain, or gate electrode. Alternatively, the at least one conductive component may be a silicide component, which is typically disposed on the source, drain, or gate electrode by a sintering process that includes at least one of thermal heating, laser irradiation, or ion beam mixing. The silicide component may be formed on a polysilicon gate (commonly referred to as a "polycide gate") or on a source / drain (commonly referred to as a "silicide") by self-aligned silicide technology. In another embodiment, the at least one conductive component may include an electrode of a capacitor or one end of a resistor. In another embodiment, the at least one conductive component is a contact connected to a contact image sensor in the first substrate 202.

[0061] In some embodiments, the first dielectric layer 204 includes one of the following materials: silicon dioxide, a low-k material, other suitable dielectric materials, or a combination thereof. The low-k material may include fluorinated silica glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO x Cy ), black diamond (trademarked by Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), SiLK (trademarked by Dow Chemical, Midland, Michigan), polyimide, and / or other low-k dielectric materials to be developed in the future. In some embodiments, the first dielectric layer 204 is deposited using plasma enhanced chemical vapor deposition (PECVD) using silane gas as a precursor gas. In some other embodiments, the first dielectric layer 204 is deposited using a physical vapor deposition (PVD) process.

[0062] Figure 2B is one of the various manufacturing stages according to some embodiments of the present invention, corresponding to Figure 1 Operation 106 of the present invention is a schematic cross-sectional view of a semiconductor device 200 including a first substrate 202, a first dielectric layer 204, and a second substrate 206. In some embodiments, the second substrate 206 includes a silicon substrate. Alternatively, the second substrate 206 may include other elemental semiconductor materials, such as germanium, depending on the optical properties of the material. The second substrate 206 may also include a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The second substrate 206 may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the second substrate 206 includes an epitaxial layer. For example, the second substrate 206 may have an epitaxial layer covering a bulk semiconductor. Furthermore, the second substrate 206 may include a semiconductor on an insulator (SOI) structure. For example, the second substrate 206 may include a buried oxide (BOX) layer formed by a process such as separation by implantation of oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding.

[0063] In some embodiments, the second substrate 206 is bonded to the first dielectric layer 204 by a wafer bonding process. In some embodiments, the wafer bonding process is a direct bonding without any additional intermediate layer. In some embodiments, the wafer bonding process includes at least one of the following steps: surface pretreatment, pre-bonding at room temperature, and annealing at high temperature. In another embodiment, surface activation can be used to avoid high temperature annealing.

[0064] Figure 2C is one of the various manufacturing stages according to some embodiments of the present invention, corresponding to Figure 1Operations 108 and 110 of the present invention are a schematic cross-sectional view of a semiconductor device 200 including a second dielectric layer 208 over a thinned second substrate 206. In some embodiments, after the second substrate 206 is bonded to the first dielectric layer 204 on the first substrate 202, the second substrate 206 is further thinned to obtain a desired thickness. In some embodiments, the second substrate 206 is etched by dry etching and / or wet etching. In some embodiments, the etched second substrate 206 has a thickness of 75 μm. In some embodiments, the second dielectric layer 208 is deposited on the etched second substrate 206. In some embodiments, the second dielectric layer 208 includes a material selected from the group consisting of silicon dioxide, a low dielectric constant (low-k) material, other suitable dielectric materials, or a combination thereof. The low dielectric constant material may include fluorinated quartz glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO x C y ), black diamond (registered by Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), SiLK (registered by Dow Chemical, Midland, Michigan), polyimide and / or other low dielectric constant dielectric materials developed in the future. In some embodiments, the second dielectric layer 208 is deposited using plasma-assisted chemical vapor deposition (PECVD) using silane gas as a precursor gas. In some other embodiments, the second dielectric layer 208 is deposited using a physical deposition process (e.g., sputtering or evaporation). In some embodiments, the second dielectric layer 208 is deposited using an atomic layer deposition (ALD) process. In some embodiments, the second dielectric layer 208 has a thickness of at least 3 μm. In some embodiments, before depositing the second dielectric layer 208 , the surface of the second substrate 206 that is not in direct contact with the first dielectric layer 204 is further planarized by chemical-mechanical polishing (CMP) after being etched.

[0065] Figure 2D is one of the various manufacturing stages according to some embodiments of the present invention, corresponding to Figure 1FIG. 1 is a cross-sectional view of a semiconductor device 200 according to operation 112, wherein a photoresist layer is patterned on the second dielectric layer 208. As described below, the patterned photoresist layer 210 is used as a mask for etching the second dielectric layer 208 and the thinned second substrate 206 to form a plurality of through holes (i.e., collimator structures) on top of the first dielectric layer 204 on the first substrate 202. Thus, in some embodiments, the patterned photoresist layer 210 is formed after a conventional patterning (e.g., photolithography) process to align the collimator structures to at least one optical sensing element in the first substrate 202.

[0066] In some embodiments, the initial photoresist layer prior to the patterning process may include a negative or positive photoresist layer that is patterned in response to a light lithography light source. In some other embodiments, the initial photoresist layer may include an electron beam (e-beam) photoresist layer (e.g., polymethyl methacrylate, methyl methacrylate, etc.) that can be patterned in response to an electron beam lithography energy source. In some embodiments, the initial photoresist layer is formed over the second dielectric layer 208 by using a deposition process known in the art (e.g., spin coating, spray coating, dip coating, roller coating, or the like). Next, the initial photoresist is patterned in a lithography process that may involve various exposure, development, baking, stripping, etching, and cleaning processes. Thus, a patterned photoresist layer 210 is formed so that a plurality of openings 212 expose at least a portion of the top surface of the second dielectric layer 208, such as Figure 2D In some embodiments, the plurality of openings 212 in the patterned photoresist layer 210 are circular and have a diameter of 4 μm. In some embodiments, the diameter of the plurality of openings 212 is in the range of 1-3 μm, and in some embodiments, the diameter is 2 μm.

[0067] Figure 2E is one of the various manufacturing stages according to some embodiments of the present invention, corresponding to Figure 1 FIG. 2 is a cross-sectional view of a semiconductor device 200 of operations 114 and 116, wherein a plurality of through holes 216 are formed in the second dielectric layer 208 and the etched second substrate 206, the patterned photoresist layer 210 is removed, and at least one conductive feature 214 is formed in the first dielectric layer 204. In some embodiments, the second dielectric layer 208 is first etched to transfer the pattern of the patterned photoresist layer 210 having the plurality of openings 212 to the second dielectric layer 208. In some embodiments, the patterned second dielectric layer 208 is then further etched to transfer the pattern in the second dielectric layer 208 to the thinned second substrate 206. In some embodiments, the etching of the second dielectric layer 208 and the second substrate 206 is performed by a dry etching process and / or a wet etching process.

[0068] In some embodiments, the patterned photoresist layer 210 is removed before etching the second substrate 206. In some embodiments, the patterned photoresist layer 210 can be removed by one or more chemical cleaning processes using acetone, N-methylpyrrolidone (1-Methyl-2-pyrrolidone, NMP), dimethyl sulfoxide (Dimethyl sulfoxide, DMSO) or other suitable removal chemicals. In some embodiments, it may be necessary to heat the chemicals used to a temperature above room temperature to effectively dissolve the patterned photoresist layer 210. The choice of remover depends on the type and chemical structure of the patterned photoresist layer 210, the second dielectric layer 208 and the second substrate 206 to ensure the chemical compatibility of these layers with the chemical cleaning process. In some embodiments, the cleaning process is followed by washing with isopropyl alcohol or the like, followed by washing with deionized water. As a result of this process, a plurality of through holes 216 (i.e., collimator structures) are formed through the second dielectric layer 208 and the second substrate 206. In some embodiments, the collimator structure includes a top surface 218 and a sidewall 220 of the second dielectric layer 208.

[0069] In some embodiments, at least one conductive component 214 is formed in the first dielectric layer 204 to provide electrical contact with at least one optical sensing element in the first substrate 202. In some embodiments, the conductive component 214 is formed by a respective conventional patterning (e.g., photolithography) process involving various exposure, development, baking, stripping, etching, and cleaning processes. In some embodiments, the conductive component 214 is formed by depositing a conductive material on a respective patterned photoresist layer using chemical vapor deposition, physical vapor deposition, spin coating, and / or other suitable techniques, followed by wet etching of the photoresist layer. Thus, at least one conductive component 214 is formed in the first dielectric layer 204.

[0070] Figure 2F is one of the various manufacturing stages according to some embodiments of the present invention, corresponding to Figure 11 is a cross-sectional schematic diagram of a semiconductor device 200 according to operation 118, wherein a sacrificial layer 222 is formed in a plurality of through holes 216 and a portion of a collimator structure is exposed. In some embodiments, the sacrificial layer 222 is a photoresist layer, which can be formed by filling the collimator structure with photoresist. In some embodiments, the sacrificial layer 222 can be partially removed in a selective dry etching process, and the dry etching process etches the second dielectric layer 208 and the second substrate 206 to a negligible extent. Therefore, a portion of the collimator structure can be exposed from its top surface. In particular, the top surface 218 of the second dielectric layer 208 and a portion (220A) of the sidewall 220 of the plurality of through holes 216 are exposed. In some embodiments, the depth of the exposed portion 220A of the sidewall 220 is less than the thickness of the second dielectric layer 208. In some other embodiments, the depth of the exposed portion 220A of the sidewall 220 is greater than the thickness of the second dielectric layer 208.

[0071] Figure 2G is one of the various manufacturing stages according to some embodiments of the present invention, corresponding to Figure 1120 , wherein a conductive layer 224 is deposited. In some embodiments, the conductive layer 224 is deposited using a physical vapor deposition process (e.g., sputtering or evaporation). In some embodiments, the conductive layer 224 includes a plurality of conductive layers stacked in a layer-by-layer form. In some embodiments, the conductive layer 224 directly contacts the top surface 218 of the collimator structure and a portion 220A of the sidewall 220. In some embodiments, the conductive layer 224 is also deposited on the surface of the sacrificial layer 222. In some embodiments, the conductive layer 224 includes an aluminum-copper (AlCu) alloy. In some embodiments, the aluminum / copper ratio is in the range of 190-210, and in some embodiments, the aluminum / copper ratio is 199. In some embodiments, the aluminum / copper ratio is controlled by the composition of the target material. In some other embodiments, the aluminum / copper ratio depends on the deposition rate of the two individual target materials. In some embodiments, the thickness of the conductive layer 224 on the surface of the sacrificial layer 222 and the top surface 218 of the collimator structure is 900 nm. In some other embodiments, the thickness of the conductive layer 224 on the surface of the sacrificial layer 222 and the top surface 218 of the collimator structure is 8-12 μm, and in some embodiments, the thickness is 10 μm. In some embodiments, the thickness of the conductive layer 224 on the portion 220A of the sidewall 220 of the collimator structure is different from the thickness of the conductive layer 224 on the top surface 218 of the collimator structure due to different deposition rates on different surfaces. In some other embodiments, a compliant coating of the conductive layer 224 can be used to obtain a comparable thickness of the conductive layer on the top surface 218 and the portion 220A of the sidewall 220. In some embodiments, other metal materials or alloys can be used for the conductive layer 224 depending on the operating conditions required for the contact image sensor (e.g., the wavelength range to be filtered by the collimator structure) and the optical properties of the material, all of which are within the scope of the embodiments of the present invention.

[0072] Figure 2H is one of the various manufacturing stages according to some embodiments of the present invention, corresponding to Figure 1122 is a cross-sectional schematic diagram of a semiconductor device 200 of operation 122, wherein a collimator structure is formed. In some embodiments, the sacrificial layer 222 is removed by one or more chemical cleaning processes using suitable chemicals. For example, when the sacrificial layer 222 is a photoresist layer, the sacrificial layer 222 can be removed by acetone, N-methylpyrrolidone (NMP) and dimethyl sulfoxide (DMSO). In some embodiments, it may be necessary to heat the chemicals used to a temperature higher than room temperature to effectively dissolve the sacrificial layer 222. The choice of remover depends on the type and chemical structure of the conductive layer 224, the second dielectric layer 208, and the second substrate 206 to ensure the chemical compatibility of these layers with the chemical cleaning process. In some embodiments, the cleaning process is followed by a cleaning process using isopropyl alcohol or the like, followed by cleaning with deionized water. Therefore, the portion of the conductive layer 224 that is in direct contact with the sacrificial layer 222 is removed.

[0073] In some embodiments, when light reaches at least one optical sensing element in the first substrate, the collimator structure narrows the incident light and allows the incident light to be aligned in a specific direction. Furthermore, the collimator structure with the conductive layer 224 is more capable of filtering unwanted surrounding noise and preventing such noise from reaching the at least one optical sensing element. Therefore, the conductive layer coated collimator structure in the embodiments of the present invention provides multiple functions, enabling the use of ordinary glass during packaging, thereby reducing costs, and further enabling the use of contact image sensor devices in limited space applications.

[0074] Figure 3 An exemplary cross-sectional view of a semiconductor device 300 having a collimator structure according to some embodiments of the present invention is shown. Figure 1 The method 100 described herein fabricates a collimator structure. Specifically, the semiconductor device 300 includes a first substrate 202, a first dielectric layer 204, a plurality of vias 216 in a second substrate 206 and a second dielectric layer 208, and a conductive layer 224. In the embodiment shown, the conductive layer 224 is deposited on a top surface 218 of the second dielectric layer 208 and a portion 220A of a sidewall 220 of the plurality of vias 216.

[0075] In some embodiments, the patterned second dielectric layer 208 has a thickness 302 in the range of 0.8-1.2 μm, and in some embodiments, the thickness 302 is 1.0 μm. In some embodiments, the patterned second substrate 206 has a thickness 304 in the range of 4-8 μm, and in some embodiments, the thickness 304 is 6 μm. In some embodiments, the patterned second dielectric layer 208 has a thickness 306 in the range of 0.8-1.2 μm, and in some embodiments, the thickness 302 is 1.0 μm.

[0076] In some embodiments, the pitch dimension 308 is in the range of 0.5-1.0 μm, and in some embodiments, the pitch dimension 308 is 0.8 μm. In some embodiments, the diameter of the through hole 216 is in the range of 0.03-0.08 μm before the conductive layer 224 is deposited, and in some embodiments, the diameter of the through hole 216 is 0.05 μm. In some embodiments, the first thickness 312 of the conductive layer 224 along the y-direction on the top surface 218 is in the range of 180-220 nm, and in some embodiments, the first thickness 312 is 200 nm. In some embodiments, the second thickness 314 of the conductive layer 224 along the x-direction on the portion 220A of the sidewall 220 of the collimator structure is 15-25 nm, and in some embodiments, the second thickness 314 is 20 nm. In some embodiments, the conductive layer 224 is deposited on the sidewall of the second substrate 206 with a thickness of 2500-3500 nm, and in some embodiments, this thickness is 3000 nm.

[0077] In the illustrated embodiment, the sidewalls 220 of the plurality of through holes 216 etched into the second dielectric layer 208 and the second substrate 206 are perpendicular to the exposed surface of the first dielectric layer 204. The profile obtained under ideal etching conditions with ideal sidewall protection in the semiconductor device 300 is for illustrative purposes and is not intended to be limiting. Actual etching conditions (i.e., etching rates in different directions) may result in, for example, tapers, undercuts, notches, bows, ripples, etc., which change the sidewall profile of the through holes 216. It should be noted that different sidewall profiles that may be obtained from actual etching conditions are within the scope of the embodiments of the present invention.

[0078] Figure 4 Various sidewall profiles 400 of etched vias in the second dielectric layer 208 and the second substrate 206 are shown in accordance with some embodiments of the present invention. The various sidewall profiles 400 include a first profile 402 with vertical sidewalls 220 under ideal etching conditions, a second profile 404 with tapered sidewalls 220 and a complete undercut 424 under the second dielectric layer 208 caused by strong sidewall protection, a third profile 406 with tapered sidewalls 220 and a partial undercut 424 under the second dielectric layer 208 caused by a spontaneous etching reaction, a fourth profile 408 with sidewalls 220 including ripples 418, a fifth profile 410 with smoothly curved sidewalls 220, a sixth profile 412 with tapered sidewalls 220 and notches 420 at the bottom of the via caused by distorted ion trajectories and / or chemical etching, a seventh profile 414 with reverse tapered sidewalls 220, and an eighth profile 416 with tapered sidewalls 220 and eroded corners 422 in the second dielectric layer 208. It should be noted that Figure 4 The sidewall profiles in FIG. 1 are for illustrative purposes only and are not intended to be limiting. Different sidewall profiles that may be obtained from various etching conditions are within the scope of embodiments of the present invention.

[0079] Please refer again Figure 3 In the embodiment shown, the conductive layer 224 has a cotton swab-shaped cross-sectional profile, wherein the cotton swab-shaped cross-sectional profile is caused by the directionality of the deposition technique used for the conductive layer 224. For example, Figure 3 As shown, a first width 318 between two adjacent surfaces of the conductive layer 224 is less than a second width 320 between two adjacent surfaces of the conductive layer 224. For example, sputtering deposition is directional, resulting in a primary deposition on surfaces facing the direction of the ion flux from the sputtering target. In another example, for directional techniques, the conductive layer 224 may be deposited only on the top of the second dielectric layer 208, while the deposition of the conductive layer 224 on the sidewalls 220 of the through-hole 216 is negligible. In another example, compared to the sputtering deposition process, the evaporation deposition is relatively less directional, which results in a more uniform deposition of the conductive layer 224 on the sidewalls 220 of the through-hole 216. Different profiles of the conductive layer 224 on the top surface and different profiles of the sidewalls 220 of the through-hole 216 may be combined and used, which is within the scope of embodiments of the present invention.

[0080] Figure 5A An exemplary top view of a semiconductor device 500 having a collimator structure according to some embodiments of the present invention is shown. The collimator structure in the semiconductor device 500 includes 81 through holes 216. In the embodiment shown, each through hole 216 has a circular cross-section. In some other embodiments, a cross-section of the through holes 216 of a different shape (e.g., square) may be used and is within the scope of embodiments of the present invention. In the embodiment shown, the through holes 216 are arranged in a 9×9 array of square cells 502. It should be noted that Figure 5A The semiconductor device 500 in FIG. 1 is for illustration purposes only; any number of through-holes 216 may be used and is within the scope of embodiments of the present invention.

[0081] Figure 5B An exemplary top view of a semiconductor device 500 with a collimator structure according to some embodiments of the present invention is shown. The collimator structure in the semiconductor device 500 includes 77 through holes 216. In the embodiment shown, each through hole 216 has a circular cross-section. In some other embodiments, a cross-section of the through hole 216 of a different shape (e.g., square) may be used and is within the scope of embodiments of the present invention. In the embodiment shown, the through holes 216 are arranged in an array of diamond units 504. It should be noted that Figure 5B The semiconductor device 500 in FIG. 1 is for illustration purposes only; any number of through-holes 216 may be used and is within the scope of embodiments of the present invention.

[0082] In one embodiment, an optical collimator includes a dielectric layer; a substrate; a plurality of through holes; and a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of through holes are configured as an array extending in a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of through holes extends in a vertical direction from the first surface of the dielectric layer through the dielectric layer and the substrate to a second surface of the substrate, and wherein the conductive layer is formed over at least one of the first surface of the dielectric layer and a portion of a sidewall of each of the plurality of through holes, and wherein the conductive layer is configured to allow the optical collimator to filter a range of wavelengths of light.

[0083] In some other embodiments, the conductive layer comprises an aluminum-copper alloy.

[0084] In some other embodiments, the first thickness of the conductive layer over the first surface of the dielectric layer is about 200 nm, and the second thickness of the conductive layer over the sidewalls of each of the plurality of through holes is about 20 nm.

[0085] In some other embodiments, the first depth of the portion where the sidewall of the conductive layer is located is about 3000 nm, wherein the first depth is measured from the first surface of the dielectric layer.

[0086] In some other embodiments, each of the plurality of through holes has a size of about 0.05 μm.

[0087] In some other embodiments, the first thickness of the dielectric layer is about 1.0 μm, and the second thickness of the substrate is about 6.0 μm.

[0088] In some other embodiments, the wavelength range is between 780nm and 1400nm.

[0089] In another embodiment, a semiconductor device includes at least one optical sensing element; and an optical collimator; wherein the optical collimator includes: a first dielectric layer, a first substrate, a plurality of through holes, and a conductive layer, wherein the first dielectric layer is formed above the first substrate, wherein the plurality of through holes are configured as an array extending in a lateral direction of a first surface of the first dielectric layer, wherein each of the plurality of through holes extends in a vertical direction from the first surface of the first dielectric layer through the first dielectric layer and the first substrate to a second surface of the first substrate, wherein the conductive layer is formed above at least one of the first surface of the first dielectric layer and a portion of a sidewall of each of the plurality of through holes, and wherein the conductive layer is configured to allow the optical collimator to filter light of a wavelength range.

[0090] In some other embodiments, at least one optical sensing element is formed in a second substrate, wherein the second substrate is further coated with a second dielectric layer, and wherein the optical collimator is formed above the second dielectric layer.

[0091] In some other embodiments, the conductive layer comprises an aluminum-copper alloy.

[0092] In some other embodiments, the first thickness of the conductive layer over the first surface of the first dielectric layer is about 200 nm, and the second thickness of the conductive layer over the sidewall of each of the plurality of vias is about 20 nm.

[0093] In some other embodiments, the first depth of the portion where the sidewall of the conductive layer is located is about 3000 nm, wherein the first depth is measured from the first surface of the dielectric layer.

[0094] In some other embodiments, each of the plurality of through holes has a size of about 0.05 μm.

[0095] In some other embodiments, the first dielectric layer has a first thickness of about 1.0 μm, and the first substrate has a second thickness of about 6.0 μm.

[0096] In some other embodiments, the wavelength range is between 780nm and 1400nm.

[0097] In another embodiment, a method for forming a semiconductor device includes forming a collimator structure on a first substrate having a first dielectric layer, wherein the collimator structure includes a plurality of through holes, wherein each of the plurality of through holes extends in a vertical direction from a first surface of a second dielectric layer through the second dielectric layer and the second substrate to a second surface of the second substrate; and forming a conductive layer over at least one of the first surface of the second dielectric layer and a portion of a sidewall of each of the plurality of through holes of the collimator structure.

[0098] In some other embodiments, the conductive layer comprises an aluminum-copper alloy.

[0099] In some other embodiments, the first thickness of the conductive layer over the first surface of the second dielectric layer is about 200 nm, and the second thickness of the conductive layer over the sidewalls of each of the plurality of vias is about 20 nm.

[0100] In some other embodiments, the first depth of the portion having the sidewall of the conductive layer is about 3000 nm, wherein the first depth is measured from the first surface of the second dielectric layer.

[0101] In some other embodiments, each of the plurality of through holes has a size of about 0.05 μm.

[0102] The foregoing text summarizes the features of many embodiments, so that those skilled in the art can better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive concept and scope of the present invention. Various changes, substitutions or modifications may be made to the embodiments of the present invention without departing from the inventive concept and scope of the present invention.

[0103] As used herein, the term "about" means within a range of plus or minus 10% of the stated value.

Claims

1. An optical collimator, comprising: a dielectric layer; a base; A plurality of through holes; as well as a conductive layer, wherein the dielectric layer is formed over the substrate, wherein the plurality of through holes are configured as an array extending in a lateral direction along a first surface of the dielectric layer, wherein each of the plurality of through holes extends in a vertical direction from the first surface of the dielectric layer through the dielectric layer and the substrate to a second surface of the substrate, and wherein the conductive layer is formed over at least one of the first surface of the dielectric layer and a portion of a sidewall of each of the plurality of through holes, and wherein the conductive layer is configured to allow the optical collimator to filter a range of wavelengths of light, wherein a first thickness of the dielectric layer is in a range of 0.8 μm to 1.2 μm, and a second thickness of the substrate is in a range of 4 μm to 8 μm.

2. The optical collimator of claim 1, wherein the conductive layer comprises an aluminum-copper alloy. 3 . The optical collimator of claim 1 , wherein a first thickness of the conductive layer over the first surface of the dielectric layer is 200 nm, and a second thickness of the conductive layer over the sidewall of each of the plurality of through holes is 20 nm.

4. The optical collimator of claim 1, wherein a portion of the sidewall of the conductive layer has a first depth of 3000 nm, wherein the first depth is measured from the first surface of the dielectric layer. 5 . The optical collimator of claim 1 , wherein each of the plurality of through holes has a diameter of 0.05 μm. The optical collimator as claimed in claim 1 , wherein the wavelength range is between 780 nm and 1400 nm.

7. A semiconductor device comprising: at least one optical sensing element; as well as an optical collimator; The optical collimator comprises: a first dielectric layer, a first substrate, a plurality of through holes and a conductive layer, wherein the first dielectric layer is formed over the first substrate, wherein the plurality of through holes are configured as an array extending in a lateral direction of a first surface of the first dielectric layer, wherein each of the plurality of through holes extends in a vertical direction from the first surface of the first dielectric layer through the first dielectric layer and the first substrate to a second surface of the first substrate, wherein the conductive layer is formed over at least one of the first surface of the first dielectric layer and a portion of a sidewall of each of the plurality of through holes, and wherein the conductive layer is configured to allow the optical collimator to filter light of a wavelength range, wherein a first thickness of the first dielectric layer is in a range of 0.8 μm to 1.2 μm, and a second thickness of the first substrate is in a range of 4 μm to 8 μm. 8 . The semiconductor device of claim 7 , wherein the at least one optical sensing element is formed in a second substrate, wherein the second substrate is further coated with a second dielectric layer, and wherein the optical collimator is formed above the second dielectric layer.

9. The semiconductor device of claim 7, wherein the conductive layer comprises an aluminum-copper alloy. 10 . The semiconductor device of claim 7 , wherein a first thickness of the conductive layer over the first surface of the first dielectric layer is 200 nm, and a second thickness of the conductive layer over the sidewall of each of the plurality of vias is 20 nm.

11. The semiconductor device of claim 8, wherein a portion of the sidewall of the conductive layer has a first depth of 3000 nm, wherein the first depth is measured from the first surface of the dielectric layer. 12 . The semiconductor device of claim 8 , wherein each of the plurality of through holes has a diameter of 0.05 μm.

13. The semiconductor device as claimed in claim 7, wherein the wavelength range is between 780 nm and 1400 nm.

14. A method for forming a semiconductor device, comprising: forming a collimator structure on a first substrate having a first dielectric layer, wherein the collimator structure comprises a plurality of through holes, wherein each of the plurality of through holes extends in a vertical direction from a first surface of a second dielectric layer through the second dielectric layer and a second substrate to a second surface of the second substrate, wherein a first thickness of the second dielectric layer is in a range of 0.8 μm to 1.2 μm, and a second thickness of the second substrate is in a range of 4 μm to 8 μm; and A conductive layer is formed over at least one of the first surface of the second dielectric layer and a portion of a sidewall of each of the plurality of through holes of the collimator structure. 15 . The method for forming a semiconductor device as claimed in claim 14 , wherein the conductive layer comprises an aluminum-copper alloy. 16 . The method for forming a semiconductor device as claimed in claim 14 , wherein a first thickness of the conductive layer on the first surface of the second dielectric layer is 200 nm, and a second thickness of the conductive layer on the sidewall of each of the plurality of through holes is 20 nm. 17 . The method for forming a semiconductor device as claimed in claim 14 , wherein a first depth of a portion of the sidewall of the conductive layer is 3000 nm, wherein the first depth is measured from the first surface of the second dielectric layer. 18 . The method for forming a semiconductor device as claimed in claim 16 , wherein each of the plurality of through holes has a diameter of 0.05 μm.

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