Semiconductor device and method for manufacturing the same

Abstract

Embodiments of the present invention relate to semiconductor devices and methods for making the same. Embodiments of the present invention provide a semiconductor device comprising a diffusion barrier structure, a bottom electrode, a top electrode above the bottom electrode, a switching layer, and a cap layer. The bottom electrode is above the diffusion barrier structure. The top electrode is above the bottom electrode. The switching layer is between the bottom electrode and the top electrode and is configured to store data. The cap layer is between the top electrode and the switching layer. The thermal conductivity of the diffusion barrier structure is greater than approximately 20 W / mK.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Resistive random access memory (RRAM) and conductive bridge random access memory (CBRAM) are strong candidates for next generation non-volatile memory technology due to their simple structure and compatibility with complementary metal oxide semiconductor (CMOS) logic manufacturing process. However, RRAM and CBRAM still suffer from degradation of switching window, switching time during cycling. Summary of the invention

[0003] One embodiment of the present invention relates to a semiconductor device comprising: a diffusion barrier structure; a bottom electrode above the diffusion barrier structure; a top electrode above the bottom electrode; a switching layer between the bottom electrode and the top electrode and configured to store data; and a cap layer between the switching layer and the top electrode, wherein the thermal conductivity of the diffusion barrier structure is greater than approximately 20 Watts / meter Kelvin (W / mK).

[0004] One embodiment of the present invention relates to a semiconductor device, comprising: a bottom electrode; a top electrode above the bottom electrode; a switching layer between the bottom electrode and the top electrode and configured to store data; a metal reservoir layer between the switching layer and the top electrode; and a metal diffusion barrier layer between the metal reservoir layer and the switching layer, wherein the metal diffusion barrier layer hinders metal ions from diffusing from the metal reservoir layer to the switching layer.

[0005] One embodiment of the present invention relates to a method for making a semiconductor device, comprising: forming a dielectric layer above a substrate, wherein the dielectric layer has an opening formed therein; forming a diffusion barrier structure in the opening; forming a bottom electrode above the diffusion barrier structure; forming a switching layer above the bottom electrode; forming a metal reservoir layer above the switching layer; and forming a top electrode above the metal reservoir layer, wherein the thermal conductivity of the diffusion barrier structure is greater than approximately 20 Watts per meter Kelvin (W / mK). BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, aspects of the embodiments of the present invention are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various structures are not necessarily drawn to scale. In fact, the dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1is a flow chart illustrating a method for fabricating a semiconductor device according to various aspects of one or more embodiments of the present invention.

[0008] Figure 2 and Figure 3 is a schematic diagram of one of various operations in fabricating a semiconductor device in accordance with one or more embodiments of the present invention.

[0009] Figure 4A , Figure 4B and Figure 4C 1 is a schematic diagram illustrating different operating states of the semiconductor device 100 according to some comparative embodiments of the present invention.

[0010] Figure 5A , Figure 5B and Figure 5C 2 is a schematic diagram illustrating different operating states of the semiconductor device 1 according to some embodiments of the present invention.

[0011] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F and Figure 6G is a schematic diagram of one of various operations in fabricating a semiconductor device in accordance with one or more embodiments of the present invention.

[0012] Figure 7 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0013] Figure 8 is a graph illustrating simulation results of set / reset time versus cycle time for some embodiments according to embodiments of the present invention.

[0014] Fig. 9 is a graph illustrating simulation results of bit count versus current for some embodiments according to embodiments of the present invention.

[0015] Fig.10 is a flow chart illustrating a method for fabricating a semiconductor device according to various aspects of one or more embodiments of the present invention.

[0016] Fig.11A , Fig. 11B , Fig. 11C and Fig.11D is a schematic diagram of various operations in fabricating a semiconductor device in accordance with one or more embodiments of the present invention.

[0017] Fig.12 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0018] Fig.13 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0019] Fig.14 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0020] Fig.15 is a flow chart illustrating a method for fabricating a semiconductor device according to various aspects of one or more embodiments of the present invention.

[0021] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D is a schematic diagram of various operations in fabricating a semiconductor device in accordance with one or more embodiments of the present invention.

[0022] Fig.17 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0023] Fig.18A and Fig.18B is a graph of simulation results of LRS / HRS windows according to comparative embodiments and some embodiments of the present invention. DETAILED DESCRIPTION

[0024] Embodiments of the present invention provide many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify embodiments of the present invention. Of course, these are merely examples and are not intended to be restrictive. For example, in the following description, a first member is formed above or on a second member and may include an embodiment in which the first member and the second member are formed to be in direct contact, and may also include an embodiment in which an additional member may be formed between the first member and the second member so that the first member and the second member may not be in direct contact. In addition, embodiments of the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplification and clarity and does not itself specify the relationship between the various embodiments and / or structural designs discussed.

[0025] Additionally, for ease of description, spatially relative terms (e.g., "below," "beneath," "below," "above," "on," "over," etc.) may be used herein to describe the relationship of one element or component to another (other) element or component, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly accordingly.

[0026] As used herein, terms such as "first," "second," and "third" describe various elements, components, regions, layers, and / or sections, which should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Unless the context clearly indicates otherwise, terms such as "first," "second," and "third" do not imply a sequence or order when used herein.

[0027] As used herein, the terms "approximately," "substantially," "substantial," and "about" are used to describe and explain small variations. When used in conjunction with an event or circumstance, the terms may refer to instances where the event or circumstance occurred exactly as well as instances where the event or circumstance occurred very approximately. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average value of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the values ​​may be considered to be "substantially" the same or equal. For example, "substantially" parallel can refer to an angular range of variation relative to 0° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, "substantially" perpendicular can refer to an angular range of variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0028] In one or more embodiments of the present invention, the semiconductor device includes a diffusion barrier layer interposed between the bottom electrode and the switching layer. The material of the diffusion barrier layer is selected to be inert or less reactive with respect to ions (e.g., oxygen ions or reactive ions), and thus the diffusion barrier layer can help prevent or hinder the permeability of oxygen ions or reactive ions during cycling and baking. The diffusion barrier layer can improve the cycling and retention performance of the semiconductor device. Therefore, the switching window can be increased after cycling and baking.

[0029] Figure 1 1 is a flow chart illustrating various aspects of a method for making a semiconductor device according to one or more embodiments of the present invention. Method 100 begins with operation 110, where a bottom electrode is formed over a substrate. Method 100 continues with operation 120, where a diffusion barrier layer is formed over the bottom electrode. Method 100 continues with operation 130, where a switching layer is formed over the diffusion barrier layer. The diffusion barrier layer hinders diffusion of ions between the switching layer and the bottom electrode. Method 100 continues with operation 140, where a top electrode is formed over the switching layer.

[0030] Method 100 is merely an example and is not intended to limit embodiments of the invention beyond those expressly recited in the claims. Additional operations may be provided before, during, and after method 100, and some of the described operations may be replaced, eliminated, or moved for additional embodiments of the method.

[0031] Figure 2 and Figure 3 FIG. 1 is a schematic diagram of one of various operations in fabricating a semiconductor device according to one or more embodiments of the present invention. Figure 2 , receiving substrate 10. Substrate 10 may include a semiconductor substrate. In some embodiments, the material of substrate 10 may include an elemental semiconductor, such as silicon or germanium; or a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, or indium arsenide; or a combination thereof.

[0032] In some embodiments, semiconductor components (eg, transistor components), electronic components (eg, resistor components, capacitor components, or inductor components), and circuit layers may be formed in or over substrate 10 .

[0033] like Figure 2 As shown in FIG. 1 , a bottom electrode 12 is formed over a substrate 10. The bottom electrode 12 is formed of a conductive material. Examples of the conductive material of the bottom electrode 12 may include, but are not limited to, metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), doped semiconductor materials (e.g., polysilicon, etc.), and metals (e.g., gold, tungsten, etc.). In some embodiments, the bottom electrode 12 may be electrically connected to semiconductor components, electronic components, and / or circuit layers formed on the substrate 10.

[0034] like Figure 3, a switching layer 16 is formed over the bottom electrode 12. A top electrode 22 is formed over the switching layer 16. The switching layer 16 may include a data storage area configured to store data. In some embodiments, the switching layer 16 may be a data storage area of ​​a resistive random access memory (RRAM). The variable resistance of the data storage area may represent a data unit, such as a data bit. Depending on the voltage applied between the top electrode 22 and the bottom electrode 12, the variable resistance may switch between a high resistance state and a low resistance state. In some embodiments, the switching layer 16 is, but is not limited to, a high-k dielectric material having a dielectric constant greater than 3.9. In some embodiments, the material of the switching layer 16 may include, but is not limited to, a metal oxide. The metal oxide may include a binary metal oxide, such as hafnium oxide, tantalum oxide, aluminum oxide, nickel oxide, titanium oxide, and the like. The metal oxide may include a ternary metal oxide, such as hafnium tantalum oxide, hafnium aluminum oxide, aluminum tantalum oxide, and the like. In some embodiments, the material of the switching layer 16 may include, but is not limited to, a semiconductor material, such as amorphous silicon, germanium selenide, germanium telluride, and the like.

[0035] The top electrode 22 is formed of a conductive material. Examples of conductive materials for the top electrode 22 may include, but are not limited to, doped semiconductor materials (e.g., polysilicon, etc.), metals (e.g., gold, tungsten, platinum, iridium, ruthenium, etc.), metal nitrides (e.g., titanium nitride, tantalum nitride, etc.).

[0036] In some embodiments, a cap layer 20 may be formed over the switching layer 16 before forming the top electrode 22. In some embodiments, the material of the cap layer 20 may include, but is not limited to, a metal such as titanium, tantalum, hafnium, aluminum, and the like. In some embodiments, the metal of the cap layer 20 may extract ions (e.g., oxygen) from the switching layer 16, so that the cap layer 20 may include an ion reservoir 18 having an oxygen concentration lower than that of the switching layer 16. In some other embodiments, the material of the cap layer 20 may include, but is not limited to, a high-k dielectric material having a dielectric constant greater than 3.9. For example, the material of the cap layer 20 may include a metal oxide such as titanium oxide, tantalum oxide, hafnium oxide, aluminum oxide, and the like. The oxygen concentration of the metal oxide of the cap layer 20 is lower than that of the metal oxide of the switching layer 16, and thus an ion reservoir 18 may be formed in the cap layer 20.

[0037] A diffusion barrier layer 14 is formed between the bottom electrode 12 and the switching layer 16 to form the semiconductor device 1 of some embodiments of the present invention. In some embodiments, the diffusion barrier layer 14 is adjacent to the switching layer 16, for example, the diffusion barrier layer 14 may be in contact with the switching layer 16. In some embodiments, the diffusion barrier layer 14 is adjacent to the bottom electrode 12, for example, the diffusion barrier layer 14 may be in contact with the bottom electrode 12. The diffusion barrier layer 14 may include an inert material or be less reactive to ions than the bottom electrode 12, so that the diffusion barrier layer 14 may hinder the diffusion of ions between the switching layer 16 and the bottom electrode 12. In some embodiments, the thickness of the diffusion barrier layer 14 may be in a range between about 50 angstroms and about 300 angstroms, but is not limited thereto.

[0038] In some embodiments, the semiconductor device 1 may include an RRAM that employs oxygen vacancies in the switching layer 16 to form a conductive filament. The ion reservoir 18 may be configured as an oxygen reservoir to store oxygen ions and promote resistance changes within the switching layer 16. In some embodiments, the diffusion barrier layer 14 may help prevent oxygen ions from diffusing from the switching layer 16 into the diffusion barrier layer 14 and the bottom electrode 12, and may help prevent oxygen ions from diffusing from the diffusion barrier layer 14 and the bottom electrode 12 into the switching layer 16. In some embodiments, the diffusion barrier layer 14 may help hinder oxygen ions from diffusing from the switching layer 16 into the diffusion barrier layer 14 and the bottom electrode 12, and may help hinder oxygen ions from diffusing from the diffusion barrier layer 14 and the bottom electrode 12 into the switching layer 16.

[0039] When the semiconductor device 1 is a resistive random access memory (RRAM), the diffusion barrier layer 14 is configured as an oxygen diffusion barrier layer. Examples of materials for the oxygen diffusion barrier layer may include metals, metal oxides, metal nitrides, silicates, silicides, or combinations thereof. For example, the metal for the oxygen diffusion barrier layer may include iridium (Ir), ruthenium (Ru), platinum (Pt), or combinations thereof. The metal oxide for the oxygen diffusion barrier layer may include iridium oxide, ruthenium oxide, or combinations thereof. The metal nitride for the oxygen diffusion barrier layer may include titanium ruthenium nitride. The silicate for the oxygen diffusion barrier layer may include tantalum silicon nitride. The silicide for the oxygen diffusion barrier layer may include tungsten silicide.

[0040] In some other embodiments, the semiconductor device 1 may include a conductive bridge random access memory (CBRAM) that employs active metal ions in the switching layer 16 to form a conductive filament. The ion reservoir 18 may be configured as an active metal reservoir to store active metal ions, such as copper ions, silver ions, aluminum ions, and the like. In some embodiments, the material of the cap layer 20 having the ion reservoir 18 may include, but is not limited to, a metal (such as copper, silver, aluminum, nickel, and the like), a metal compound (such as copper tantalum, and the like), or a metal compound (such as copper telluride, and the like). The material of the switching layer 16 may include, but is not limited to, a compound, such as an ionic compound, a covalent compound, an oxide compound, a semiconductor material, and the like. For example, the ionic compound may include germanium sulfide (GeS), germanium antimony telluride (GeSbTe), and the like. The covalent compound may include arsenic sulfide (AsS), and the like. The oxide compound may include tantalum oxide, silicon oxide, aluminum oxide, titanium oxide, and the like. The semiconductor material may include amorphous silicon, and the like.

[0041] In some embodiments, the diffusion barrier layer 14 can help prevent metal ions (e.g., copper ions, silver ions, aluminum ions, etc.) from diffusing from the switching layer 16 into the diffusion barrier layer 14 and the bottom electrode 12, and can help prevent active metal ions from diffusing from the diffusion barrier layer 14 and the bottom electrode 12 into the switching layer 16. In some embodiments, the diffusion barrier layer 14 can help hinder the diffusion of active metal ions from the switching layer 16 into the diffusion barrier layer 14 and the bottom electrode 12, and can help hinder the diffusion of active metal ions from the diffusion barrier layer 14 and the bottom electrode 12 into the switching layer 16.

[0042] When the semiconductor device 1 is a CBRAM, the diffusion barrier layer 14 is configured as an active metal diffusion barrier layer. Examples of materials for the active metal diffusion barrier layer may include metals, metal nitrides, metal alloys, or combinations thereof. For example, the metal for the active metal diffusion barrier layer may include palladium (Pd), tantalum (Ta), hafnium (Hf), zirconium (Zr), niobium (Nb), cobalt (Co), ruthenium (Ru), or combinations thereof. The metal nitride for the active metal diffusion barrier layer may include titanium nitride, tantalum nitride, tungsten nitride, tantalum tungsten nitride, titanium ruthenium nitride, tantalum ruthenium nitride, tantalum silicon nitride, tantalum germanium oxynitride (Ta-Ge-(O)N), or combinations thereof. The metal alloy for the active metal diffusion barrier layer may include a nickel-chromium alloy.

[0043] After the semiconductor device 1 is manufactured, an initialization operation is performed. In the case where the semiconductor device 1 is an RRAM, the initialization operation may be performed to break the bonding between the metal and oxygen, thereby forming oxygen vacancies, i.e., conductive filaments, in the switching layer 16. In the case where the semiconductor device 1 is a CBRAM, the initialization operation may be performed to migrate active metal ions from the ion reservoir 18 to the switching layer 16, thereby forming a metal bridge, i.e., a conductive filament, in the switching layer 16. The semiconductor device 1 may also undergo a baking operation to verify data retention at high temperatures. After the initialization operation, the semiconductor device 1 may operate in a reset state or in a set state.

[0044] Figure 4A , Figure 4B and Figure 4C 1 is a schematic diagram illustrating different operating states of the semiconductor device 100 according to some comparative embodiments of the present invention. Figure 4A , an initialization operation is performed by applying a forming voltage across the top electrode 22 and the bottom electrode 12 to initially form the conductive filament 16F. In some embodiments, a positive voltage is supplied to the top electrode 22, and a negative voltage is supplied to the bottom electrode 12. In the case where the semiconductor device 1 is an RRAM, the forming voltage is applied to break the bonding between the metal and the oxygen, thereby forming an oxygen vacancy, i.e., a conductive filament, in the switching layer 16. The local vacancies 16V tend to align to form a conductive filament 16F that can extend through the switching layer 16 and can be relatively permanent. In the case where the semiconductor device 1 is a CBRAM, a forming voltage is applied to migrate the active metal ions from the ion reservoir 18 to the switching layer 16, thereby forming a metal bridge, i.e., a conductive filament, in the switching layer 16. In the initialization operation of the CBRAM, the ions 16S may also diffuse into the bottom electrode 12.

[0045] like Figure 4B , a reset operation is performed by applying a reset voltage across the top electrode 22 and the bottom electrode 12 to switch the switching layer 16 from a low resistance state (LRS) to a high resistance state (HRS). In some embodiments, a negative voltage is supplied to the top electrode 22, and a positive voltage is supplied to the bottom electrode 12. The ions 16S will move back from the ion reservoir 18 to the switching layer 16, thereby filling the vacancies 16V and destroying the conductive filaments 16F to increase the resistivity. During the reset operation, some ions 16S may diffuse from the switching layer 16 to the bottom electrode 12, so that the conductive filaments 16F cannot be completely closed. In some embodiments, some ions 16S may also diffuse from the switching layer 16 to the bottom electrode 12 during the baking operation, thereby adversely affecting the closure of the conductive filaments 16F.

[0046] like Figure 4C, a set operation is performed by applying a set voltage across the top electrode 22 and the bottom electrode 12 to switch the switching layer 16 from a high resistance state (HRS) to a low resistance state (LRS). In some embodiments, a positive voltage is supplied to the top electrode 22, and a negative voltage is supplied to the bottom electrode 12. The ions 16S in the switching layer 16 will move to the ion reservoir 18, thereby leaving a vacancy 16V and reforming the conductive filament 16F to reduce the resistivity. During the set operation, some ions 16S may diffuse from the bottom electrode 12 to the switching layer 16, so that the conductive filament 16F cannot be completely disconnected. In some embodiments, some ions 16S may also diffuse from the bottom electrode 12 to the switching layer 16 during the baking operation, thereby adversely affecting the disconnection of the conductive filament 16F.

[0047] Figure 5A , Figure 5B and Figure 5C 1 is a schematic diagram illustrating different operating states of the semiconductor device 1 according to some embodiments of the present invention. Figure 5A , after the semiconductor device 1 is manufactured, an initialization operation is performed by applying a formation voltage across the top electrode 22 and the bottom electrode 12 to initially form the conductive filament 16F. In some embodiments, a positive voltage is supplied to the top electrode 22, and a negative voltage is supplied to the bottom electrode 12. The formation voltage is applied to break the bonding between the atoms 16S and other elements of the switching layer 16, thereby forming vacancies 16V in the switching layer 16, and driving the ions 16S to the ion reservoir 18. The local vacancies 16V tend to align to form the conductive filament 16F, which can extend through the switching layer 16 and can be relatively permanent. During the initialization operation, the diffusion barrier layer 14, which is inert or less reactive to the ions 16S than the bottom electrode 12, can help prevent or hinder the ions 16S from diffusing from the switching layer 16 into the diffusion barrier layer 14 and the bottom electrode 12.

[0048] like Figure 5B , a reset operation is performed by applying a reset voltage across the top electrode 22 and the bottom electrode 12 to switch the switching layer 16 from LRS to HRS. In some embodiments, a negative voltage is supplied to the top electrode 22, and a positive voltage is supplied to the bottom electrode 12. The ions 16S will move back from the ion reservoir 18 to the switching layer 16, thereby filling the vacancies 16V and destroying the conductive filaments 16F to increase the resistivity. During the reset operation, the diffusion barrier layer 14 can help prevent or hinder the ions 16S from diffusing from the switching layer 16 to the diffusion barrier layer 14 and the bottom electrode 12. Therefore, the diffusion barrier layer 14 can help retain the ions 16S in the switching layer 16 so that the conductive filaments 16F can be closed more robustly in the reset state. During the baking operation, the diffusion barrier layer 14 can also help prevent or hinder the ions 16S from diffusing from the switching layer 16 to the diffusion barrier layer 14 and the bottom electrode 12.

[0049] like Figure 5C , a set operation is performed by applying a set voltage across the top electrode 22 and the bottom electrode 12 to switch the switching layer 16 from HRS to LRS. In some embodiments, a positive voltage is supplied to the top electrode 22, and a negative voltage is supplied to the bottom electrode 12. The ions 16S in the switching layer 16 will move to the ion reservoir 18, thereby leaving vacancies 16V and reforming the conductive filament 16F to reduce the resistivity. During the set operation, the diffusion barrier layer 14 can help prevent or hinder the ions 16S from diffusing from the bottom electrode 12 and the diffusion barrier layer 14 into the switching layer 16. Therefore, the diffusion barrier layer 14 can help block the ions 16F from diffusing from the bottom electrode 12 into the switching layer 16, so that the conductive filament 16F can be disconnected more robustly in the set state. During the baking operation, the diffusion barrier layer 14 can also help prevent or hinder the ions 16S from diffusing from the bottom electrode 12 and the diffusion barrier layer 14 into the switching layer 16.

[0050] The semiconductor device and the method for manufacturing the same according to the embodiment of the present invention are not limited to the above-mentioned embodiment and may have other different embodiments. In order to simplify the description and to facilitate comparison between each embodiment of the present invention, the same components in each of the following embodiments are marked with the same numbers. In order to make it easier to compare the differences between the embodiments, the following description will detail the differences between the different embodiments and the same features will not be repeated.

[0051] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F and Figure 6G FIG. 1 is a schematic diagram of one of various operations in fabricating a semiconductor device according to one or more embodiments of the present invention. Fig. 6A , receiving substrate 10. In some embodiments, a bottom interconnect structure 32 may be formed over substrate 10. In some embodiments, bottom interconnect structure 32 includes a bottom metallization layer 321 and a bottom interlayer dielectric (ILD) layer 322 laterally surrounding bottom metallization layer 321. In some embodiments, bottom metallization layer 321 may be a layer of a back-end of line (BEOL). In some embodiments, the material of bottom metallization layer 321 may include a metal or an alloy, such as copper, tungsten, an alloy thereof, and the like. The material of bottom ILD layer 322 may include a dielectric material (e.g., a low-k dielectric material having a dielectric constant of less than 2.0), and the like, but is not limited thereto.

[0052] like Figure 6B, a dielectric layer 34 is formed over the substrate 10. In some embodiments, the dielectric layer 34 is formed over the bottom interconnect structure 32 and includes an opening 34R exposing a portion of the bottom metallization layer 321. The material of the dielectric layer 34 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, and the like.

[0053] like Figure 6C , a bottom electrode 12 is formed over the dielectric layer 34 and is electrically connected to the exposed bottom metallization layer 321. In some embodiments, the bottom electrode 12 may be formed to have a substantially flat upper surface. Subsequently, a diffusion barrier layer 14, a switching layer 16, and a top electrode 22 may be formed over the bottom electrode 12. In some embodiments, an ion reservoir 18 may be formed over the switching layer 16 before forming the top electrode 22. In some embodiments, a cap layer 20 may be formed over the ion reservoir 18 before forming the top electrode 22. The diffusion barrier layer 14, the switching layer 16, the ion reservoir 18, the cap layer 20, and the top electrode 22 may have a substantially flat upper surface like the bottom electrode 12. The materials used for the bottom electrode 12, the diffusion barrier layer 14, the switching layer 16, the cap layer 20, and the top electrode 22 may be the same as those in the aforementioned embodiments, and will not be described in detail.

[0054] like Fig.6D , a mask layer 36 is formed over the top electrode 22. The mask layer 36 covers a portion of the top electrode 22 and exposes the remaining portion of the top electrode 22. In some embodiments, the mask layer 36 may include a photoresist layer, but is not limited thereto.

[0055] like Fig. 6EAs shown in FIG. 3 , the top electrode 22, the cap layer 20, the ion reservoir 18, the switching layer 16, the diffusion barrier layer 14, and the bottom electrode 12 are patterned. In some embodiments, the mask layer 36 is used as an etching mask to pattern the top electrode 22, the cap layer 20, the ion reservoir 18, the switching layer 16, the diffusion barrier layer 14, and the bottom electrode 12. In some embodiments, the top electrode 22, the cap layer 20, the ion reservoir 18, the switching layer 16, the diffusion barrier layer 14, and the bottom electrode 12 are patterned by etching. In some embodiments, etching may include dry etching, wet etching, or a combination thereof. The top electrode 22, the cap layer 20, the ion reservoir 18, the switching layer 16, the diffusion barrier layer 14, and the bottom electrode 12 may be patterned by one etching operation or multiple etching operations. In some embodiments, after etching, the width of the top electrode 22, the cap layer 20, and the ion reservoir 18 may be smaller than the width of the switching layer 16, the diffusion barrier layer 14, and the bottom electrode 12, and a portion of the upper surface of the switching layer 16 may be exposed. The mask layer 36 may be removed after patterning the top electrode 22, the cap layer 20, the ion reservoir 18, the switching layer 16, the diffusion barrier layer 14, and the bottom electrode 12.

[0056] like Fig. 6F , a passivation layer 38 may be optionally formed. In some embodiments, the passivation layer 38 is insulating. In some embodiments, the passivation layer 38 covers the upper surface of the top electrode 22. In some embodiments, the passivation layer 38 covers the edge of the top electrode 22, the cap layer 20, and the ion reservoir 18. In some embodiments, the passivation layer 38 further covers a portion of the switching layer 16. In some embodiments, the material of the passivation layer 38 includes a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.), but is not limited thereto.

[0057] like Figure 6G , a top interlayer dielectric (ILD) layer 40 is formed over the substrate 10, covering the passivation layer 38. In some embodiments, the material of the top ILD layer 322 may include a dielectric material (e.g., a low-k dielectric material having a dielectric constant of less than 2.0), etc., but is not limited thereto. The top ILD layer 40 and the passivation layer 38 may be patterned by, for example, photolithography and etching techniques to expose a portion of the top electrode 22. In some embodiments, a top metallization layer 42 is formed and electrically connected to the top electrode 22 to form the semiconductor device 2. In some embodiments, the material of the top metallization layer 42 may include a metal or an alloy, such as copper, tungsten, an alloy thereof, etc. In some embodiments, the top metallization layer 42 and the top ILD layer 40 form a top interconnect structure 44. The semiconductor device 2 is a planar type semiconductor device, in which the top electrode 22, the cap layer 20, the ion reservoir 18, the switching layer 16, the diffusion barrier layer 14, and the bottom electrode 12 may have a planar upper surface.

[0058] In some embodiments, semiconductor device 2 may be driven by a transistor device. For example, bottom metallization layer 321 may be electrically connected to a drain electrode of the transistor device. A source electrode of the transistor device may be electrically connected to a source line, and a gate electrode of the transistor device may be electrically connected to a word line. Top metallization layer 42 may be electrically connected to a bit line.

[0059] In some embodiments, semiconductor device 2 may be driven by a pair of transistor devices. For example, bottom metallization layer 321 may be electrically connected to a common drain electrode of the transistor devices. The source electrodes of the pair of transistor devices may be electrically connected to a source line, and the gate electrodes of the transistor devices may be electrically connected to a word line. Top metallization layer 42 may be electrically connected to a bit line.

[0060] Figure 7 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention. Figure 7 As shown in Figure 6G Compared with the semiconductor device 2 of FIG. 1 , the semiconductor device 3 is a non-planar type semiconductor device, in which the upper surface of the bottom electrode 12 is concave. In some embodiments, the upper surfaces of the top electrode 22, the cap layer 20, the switching layer 16, and the diffusion barrier layer 14 may be non-planar. For example, the upper surfaces of the top electrode 22, the cap layer 20, the switching layer 16, and the diffusion barrier layer 14 may be concave.

[0061] Figure 8 is a graph illustrating simulation results of the set / reset time versus cycle time for some embodiments according to embodiments of the present invention. Figure 8 As shown in FIG. 1 , the degradation of the set / reset time of a semiconductor device having a diffusion barrier layer is significantly resolved.

[0062] Fig. 9 is a graph illustrating simulation results of bit count versus current according to some embodiments of the present invention. Fig. 9 As shown in , the switching window between the retained after cycling (RAC) Ir0 and Ir1 is close to the original switching window between the initial Ir0 and Ir1, thus significantly resolving the degradation of the switching window of the semiconductor device with the diffusion barrier layer.

[0063] Fig.105 is a flow chart illustrating a method for making a semiconductor device according to various aspects of one or more embodiments of the present invention. Method 500 begins with operation 510, where a dielectric layer is formed over a substrate. The dielectric layer may have an opening formed therein. Method 500 continues with operation 520, where a diffusion barrier structure is formed in the opening. Method 500 continues with operation 530, where a bottom electrode is formed over the diffusion barrier structure. Method 500 continues with operation 540, where a switching layer is formed over the bottom electrode. Method 500 continues with operation 550, where a cap layer is formed over the switching layer. Method 500 continues with operation 560, where a top electrode is formed over the cap layer.

[0064] The method 500 is merely an example of forming a conductive bridge random access memory (CBRAM) and is not intended to limit the embodiments of the present invention beyond those expressly recited in the claims. Additional operations may be provided before, during, and after the method 500, and some of the described operations may be replaced, eliminated, or moved for additional embodiments of the method.

[0065] Fig.11A , Fig. 11B , Fig. 11C and Fig.11D Schematic diagram of various operations in the fabrication of a semiconductor device according to one or more embodiments of the present invention. Fig.11A , receiving substrate 50. The material of substrate 50 may be similar to the materials described above, and thus such details are omitted. In some embodiments, semiconductor components (such as transistor components), electronic components (such as resistor components, capacitor components, or inductor components), and circuit layers may be formed in or over substrate 50. In some embodiments, bottom interconnect structure 72 may be formed over substrate 50. In some embodiments, bottom interconnect structure 72 includes bottom metallization layer 721 and bottom ILD layer 722 that laterally surrounds bottom metallization layer 721. In some embodiments, the material of bottom metallization layer 721 and the material of bottom ILD layer 722 may be similar to the materials described above, and thus such details are omitted for the sake of brevity.

[0066] like Fig.11A , in operation 510, a dielectric layer 74 is formed over the substrate 50. In some embodiments, the dielectric layer 74 is formed over the bottom interconnect structure 72 and includes an opening 74R that exposes a portion of the bottom metallization layer 721. In some embodiments, the material of the dielectric layer 74 can be similar to that described above, and thus such details are omitted for brevity.

[0067] like Fig.11AAs shown in FIG. 5 , a diffusion barrier structure 52 is formed over the substrate 50. In operation 520, the diffusion barrier structure 52 may be formed in the opening 74R in and over the dielectric layer 74. In addition, the diffusion barrier structure 52 is electrically connected to the exposed bottom metallization layer 721. Fig.11A As shown in FIG. 5 , the diffusion barrier structure 52 is in contact with the bottom metallization layer 721. In some embodiments, the diffusion barrier structure 52 is conformally formed in the opening 74R and includes a uniform thickness (eg, Fig.14 In other embodiments, the diffusion barrier structure 52 may be formed to fill the opening 74R and thus may have a Fig.11A In such embodiments, the diffusion barrier structure 52 may have a first portion 521 mainly in the opening 74R and a second portion 522 surrounding the first portion 521. The thickness of the first portion 521 is greater than the thickness of the second portion 522. In some embodiments, the thickness of the second portion 522 is uniform, while the thickness of the first portion varies.

[0068] It should be noted that the diffusion barrier structure 52 is an effective metal diffusion barrier structure. For example, the diffusion barrier structure 52 is an effective copper (Cu) diffusion barrier structure. It is known that metals (such as Cu) used in BEOL metallization layers can diffuse into adjacent components and thus degrade device performance. Therefore, a diffusion barrier structure 52 comprising a material that is thermally stable to Cu is provided to mitigate Cu diffusion. In addition to the Cu diffusion barrier function, the diffusion barrier structure 52 provided by an embodiment of the present invention further includes a heat conduction function. In some embodiments, the thermal conductivity of the diffusion barrier structure 52 is greater than approximately 20 watts / meter Kelvin temperature (W / mK) in order to improve heat dissipation. In some embodiments, the diffusion barrier structure 52 may include a metal, a metal nitride, or a two-dimensional (2D) material.

[0069] In some embodiments, the diffusion barrier structure 52 comprises a single layer structure, such as Fig.11A . In such embodiments, the diffusion barrier structure 52 may include a metal nitride (e.g., titanium nitride (TiN)) having a thermal conductivity of approximately 28.8 W / mK, but embodiments of the present invention are not limited thereto. In other embodiments, the diffusion barrier structure 52 may include a 2D material, such as graphene, molybdenum disulfide (MoS2), or hexagonal boron nitride (h-BN). The thermal conductivity of graphene is between approximately 2000 W / mK and approximately 4000 W / mK, the thermal conductivity of MoS2 is between approximately 98 W / mK and approximately 138 W / mK, and the thermal conductivity of h-BN is between approximately 1700 W / mK and approximately 2000 W / mK; all of these thermal conductivities are greater than 20 W / mK. In some embodiments, the thickness of the single-layer diffusion barrier structure 52 is between approximately 70 angstroms and approximately 200 angstroms, but embodiments of the present invention are not limited thereto.

[0070] In some embodiments, the diffusion barrier structure 52 includes a multilayer structure. In such embodiments, the diffusion barrier structure 52 includes a metal and a metal nitride. For example, the diffusion barrier structure 52 may include a tantalum nitride (TaN) layer 52a and a tantalum (Ta) layer 52b (e.g., Fig.12 ). In addition, the TaN layer 52a is in contact with the bottom metallization layer 721. In such embodiments, the nitrogen concentration in the TaN layer 52a is between approximately 10% and approximately 40% so as to provide an effective diffusion barrier function. However, it is found that the thermal conductivity of TaN is approximately 3.4 W / mK, which is much less than 20 W / mK. In order to increase the thermal conductivity, a Ta layer 52b having a thermal conductivity of approximately 57.5 W / mK is provided. In addition, the thickness of the Ta layer 52b is greater than the thickness of the TaN layer 52a. In some embodiments, the TaN layer 52a may be conformally formed in the opening 74R, and then the Ta layer 52b may be formed to fill the opening 74R, as shown in FIG. Fig.12 As shown in .

[0071] In other embodiments, the diffusion barrier structure 52 may include a first TaN layer 52a, a second TaN layer 52c, and a Ta layer 52b disposed between the first TaN layer 52a and the second TaN layer 52c (eg, Fig.13 ). In other words, a TaN / Ta / TaN structure may be provided. In such embodiments, the nitrogen concentration in the first TaN layer 52a and the second TaN layer 52c is between approximately 10% and approximately 40% in order to provide an effective diffusion barrier function, while the Ta layer 52b is provided to increase thermal conductivity. The thickness of the Ta layer 52b is greater than the sum of the thickness of the first TaN layer 52a and the thickness of the second TaN layer 52c. For example, the thickness of each of the first TaN layer 52a and the second TaN layer 52c may be between approximately 10 angstroms and 30 angstroms, while the thickness of the Ta layer 52b is between approximately 30 angstroms and 70 angstroms. In some embodiments, the first TaN layer 52a may be conformally formed in the opening 74R, the Ta layer 52b may then be formed to fill the opening 74R, and the second TaN layer 52c may be formed over the Ta layer 52b, as shown. Fig.13 Therefore, the top surface of the Ta layer 52b and the top surface of the TaN layer 52c may be substantially flat, but the embodiment of the present invention is not limited thereto.

[0072] refer to Fig. 11B Then, in operation 530, a bottom electrode 54 is formed over the diffusion barrier structure 52. In some embodiments, when the diffusion barrier structure 52 includes a TaN / Ta multilayer, the Ta layer 52b is adjacent to the bottom electrode 54 ( Fig.12 ). Examples of conductive materials for the bottom electrode 54 may include metals such as gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), and the like.

[0073] Still refer to Fig. 11B In operation 540, a switching layer 56 is formed over the bottom electrode 54. The switching layer 56 may include a data storage region configured to store data, and the variable resistance of the data storage region may represent a data unit, such as a data bit.

[0074] like Fig. 11B As shown in FIG. 5 , in operation 550, a cap layer 58 is formed over the switching layer 56. In some embodiments, the method 500 is used to form a conductive bridge random access memory (CBRAM) that employs active metal ions in the cap layer 58 to form conductive filaments. Therefore, the cap layer 58 is also referred to as a metal reservoir layer, which is configured as an active metal reservoir to store active metal ions, such as copper ions, silver ions, aluminum ions, and the like.

[0075] In operation 560, a top electrode 60 is formed over the cap layer 58. In some embodiments, the bottom electrode 54, the switching layer 56, the cap layer 58, and the top electrode 60 (together including the diffusion barrier structure 52) may have a substantially flat upper surface. The materials used for the switching layer 56, the cap layer 58, and the top electrode 60 may be the same as those of the previous embodiments, and will not be described in detail.

[0076] In some embodiments, a mask layer (not shown) may be formed over the top electrode 60. The mask layer covers a portion of the top electrode 60 and exposes the rest of the top electrode 60. In some embodiments, the mask layer may include a photoresist layer, but is not limited thereto. Fig. 11C , the top electrode 60, the cap layer 58, the switching layer 56, the bottom electrode 54, and the diffusion barrier structure 52 are patterned by the mask layer. In some embodiments, the top electrode 60, the cap layer 58, the switching layer 56, the bottom electrode 54, and the diffusion barrier structure 52 are patterned by etching. In some embodiments, etching may include dry etching, wet etching, or a combination thereof. The top electrode 60, the cap layer 58, the switching layer 56, the bottom electrode 54, and the diffusion barrier structure 52 may be patterned by one etching operation or by multiple etching operations. In some embodiments, the width of the diffusion barrier structure 52 and the width of the bottom electrode 54 may be greater than the width of the cap layer 58 and the width of the top electrode 60, but embodiments of the present invention are not limited thereto. In such embodiments, a portion of the upper surface of the bottom electrode 54 or a portion of the switching layer 56 may be exposed, but embodiments of the present invention are not limited thereto. The mask layer may be removed after patterning the top electrode 60, the cap layer 58, the switching layer 56, the bottom electrode 54, and the diffusion barrier structure 52.

[0077] like Fig.11D, a passivation layer 76 may be optionally formed. In some embodiments, the passivation layer 76 is insulating. In some embodiments, the passivation layer 76 covers the upper surface of the top electrode 60. In some embodiments, the passivation layer 76 covers the sidewalls of the top electrode 60, the sidewalls of the cap layer 58, and the sidewalls of a portion of the switching layer 56. The material of the passivation layer 76 may be similar to the materials described above, and therefore such details are omitted for brevity.

[0078] Still refer to Fig.11D , a top ILD layer 78 is formed over the substrate 50, thereby covering the passivation layer 76. The material of the top ILD layer 78 may be similar to the above-mentioned materials, and thus such details are omitted. The top ILD layer 78 and the passivation layer 76 may be patterned by, for example, photolithography and etching techniques to expose a portion of the top electrode 60. In some embodiments, a top metallization layer 80 is formed and electrically connected to the top electrode 60 to form the semiconductor device 5. The material of the top metallization layer 60 may be similar to the above-mentioned materials, and thus such details are omitted. The semiconductor device 5 is a planar type semiconductor device, in which the top electrode 60, the cap layer 58, the switching layer 56, the bottom electrode 54, and the diffusion barrier structure 52 may have a planar upper surface.

[0079] Please refer to Fig.14 , which is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention. Fig.14 As shown in Fig.11D Compared to the semiconductor device 5 of FIG. 5 , the semiconductor device 6 is a non-planar type semiconductor device in which the upper surfaces of the diffusion barrier structure 52 and the bottom electrode 54 are concave. In some embodiments, the upper surfaces of the top electrode 60, the cap layer 58, and the switching layer 56 may be non-planar. For example, the upper surfaces of the top electrode 60, the cap layer 58, and the switching layer 56 may be concave. In such embodiments, the diffusion barrier structure 52 may have a uniform thickness. When the diffusion barrier structure 52 is a single-layer structure, the diffusion barrier structure 52 may have a uniform thickness. When the diffusion barrier structure 52 is a multi-layer structure, all layers of the diffusion barrier structure 52 (e.g., TaN layers 52a and 52c and Ta layer 52b) may have a uniform thickness.

[0080] In some embodiments, semiconductor devices 5 and 6 may be driven by transistor devices. For example, bottom metallization layer 721 may be electrically connected to the drain electrode of the transistor device. The source electrode of the transistor device may be electrically connected to the source line, and the gate electrode of the transistor device may be electrically connected to the word line. Top metallization layer 80 may be electrically connected to the bit line. In other embodiments, semiconductor devices 5 and 6 may be driven by a pair of transistor devices. For example, bottom metallization layer 721 may be electrically connected to the common drain electrode of the transistor device. The source electrode of the pair of transistor devices may be electrically connected to the source line, and the gate electrode of the transistor device may be electrically connected to the word line. Top metallization layer 80 may be electrically connected to the bit line.

[0081] refer to Figures 11D to 14 , using the CBRAM semiconductor devices 5 and 6, an initialization operation may be performed to migrate active metal ions from the cap layer 58 to the switching layer 56, thereby forming a metal bridge, i.e., a conductive filament, in the switching layer 56. The semiconductor devices 5 and 6 may also undergo a baking operation to verify data retention at high temperatures. After the initialization operation, the semiconductor devices 5 and 6 may be operated in a reset state or in a set state. In the reset operation, a reset voltage is applied across the top electrode 60 and the bottom electrode 54 to switch the switching layer 56 from a lower resistance state (LRS) to a high resistance state (HRS), thereby destroying the conductive filament to increase the resistivity. In the set operation, a set voltage is applied across the top electrode 60 and the bottom electrode 54 to switch the switching layer 56 from a high resistance state to a lower resistance state, thereby reforming the conductive filament to reduce the resistivity.

[0082] During the set operation, a conductive filament may be formed at a temperature greater than approximately 900° C. due to Joule heating. It was found that in some comparative embodiments employing a TaN layer used as a diffusion barrier layer between the bottom electrode and the bottom metallization layer, heat was accumulated in the bottom electrode due to the poor thermal conductivity (less than approximately 3.4) of the TaN layer. In detail, because the thermal conductivity of the TaN layer is less than approximately 3.4, heat cannot be effectively dissipated and may accumulate in the interface between the bottom electrode and the switching layer. Therefore, the metal oxide bond is easily broken due to heat accumulation, and the conductive filament cannot be broken during the reset operation. In other words, a large leakage path may be formed and the CBRAM is not easily closed, and thus the bit error rate (BER) is increased.

[0083] In order to alleviate the BER problem, a diffusion barrier structure 52 is provided. As described above, the conductivity of the diffusion barrier structure 52 is greater than approximately 20 W / mK; therefore, the heat generated during the set operation can be easily dissipated from the interface IN1 between the switching layer 56 and the bottom electrode 54 to the interface IN2 between the diffusion barrier structure 52 and the bottom metallization layer 721, and thus the heat accumulation at the interface IN1 is reduced. Therefore, the conductive filament can be easily destroyed in the reset operation and the BER can be reduced.

[0084] It should be noted that the diffusion barrier structure 52 in the semiconductor devices 5 and 6 has potential problems in at least two aspects: metal diffusion barrier and thermal conductivity. For example, TaN can form an effective metal diffusion barrier, but suffers from poor thermal conduction. Therefore, a Ta layer can be disposed above a TaN layer or sandwiched between TaN layers to provide effective heat dissipation. It should be noted that a Ta layer itself is not a preferred diffusion barrier structure because Ta is easily oxidized and thus the resistivity can increase.

[0085] In some embodiments of the present invention, the semiconductor device includes a diffusion barrier structure interposed between the bottom electrode and the bottom metallization layer. The material of the diffusion barrier structure is selected to provide diffusion barrier function and heat conduction. Therefore, the diffusion barrier layer helps to hinder metal diffusion and heat dissipation, and alleviates the BER problem.

[0086] Fig.15 9 is a flow chart illustrating a method for fabricating a semiconductor device according to various aspects of one or more embodiments of the present invention. The method 900 begins with operation 910, where a bottom electrode is formed over a substrate. The method 900 continues with operation 920, where a switching layer is formed over the bottom electrode. The method 900 continues with operation 930, where a metal diffusion barrier layer is formed over the switching layer. The method 900 continues with operation 940, where a cap layer is formed over the metal diffusion barrier layer. The method 900 continues with operation 950, where a top electrode is formed over the cap layer.

[0087] The method 900 is merely an example of forming a conductive bridge random access memory (CBRAM) and is not intended to limit the embodiments of the present invention beyond the scope explicitly recited in the claims. Additional operations may be provided before, during, and after the method 900, and some of the described operations may be replaced, eliminated, or moved for additional embodiments of the method.

[0088] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D is a schematic diagram of various stages in the fabrication of a semiconductor device according to one or more embodiments of the present invention. To simplify the description and to facilitate comparison of each embodiment of the present invention, the same components in each of the following embodiments are labeled with the same numbers and have similar materials, and therefore the details are omitted for brevity. To facilitate comparison of the embodiments, the following description will detail the differences among the different embodiments and the same features will not be repeated. Fig.16A, receiving substrate 50. A bottom interconnect structure 72 may be formed over substrate 50. In some embodiments, bottom interconnect structure 72 includes a bottom metallization layer 721 and a bottom ILD layer 722 laterally surrounding bottom metallization layer 721. A dielectric layer 74 is formed over substrate 50. Dielectric layer 74 may include an opening 74R exposing a portion of bottom metallization layer 721.

[0089] refer to Fig.16A In operation 910, a bottom electrode 54 is formed over the substrate 50. Fig.16A As shown in FIG. 5 , the bottom electrode 54 contacts the bottom metallization layer 721. In some embodiments, the bottom electrode 54 is conformally formed in the opening 74R and includes a uniform thickness (eg, Fig.17 In other embodiments, the bottom electrode 54 may be formed to fill the opening 74R and thus may have a substantially flat upper surface, such as Fig.16A As shown in .

[0090] In operation 920, a switching layer 56 is formed over the bottom electrode 54. The switching layer 56 may include a data storage region configured to store data. As described above, the variable resistance of the data storage region may represent a unit of data, such as a data bit.

[0091] Still refer to Fig.16A In operation 930, a metal diffusion barrier layer 57 is formed over the switching layer 56. The material of the metal diffusion barrier layer 57 may include a metal, a metal nitride, or a combination thereof. In some embodiments, the metal diffusion barrier layer 57 may include a metal, and the metal includes at least one of iridium (Ir), ruthenium (Ru), platinum (Pt), tantalum (Ta), titanium (Ti), titanium tungsten (TiW), and tungsten (W). In other embodiments, the metal diffusion barrier layer 57 may include a metal nitride, and the metal nitride may include at least one of titanium tungsten nitride (TiW(N)), titanium nitride (TiN), and tungsten nitride (WN). In some embodiments, the thickness of the metal diffusion barrier layer 57 is between approximately 2 angstroms and approximately 25 angstroms, but the embodiments of the present invention are not limited thereto. The metal diffusion barrier layer 57 helps to hinder the diffusion of metal ions into the switching layer 56. It should be noted that in some comparative embodiments, when the thickness of the metal diffusion barrier layer is less than 2 angstroms, the metal diffusion barrier layer is too thin to be an effective barrier layer. However, in other comparative embodiments in which the thickness of the metal diffusion barrier layer was greater than 25 angstroms, the metal diffusion barrier layer was so thick that the resistance of the semiconductor device was undesirably increased.

[0092] Still refer to Fig.16AIn operation 940, a cap layer 58 is formed over the metal diffusion barrier layer 57. As described above, the cap layer 58 is referred to as a metal reservoir layer, which is configured as an active metal reservoir to store active metal ions. In operation 950, a top electrode 60 is formed over the cap layer 58. In some embodiments, the bottom electrode 54, the switching layer 56, the metal diffusion barrier layer 57, the cap layer 58, and the top electrode 60 may have substantially flat upper surfaces.

[0093] refer to Fig. 16B , the top electrode 60, the cap layer 58, the metal diffusion barrier layer 57, the switching layer 56, and the bottom electrode 54 are patterned by etching. In some embodiments, etching may include dry etching, wet etching, or a combination thereof. The top electrode 60, the cap layer 58, the metal diffusion barrier layer 57, the switching layer 56, and the bottom electrode 54 may be patterned by one etching operation or by multiple etching operations. In some embodiments, the width of the bottom electrode 54 and the width of the switching layer 56 may be greater than the width of the cap layer 58, the width of the metal diffusion barrier layer 57, and the width of the top electrode 60, but embodiments of the present invention are not limited thereto. In such embodiments, a portion of the upper surface of the switching layer 56 may be exposed, but embodiments of the present invention are not limited thereto.

[0094] refer to Fig. 16C , a passivation layer 76 may be optionally formed. In some embodiments, the passivation layer 76 is insulating. In some embodiments, the passivation layer 76 covers the upper surface of the top electrode 60. In some embodiments, the passivation layer 76 covers the sidewalls of the top electrode 60, the sidewalls of the cap layer 58, and the sidewalls of the metal diffusion barrier layer 57. In some embodiments, the passivation layer 76 further covers a portion of the top surface of the switching layer 56.

[0095] Still refer to Fig. 16C , a top ILD layer 78 is formed over the substrate 50 to cover the passivation layer 76. Fig.16D , the top ILD layer 78 and the passivation layer 76 may be patterned by, for example, photolithography and etching techniques to expose a portion of the top electrode 60. In some embodiments, a top metallization layer 80 is formed and electrically connected to the top electrode 60 to form the semiconductor device 7. The semiconductor device 7 is a planar type semiconductor device, in which the top electrode 60, the cap layer 58, the metal diffusion barrier layer 57, the switching layer 56, and the bottom electrode 54 may have a planar upper surface.

[0096] Please refer to Fig.17 , which is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention. Fig.17 As shown in Fig. 16CCompared to the semiconductor device 7 of FIG. 5 , the semiconductor device 8 is a non-planar type semiconductor device in which the upper surface of the bottom electrode 54 is concave. In some embodiments, the upper surfaces of the top electrode 60, the cap layer 58, the metal diffusion barrier layer 57, and the switching layer 56 may be non-planar. For example, the upper surfaces of the top electrode 60, the cap layer 58, the metal diffusion barrier layer 57, and the switching layer 56 may be concave. In such embodiments, the bottom electrode 54 may have a uniform thickness.

[0097] As described above, semiconductor devices 7 and 8 may be driven by transistor devices. For example, bottom metallization layer 721 may be electrically connected to the drain electrode of the transistor device. The source electrode of the transistor device may be electrically connected to the source line, and the gate electrode of the transistor device may be electrically connected to the word line. Top metallization layer 80 may be electrically connected to the bit line. In other embodiments, semiconductor devices 7 and 8 may be driven by a pair of transistor devices. For example, bottom metallization layer 721 may be electrically connected to the common drain electrode of the transistor device. The source electrode of the pair of transistor devices may be electrically connected to the source line, and the gate electrode of the transistor device may be electrically connected to the word line. Top metallization layer 80 may be electrically connected to the bit line.

[0098] Please refer to Fig.18A and Fig.18B , which is a graph of simulation results of LRS / HRS windows according to comparative embodiments and some embodiments of the present invention. The initialization operation, baking operation (for retention), setting operation and reset operation of semiconductor devices 7 and 8 may be similar to the operations described above, and therefore such details are omitted for the sake of brevity. It was found that undesirable metal ion diffusion may occur during the retention and setting operations due to the temperature reaching the ionization temperature of the metal. For example, the ionization temperature of Al is approximately 87.8°C, the ionization temperature of Cu is approximately 69.3°C, and the ionization temperature of Ag is approximately 89.6°C. This means that such metals may be ionized and diffused at the ionization temperature. In some embodiments, retention occurs at approximately 125°C and the setting operation may be performed on the conductive filament at a temperature greater than approximately 900°C, and therefore some metal ions may be ionized and diffused from the cap layer 58 to the switching layer 16, thereby adversely damaging the conductive filament and the set / reset cycle. As Fig.18A As shown in FIG. 1 , in such comparative embodiments, the current in the high resistance state and the current in the low resistance state may be the same. As is well known, LRS and HRS correspond to a logic "1" state and a logic "0" state, respectively (or vice versa), and the presence of the same current at both LRS and HRS indicates retention failure.

[0099] To mitigate the retention failure problem, a metal diffusion barrier layer 57 is provided. The metal diffusion barrier layer 57 helps to hinder the diffusion of metal ions from the metal reservoir layer 58 to the switching layer 56, and thus the conductive filaments can be formed at the LRS and destroyed at the HRS, as expected during cycling and retention. In some embodiments, it is found that the current ratio of the LRS to the HRS (sometimes referred to as the on-off ratio) can be greater than 10 4 ,like Fig.18B As shown in . Therefore, the retention failure problem can be alleviated and leakage can be reduced.

[0100] In some embodiments, a metal diffusion barrier layer is interposed between the cap layer and the switching layer. The material of the diffusion barrier layer is selected to hinder metal diffusion from the metal reservoir layer to the switching layer during cycling and retention. The diffusion barrier layer can improve the cycling and retention performance of semiconductor devices.

[0101] In some embodiments, a semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode above the bottom electrode, a switching layer, and a cap layer. The bottom electrode is above the diffusion barrier structure. The top electrode is above the bottom electrode. The switching layer is between the bottom electrode and the top electrode and is configured to store data. The cap layer is between the top electrode and the switching layer. The thermal conductivity of the diffusion barrier structure is greater than approximately 20 W / mK.

[0102] In some embodiments, a semiconductor device includes a bottom electrode, a top electrode, a switching layer, a metal reservoir layer, and a metal diffusion barrier layer. The top electrode is above the bottom electrode. The switching layer is between the bottom electrode and the top electrode and is configured to store data. The metal reservoir layer is between the switching layer and the top electrode. The metal diffusion barrier layer is between the metal reservoir layer and the switching layer, wherein the metal diffusion barrier layer is configured to hinder metal ions from diffusing from the metal reservoir layer to the switching layer.

[0103] In some embodiments, a method for making a semiconductor device includes the following operations. Forming a dielectric layer over a substrate, wherein the dielectric layer has an opening formed therein. Forming a diffusion barrier structure in the opening. Forming a bottom electrode over the diffusion barrier structure. Forming a switching layer over the bottom electrode. Forming a metal reservoir over the switching layer. Forming a top electrode over the metal reservoir. The thermal conductivity of the diffusion barrier structure is greater than approximately 20 W / mK.

[0104] The foregoing summarizes the structures of several embodiments so that those skilled in the art can better understand aspects of the embodiments of the present invention. Those skilled in the art should understand that they can easily use the embodiments of the present invention as a basis for designing or modifying other processes and structures that implement the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also be aware that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present invention, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present invention.

[0105] Explanation of symbols

[0106] 1 Semiconductor devices

[0107] 2 Semiconductor devices

[0108] 3 Semiconductor devices

[0109] 5 Semiconductor devices

[0110] 6 Semiconductor devices

[0111] 7 Semiconductor devices

[0112] 8 Semiconductor devices

[0113] 10 Substrate

[0114] 12 Bottom electrode

[0115] 14 Diffusion barrier layer

[0116] 16 Switching Layers

[0117] 16F Conductive filament

[0118] 16S ion

[0119] 16V Empty

[0120] 18 Ion reservoir

[0121] 20 Cover layer

[0122] 22 Top electrode

[0123] 32 Bottom interconnect structure

[0124] 34 Dielectric layer

[0125] 34R Open

[0126] 36 Mask layer

[0127] 38 Passivation layer

[0128] 40 Top interlayer dielectric (ILD) layer

[0129] 42 Top metallization layer

[0130] 44 Top interconnect structure

[0131] 50 substrate

[0132] 52 Diffusion barrier structure

[0133] 52a First Tantalum Nitride (TaN) layer

[0134] 52b Tantalum (Ta) layer

[0135] 52c Second Tantalum Nitride (TaN) layer

[0136] 54 Bottom electrode

[0137] 56 Switch Layer

[0138] 57 Metal Diffusion Barrier Layer

[0139] 58 Cover layer

[0140] 60 Top electrode

[0141] 72 Bottom interconnect structure

[0142] 74 Dielectric layer

[0143] 74R Open

[0144] 76 Passivation layer

[0145] 78 Top interlayer dielectric (ILD) layer

[0146] 80 Top metallization layer

[0147] 100 Method / Semiconductor Device

[0148] 110 Operation

[0149] 120 Operations

[0150] 130 Operations

[0151] 140 Operations

[0152] 321 Bottom metallization layer

[0153] 322 Bottom interlayer dielectric (ILD) layer

[0154] 500 Methods

[0155] 510 Operation

[0156] 520 Operation

[0157] 521 Part 1

[0158] 522 Part 2

[0159] 530 Operation

[0160] 540 Operation

[0161] 550 Operations

[0162] 560 Operations

[0163] 721 Bottom metallization layer

[0164] 722 Bottom interlayer dielectric (ILD) layer

[0165] 900 Methods

[0166] 910 Operation

[0167] 920 Operation

[0168] 930 Operation

[0169] 940 Operation

[0170] 950 Operation

[0171] IN1 interface

[0172] IN2 interface

Claims

1. A semiconductor device comprising: Diffusion barrier structure; a bottom electrode above the diffusion barrier structure; a top electrode above the bottom electrode; a switching layer between the bottom electrode and the top electrode and configured to store data; and a cap layer between the switching layer and the top electrode, wherein the thermal conductivity of the diffusion barrier structure is greater than 20 Watts / meter Kelvin W / mK, and The diffusion barrier structure includes a first tantalum nitride TaN layer and a tantalum Ta layer on the first tantalum nitride TaN layer, and the tantalum Ta layer is adjacent to the bottom electrode. 2 . The semiconductor device of claim 1 , wherein a thermal conductivity of the bottom electrode is greater than the thermal conductivity of the barrier structure. The semiconductor device of claim 1 , wherein the diffusion barrier structure comprises a uniform thickness. 4 . The semiconductor device according to claim 1 , wherein the diffusion barrier structure comprises a first portion and a second portion surrounding the first portion, and a thickness of the first portion is greater than a thickness of the second portion. The semiconductor device according to claim 1 , wherein the diffusion barrier structure comprises a single-layer structure. The semiconductor device according to claim 1 , wherein the diffusion barrier structure comprises titanium nitride (TiN) or a two-dimensional (2D) material.

7. The semiconductor device according to claim 6, wherein the 2D material comprises graphene, molybdenum disulfide MoS2 or hexagonal boron nitride h-BN. 8 . The semiconductor device according to claim 1 , wherein the diffusion barrier structure comprises a multi-layer structure. 9 . The semiconductor device of claim 1 , wherein the switching layer directly contacts an upper surface of the bottom electrode. 10 . The semiconductor device according to claim 1 , wherein a sidewall of the switching layer has an inclined portion, a vertical portion, and a horizontal portion, the horizontal portion being coupled with the vertical portion and the inclined portion. 11 . The semiconductor device of claim 1 , wherein the diffusion barrier structure further comprises a second tantalum nitride (TaN) layer over the first tantalum nitride (TaN) layer, and the tantalum Ta layer is disposed between the first tantalum nitride (TaN) layer and the second tantalum nitride (TaN) layer. 12 . The semiconductor device according to claim 11 , wherein a thickness of the tantalum Ta layer is greater than a sum of a thickness of the first tantalum nitride TaN layer and a thickness of the second tantalum nitride TaN layer.

13. A semiconductor device comprising: Bottom electrode; a top electrode above the bottom electrode; a switching layer between the bottom electrode and the top electrode and configured to store data; a metal reservoir layer between the switching layer and the top electrode; and A metal diffusion barrier layer is between the metal reservoir layer and the switching layer, wherein the metal diffusion barrier layer hinders metal ions from diffusing from the metal reservoir layer to the switching layer. 14 . The semiconductor device according to claim 13 , wherein a material of the metal diffusion barrier layer comprises metal, metal nitride or a combination thereof. 15 . The semiconductor device according to claim 14 , wherein the metal comprises at least one of iridium (Ir), ruthenium (Ru), platinum (Pt), tantalum (Ta), titanium (Ti), tungsten (TiW), and tungsten (W). 16 . The semiconductor device according to claim 14 , wherein the metal nitride comprises at least one of titanium tungsten nitride (TiW(N), titanium nitride (TiN), and tungsten nitride (WN).

17. The semiconductor device of claim 13, wherein the thickness of the metal diffusion barrier layer is between 2 angstroms and 25 angstroms.

18. A method for making a semiconductor device, comprising: forming a dielectric layer over a substrate, wherein the dielectric layer has an opening formed therein; forming a diffusion barrier structure in the opening; forming a bottom electrode above the diffusion barrier structure; forming a switching layer over the bottom electrode; forming a metal reservoir above the switching layer; and forming a top electrode above the metal reservoir, wherein the thermal conductivity of the diffusion barrier structure is greater than 20 Watts / meter Kelvin W / mK, and The diffusion barrier structure includes a first tantalum nitride TaN layer and a tantalum Ta layer on the first tantalum nitride TaN layer, and the tantalum Ta layer is adjacent to the bottom electrode. 19 . The method of claim 18 , wherein the diffusion barrier structure is conformally formed in the opening, and a portion of a top surface of the diffusion barrier structure is lower than a top surface of the dielectric layer.

20. The method of claim 18, wherein the diffusion barrier structure fills the opening and a top surface of the diffusion barrier structure is above a top surface of the dielectric layer.

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