Neural network random number generator shared circuit, shared method, and processor chip

Abstract

The present invention discloses a neural network random number generator sharing circuit, sharing method, and processor chip, which belongs to the field of new computing technology and is applied to artificial neural network circuits; it includes a random number module, a bit stream generation module, a random calculation module, and a data storage module. The random calculation module includes a plurality of neural computing units, and the neural computing unit includes a multiplication circuit, a scaling addition circuit, and an activation function circuit. The scaling addition circuit is based on a parallel accumulator, which can reduce the requirements of the operation circuit for the non-correlation of the input bit stream, thereby enabling the random number generator to be shared in the entire artificial neural network circuit, and a complete neural network only needs to use one random number generator. Compared with the existing neural network circuit based on random calculation, the present invention greatly saves hardware resources, reduces power consumption, and improves the calculation accuracy.

Description

Technical Field

[0001] The present invention belongs to the field of novel computing technology, and in particular relates to a neural network random number generator (RNG) sharing circuit, a sharing method, and a processor chip, and specifically relates to a neural network random number generator sharing circuit based on stochastic computing (SC), which is applied to an artificial neural network (ANN) circuit. Background Art

[0002] With the development of big data industry and artificial intelligence, digital signal processing systems are becoming more and more complex, which requires a large number of specific operations such as floating-point multiplication and addition, convolution, etc. Conventional processor chips are inefficient when performing these operations, consume a lot of energy, and cannot support the required large-scale parallel computing needs.

[0003] Random computing circuits have been a research hotspot in recent years. They use random bit streams to represent numerical values ​​for operations. Unipolar and bipolar representations are commonly used for bit streams in random computing. Assuming that the length of the bit stream sequence is m, and there are n1 "1s", then its probability P = n1 / m. When the unipolar representation is used, the numerical value represented is P; when the bipolar representation is used, the numerical value represented is 2P–1. In this data representation system, the operations between data can be simplified to simple logic gate operations. The AND gate can be used to complete the unipolar multiplication operation, and the XNOR gate can be used to complete the bipolar multiplication operation. For addition operations, traditional random computing adders are generally composed of dual-way data selectors. By applying a highly random sequence with a probability of 0.5 at the selection end, the two input bit stream data A and B are recombined to obtain an output bit stream with a value of (A+B) / 2. It is worth noting that in the random computing multiplication and addition operation circuits, the input bit streams must be non-correlated to ensure the accuracy of the operation results.

[0004] Artificial neural network is an emerging data processing technology. It abstracts the human brain neural network from the perspective of information processing and establishes a mathematical model. The core part of the artificial neural network is the artificial neuron. Each neuron receives the output from neurons in other network layers, multiplies them by weight parameters, sums them, and adds offset parameters. Finally, the sum is applied to the activation function before passing it to the next one or more neurons. The multi-layer interconnected neuron structure constitutes a complete artificial neural network, which can be applied to image classification, speech recognition and other fields.

[0005] By combining random computing with artificial neural networks, a large number of multiplication and addition operations involved in the network can be implemented using a single logic gate and data selector, which greatly saves hardware resources and reduces circuit power consumption.

[0006] However, in the prior art, the neural network circuit based on random calculation has two defects:

[0007] First, although the cost of random computing circuits is low, the cost of conversion circuits is high. A random number generator is needed to convert traditional binary data into a random bit stream, and a counter is needed to convert the network operation results into binary output. The large number of neural network computing nodes causes the conversion circuit area to account for about 80% of the entire operation circuit, reducing the cost advantage of the random computing operation part.

[0008] Second, the existing technology uses data selectors to complete addition operations in the network, which has high requirements for the randomness of the selection sequence and the non-correlation between the input bit streams. At the same time, the addition of a large number of computing node data requires the cascading use of multiple data selectors, and the errors in the summation results continue to accumulate, which significantly reduces the recognition rate of the entire neural network.

[0009] Therefore, a new circuit structure is needed to further reduce the resource occupancy rate of the conversion circuit, reduce the error of random calculation addition operation, and improve the recognition rate of the network. Summary of the invention

[0010] In response to the problems existing in the prior art, the present invention provides a neural network random number generator shared circuit, sharing method, and processor chip, and specifically relates to a neural network random number generator shared circuit based on random calculation, which reduces resource usage while optimizing the circuit architecture.

[0011] The present invention is implemented as follows: a neural network random number generator shared circuit based on random calculation includes a random number module, a bit stream generation module, a random calculation module and a data storage module; the random number module is used to generate random numbers with a fixed bit width; the bit stream generation module is used to convert traditional binary data into bit stream data; the random calculation module is used to complete matrix multiplication, matrix convolution and activation function operations in artificial neural networks; the data storage module is used to store network weight parameters and offset parameters.

[0012] Furthermore, the random calculation module includes multiple neural computing units, and a single neural computing unit includes a multiplication circuit, a scaling addition circuit and an activation function circuit, which performs operations of first multiplying and then summing, then scaling and finally activating the input bit stream data in the probability domain; when using the unipolar representation, the multiplication circuit is implemented using an AND gate, and when using the bipolar representation, the multiplication circuit is implemented using an XNOR gate; the scaling addition circuit is based on a parallel accumulator, includes multiple bit stream input ports, and can add multiple input data in the same clock cycle. When the accumulation process is completed, the operation result is enlarged or reduced by selecting a suitable scaling factor according to the operation result, so that the value range meets the input requirements of the next level bit stream generation module; the activation function circuit includes but is not limited to the use of a linear rectifier function (Rectified Linear Unit, ReLU), which is used to activate neurons in the artificial neural network and add nonlinear characteristics to the network.

[0013] Furthermore, the random number module has two random number outputs, which are shared in the entire network. The first random number is connected to the input data bit stream generator array of each network layer, and the second random number is connected to the weight parameter bit stream generator array of each network layer.

[0014] Furthermore, the random number module is composed of an n-bit wide random number generator and a multiplexing circuit; the random number generator can be a pseudo-random number generator, such as a linear feedback shift register (LFSR), or a true random number generator, such as a random number generator based on circuit noise, a polymorphic random number generator based on electron spin, etc.; if the random number generator is a pseudo-random number generator, the shift register is used to delay the random number generated by the pseudo-random number generator for several clock cycles as one random number output of the random number module, and the random number generated by the pseudo-random number generator without delay processing is used as another random number output of the random number module; if the random number generator is a true random number generator, the random number generated by the true random number generator is divided into two groups according to odd clock cycles and even clock cycles, and used as two random number outputs of the random number module respectively.

[0015] Furthermore, the bit stream generation module includes two groups of bit stream generator arrays, each bit stream generator is composed of an n-bit wide digital comparator, and the n-bit wide digital comparator includes two n-bit wide input data terminals and a 1-bit wide data output terminal; one of the n-bit wide input data terminals is a fixed terminal, connected to n-bit wide traditional binary data, and the other is a random terminal, connected to n-bit wide random data; the 1-bit wide data output terminal outputs the comparison result of the two n-bit wide input data, if the fixed end data is greater than or equal to the random end data, then "1" is output, otherwise "0" is output; repeat the comparison m times, m>0, then the n-bit traditional binary data of the fixed end can be converted into bit stream data with a length of m bits.

[0016] Furthermore, the bitstream generation module includes two groups of bitstream generator arrays, the first group converts input data into a bitstream sequence, the fixed end of each bitstream generator is respectively connected to each input data in the network layer, and the random end is commonly connected to the first random number of the random number module; the second group converts weight parameters into a bitstream sequence, the fixed end of each bitstream generator is respectively connected to each weight parameter in the network layer, and the random end is commonly connected to the second random number of the random number module.

[0017] Another object of the present invention is to provide a data sharing method for a neural network random number generator sharing circuit based on random calculation, the data sharing method for a neural network random number generator sharing circuit based on random calculation comprising:

[0018] Use a random number generator and multiplexing circuit to generate two random number outputs in the same clock cycle;

[0019] The two random number outputs are connected to two groups of bit stream generator arrays respectively, wherein the first group of the bit stream generator arrays converts the input data of the neural network operation layer, and the second group converts the weight parameters of the neural network operation layer;

[0020] The input data bit stream and the weight parameter bit stream generated by the bit stream generator array are respectively multiplied by a random calculation multiplication circuit;

[0021] The output bit streams of each random calculation multiplication circuit are summed up through a scaling adder. The adder is based on a parallel accumulator, which adds multiple input bit streams simultaneously and scales the results to a suitable range through a shift operation. After an activation operation, the output data of the neural network calculation layer is generated.

[0022] Further, when the random number generator is a pseudo-random number generator, the method for generating two random number outputs in the same clock cycle includes:

[0023] By using a linear feedback shift register, a pseudo-random number generator generates an n-bit wide random number per clock cycle; a shift register unit is added to the output of the pseudo-random number generator, and the output random number is delayed for several clock cycles before being output; when the delay time is t clock cycles and the functional function of the pseudo-random number generator is y=f(x), at time x1, the delayed output of the pseudo-random number generator is f(x1-t), the original output is f(x1), and the delayed output sequence is non-correlated with the original sequence; after time t, the pseudo-random number generator can output two different random numbers in each clock cycle.

[0024] Further, when the random number generator is a true random number generator, the method for generating two random number outputs in the same clock cycle includes:

[0025] The output random number sequence of a true random number generator is converted into two unrelated random number sequences by using the time division multiplexing method; through the three-state gate array, the true random number generator generates one output and stores it in the odd clock cycle, and generates another output and stores it in the even clock cycle;

[0026] When the clock frequency of the true random number generator is twice that of the neural network operation clock, the random number module can output two different random numbers in each neural network operation clock cycle.

[0027] Furthermore, the artificial neural network operation layer based on random calculation includes:

[0028] The fully connected layer contains k neurons. 1 ~In j Out is the input data of this layer; 1 ~Out k is the output data of this layer; W 11 ~W jk are weight parameters, corresponding to the weight relationship between j inputs and k neurons; b 1 ~b k is the offset parameter, corresponding to k neurons; the operation completed by the fully connected layer is expressed as:

[0029]

[0030] Among them, 1≤i≤k, Active(x) is the activation function;

[0031] Convolution layer, let the convolution operation input feature map be In and the filter be W 1 ~W k , the offset is b 1 ~b k , then the output feature map O u t is:

[0032] Out i =Active(In*W i +b i );

[0033] Among them, 1≤i≤k, Active(x) is the activation function, and “*” is the convolution operator.

[0034] Another object of the present invention is to provide a processor chip, which carries the neural network random number generator sharing circuit based on random calculation and implements the data sharing method of the neural network random number generator sharing circuit based on random calculation.

[0035] Another object of the present invention is to provide an information data processing terminal, which is equipped with the processor chip and is used to implement the data sharing method of the neural network random number generator sharing circuit based on random calculation.

[0036] Compared with the prior art solutions, the present invention has the following beneficial effects:

[0037] The present invention introduces a scaling addition circuit, which utilizes a parallel accumulator to simultaneously and accurately count the bit stream data of multiple multiplication outputs, and can efficiently scale the summation result, thereby improving the calculation accuracy and reducing the requirement of random calculation for the non-correlation of the input bit stream, so that the random number generator can be shared in the entire artificial neural network circuit, and the network operation only needs two non-correlated random numbers.

[0038] Furthermore, for two different types of random number generators, namely pseudo-random number generators and true random number generators, the present invention proposes a circuit structure that processes the output of a single random number generator into two random number outputs, and the two random numbers outputted have a high degree of non-correlation, so that the number of random number generators used in the entire network is reduced to one, which greatly saves the area of ​​the bit stream conversion circuit, saves hardware resources, reduces circuit power consumption, and improves the recognition accuracy of traditional neural networks based on random calculations. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a shared circuit framework diagram of a neural network random number generator based on random calculations.

[0040] Figure 2 This is a schematic diagram of the random number module structure based on a pseudo-random number generator.

[0041] Figure 3 This is a schematic diagram of the random number module structure based on a true random number generator.

[0042] Figure 4This is a schematic diagram of the fully connected layer structure of a neural network based on random computing.

[0043] Figure 5 This is a schematic diagram of the scaling adder structure.

[0044] Figure 6 This is a schematic diagram of the convolution operation structure based on random calculation. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0046] In view of the problems existing in the prior art, the present invention provides a neural network random number generator sharing circuit, sharing method, and processor chip. Based on the random computing theory, a scaling adder circuit is used to replace the traditional data selector-based adder circuit to improve the calculation accuracy and reduce the non-correlation requirements, so that the random number generator can be highly shared, and a method for a single random number generator to generate two non-correlated random number outputs is proposed, reducing the number of random number generators in the entire neural network circuit to one.

[0047] The present invention is described in detail below with reference to the accompanying drawings and implementation examples.

[0048] Implementation examples:

[0049] The shared circuit framework of the neural network random number generator based on random calculation proposed in the present invention is as follows Figure 1 As shown. In the figure, the input data In and the output data O u t, weight parameter W and offset parameter b are all matrix data, not single variables. The whole circuit includes a random number module, a bit stream generation module, a random calculation module and a data storage module. The random number module is based on a random number generator circuit, which can generate two random numbers with fixed bit widths per clock cycle through a multiplexing circuit, and has good non-correlation; the bit stream generation module is based on a digital comparator circuit, which is used to convert traditional binary data into bit stream data; the random calculation module includes an operation unit based on random calculation theory, which is used to complete matrix multiplication, matrix convolution and activation function operations in artificial neural networks; the data storage module is used to store network weight parameters W and offset parameters b.

[0050] As shown in the figure, the bitstream generation module includes two groups of bitstream generator arrays, the two outputs of the random number module are connected to the two groups of bitstream generator arrays respectively, the input data In of the circuit is connected to the first group of bitstream generator arrays, and the weight parameter W is connected to the second group of bitstream generator arrays. The outputs of the two groups of bitstream generator arrays and the offset parameter b are connected to the random calculation module, and the calculation results are used as the output of the circuit. u t.

[0051] The random number module is composed of a random number generator and a multiplexing circuit. The present invention proposes different multiplexing methods for different types of random number generators. Figure 2 The figure is a schematic diagram of the random number module structure based on the pseudo-random number generator. Using the linear feedback shift register, the pseudo-random number generator can generate an n-bit wide random number per clock cycle. Adding a shift register unit to its output is equivalent to delaying its output random number for several clock cycles before outputting it. The delay period depends on the number of shift registers. Assuming the delay time is t cycles, the pseudo-random number generator function is y=f(x). At time x1, the random number module outputs random number 1 as f(x1-t) and random number 2 as f(x1). The output sequence after the delay has a good non-correlation with the original sequence. Therefore, after time t, the random number module can output two different random numbers in each clock cycle.

[0052] Attached Figure 3 The diagram is a schematic diagram of the random number module structure based on a true random number generator. Since there is no relationship between the random numbers generated by the true random number generator, the output random number sequence of a true random number generator can be converted into two unrelated random number sequences by using the time division multiplexing method. More specifically, in odd clock cycles, the true random number generator outputs from the upper branch in the figure, and in even clock cycles, the true random number generator outputs from the lower branch in the figure. When the clock frequency of the true random number generator is twice the operating clock of the neural network, the random number module can output two different random numbers in each neural network operation clock cycle. In summary, only one random number generator is used to allow the random number module to generate two random number outputs, and the output sequences have good non-correlation.

[0053] Commonly used computing layers in neural networks are fully connected layers and convolutional layers. Figure 4 This is a schematic diagram of the structure of a fully connected layer of a neural network based on random computing. The fully connected layer has a total of k neurons. 1 ~In j Out is the input data of this layer; 1 ~Out k is the output data of this layer; W 11 ~W jkare weight parameters, corresponding to the weight relationship between j inputs and k neurons; b 1 ~b k is the offset parameter, corresponding to k neurons. The operation completed by this fully connected layer can be expressed as:

[0054]

[0055] The dotted box on the right side of the figure is a random computing module, which contains multiple neural computing units to complete multiplication, summation, shift scaling and ReLU activation function operations. In and W correspond to two groups of bit stream generation modules, the first group is the input data bit stream generation module, whose positive end (fixed end) is connected to each input data in the network layer, and the negative end (random end) is connected to the first random number output of the random number module; the second group is the weight parameter bit stream generation module, whose positive end is connected to each weight parameter in the network layer, and the negative end is connected to the second random number output of the random number module.

[0056] After the input data In and the weight parameter W are converted into a bit stream, they enter the random calculation module. First, multiplication is performed according to the above formula. Since the two output random number sequences of the random number module are unrelated, the bit streams of the input terminals In and W of each multiplier are unrelated. After the multiplication, there is a summation circuit. It is worth noting that since the multipliers of the previous stage use the same random number module, there is a correlation between any two multiplication result bit streams. If the adder is implemented using a data selector circuit, a large operation error will be generated. Therefore, it is necessary to use an adder circuit that does not require high correlation of the input bit stream, so that the random number generator sharing solution proposed by the present invention becomes possible.

[0057] Attached Figure 5 The diagram is a schematic diagram of a scaling adder, which is based on an accumulator. The positions of "0" and "1" in the input bit stream can be arbitrary, and there is no requirement for the correlation of the bit stream. At the same time, it can accurately sum. After applying this adder to a neural network based on random calculation, each random calculation multiplier can use the same random number module, so that the entire network uses only one random number generator. The adder shown in the figure is based on a unipolar representation with a signed bit, S is the sign bit of the data, and M is the absolute value of the data. If the sign bit of the input bit stream is "1", it is directed to the negative accumulator by a three-state gate, and if it is "0", it is directed to the positive accumulator by a three-state gate. After all the bit streams are accumulated, the comparator outputs the sign bit of the summation result, and the absolute value of the result is obtained by subtracting the two accumulators. The scaling function is realized by a data shift operation, and the summation result is adjusted to n-bit wide data, which is convenient for the bit stream generator of the next layer of the network to compare and convert.

[0058] Attached Figure 6It is a schematic diagram of the convolution operation structure based on random calculation. The random number generator sharing circuit of the neural network based on random calculation proposed by the present invention is universal, and in addition to the fully connected layer, the convolution layer can also be used. The convolution operation input feature map In shown in the figure is 5*5, and the filter W is 3*3. According to the convolution operation principle, it can be known that the output feature map Out size is 3*3. In the operation, the bit stream generator is still divided into two groups. The first group converts the input data and uses the first output of the random number module; the second group converts the filter data and uses the second output of the random number module. When the number of filters used in the convolution operation is more than one, the operation circuit except the random number module is repeated, and the two outputs of the random number module are respectively connected to the first group of bit stream generators and the second group of bit stream generators of each other convolution circuit, so as to achieve the purpose of sharing only one random number generator circuit for the whole network. The random number generator sharing method meets the non-correlation requirements of the input bit stream of the random calculation multiplier array, and at the same time, the above-mentioned scaling adder is used to eliminate the non-correlation requirements between the multiplier output bit streams, so that the hardware resource consumption is reduced.

[0059] In the embodiment, according to the random number generator sharing circuit scheme proposed in the present invention, a fully connected artificial neural network for handwritten digit recognition based on random calculation is built using the Verilog hardware description language. The network node parameters are 784-50-10, and the MNIST handwritten digit data set is used for training. The simulation and DC synthesis results of this embodiment and the comparative circuit are shown in Table 1.

[0060] Table 1 Comparison of simulation and comprehensive results based on 14nm CMOS process

[0061]

[0062] As can be seen from the table, the number of logic gates of the neural network based on random calculation in this embodiment after using the random number generator shared circuit is only 12% of the traditional 32-bit floating-point calculation, and the power consumption is only 22%, while the image recognition accuracy of the MNIST handwritten digit data set is only 0.3% different from that of the floating-point calculation. When compared with the existing non-shared random calculation algorithm circuit, its recognition accuracy is improved by 1%, the logic resource occupancy is reduced by 72%, and the power consumption is reduced by 86%. Therefore, whether compared with the traditional floating-point operation network or the existing neural network based on random calculation, the circuit structure proposed by the present invention has lower resource occupancy and lower power consumption.

[0063] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A data sharing method for a neural network random number generator sharing circuit based on random calculation, characterized in that: The data sharing method of the neural network random number generator sharing circuit based on random calculation includes: Use a random number generator and multiplexing circuit to generate two random number outputs in the same clock cycle; The two random number outputs are connected to two groups of bit stream generator arrays respectively, wherein the first group of the bit stream generator arrays converts the input data of the neural network operation layer, and the second group converts the weight parameters of the neural network operation layer; The input data bit stream and the weight parameter bit stream generated by the bit stream generator array are respectively multiplied by a random calculation multiplication circuit; The output bit streams of each random calculation multiplication circuit are summed up through a scaling adder. The adder is based on a parallel accumulator, which adds multiple input bit streams simultaneously and scales the results to a suitable range through a shift operation. After an activation operation, the output data of the neural network calculation layer is generated.

2. The data sharing method of the neural network random number generator sharing circuit based on random calculation as claimed in claim 1, characterized in that: When the random number generator is a pseudo-random number generator, the method for generating two random number outputs in the same clock cycle includes: By using a linear feedback shift register, a pseudo-random number generator generates an n-bit wide random number per clock cycle; a shift register unit is added to the output of the pseudo-random number generator, and the output random number is delayed for several clock cycles before being output; when the delay time is t clock cycles and the functional function of the pseudo-random number generator is y=f(x), at time x1, the delayed output of the pseudo-random number generator is f(x1-t), the original output is f(x1), and the delayed output sequence is non-correlated with the original sequence; after time t, the pseudo-random number generator can output two different random numbers in each clock cycle.

3. The data sharing method of the neural network random number generator sharing circuit based on random calculation as claimed in claim 1, characterized in that: When the random number generator is a true random number generator, the method for generating two random number outputs in the same clock cycle includes: The output random number sequence of a true random number generator is converted into two unrelated random number sequences by using the time division multiplexing method; through the three-state gate array, the true random number generator generates one output and stores it in the odd clock cycle, and generates another output and stores it in the even clock cycle; When the clock frequency of the true random number generator is twice that of the neural network operation clock, the true random number generator can output two different random numbers in each neural network operation clock cycle.

4. The data sharing method of the neural network random number generator sharing circuit based on random calculation as claimed in claim 1, characterized in that: The neural network computing layer includes: The fully connected layer contains k neurons, In1~In j is the input data of this layer; Out1~Outk are the output data of this layer; W 11 ~Wjk are weight parameters, corresponding to the weight relationship between j inputs and k neurons; b1~b k is the offset parameter, corresponding to k neurons; the operation completed by the fully connected layer is expressed as: Among them, 1≤i≤k, Active(x) is the activation function; Convolution layer, assuming that the convolution operation input feature map is In, and the filter is W1~W k , the offset is b1~b k , then the output feature map Out is: OutActive(Im*W+b); Among them, 1≤i≤k, Active(x) is the activation function, and "*" is the convolution operator.

5. A neural network random number generator sharing circuit based on random calculation, characterized in that: The neural network random number generator shared circuit based on random calculation includes: Random number module; Bitstream generation module; Random calculation module; Data storage module; The random calculation module includes multiple neural computing units, and a single neural computing unit includes a multiplication circuit, a scaling addition circuit and an activation function circuit, which performs operations of multiplication, summation, scaling and activation on the input bit stream data in the probability domain; when using the unipolar representation, the multiplication circuit is implemented using an AND gate, and when using the bipolar representation, the multiplication circuit is implemented using an XNOR gate; the scaling addition circuit is based on a parallel accumulator and includes multiple bit stream input ports, which can add multiple input data in the same clock cycle, and when the accumulation process is completed, the operation result is enlarged or reduced by selecting a suitable scaling factor according to the operation result, so that the value range meets the input requirements of the next level bit stream generation module; the activation function circuit includes using a linear rectification function to activate neurons in the artificial neural network and add nonlinear characteristics to the network; The random number module has two random number outputs, which are shared in the entire network. The first random number is connected to the input data bit stream generator array of each network layer, and the second random number is connected to the weight parameter bit stream generator array of each network layer.

6. The neural network random number generator sharing circuit based on random calculation as claimed in claim 5, characterized in that: The random number module is composed of an n-bit wide random number generator and a multiplexing circuit, and the random number generator is a pseudo-random number generator or a true random number generator; if the random number generator is a pseudo-random number generator, a shift register is used to delay the random number generated by the pseudo-random number generator for several clock cycles as one random number output of the random number module, and the random number generated by the pseudo-random number generator without delay processing is used as another random number output of the random number module; If the random number generator is a true random number generator, the random numbers generated by the true random number generator are divided into two groups according to odd clock cycles and even clock cycles, and are respectively used as two random number outputs of the random number module; The bit stream generation module comprises two groups of bit stream generator arrays, each bit stream generator is composed of an n-bit wide digital comparator, and the n-bit wide digital comparator comprises two n-bit wide input data terminals and a 1-bit wide data output terminal; The n-bit width input data terminal comprises: Fixed end, connecting n-bit wide traditional binary data; Random end, connects n-bit wide random data; The 1-bit wide data output end outputs the comparison result of the two n-bit wide input data. If the fixed end data is greater than or equal to the random end data, it outputs "1", otherwise it outputs "0"; repeat the comparison m times, m>0, then the n-bit traditional binary data of the fixed end is converted into bit stream data of m bits in length.

7. A processor chip, characterized in that: The processor chip is equipped with a neural network random number generator sharing circuit based on random calculation as described in any one of claims 5-6, and implements a data sharing method for a neural network random number generator sharing circuit based on random calculation as described in any one of claims 1-4.

8. An information data processing terminal, characterized in that: The information data processing terminal is equipped with the processor chip described in claim 7, and is used to implement the data sharing method of the neural network random number generator sharing circuit based on random calculation as described in any one of claims 1-4.

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