Configurable Memory Termination

Abstract

This application relates to configurable memory termination. In one example, a memory system, such as a memory module or memory assembly, may include: one or more memory devices (e.g., memory arrays, memory chips); and input / output circuitry coupled to the one or more memory devices and communicating through a channel. The memory system may also include a selection component operable to selectively isolate one or more signal paths of the input / output circuitry from the channel, at least in part based on a signal received from a host device. In some examples, the selection component is operable to selectively couple the one or more signal paths of the channel with one or more termination resistor elements.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 16 / 660,745, filed on October 22, 2019, entitled "CONFIGURABLE MEMORY TERMINATION" by Kabir, which is assigned to its assignee and is hereby incorporated by reference in its entirety.

[0003] The technical field relates to configurable memory device termination. BACKGROUND OF THE INVENTION

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, typically denoted by a logic 1 or a logic 0. In other devices, more than two states can be stored. To access the stored information, components of the device can read or sense at least one of the stored states in the memory device. To store information, components of the device can write or program a state in the memory device.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for an extended period even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state when disconnected from an external power source.

[0006] Some systems can include a host device that communicates electronically with a set of memory systems (e.g., memory modules, memory assemblies) through a common channel such as a common data channel. SUMMARY OF THE INVENTION

[0007] A device is described. The device can include: one or more memory devices; input / output circuitry associated with the one or more memory devices and configured to communicate with a host device through a channel; and a selection component operable to selectively isolate one or more signal paths of the input / output circuitry from the channel at least in part based on a signal received from the host device.

[0008] Describe a method. The method may include: at a memory system including one or more memory devices, receiving, from a host device, a signal indicating whether the memory system is being accessed by the host system; and at the memory system, modifying, at least in part based on receiving the signal from the host device, a connection between an input / output circuit of the memory system and one or more signal paths between the host device and the memory system.

[0009] Describe a system. The system may include: a host device having a first input / output circuit for communicating via a channel; a plurality of memory systems, each of the plurality of memory systems including one or more memory devices and a second input / output circuit for communicating via the channel; and a plurality of selection components. Each of the plurality of selection components may correspond to a respective one of the plurality of memory systems and may be operable to selectively isolate the second input / output circuit of the respective one of the plurality of memory systems from the first input / output circuit, at least in part based on signaling from the host device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 Illustrate an example of a system that supports configurable memory termination according to an example disclosed herein.

[0011] Figure 2 Illustrate an example of a system that supports configurable memory termination according to an example disclosed herein.

[0012] Figure 3 Illustrate an example of a memory system that supports configurable memory termination according to an example disclosed herein.

[0013] Figure 4 Illustrate an example of a termination selector that supports configurable memory device termination according to an example disclosed herein.

[0014] Figure 5 Illustrate an example of a system that supports configurable memory device termination according to an example disclosed herein.

[0015] Figure 6 Show a block diagram of a memory system that supports configurable memory termination according to an example disclosed herein.

[0016] Figure 7 Show a flowchart illustrating one or more methods that support configurable memory termination according to an example disclosed herein. DETAILED DESCRIPTION

[0017] Some systems that include a memory device for information storage may include a host device that communicates electronically with a set of memory systems (e.g., memory modules, memory assemblies) via a common channel such as a data channel. In some cases, components or circuits of one memory system coupled to the common channel may cause degradation or attenuation of the signaling associated with another memory system coupled to the common channel. For example, signal reflections from a first memory system coupled to the common channel may interfere with communication between the host device and a second memory system coupled to the common channel (e.g., cause a noise component on the channel, reduce the signal-to-noise ratio on the channel, or otherwise degrade or attenuate the communication on the channel). This degradation or attenuation may be associated with data access errors, reduced margin for performing data access operations, or other adverse effects.

[0018] In accordance with aspects of the present invention, a memory system may include one or more memory devices (e.g., memory arrays, memory chips) and input / output circuitry (e.g., of or associated with the one or more memory devices) for communicating with a host device via a channel. The memory system may further include a selection component operable to selectively isolate or disconnect one or more signal paths of the input / output circuitry from the channel, at least in part based on receiving a signal (e.g., a deactivate signal, an idle signal) from the host device. In some instances, the selection component is operable to selectively connect or couple one or more signal paths of the channel to one or more termination resistor elements. In other words, the memory system according to the present invention may include a configurable termination that responds to signaling from the host device. By isolating the input / output circuitry of the memory system from one or more signal paths of this channel, signal degradation or attenuation that might otherwise be caused by the input / output circuitry of the memory system or associated signal paths can be reduced or eliminated.

[0019] First, reference Figure 1 The features of the present invention are described in the context of a system that includes a memory device. Reference Figures 2 to 5 The features of the present invention are further described in the context of a system having various configurations of a selection component and a termination component. Reference is made to the device diagrams and flowcharts related to a configurable memory termination as described in reference Figure 6 and 7 to further illustrate and describe these and other features of the present invention.

[0020] Figure 1Describe an example of a system 100 that utilizes one or more memory devices according to the examples disclosed herein. The system 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 to the memory device 110. The system 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0021] The system 100 may include portions of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. The system 100 may be an example of a portable electronic device. The system 100 may be an example of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, etc. The memory device 110 may be a component of the system that is configured to store data for one or more other components of the system 100.

[0022] At least a portion of the system 100 may be an example of a host device. This host device may be an example of a device that uses memory to perform processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, some other fixed or portable electronic device, a vehicle, a vehicle controller, etc. In some cases, the host device may refer to hardware, firmware, software, or a combination thereof that implements the functions of the external memory controller 105. In some cases, the external memory controller 105 may be referred to as the host or the host device. In some examples, the system 100 is a graphics card.

[0023] In some cases, the memory device 110 may be a stand-alone device or component that is configured to communicate with other components of the system 100 and provide physical memory addresses / spaces potentially for use or reference by the system 100. In some examples, the memory device 110 may be configured to work with at least one or more different types of systems 100. Signaling between the components of the system 100 and the memory device 110 may operate to support modulation schemes for modulating signals, different pin designs for conveying signals, dissimilar packages of the system 100 and the memory device 110, clock signaling and synchronization between the system 100 and the memory device 110, timing conventions, and / or other factors.

[0024] The memory device 110 may be configured to store data for components of the system 100. In some cases, the memory device 110 may act as a slave device of the system 100 (e.g., responsive to and executing commands provided by the system 100 via the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) to support a desired or specified data storage capacity. A memory device 110 that includes two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0025] The system 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. Components of the system 100 may communicate electronically with each other using a bus 140.

[0026] The processor 120 may be configured to control at least a portion of the system 100. The processor 120 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or it may be a combination of these types of components. In such cases, the processor 120 may be an instance of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), or a system-on-chip (SoC), among other examples.

[0027] The BIOS component 125 may be a software component that includes the BIOS operating as firmware, which may initialize and run various hardware components of the system 100. The BIOS component 125 may also manage the flow of data between the processor 120 and various components of the system 100 (e.g., peripheral components 130, I / O controller 135, etc.). The BIOS component 125 may include programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0028] (One or more) peripheral components 130 may be any input or output device that may be integrated into or integrated with the system 100, or an interface for such a device. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a universal serial bus (USB) controller, a serial or parallel port, or a peripheral card slot, such as a peripheral component interconnect (PCI) or a dedicated graphics port. (One or more) peripheral components 130 may be other components understood by those skilled in the art as peripheral devices.

[0029] The I / O controller 135 may manage data communication between the processor 120 and the (several) peripheral components 130, the input device 145, or the output device 150. The I / O controller 135 may manage peripheral devices not integrated into or not integrated with the system 100. In some cases, the I / O controller 135 may represent a physical connection or port to external peripheral components.

[0030] The input 145 may represent a device or signal external to the system 100 that provides information, signals, or data to the system 100 or its components. This may include a user interface or an interface that interfaces with or between other devices. In some cases, the input 145 may be a peripheral device that interfaces with the system 100 via one or more peripheral components 130 or may be managed by the I / O controller 135.

[0031] The output 150 may represent a device or signal external to the system 100 that is configured to receive output from any of the system 100 or its components. Examples of the output 150 may include a display, an audio speaker, a printing device, or another processor on a printed circuit board, etc. In some cases, the output 150 may be a peripheral device that interfaces with the system 100 via one or more peripheral components 130 or may be managed by the I / O controller 135.

[0032] The components of the system 100 may consist of general-purpose or special-purpose circuits designed to perform their functions. This may include various circuit elements configured to perform the functions described herein, such as conductive wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements.

[0033] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., a grid), where each memory cell is configured to store at least one digital data bit. Refer to Figure 2 The characteristics of the memory array 170 and / or the memory cells are described in more detail.

[0034] Memory device 110 may be an example of a two-dimensional (2D) memory cell array or may be an example of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other or stacked adjacent to each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as levels, tiers, layers, or dies. A 3D memory device may include any number of stacked memory dies 160-N (e.g., two high, three high, four high, five high, six high, seven high, eight high). Compared to a single 2D memory device, this may increase the number of memory cells that can be positioned on a substrate, which in turn may reduce production costs or increase the performance of the memory array or both. In a certain 3D memory device, different levels may share at least one common access line such that some levels may share at least one of word lines, digit lines, and / or plate lines.

[0035] Device memory controller 155 may include circuitry or components configured to control the operation of memory device 110. Thus, device memory controller 155 may include hardware, firmware, and software that enable memory device 110 to execute commands and may be configured to receive, transmit, or execute commands, data, or control information related to memory device 110. Device memory controller 155 may be configured to communicate with external memory controller 105, one or more memory dies 160, or processor 120. In some cases, memory device 110 may receive data and / or commands from external memory controller 105. For example, memory device 110 may receive a write command indicating that memory device 110 is to store certain data on behalf of a component of system 100 (e.g., processor 120) or a read command indicating that memory device 110 is to provide certain data stored in memory die 160 to a component of system 100 (e.g., processor 120). In some cases, device memory controller 155 may control the operation of memory device 110 described herein in conjunction with local memory controller 165 of memory die 160. Examples of components included in device memory controller 155 and / or local memory controller 165 may include a receiver for demodulating signals received from external memory controller 105, a decoder for modulating and transmitting signals to external memory controller 105, logic, decoders, amplifiers, filters, etc.

[0036] The local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. Moreover, the local memory controller 165 may be configured to communicate (e.g., receive and transmit data and / or commands) with the device memory controller 155. The local memory controller 165 may support the device memory controller 155 in controlling the operation of the memory device 110 as described herein. In some cases, the memory device 110 does not include the device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform the various functions described herein. Thus, the local memory controller 165 may be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0037] The external memory controller 105 may be configured to enable information, data, and / or command communication between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 may act as a liaison between the components of the system 100 and the memory device 110 such that the components of the system 100 need not know the details of the operation of the memory device. The components of the system 100 may present requests (e.g., read commands or write commands) to the external memory controller 105 that the external memory controller 105 will satisfy. The external memory controller 105 may translate or transpose the communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0038] In some cases, the external memory controller 105 or other components of the system 100 described herein, or their functionality, may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, software, or some combination thereof implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or its functionality described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, software, or some combination thereof implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110 such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Similarly, in some cases, one or more functions attributed to the device memory controller 155 or the local memory controller 165 herein may be performed by the external memory controller 105 (separate from or as included in the processor 120).

[0039] The components of the system 100 may exchange information with the memory device 110 using multiple channels 115. In some instances, the channels 115 may enable communication between the external memory controller 105 and the memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. For example, the channel 115 may include a first terminal that includes one or more pins or pads at the external memory controller 105 and one or more pins or pads at the memory device 110. Pins may be examples of conductive input or output points of devices of the system 100, and the pins may be configured to act as part of the channel.

[0040] In some cases, the pins or pads of the terminals may be part of the signal path of the channel 115. Additional signal paths may be coupled to the terminals of the channel to route signals within the components of the system 100. For example, the memory device 110 may include signal paths (e.g., signal paths internal to the memory device 110 or its components (e.g., internal to the memory die 160)) that route signals from the terminals of the channel 115 to various components of the memory device 110 (e.g., the device memory controller 155, the memory die 160, the local memory controller 165, the memory array 170).

[0041] Channel 115 (and associated signal paths and terminals) can be dedicated to conveying a particular type of information. In some cases, channel 115 can be a summary channel and can thus include multiple individual channels. For example, data channel 190 can be x4 (e.g., include four signal paths), x8 (e.g., include eight signal paths), x16 (e.g., include sixteen signal paths), etc. Signals conveyed through the channel can use a double data rate (DDR) timing scheme. For example, some symbols of the signal can be latched on the rising edge of the clock signal and other symbols of the signal can be latched on the falling edge of the clock signal. Signals conveyed through the channel can use single data rate (SDR) signaling. For example, one symbol of the signal can be latched for each clock cycle.

[0042] In some cases, channel 115 can include one or more command and address (CA) channels 186. CA channel 186 can be configured to convey commands between external memory controller 105 and memory device 110, including control information (e.g., address information) associated with the commands. For example, CA channel 186 can include a read command with an address of the desired data. In some cases, CA channel 186 can be latched on the rising clock signal edge and / or the falling clock signal edge. In some cases, CA channel 186 can include any number of signal paths to decode the address and command data (e.g., eight or nine signal paths).

[0043] In some cases, channel 115 can include one or more clock signal (CK) channels 188. CK channel 188 can be configured to convey one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal can be configured to oscillate between a high state and a low state and coordinate the actions of external memory controller 105 and memory device 110. In some cases, the clock signal can be a differential output (e.g., CK_t signal and CK_c signal) and the signal paths of CK channel 188 can be configured accordingly. In some cases, the clock signal can be single-ended. CK channel 188 can include any number of signal paths. In some cases, clock signal CK (e.g., CK_t signal and CK_c signal) can provide a timing reference for command and addressing operations of memory device 110 and / or other system-wide operations of memory device 110. Thus, clock signal CK can alternatively be referred to as control clock signal CK, command clock signal CK, or system clock signal CK. The system clock signal CK can be generated by a system clock, which can include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors, etc.).

[0044] In some cases, channel 115 may include one or more data (DQ) channels 190. The data channels 190 may be configured to communicate data and / or control information between the external memory controller 105 and the memory device 110. For example, the data channels 190 may communicate information (e.g., bidirectionally) to be written to the memory device 110 or read from the memory device 110.

[0045] In some cases, channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may include any number of signal paths.

[0046] Channel 115 may couple the external memory controller 105 and the memory device 110 using a variety of different architectures. Examples of various architectures may include a bus, a point-to-point connection, a crossbar switch, a high-density interposer (e.g., a silicon interposer), or a channel formed in an organic substrate or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer, such as a silicon interposer or a glass interposer.

[0047] The signals communicated on channel 115 may be modulated using a variety of different modulation schemes. In some cases, a binary symbol (or binary-level) modulation scheme may be used to modulate the signals communicated between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an instance of an M-ary modulation scheme, where M equals 2. Each symbol of the binary symbol modulation scheme may be configured to represent one digital data bit (e.g., the symbol may represent a logic 1 or a logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar coding, bipolar coding, Manchester coding, pulse amplitude modulation with two symbols (e.g., PAM2), and / or others.

[0048] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate the signals communicated between the external memory controller 105 and the memory device 110. The multi-symbol modulation scheme may be an instance of an M-ary modulation scheme, where M is greater than or equal to 3. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one digital data bit (e.g., the symbol may represent logic 00, logic 01, logic 10, or logic 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or others. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one information bit per symbol. The multi-symbol modulation scheme and symbols may alternatively be referred to as non-binary, multi-bit, or high-order modulation schemes and symbols.

[0049] In some cases, a memory system may include one or more memory devices 110 and may be referred to as a memory module or memory assembly. In some instances, a memory system may refer to a single in-line memory module (SIMM), a dual in-line memory module (DIMM), or other types of modules or assemblies. The system may be configured such that a host device communicates electronically with a set of memory systems via a common channel such as a data channel. In some cases, components or circuitry of one memory system coupled to the common channel may cause degradation or attenuation of signaling associated with another memory system connected or coupled to the common channel. To reduce or eliminate such degradation or attenuation, a memory system according to the present invention may include a selection component operable to selectively isolate or connect various components or circuitry of the memory system to the common channel, the selection component being responsive to signaling from the host device. In other words, a memory system according to the present invention may include a configurable termination (e.g., of or associated with the common channel) that may be configured based on whether a particular memory system is being accessed or will be available for access. By isolating the circuitry of the memory system from one or more signal paths of the channel or disconnecting the circuitry of the memory system from one or more signal paths of the channel, signal degradation or attenuation that might otherwise be caused by input / output circuitry of or associated with the memory system or by the associated signal paths may be reduced or eliminated.

[0050] Figure 2 An example of a system 200 according to an example disclosed herein is illustrated. System 200 includes a host device 210, a memory system 240-a, and a memory system 240-b. The host device 210, the memory system 240-a, and the memory system 240-b may be (e.g., electrically) coupled or connected to each other via a channel 280 (e.g., a common channel, a shared channel). In some instances, the channel 280 may be or include a data channel, such as a DQ channel. In some instances, the channel 280 may illustrate one or more signal paths, traces, or conduits of a set of one or more channels for various types or classes of signaling between the host device 210, the memory system 240-a, and the memory system 240-b. For example, the channel 280 may illustrate a bus having 72 signal paths or any other number of signal paths. Although system 200 is illustrated as including two memory systems 240, a system according to the present invention may include any number of memory systems 240.

[0051] In some instances, the memory system 240 may refer to a set of components that are physically distinct from the host device, such as a memory module or a memory assembly. For example, the memory system 240 may refer to a SIMM, DIMM, or other type of module or assembly. In some instances, the memory system 240 may include pins, slots, connectors, or other terminals that support an electrical connection to the channel 280, where such terminals may support physically separable connections, assemblies, or installations. In some instances, the memory system 240 may include electrical contacts that support separately manufacturing and then permanently, semi-permanently, or temporarily installing the memory system 240. The memory system 240 may be manufactured according to various form factors, and one memory system 240 of the system 200 may have or may not have a different form factor from another memory system 240 of the system 200.

[0052] Each of the memory systems 240 may include one or more memory devices 110 and I / O circuitry 250 to support communication between the memory devices 110 and the channel 280. The memory devices 110 (e.g., memory devices 110-a, 110-b) may be examples of the memory devices 110 described in reference Figure 1 such as DRAM devices. The I / O circuitry 250 may include one or more modulators, one or more demodulators, or both, to support unidirectional or bidirectional communication (e.g., with the host device 210) through the channel 280 along with various other components or signal paths between the channel 280 and the memory devices 110. In some instances, the I / O circuitry 250 of or associated with a respective memory system 240 may be coupled to a device memory controller 155 corresponding to each of the memory devices 110 of the respective memory system 240.

[0053] In instances where the memory system 240 includes two or more separate memory devices 110 (e.g., two or more sets of independent memory chips connected to the same address and data buses), each such set may be referred to as a rank. In some instances, a particular rank may be activated by a chip select (CS) signal corresponding to the rank, and in some instances, other ranks of the memory system 240 may be deactivated. In some instances, the I / O circuitry 250 may include a selection or multiplexing circuit configured to select a rank or otherwise route access signals to a particular rank of the associated memory system 240.

[0054] The host device 210 may refer to a device that uses the memory system 240 for data storage or otherwise coordinates the use of the memory system 240 for data storage. The host device 210 may include an I / O circuit 220 operable to communicate signaling over a channel 280. For example, the I / O circuit 220 may include one or more modulators, one or more demodulators, or both, to support unidirectional or bidirectional communication over the channel 280 (e.g., with memory systems 240-a and 240-b) along with various other components or signal paths.

[0055] In some instances, the host device 210 may include pins, slots, connectors, or other terminals that support electrical connection to the channel 280. In some instances, the memory system 240 may include a mating connector for direct physical or electrical coupling to the host device 210. In other instances, the host device 210 and the memory system 240 may be physically or electrically coupled via an intermediary component or assembly (e.g., a motherboard or other printed circuit board) that includes the signal path of the channel 280 between the host device 210 and the memory system 240.

[0056] In some cases, the host device 210 may perform an access operation on one of the memory systems 240, where information is exchanged via signaling over the channel 280. For example, when the host device 210 accesses the memory system 240-a, signaling may be transmitted by the host device 210 and received by the memory system 240-a (e.g., data signaling supporting a write operation, command signaling supporting a read or write operation), or transmitted by the memory system 240-a and received by the host device 210 (e.g., data signaling supporting a read operation), or both. To support this signaling, the transmitting device may control the voltage of one or more signal paths of the channel 280 (e.g., as the voltage control authority of the signal path), and the receiving device may detect the corresponding voltage or other signal of the signal path. Based on this detection, the receiving device may detect the information transmitted by the transmitter.

[0057] In some instances of the communication signaling between the host device 210 and the memory system 240-a, signal degradation or attenuation on the channel 280 may cause errors in the signals communicated between the host device 210 and the memory system 240-a. For example, for a given signaling, the receiving device may not detect the same information intended to be transmitted by the transmitting device. In a binary signaling instance, in the presence of signal degradation or attenuation, when the transmitting device attempts to signal a logic 0, the receiving device may detect a logic 1, or vice versa.

[0058] In some cases, signal degradation or attenuation on channel 280 during communication between host device 210 and memory system 240-a may be associated with the circuitry (e.g., signal paths, components) of memory system 240-b that is electrically coupled or connected to channel 280. For example, when I / O circuitry 250-b is connected to channel 280 during this communication between host device 210 and memory system 240-a, the components or signal paths of I / O circuitry 250-b may interact with or otherwise impair the signaling or voltage control (e.g., voltage control authority) of the transmitter. Examples of such interactions may include voltage drops or other biases across signal paths or terminals, reflective or oscillatory signal characteristics associated with signal paths or components, capacitance or other impedance of I / O circuitry 250-b, and other effects. Interactions such as these may cause (e.g., from the perspective of memory system 240-a, from the perspective of host device 210) signal level changes (e.g., decreases, increases), may cause signal stability changes (e.g., may introduce oscillatory components), may cause signal timing changes (e.g., may introduce signal delays or advances), or other interference or signal noise, which may impair the communication of signaling between host device 210 and memory system 240-a.

[0059] In some cases, where memory system 240-a is more closely connected to host device 210 than memory system 240-b, memory system 240-a may have a relatively impaired communication margin compared to memory system 240-b. For example, when memory system 240-a receives signaling from host device 210, memory system 240-a may receive or interpret not only the basic signal transmitted or controlled by host device 210, but also the reflected component caused by the interaction with I / O circuit 250-b and the intermediate signal path. In another example, when host device 210 receives signaling from memory system 240-a, host device 210 may receive or interpret not only the basic signal transmitted or controlled by memory system 240-a, but also the reflected component caused by the interaction with I / O circuit 250-b and the intermediate signal path. In this configuration, memory system 240-b may also receive or interpret not only the basic signal transmitted or controlled by host device 210, but also the reflected signal component caused by the interaction with I / O circuit 250-a. Similarly, host device 210 may also receive or interpret not only the basic signal transmitted or controlled by memory system 240-b, but also the reflected signal component caused by the interaction with I / O circuit 250-a. In some cases, the reflections associated with I / O circuit 250-a (e.g., as perceived at memory system 240-b, as perceived at host device 210) may be lower or less than the reflections associated with I / O circuit 250-b (e.g., as perceived at memory system 240-a, as perceived at host device 210). More generally, an I / O circuit or associated signal path coupled to channel 280 in one memory system 240 may be associated with different (e.g., greater or lesser) signal degradation or attenuation compared to an I / O circuit or associated signal path coupled to the same channel 280 in another memory system 240.

[0060] In some circuits, reflections may be related to the length of the signal path (e.g., stub length), which may be related to the signal path length of the I / O circuit 250 or the signal path between the I / O circuit 250 and the channel 280 (e.g., the sub-length between a pin of the memory system 240 and a portion of the I / O circuit 250). For example, reflections may be relatively large for relatively long signal paths. In some instances, since the signal paths of the channel 280 are associated with different stub lengths in the memory system 240, the signal path layout of the memory system 240 may result in reflection asymmetries from one signal path to another, which may further affect the communication margin. More generally, reflections or other phenomena related to signal degradation or attenuation may be based on various characteristics of the circuits and signal paths of the system 200, which may vary from one memory system 240 to another memory system 240, or from one signal path of the channel 280 to another signal path of the channel 280.

[0061] In some cases, the memory system 240 may include a direct plug-in resistive element (e.g., included in the I / O circuit 250, between the I / O circuit 250 and the channel 280) between the channel 280 and the memory device 110 to mitigate some instances of signal degradation. For example, this resistive element may be included to reduce or attenuate reflections that may be carried along the channel 280 (e.g., where the resistive element of the memory system 240-b may reduce the reflections or other degradations as sensed at the memory system 240-a). However, although passive resistive elements may reduce some aspects of signal degradation or attenuation, the channel 280 may still experience various interactions associated with connecting multiple memory systems 240 to the same channel 280.

[0062] To mitigate interactions associated with connecting multiple memory systems 240 to the same channel 280, each of the memory systems 240 may include a selection component 260 operable to selectively isolate a respective I / O circuit 250 from the channel 280 (e.g., one or more signal paths of the channel 280). For example, when the host device 210 is accessing the memory system 240-a, the selection component 260-a may be used to selectively connect or couple the I / O circuit 250-a to the channel 280 and the selection component 260-b may be used to selectively disconnect or isolate the I / O circuit 250-b from the channel 280. This disconnection or isolation of the I / O circuit 250-b may reduce or eliminate signal degradation or attenuation (e.g., as perceived or interpreted at the memory system 240-a or the host device 210) that may otherwise occur if the I / O circuit 250-b were connected to the channel 280, such as reflections. Additionally, this selective isolation may support balancing aspects of signal degradation or attenuation among the respective signal paths of the channel 280. In some cases, this selective isolation may enable a greater number of memory systems 240 to share the channel 280, such as supporting a system or architecture with more than two memory systems 240 (e.g., more than two DIMMs) sharing a common channel or channel bus.

[0063] In some instances, the selection component 260 may be responsive to signaling from the host device 210 regarding which memory system 240 is being accessed by the host device 210. For example, the host device 210 may include an activation controller 230 that may know or control which memory systems 240 will be activated (e.g., made available for access operations) and which memory systems 240 will be deactivated (e.g., made unavailable for access operations). The activation controller 230 may determine or identify that memory system 240-a will be accessed and memory system 240-b will be idle, and reflect the relevant signaling to memory system 240-a and memory system 240-b. By isolating or idling some memory systems 240 (e.g., memory system 240-b), signals communicating with another memory system 240 (e.g., memory system 240-a) may experience less interference. The host device 210 may reflect a first signal (e.g., an activation signal) to memory system 240-a and a second signal (e.g., a deactivation signal) to memory system 240-b. In some instances, the host device 210 may reflect the same signal (e.g., a signal indicating that memory system 240-a is being accessed) to both memory system 240-a and memory system 240-b, and the respective memory systems 240 may interpret the same signal relative to their own operations (e.g., memory system 240-a receives the same signal and activates selection component 260-a, while memory system 240-b receives the same signal and deactivates selection component 260-b). In some instances, this signaling may be carried from the activation controller 230 to the memory systems 240 via the channel 280 itself. In other instances, the system 200 may be configured with a control path 290 that is configured to convey activation / deactivation signaling to each of the memory systems 240, and the control path 290 may or may not be a signal path or signaling specifically dedicated to the activation or deactivation of the selection component 260. In some instances, the control path 290 may couple together components that are the same as or similar to the channel 280 (e.g., a common I / O circuit). In such instances, signaling from the activation controller 230 to the memory systems 240 may be conveyed via the control path 290. For example, the control path 290 may be a communication path that is connected to or between the I / O circuit 220, the I / O circuit 250-a, or the I / O circuit 250-b.

[0064] In some instances, control path 290 may communicate between the I / O circuitry 220 of host device 210 and one or more memory systems 240-a or 240-b. In some of these instances, control path 290 may not be coupled to the I / O circuitry 250 of memory system 240. In some cases, signaling from activation controller 230 may be part of an address / control signal group that is separate from data such as data signals or channels (DQ) or data strobe (DQS). In some architectures, the DQ or DQS signal or both are twice the speed of the address / control group. Channel 280 and control path 290 may be different channels for different signal groups. For example, data signals (e.g., DQ or DQS) may be driven from the I / O circuitry (e.g., DQ / DQS is driven from I / O circuitry 220 for write operations, and the I / O circuitry 250 of memory system 240 may drive signals for read operations). However, the address / control signals may be driven by the I / O circuitry 220 of host device 210. In some cases, the address / control signals may be half the data speed, and thus the components of I / O circuitry 220 and 250 may be different for different signals in host device 210 and memory system 240 may be different for different signal groups such as data and address / control.

[0065] In instances where system 200 includes control path 290 or the system conveys activation / deactivation signaling via channel 280, each of memory systems 240 may include a receiver (not shown) for receiving this signaling for selective connection or isolation by corresponding select component 260. In various instances, this receiver may be a signal path operable to selectively activate a switch (e.g., transistor, multiplexer), or may be a component that demodulates or demultiplexes this signal for other processing to selectively activate or deactivate corresponding select component 260.

[0066] Figure 3 An example of memory system 240-c that supports configurable memory termination in accordance with an example disclosed herein is illustrated. Memory system 240-c includes a set of terminals 320-a (e.g., terminals 320-a-1 to 320-a-n) configurable to connect or couple to channel bus 310, where the channel bus 310 may be in reference to Figure 2A bus associated with the described channel 280. For example, each of the terminals 320 can be an electrical pin or other contact corresponding to a respective signal path of the channel bus 310. The memory system 240-c also includes a memory device 110-c connected or coupled to a set of I / O circuits 250-c (e.g., I / O circuits 250-c-1 to 250-c-n). Although a single memory device 110-c is shown, in various instances, the memory system 240-c can include one or more memory devices 110-c. In an instance of the memory system 240-c, each of the I / O circuits 250-c can correspond to a respective one of the terminals 320-a. Although each of the I / O circuits 250-c is illustrated as a separate component, the I / O circuits 250 can collectively refer to I / O circuits shared across signal paths corresponding to the channel bus 310, where one or more memory devices 110-c of the memory system 240-c can share this I / O circuit.

[0067] The memory system 240-c also includes a set of corresponding termination selectors 330-a (e.g., termination selectors 330-a-1 to 330-a-n) operable to select a termination configuration of the memory system 240-c. For example, each of the termination selectors 330-a can illustrate or include a selection component operable to selectively isolate a respective I / O circuit 250-c from a respective signal path of the channel 280 corresponding to the channel bus 310. In an instance of the memory system 240-c, this function can be provided by the termination selector 330-a operable to selectively isolate a respective I / O circuit 250-c from a respective terminal 320-a (e.g., disconnect a respective I / O circuit 250-c from a respective terminal 320-a). In various instances, this selective isolation by the termination selector 330-a can be based on or in response to signaling from a host device connected or coupled to the channel bus 310, where this signaling can be carried via the channel bus 310 itself or via a control bus 315.

[0068] In various instances, each of the termination selectors 330-a may include one or more termination resistor elements. In some instances, such termination resistor elements may be positioned along the signal path between the respective terminals 320-a and the corresponding I / O circuit 250-c. Additionally or alternatively, such termination resistor elements may be positioned along the signal path between the respective terminals 320-a and another portion of the memory system 240-c (e.g., not between the respective terminals 320-a and the I / O circuit 250), such other portion being, for example, ground, chassis ground, a reference voltage source, or some other alternative termination of the memory system 240-c or of a system including the memory system 240-c. In various instances, the termination resistor element may include a resistor (e.g., a resistor element), a transistor, or some other portion of the respective signal path. In some instances, the resistance or impedance of a particular termination resistor element may be configured based on signaling indicating the type of access operation being performed via the channel bus 310 (e.g., by a host device coupled to the channel bus 310), such as whether a read operation is being performed via the channel bus 310 or a write operation is being performed via the channel bus 310. In some instances, this signaling indicating the type of access operation being performed may be carried via the control bus 315.

[0069] According to various instances, the termination selector 330-a may select or otherwise configure the termination of the memory system 240-c (e.g., for the respective signal paths of channel 280 corresponding to the channel bus 310) based on signaling originating from or received from a host device connected or coupled to the channel bus 310. This signaling may, for example, indicate the access state of the memory system 240-c, such as whether the memory system 240-c is being accessed by the host device, is accessible by the host device, is not being accessed by the host device, or will be in an idle state. Accordingly, the termination of the channel bus 310 with respect to the memory system 240-c may be configured (e.g., via the termination selector 330-a) based on the operation of the memory system 240-c or the operation of any other memory system 240 connected or coupled to the channel bus 310. In other words, the termination selector 330-a may illustrate an example of a component operable to modify the connection between the I / O circuit 250-c and one or more signal paths of the channel bus 310 at least in part based on receiving signals from the host device at the memory system 240-c.

[0070] In various instances, such configurable terminations can reduce or eliminate degradation or attenuation of signaling through channel bus 310, which may otherwise be associated with other termination characteristics of I / O circuit 250-c or memory system 240-c. For example, in a case where a signal path between a portion of I / O circuit 250-c or termination selector 330-a and I / O circuit 250-c can be a source of reflections that can be fed back to channel bus 310, termination selector 330-a can be operative to reduce or eliminate this source of reflections. In another instance, in a case where memory system 240-c is configured such that corresponding signal paths to channel bus 310 have different lengths (e.g., where the signal path between I / O circuit 250-c-1 or between I / O circuit 250-c-1 and termination selector 330-a-1 has a length different from the signal path between I / O circuit 250-c-n or between I / O circuit 250-c-n and termination selector 330-a-n), or any other source of mismatched impedance, termination selector 330-a can be operative to reduce or eliminate this impedance mismatch, such as when the impedance between corresponding terminal 320-a and termination selector 330-a is relatively balanced. Thus, in accordance with various instances disclosed herein, termination selector 330-a can be operative to improve signaling through channel bus 310, such as to support more direct point-to-point communication through channel bus 310 between a transmitter and a receiver, reduce differences in the positioning of memory systems 240 in the system (e.g., minimize socket dependencies of one memory system 240 relative to another memory system 240 within the system), improve voltage or other signaling margins through channel bus 310, support an increase in data transfer rate or frequency through channel bus, and other benefits.

[0071] Figure 4 An example of termination selector 330-b that supports configurable memory termination in accordance with an example as disclosed herein. Termination selector 330-b can be a reference Figure 3An example of the termination selector 330-a described and may be included in the memory system 240. In some examples, the termination selector 330-b may be implemented as an integrated circuit, which may be mounted or assembled as a discrete component of the memory system 240 (e.g., as a discrete "integrated circuit" repeated for each signal path of the channel 280), or as part of such a component (e.g., as part of an integrated circuit that collectively supports the described functions of multiple signal paths of the channel 280). In some examples, the termination selector 330-b may be part of an integrated circuit component separate from other components of the memory system 240, such as a component separate from the I / O circuit 250 of a component separate from the memory device 110. In some examples, the boundary of the termination selector 330-b may be illustrative, such that the components of the termination selector 330-b are otherwise integrated in the memory system 240 (e.g., where the selection component 260-b and one or more of the termination resistors 450 or 460 are separate components mounted to the printed circuit board of the memory system 240, where the termination resistor 460 or the signal path 430 refers to an off-chip terminal). In some cases, the termination resistor 460 may range between about 13.5 ohms and 16.5 ohms, 14 ohms and 16 ohms, 14.5 ohms and 15.5 ohms, or may be about 15 ohms. In some cases, the termination resistor 460 may range between about 8.5 ohms and 11.5 ohms, 9 ohms and 11 ohms, 9.5 ohms and 10.5 ohms, or may be about 10 ohms. In some cases, the termination resistor 460 may range between 10 ohms and 15 ohms and may be about 10 ohms, 10.5 ohms, 11 ohms, 11.5 ohms, 12 ohms, 12.5 ohms, 13 ohms, 13.5 ohms, 14 ohms, 14.5 ohms, or 15 ohms.

[0072] The termination selector 330-b may be connected or coupled or connected and coupled therebetween with the signal path 410, the signal path 420, and the signal path 430. The signal path 410 may be operable to connect to the channel 280 or the channel bus 310 (e.g., connect to the terminal 320 of the memory system 240), and the channel 280 or the channel bus 310 may support communication or signaling with the host device 210. The signal path 420 may be coupled to the I / O circuit 250, and the I / O circuit 250 may support communication or signaling with one or more memory devices 110 (e.g., to a DRAM memory device). The signal path 430 may be coupled to another signal path of the memory system 240, such as ground, chassis ground, a reference voltage source (e.g., having a voltage VDDQ), or some other alternative terminal of the memory system 240 or a system including the memory system 240.

[0073] The termination selector 330-b may also include a selection component 260-b, which may be an instance of a component operable to modify the termination of the memory system 240 (e.g., the termination of the channel 280 or the channel bus 310 or associated with the channel 280 or the channel bus 310). For example, the termination selector 330-b may be operable to connect the signal path 410 to one of the signal path 420 or the signal path 430. In some instances, the selection component 260-b may be operable to disconnect the signal path 410 from the signal path 420 when the memory system 240 including the termination selector 330-b is not accessed, and instead connect the signal path 410 to the signal path 430 (connect the signal path to the termination circuit associated with the signal path 430). In some instances, the selection component 260-b may be operable to connect the signal path 410 to the signal path 420 when the memory system 240 including the termination selector 330-b is being accessed or otherwise accessible, and correspondingly disconnect the signal path 410 from the signal path 430. The selection component 260-b may be referred to as a 1:2 multiplexer or demultiplexer.

[0074] The termination selector 330-b may operate based on signaling from a host device, which may be received via the signal path 440, which may be associated with the same channel 280 or channel bus as the signal path 410 in various instances, or may be associated with the control bus 315. Although the selection component 260-b is illustrated as a single component, the selection component 260-b may include or refer to one or more sub-components, such as multiple transistors in a switching network (e.g., a first transistor for connecting the signal path 410 to the signal path 420 and a second transistor for connecting the signal path 410 to the signal path 430).

[0075] In some instances, the termination selector 330-b may include a termination resistor 450 that describes the signaling for the path between the signal path 410 and the signal path 420. In some instances, the termination resistor 450 may include a passive resistor having a nominal resistance (e.g., a 15Ω resistor element, a discrete resistor, an on-board DIMM resistor). In other instances, the termination resistor 450 may refer to an active resistor biased to impose a nominal resistance, such as a field effect transistor (FET) (e.g., an FET biased to a 15Ω resistance).

[0076] Although the termination resistor 450 is illustrated as a component of the termination selector 330-b, in some instances, the termination resistor 450 may alternatively or additionally be included in another component of the memory system 240 that includes the termination selector 330-b, such as a component of the I / O circuitry 250. Further, although the termination resistor 450 is illustrated as a separate component, the termination resistor associated with the signal path 420 may refer to or otherwise include a resistor or impedance associated with a component of the signal path 420, or a resistor or impedance associated with the selection component 260-b (e.g., the resistance or impedance of a transistor associated with the selection component 260-b). In some instances of the termination selector 330-b, the termination resistor 450 may be omitted (e.g., providing a direct electrical connection between the selection component 260-b and the signal path 420), which is supported when the impedance of the selection component 260-b or the signal path itself is sufficient for various signaling or termination requirements.

[0077] In some instances, the termination selector 330-b may alternatively or additionally include a termination resistor 460 that describes a resistor or impedance for signaling along a path between the signal path 410 and the signal path 430. In some instances, the termination resistor 460 may include a passive resistor having a nominal resistance (e.g., a 15Ω resistor element, a discrete resistor, an on-board DIMM resistor). In other instances, the termination resistor 460 may refer to an active resistor, such as a FET biased to impose a nominal resistance (e.g., a FET biased as a 15Ω resistor). In instances where the termination selector 330-b includes or is otherwise associated with both the termination resistor 450 and the termination resistor 460, the termination resistor 460 may have a resistance or impedance different from that of the termination resistor 450. In one instance, the termination resistor 450 may have an impedance of 15Ω (e.g., associated with a resistor element or a FET), and the termination resistor 460 may have an impedance of 50Ω (e.g., associated with a resistor element or a FET). Thus, the termination selector 330-b may be operable to select between one signal path having a first resistance or impedance and another signal path having a second resistance or impedance different from the first resistance or impedance.

[0078] Although the termination resistor 460 is illustrated as a component of the termination selector 330-b, in some instances, the termination resistor 460 may alternatively or additionally be included in another component of the memory system 240 that includes the termination selector 330-b, such as a component that shares a termination circuit. Further, although the termination resistor 460 is illustrated as a separate component, the termination resistor associated with the signal path 430 may refer to or otherwise include a resistor or impedance associated with the signal path 430, or a resistor or impedance associated with the selection component 260-b (e.g., the resistance or impedance of a transistor associated with the selection component 260-b). In some instances of the termination selector 330-b, the termination resistor 460 may be omitted (e.g., providing a direct electrical connection between the selection component 260-b and the signal path 430), which is supported when the impedance of the selection component 260-b or the signal path itself is sufficient for various signaling or termination requirements.

[0079] In some instances, the impedance or resistance of the termination resistor 460 may be configurable. For example, the termination resistor 460 may have a relatively high resistance or impedance in one operating mode and a relatively low resistance or impedance in another operating mode. In some instances, the impedance or resistance of the termination resistor 460 may be configured based on signaling through the signal path 465, which may carry signaling from the host device 210 or the memory device 110. In one instance, the impedance of the termination resistor 460 may be configured based on the type of access operation performed by the host device 210 (e.g., a memory system 240 different from the memory device that includes the termination selector 330-b, which may also be connected to the channel 280 associated with the signal path 410). For example, when the signaling received through the signal path 465 indicates that the host device is performing a read operation, the termination resistor 460 may have a first impedance, and when the signaling received through the signal path 465 indicates that the host device is performing a write operation, the termination resistor 460 may have a second different impedance.

[0080] Figure 5 An example of a system 500 that supports configurable memory termination in accordance with an example disclosed herein is illustrated. The system 500 includes a first memory system 240-c and a second memory system 240-d that are connected or coupled to a channel bus 310-a. In an example of the system 500, each of the memory systems 240 includes a first switch network 520 and a second switch network 530.

[0081] The respective first switch networks 520 of the memory system 240 are operable to selectively connect or isolate corresponding memory devices 110 (e.g., via the I / O circuitry of the memory system 240, not shown) from the channel bus 310. Each of the first switch networks 520 may include a set of one or more switches 525 that may operate based on signaling communicated via a respective signal bus 555. In some instances, the switches 525 may be transistors.

[0082] The respective second switch networks 530 of the memory system 240 are operable to selectively connect or isolate corresponding termination circuits 540 from the channel bus 310-a. Each of the second switch networks 530 may include a set of one or more switches 535 that may operate based on signaling communicated via a respective signal bus 555. In some instances, the switches 535 may be transistors. In some examples in accordance with the present invention, the second switch network 530 or the termination circuit 540 may be omitted (e.g., to selectively isolate the memory device 110 from the channel bus 310-a without connecting an alternative circuit).

[0083] In some instances, the respective first switch networks 520 may receive different signals than the respective second switch networks 530. For example, when the respective second switch networks 530 receive a “disable” signal, the respective first switch networks 520 may receive an “enable” signal, or vice versa. In some instances, this functionality may be supported by a signal inverter between the first switch network 520 and the second switch network 530 that may generate two control signals based on a single status signal (e.g., corresponding to whether the respective memory system is accessible). In other instances, different signals may be communicated on different signal paths of a control bus. In another example, the respective first switch networks 520, the respective second switch networks 530 may receive the same signal, but the first switch network 520 and the second switch network 530 may be otherwise configured to provide the described functionality. For example, the switches 525 may be normally open switches, while the switches 535 may be normally closed switches, or vice versa.

[0084] Each of the memory systems 240 may also include a receiver 550 operable to receive signaling from a host device for configuring various operations of the corresponding memory system 240. For example, the receiver 550 may be configured to receive various select or enable signals (e.g., SEL0, SEL1, EN), where such signaling may be specific to a particular memory system 240 or may be signaled jointly for any one of a group of memory systems 240 connected to the channel bus 310-a. The receiver 550 may communicate the signaling via a corresponding signal bus 555 to selectively enable or disable the switch 525 or the switch 535. For example, the receiver 550 may include control logic or circuitry configured to identify (e.g., based on signaling from the host device) whether the corresponding memory system 240 is available for access operations via the channel bus 310-a and to operate the corresponding first switch network 520 and the corresponding second switch network 530 accordingly.

[0085] In some instances, the first switch network 520 or a combination of the first switch network 520, the second switch network 530, and the receiver 550 may be referred to as a selection component (e.g., selection component 260) operable to selectively isolate the memory device 110 or the associated I / O circuitry 250 from the channel bus 310-a based at least in part on signals received from the host device. In some instances, the second switch network 530 or a combination of the first switch network 520, the second switch network 530, and the receiver 550 may be referred to as a selection component (e.g., selection component 260) operable to selectively connect one or more signal paths of the channel bus 310-a to one or more termination resistor elements (e.g., termination circuitry 540), which may operate during the selective isolation of the memory device 110 or the associated I / O circuitry 250 from one or more signal paths of the channel. In some instances, the first switch network 520, the second switch network 530, or the receiver 550 or a combination thereof may be operable to modify the connection between the input / output circuitry of the memory system 240 (e.g., the I / O circuitry 250 associated with one or more memory devices 110 of the memory system 240) and one or more signal paths between the host device and the memory system (e.g., of the channel bus 310-a) based at least in part on signals received from the host device.

[0086] System 500 can illustrate an example in which a first memory system 240-c is configured to be accessed via a channel bus 310-a and in which a second memory system 240-d is not configured to be accessed via the channel bus 310-a. Accordingly, a first switch network 520-a can be enabled, thereby allowing signaling between the channel bus 310-a and the memory devices of the first memory system 240-c. Correspondingly, a second switch network 530-a can be disabled, thereby isolating the termination circuit 540-a from the channel bus 310-a. Additionally, a first switch network 520-b can be disabled, thereby isolating the channel bus 310-a from the memory devices of the second memory system 240-d. Correspondingly, a second switch network 530-b can be enabled, thereby connecting the termination circuit 540-b to the channel bus 310-a. By connecting the termination circuit 540-b to the channel bus 310-a, signaling between the first memory system 240-c and the channel bus 310-a can be improved because various sources of signal attenuation or degradation associated with the signal path between the first switch network 520-b and the memory devices of the second memory system 240-d can be reduced or eliminated.

[0087] Figure 6 FIG. 600 is a block diagram showing a memory system 605 supporting configurable memory termination according to an example as disclosed herein. The memory system 605 can be an example of an aspect of a memory system as described with reference to Figures 2 to 5 The memory system 605 can include a selection component 610, an I / O circuit 615, a receiver 620, a termination circuit 625, and one or more memory devices 630. Each of these modules can communicate with each other directly or indirectly (e.g., via one or more buses).

[0088] The selection component 610 can modify the connection between the I / O circuit 615 and one or more signal paths between the host device and the memory system 605 based on signals received from the host device at the memory system 605. In some examples, the selection component 610 can isolate the I / O circuit 615 from one or more signal paths based on a signal indicating that the memory system 605 is not accessed by the host system. In some examples, the selection component 610 can connect the I / O circuit 615 to one or more signal paths based on a signal indicating that the memory system 605 is available for access by the host device. In some cases, one or more signal paths are associated with data channels.

[0089] The receiver 620 can receive signals from the host device indicating whether the memory system 605 is being accessed by the host system. In some examples, the receiver 620 can receive signals from the host device via a signal path (e.g., a control bus) different from one or more signal paths (e.g., a data bus).

[0090] The termination circuit 625 can connect one or more signal paths to a termination circuit 625 (e.g., of the memory system 605, associated with the memory system 605, of the selection component 610, associated with the selection component 610) based on an indication that the memory system 605 is not being accessed by the host device. In some instances, the termination circuit 625 can connect one or more signal paths to one or more resistive elements (e.g., of the memory system 605, associated with the memory system 605, of the selection component 610, associated with the selection component 610). In some instances, the termination circuit 625 can receive a second signal from the host device indicating the type of access operation. In some instances, the termination circuit 625 can modify the impedance of the termination circuit 625 based on receiving the second signal from the host device.

[0091] Figure 7 FIG. shows a flowchart illustrating one or more methods 700 for supporting configurable memory termination according to an example as disclosed herein. The operations of method 700 can be implemented by a memory system or its components as described herein. For example, the operations of method 700 can be performed by a memory system as described with reference to Figure 6 that described. In some instances, the memory system can execute a set of instructions to control functional elements of the memory system to perform the described functions. Additionally or alternatively, the memory system can perform aspects of the described functions using dedicated hardware.

[0092] At 705, the memory system can receive, at a memory system including one or more memory devices, a signal from the host device indicating whether the memory system is being accessed by the host device. Operation 705 can be performed according to the methods described herein. In some instances, aspects of operation 705 can be performed by a receiver as described with reference to Figure 6 that described.

[0093] At 710, the memory system can modify, at the memory system, a connection between an input / output circuit of the memory system and one or more signal paths between the host device and the memory system based on receiving the signal at the memory system. Operation 710 can be performed according to the methods described herein. In some instances, aspects of operation 710 can be performed by a selection component as described with reference to Figure 6 that described.

[0094] In some instances, the devices described herein may perform one or more methods, such as method 700. The device may include features, circuitry, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: at a memory system including one or more memory devices, receiving from a host device a signal indicating whether the memory system is being accessed by the host system; and at the memory system, modifying a connection between an input / output circuit of the memory system and one or more signal paths between the host device and the memory system, at least in part based on receiving the signal from the host device.

[0095] In some instances of method 700 and the device described herein, modifying the connection between the input / output circuit and the one or more signal paths may include operations, features, circuitry, components, or instructions for: isolating the input / output circuit from the one or more signal paths, at least in part based on the signal indicating that the memory system may not be accessed by the host device. Some instances of method 700 and the device described herein may further include operations, features, circuitry, components, or instructions for: connecting the one or more signal paths to a termination circuit (e.g., of the memory system, associated with the memory system, of a select component, associated with a select component), at least in part based on indicating that the memory system may not be accessed by the host device.

[0096] In some instances of method 700 and the device described herein, connecting the one or more signal paths to the termination circuit may include operations, features, circuitry, components, or instructions for: connecting the one or more signal paths to one or more resistive elements (e.g., of the memory system, associated with the memory system, of a select component, associated with a select component). Some instances of method 700 and the device described herein may further include operations, features, circuitry, components, or instructions for: receiving from the host device a second signal indicating a type of access operation; and modifying an impedance of the termination circuit, at least in part based on receiving the second signal from the host device.

[0097] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, components, or instructions for: connecting the input / output circuitry to the one or more signal paths based at least in part on signals indicative of what may be accessible to the host device by the memory system. In some examples of the method 700 and apparatus described herein, receiving the signals may include operations, features, circuitry, components, or instructions for: receiving the signals from the host device via a signal path different from the one or more signal paths. In some examples of the method 700 and apparatus described herein, the one or more signal paths may be associated with a data channel.

[0098] Note that the methods described herein are possible implementations, and the operations and steps may be rearranged or otherwise modified and other implementations are possible. Additionally, portions from two or more methods may be combined.

[0099] A device is described. The device may include: one or more memory devices; input / output circuitry associated with the one or more memory devices and for communicating with a host device via a channel; and a selection component operable to selectively isolate the input / output circuitry from one or more signal paths of the channel based at least in part on signals received from the host device.

[0100] Some examples of the device may include a receiver for receiving the signals from the host device via a signal path different from the one or more signal paths of the channel. Some examples of the device may include one or more termination resistor elements, and the selection component may be operable to selectively connect the one or more signal paths of the channel to the one or more termination resistor elements based at least in part on the signals received by the device from the host device during selective isolation of the input / output circuitry from the one or more signal paths of the channel.

[0101] In some examples, each of the one or more termination resistor elements includes a transistor. In some examples, each of the one or more termination resistor elements includes a resistor element. In some examples, the resistance of each termination resistor element may be configured based at least in part on signaling indicative of the type of access operation performed by the host device. Some examples of the device may include one or more resistor elements connected between the selection component and the input / output circuitry.

[0102] Describe a system. The system may include: a host device having a first input / output circuit for communicating via a channel; and a plurality of memory systems, each memory system having one or more memory devices and a corresponding second input / output circuit for communicating via the channel. The system may also include a plurality of selection components, each selection component corresponding to a respective one of the plurality of memory systems and operable to selectively isolate the second input / output circuit of the respective memory system from the first input / output circuit at least in part based on signaling from the host device.

[0103] In some instances of the system, each of the plurality of memory systems may include a respective termination circuit, and each of the selection components may be operable to selectively connect the respective termination circuit of the corresponding memory system to the first input / output circuit at least in part based on the signaling from the host device.

[0104] In some instances of the system, the impedance of each of the respective termination circuits may be configured at least in part based on the type of access operation performed by the host device.

[0105] In some instances of the system, when the signaling from the host device indicates that a first memory system among the plurality of memory systems is being accessed: a first selection component among the plurality of selection components corresponding to the first memory system may be operable to selectively connect the corresponding second input / output circuit of the first memory system to the first input / output circuit; and a second selection component among the plurality of selection components corresponding to a second memory system among the plurality of memory systems may be operable to selectively isolate the corresponding second input / output circuit of the second memory system from the first input / output circuit.

[0106] In some instances of the system, the signaling from the host device may be conveyed via a signal path different from the one or more signal paths of the channel.

[0107] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may illustrate a signal as a single signal; however, those of ordinary skill in the art will understand that a signal may represent a signal bus, where the bus may have a variety of bit widths.

[0108] As used herein, the term "virtual ground" refers to a node of a circuit that is held at an approximate zero volts (0V) voltage but is not directly coupled to ground. Thus, the voltage of the virtual ground may fluctuate temporarily and return to approximately 0V in the steady state. A virtual ground can be implemented using various electronic circuit elements, such as a voltage divider consisting of an operational amplifier and a resistor. Other implementations are possible. "Virtual ground" or "virtual earth ground" means connected to approximately 0V.

[0109] The terms "electronically communicate", "electrically contact", "connected", and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to electronically communicate (or electrically contact or be connected or be coupled) with each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that electronically communicate (or electrically contact or are connected or are coupled) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some cases, the flow of signals between the connected components may be interrupted for a period of time using one or more intermediate components such as switches or transistors.

[0110] The term "coupled" refers to the condition of moving from an open-circuit relationship between components (where signals cannot currently be communicated between the components through a conductive path) to a closed-circuit relationship between components (where signals can be communicated between the components through a conductive path). When a component, such as a controller, is coupled with other components, the component initiates a change that allows signals to flow between the other components through a conductive path that previously did not allow signal flow.

[0111] The term "isolated" refers to a relationship between components where signals cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, two components separated by a switch positioned between the components are isolated from each other when the switch is open. When a controller isolates two components, the controller creates a change that prevents signals from flowing between the components through a conductive path that previously allowed signal flow.

[0112] As used herein, the term "shorted" refers to a relationship between components where a conductive path is established between the components by activating a single intermediate component between the two components under discussion. For example, a first component shorted to a second component may exchange signals with the second component when a switch between the two components is closed. Thus, shorting can be a dynamic operation that enables charge to flow between components (or lines) that are in electronic communication.

[0113] The devices (including memory arrays) discussed herein may be formed on a semiconductor substrate (such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate (such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species (including but not limited to phosphorus, boron, or arsenic). Doping may be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0114] The switching components or transistors discussed herein may represent FETs and include three-terminal devices comprising a source, a drain, and a gate. The terminals may be connected to other electronic components by a conductive material (such as metal). The source and the drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and the drain may be separated by a lightly doped semiconductor region or a channel. If the channel is n-type (i.e., the majority carriers are signals), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0115] The descriptions presented herein describe example configurations in conjunction with the accompanying drawings and do not represent all examples that may be implemented or within the scope of the claims. The term "example" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "superior to other examples". The detailed description includes specific details to provide an understanding of the described technology. However, the technology may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0116] In the figures, similar components or features may have the same reference labels. Additionally, various components of the same type may be distinguished by adding a dash and a second label that differentiates the similar components after the reference label. When only the first reference label is used in the specification, the description may apply to any of the similar components having the same first reference label, regardless of the second reference label.

[0117] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0118] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the present invention and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. The features implementing the functions can also be physically located in various places, including being distributed such that portions of the functions are implemented at different physical locations. Also, as used herein (including in the claims), the "or" as used in a list of items (e.g., a list of items that begins with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of A, B, or C represents A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, without departing from the scope of the present invention, an example step described as "based on condition A" can be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0119] The present description is provided to enable a person skilled in the art to make or use the present invention. Those skilled in the art will recognize various modifications to the present invention, and without departing from the scope of the present invention, the general principles defined herein can be applied to other variations. Thus, the present invention is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system, comprising: a group of one or more memory devices of the memory system; one or more terminals of the memory system, operable to be coupled to a channel between the memory system and a host device; an input / output circuit of the memory system, coupled to the group of the one or more memory devices, the input / output circuit operable to communicate information between the channel and the group of the one or more memory devices of the memory system; and a selection component, coupled between the one or more terminals and the input / output circuit of the memory system, the selection component operable to electrically disconnect the input / output circuit from the one or more terminals of the memory system at least in part based on a signal received from the host device.

2. The memory system according to claim 1, further comprising: a receiver, for receiving the signal from the host device through a signal path different from the one or more signal paths of the channel coupled to the one or more terminals of the memory system.

3. The memory system according to claim 1, further comprising: one or more termination resistor elements, wherein the selection component is operable to electrically connect the one or more termination resistor elements to the one or more terminals of the memory system at least in part based on the memory system receiving the signal from the host device during the electrical disconnection between the input / output circuit and the one or more terminals of the memory system.

4. The memory system according to claim 3, wherein each of the one or more termination resistor elements includes a transistor.

5. The memory system according to claim 3, wherein each of the one or more termination resistor elements includes a resistor element.

6. The memory system according to claim 3, wherein the resistance of each termination resistor element is configurable at least in part based on signaling indicating a type of access operation performed by the host device.

7. The memory system according to claim 1, further comprising: one or more resistor elements, connected between the selection component and the input / output circuit.

8. A method for operating a memory system, the method comprising: receiving, at the memory system including one or more memory devices and one or more terminals, a signal from a host device indicating whether the memory system is being accessed by the host device, the one or more terminals being connected to one or more signal paths of a channel between the memory system and the host device; and modifying, at the memory system, an electrical connection between an input / output circuit of the memory system and the one or more terminals of the memory system at least in part based on receiving the signal from the host device, the one or more terminals of the memory system being connected to the one or more signal paths of the channel between the host device and the memory system.

9. The method according to claim 8, wherein modifying the electrical connection between the input / output circuit and the one or more terminals of the memory system includes: disconnecting the input / output circuit from the one or more terminals of the memory system at least in part based on the signal indicating that the memory system is not accessed by the host device.

10. The method according to claim 9, further comprising: connecting the one or more terminals of the memory system to a termination circuit at least in part based on the indication that the memory system is not accessed by the host device.

11. The method according to claim 10, wherein connecting the one or more terminals of the memory system to the termination circuit includes: connecting the one or more terminals of the memory system to one or more resistive elements.

12. The method according to claim 10, further comprising: receiving a second signal from the host device indicating the type of access operation; and modifying the impedance of the termination circuit at least in part based on receiving the second signal from the host device.

13. The method according to claim 9, further comprising: connecting the input / output circuit to the one or more terminals of the memory system at least in part based on a signal indicating that the memory system is accessible by the host device.

14. The method according to claim 8, wherein receiving the signal includes: receiving the signal from the host device through a signal path different from the one or more signal paths.

15. The method according to claim 8, wherein the one or more signal paths are associated with data channels.

16. An electronic system, comprising: a host device having a first input / output circuit for communicating through a channel shared by a plurality of memory systems; the plurality of memory systems, each of the plurality of memory systems including one or more memory devices, one or more terminals coupled to the channel, and a corresponding second input / output circuit for communicating through the channel; and a plurality of selection components, each of the plurality of selection components corresponding to a respective one of the plurality of memory systems and each operable to electrically disconnect the corresponding second input / output circuit of the corresponding one of the plurality of memory systems from the first input / output circuit of the host device at least in part based on signaling from the host device.

17. The electronic system according to claim 16, wherein each of the plurality of memory systems includes a corresponding termination circuit, and wherein each of the selection components is operable to electrically connect the corresponding termination circuit of the corresponding memory system to the first input / output circuit at least in part based on the signaling from the host device.

18. The electronic system according to claim 17, wherein the impedance of each of the corresponding termination circuits is configurable at least in part based on the type of access operation performed by the host device.

19. The electronic system according to claim 16, wherein when the signaling from the host device indicates that the first memory system among the multiple memory systems is being accessed: The first selection component corresponding to the first memory system among the multiple selection components is operable to electrically connect the corresponding second input / output circuit of the first memory system to the first input / output circuit; and The second selection component corresponding to the second memory system among the multiple memory systems is operable to electrically disconnect the corresponding second input / output circuit of the second memory system from the first input / output circuit.

20. The electronic system according to claim 16, wherein the signaling from the host device is conveyed through a signal path different from one or more signal paths of the channel.

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