Electronic devices and methods and systems of manufacturing the same

Abstract

Electronic devices and methods and systems of manufacturing the same are provided. The electronic devices include a dielectric layer including grains having aligned crystal orientations, which can be between a substrate and a gate electrode. The dielectric layer can be between spaced apart first and second electrodes. Methods of manufacturing electronic devices can include preparing a substrate having a channel layer; forming a dielectric layer on the channel layer; and forming a gate electrode on the dielectric layer.

Description

Technical Field

[0001] The present invention relates to electronic devices and methods and / or systems for manufacturing such electronic devices, and more specifically, to electronic devices comprising a dielectric layer having a controlled crystal orientation and methods and / or systems for manufacturing such electronic devices. Background Technology

[0002] Conventional silicon-based electronics have limitations in improving operating characteristics and scaling down in size. For example, when measuring the operating voltage and current characteristics in a conventional silicon-based logic transistor, the subthreshold swing (SS) is known to be limited to about 60 mV / dec. Such limitations may be a suppressor factor in reducing the operating voltage to about 0.8 V or less when shrinking the logic transistor size, thus increasing the power density and limiting the scaling down of the logic transistor. Summary of the Invention

[0003] Some example implementations provide electronic devices including dielectric layers having controlled crystal orientations, and methods and / or systems for manufacturing such electronic devices.

[0004] Other aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing some of the exemplary embodiments of this disclosure.

[0005] According to some example embodiments, an electronic device may include a substrate, a dielectric layer on the substrate, and a gate electrode on the dielectric layer. The dielectric layer may include grains having aligned crystal orientations.

[0006] The electronic device may also include a channel layer on a substrate, wherein the channel layer overlaps with a gate electrode in a direction perpendicular to the top surface of the substrate, and a source and a drain are provided on opposite sides of the channel layer in a direction parallel to the top surface of the substrate.

[0007] The channel layer may include at least one of Si, Ge, SiGe, III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, 2D semiconductor materials, quantum dots, and organic semiconductors.

[0008] The dielectric layer may include ferroelectric materials.

[0009] The dielectric layer may include an oxide of at least one of Hf, Si, Al, Zr, Y, La, Gd and Sr.

[0010] The dielectric layer may also include dopants.

[0011] The dielectric layer can have a thickness of about 0.5 nm to about 4 nm in a direction perpendicular to the top surface of the substrate.

[0012] Grains can have <111> Crystal orientation.

[0013] Electronic devices may also include amorphous or crystalline dielectric layers between a substrate and a dielectric layer, between a dielectric layer and a gate electrode, or combinations thereof. A crystalline dielectric layer includes grains having a crystal orientation different from that of the grains of the dielectric layer.

[0014] The amorphous dielectric layer may include an oxide of at least one of Hf, Si, Al, Zr, Y, La, Gd and Sr.

[0015] The crystalline dielectric layer may include a 2D insulating material.

[0016] According to some example embodiments, an electronic device may include: a first electrode and a second electrode spaced apart from each other and not in direct contact; and a dielectric layer between the first electrode and the second electrode. The dielectric layer may include grains having aligned crystal orientations.

[0017] The first electrode and the second electrode include grains having a crystal orientation different from that of the grains of the dielectric layer.

[0018] The dielectric layer may include ferroelectric materials.

[0019] The electronic device may also include an amorphous or crystalline dielectric layer between the first electrode and the dielectric layer, between the second electrode and the dielectric layer, or a combination thereof. The crystalline dielectric layer may include grains having a crystal orientation different from the aligned crystal orientation of the grains in the dielectric layer.

[0020] According to some example embodiments, a method of manufacturing an electronic device may include: preparing a substrate having a channel layer; forming a dielectric layer on the channel layer, wherein the dielectric layer includes grains having aligned crystal orientations; and forming a gate electrode on the dielectric layer.

[0021] The method may also include forming an amorphous dielectric layer or a crystalline dielectric layer between a substrate and a dielectric layer, between a dielectric layer and a gate electrode, or a combination thereof. A crystalline dielectric layer may include grains having a crystal orientation different from the aligned crystal orientation of the grains in the dielectric layer.

[0022] The formation of the dielectric layer may include: depositing an amorphous dielectric material layer on a channel layer, and then crystallizing the amorphous dielectric material layer to form the dielectric layer, such that the crystallized amorphous dielectric material layer includes grains having aligned crystal orientations.

[0023] The dielectric layer may include ferroelectric materials.

[0024] The dielectric layer can have a thickness of about 0.5 nm to about 4 nm.

[0025] According to some exemplary embodiments, a method of manufacturing a computing device may include: manufacturing electronic devices according to some exemplary embodiments; and forming a computing device by incorporating electronic devices into computing device components.

[0026] The computing device components may include at least one of processing circuitry and memory.

[0027] According to some exemplary embodiments, a method of manufacturing an electronic device may include forming a dielectric layer on a first electrode and forming a second electrode on the dielectric layer. The first and second electrodes may comprise conductive metals. The dielectric layer may comprise grains having aligned crystal orientations.

[0028] The method may also include forming at least one amorphous dielectric layer between the first electrode and the dielectric layer, between the dielectric layer and the second electrode, or a combination thereof.

[0029] The method may further include forming at least one crystalline dielectric layer between the first electrode and the dielectric layer, between the dielectric layer and the second electrode, or a combination thereof. The at least one crystalline dielectric layer may include grains having a crystal orientation different from the aligned crystal orientation of the grains in the dielectric layer.

[0030] The formation of the dielectric layer may include: depositing an amorphous dielectric material layer on a first electrode, and then crystallizing the amorphous dielectric material layer to form the dielectric layer, such that the crystallized amorphous dielectric material layer includes grains having aligned crystal orientations.

[0031] According to some exemplary embodiments, a method of manufacturing a computing device may include: manufacturing electronic devices according to some exemplary embodiments; and forming a computing device by incorporating electronic devices into computing device components.

[0032] The computing device components may include at least one of processing circuitry and memory.

[0033] According to some example embodiments, a system for manufacturing electronic devices may include a process chamber comprising a base or chuck configured to structurally support one or more devices or layers within the process chamber. The system may include multiple component sources and multiple controllers, each component source being coupled to the process chamber via a separate controller, each controller configured to control the supply of individual materials held in the separately coupled component source to the process chamber. The system may include processing circuitry configured to control at least the plurality of controllers to manufacture electronic devices based on: preparing a substrate having a channel layer on the base or chuck; forming a dielectric layer on the channel layer, wherein the dielectric layer includes grains having aligned crystal orientations; and forming a gate electrode on the dielectric layer.

[0034] The processing circuit may be further configured to control at least the plurality of controllers to form at least one amorphous dielectric layer between the substrate and the dielectric layer, between the dielectric layer and the gate electrode, or a combination thereof.

[0035] The processing circuitry may be further configured to control at least the plurality of control devices to form at least one crystalline dielectric layer between the substrate and the dielectric layer, between the dielectric layer and the gate electrode, or a combination thereof. The at least one crystalline dielectric layer may include grains having a crystal orientation different from the aligned crystal orientation of the grains in the dielectric layer.

[0036] The formation of the dielectric layer may include: depositing an amorphous dielectric material layer on a channel layer, and then crystallizing the amorphous dielectric material layer to form the dielectric layer, such that the crystallized amorphous dielectric material layer includes grains having aligned crystal orientations. Attached Figure Description

[0037] The above and other aspects, features, and advantages of some exemplary embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0038] Figure 1 This is a cross-sectional view showing an electronic device according to some example embodiments;

[0039] Figure 2 yes Figure 1 An enlarged cross-sectional view of the dielectric layer shown;

[0040] Figure 3 It is a graph showing the improved subthreshold swing (SS) characteristics of an electronic device according to some example embodiments;

[0041] Figure 4 This is a cross-sectional view showing an electronic device according to some example embodiments;

[0042] Figure 5 This is a cross-sectional view showing an electronic device according to some example embodiments; and

[0043] Figure 6A , Figure 6B , Figure 6C and Figure 6D This is a diagram illustrating a method of manufacturing an electronic device according to some example embodiments.

[0044] Figure 7 A schematic diagram is shown of a system configured to control the manufacture of electronic devices according to some example embodiments;

[0045] Figure 8 A schematic diagram of an electronic device that may include the electronic device according to some example embodiments is shown;

[0046] Figure 9 A schematic diagram of a system configured to control the manufacture of an electronic device according to some example embodiments is shown; and

[0047] Figure 10 This illustrates the implementation of some example methods by Figure 9 The system shown is a flowchart of a method for manufacturing electronic devices. Detailed Implementation

[0048] Reference will now be made in detail to exemplary embodiments, some of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements.

[0049] In this regard, some example implementations may take different forms and should not be construed as limited to the description set forth herein.

[0050] Therefore, only some exemplary embodiments are described below with reference to the accompanying drawings to explain various aspects.

[0051] As used herein, the term “and / or” includes any and all combinations of one or more of the related listed items (e.g., A, B, and C).

[0052] Expressions such as "at least one of..." modify the entire column of elements when they follow a column of elements, but not individual elements within that column. For example, "at least one of A, B, and C" and "at least one of A, B, or C" can be interpreted to cover any of the following combinations: A; B; A and B; A and C; B and C; and A, B, and C.

[0053] In the following text, being described as "on top of" or "above" can include not only being directly above (e.g., overlapping in the vertical direction) and in contact, but also covering over in the presence of intervening elements and / or spaces. When an element or layer is referred to as being "on" or "above" another element or layer, the element or layer may be directly on the other element or layer (e.g., in direct contact with it), or the element or layer may be indirectly on the other element or layer (e.g., separated from the other element or layer by one or more intervening spaces and / or structures without direct contact). When an element is described as being directly between two other elements, the element may be in direct contact with each of the two other elements; for example, opposite sides or opposite surfaces of the element may each be in direct contact with separate elements of the two other elements.

[0054] Unless the context clearly indicates otherwise, singular expressions include plural expressions. The term "the" and similar terms may be used in both singular and plural forms. Regarding the steps constituting the method, unless there is an explicit description of the order or otherwise, the steps may be performed in an appropriate order. It is not necessary to be limited to the order described in conjunction with the steps. All examples or exemplary terms used are for the purpose of describing the technical conception in detail only, and examples or exemplary terms are not intended to limit the scope unless they are limited by the scope claimed.

[0055] Furthermore, when a portion is described as "comprising" a component, this means that it may also include other components, and unless otherwise stated, other components are not excluded. The term "above" and similar terms may be used in both singular and plural forms. If the steps constituting a method are not explicitly stated to have a corresponding order or the reverse of a corresponding order, the steps may be performed in an appropriate order. It is not necessary to be limited to the order provided in the description of the steps above. All examples or exemplary terms are used only for the purpose of describing the technical concept in detail, and the scope of this disclosure is not limited by the use of examples or exemplary terms unless defined by the claims.

[0056] It will be understood that a component and / or its properties may be stated herein as “identical” or “equivalent” to other components, and it will also be understood that a component and / or its properties stated herein as “identical” or “equivalent” to other components may be “identical” or “equivalent” or “substantially” or “substantially” similar to ...

[0057] It will be understood that elements and / or their properties (e.g., structure, properties of one or more elements, length, distance, energy level, energy barrier, etc.) described herein as "substantially" identical encompass elements and / or their properties (e.g., structure, properties of one or more elements, length, distance, energy level, energy barrier, etc.) within manufacturing and / or material tolerances, and / or elements and / or their properties (e.g., structure, properties of one or more elements, length, distance, energy level, energy barrier, etc.) that have a relative difference in size equal to or less than 10%. Furthermore, regardless of whether elements and / or their properties (e.g., structure, properties of one or more elements, length, distance, energy level, energy barrier, etc.) are modified to "substantially," it will be understood that these elements and / or their properties (e.g., structure, properties of one or more elements, length, distance, energy level, energy barrier, etc.) should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around the described elements and / or their properties (e.g., structure, properties of one or more elements, length, distance, energy level, energy barrier, etc.).

[0058] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical value includes a tolerance of ±10% around said value. When a range is specified, the range includes all values ​​therebetween, such as in increments of 0.1%.

[0059] Where elements, properties, etc. are described herein as having “small” or “very small” differences between each other, it will be understood that the variation between the sizes of the elements and / or properties may be equal to or less than 10% of the size of the described elements, properties, etc.

[0060] Throughout this specification, it will be understood that although the terms first, second, etc., may be used to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another.

[0061] It will be understood that when an element, layer, structure, etc. is described herein as being "made" and / or "formed" from one or more materials, the element, layer, structure, etc. may "at least partially comprise" the one or more materials.

[0062] Figure 1 This is a cross-sectional view showing an electronic device 100 according to some example embodiments. Figure 1 The illustrated electronic device 100 (as a semiconductor-based device) may have a gate stack structure having a ferroelectric material and a gate electrode. Such an electronic device 100 may be, for example, a logic device or a memory device.

[0063] Reference Figure 1The electronic device 100 includes a substrate 110, an amorphous dielectric layer 130, a dielectric layer 140, and a gate electrode 150. A channel layer 115 is located on the substrate 110 (e.g., above) at a position corresponding to the gate electrode 150 (e.g., the channel layer 115 may be in a direction perpendicular to the top surface 110S of the substrate 110, such as...). Figure 1 The source electrode S 121 and the drain electrode D 122 can be aligned in a direction parallel to the top surface 110S of the substrate 110 (e.g., in the Z direction shown) with the gate electrode 150 (also referred to herein as alignment). Figure 1 Provided on both sides (e.g., opposite sides) of the channel layer 115 in the X direction (as shown) (e.g., on it, in direct contact, etc.). Figure 1 As shown, source 121 can be electrically connected to one side of channel layer 115, and drain 122 can be electrically connected to the opposite side of channel layer 115. Source 121 and drain 122 can be formed by implanting impurities into different regions of substrate 110, with the substrate 110 in a direction parallel to the top surface 110S of substrate 110 (e.g.,...). Figure 1 The region between the source 121 and the drain 122 (shown in the X direction) can be defined as channel layer 115. Therefore, channel layer 115 can be a portion of substrate 110 having side boundaries defined by source 121 and drain 122, a bottom boundary 115B defined by bottom boundaries 121B and 122B of source 121 and drain 122, and a top surface 115S of channel layer 115 can be a portion (e.g., a confined portion) of top surface 110S extending between source 121 and drain 122. Figure 1 As shown, a portion of the top surface 110S that serves as either the source 121 or the drain 122 may be exposed from layers 130-150. Such a channel layer 115, which is part of the substrate 110, will be understood as being "on" the substrate 110.

[0064] like Figure 1 As shown, the source 121 and drain 122 can be in a direction parallel to the top surface 110S of the substrate 110 (e.g., Figure 1 Located on the opposite side of the channel layer 115 in the X direction shown. The depth of the channel layer 115 can be determined by the source 121 and drain 122 extending from the top surface 110S of the substrate 110 in a direction perpendicular to the surface 110S (which can be...). Figure 1 Depth limitation in the Z direction (as shown). Figure 1 As shown, each of layers 130-150 may overlap at least partially perpendicularly with channel layer 115 (e.g., as shown in the diagram). Figure 1 (As shown, they completely overlap) (for example, they overlap in a direction perpendicular to the extension of surface 110S, which could be...) Figure 1(as shown in the Z direction), the source 121 and drain 122 can be exposed by the stack of layers 130-150 (e.g., as shown in the Z direction). Figure 1 (As shown, it is fully exposed).

[0065] In some example embodiments, substrate 110 may be a Si substrate, but may be a substrate comprising materials other than Si (such as Ge, SiGe, III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional (2D) semiconductor materials, quantum dots, or organic semiconductors, any combination thereof). In some example embodiments, channel layer 115 (which may be as follows) Figure 1 The material shown (which may be a portion of substrate 110 or a separate piece of material relative to substrate 110) may include at least one of Si, Ge, SiGe, III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional (2D) semiconductor materials, quantum dots, or organic semiconductors. The material of substrate 110 is not limited thereto and may be varied.

[0066] In some example implementations, as described below, the channel layer 115 may be formed as a material layer distinct from the substrate 110 (e.g., a separate piece of material relative to the substrate 110), rather than as... Figure 1 The material layer shown is a portion of substrate 110 (e.g., channel layer 115 is a portion of a monolithic material at least partially constituting substrate 110). An amorphous dielectric layer 130 is provided on the surface of channel layer 115 of substrate 110 (e.g., the portion of surface 110S that extends between source 121 and drain 122 and defines the upper boundary of channel layer 115). Therefore, it will be understood that amorphous dielectric layer 130 can be on substrate 110 (e.g., directly on substrate 110).

[0067] The amorphous dielectric layer 130 may include, but is not limited to, at least one oxide selected from Hf, Si, Al, Zr, Y, La, Gd, and Sr. The amorphous dielectric layer 130 may be deposited on the channel layer 115 of the substrate 110 by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. (e.g., directly on and in contact with a portion of the top surface 115S of the channel layer 115 defined on surface 110S, such as...). Figure 1 (As shown).

[0068] Furthermore, a dielectric layer 140 comprising grains having aligned crystal orientations 140a (e.g., at least some or all of the grains may have aligned crystal orientations, such as extending parallel in a particular direction) is provided over the amorphous dielectric layer 130 (e.g., directly on the top surface 130S of the amorphous dielectric layer 130). The amorphous dielectric layer 130 is provided between the channel layer 115 and the dielectric layer 140 of the substrate 110 (e.g., as shown in the image). Figure 1 The amorphous dielectric layer 130 is directly between (e.g., in direct contact with both surfaces 110S and 140B) so that it is unaffected by the crystal structure of the substrate 110, and the amorphous dielectric layer 130 can be configured to assist the grains of the dielectric layer 140 in having a crystal orientation 140a aligned to a specific (or alternatively, predetermined) direction. In some example embodiments, the amorphous dielectric layer 130 may be between the dielectric layer 140 and the gate electrode 150 (e.g., directly between them). In some example embodiments, the electronic device 100 may include a first amorphous dielectric layer 130 between the channel layer 115 and the dielectric layer 140 (e.g., directly between them) and a second amorphous dielectric layer between the dielectric layer 140 and the gate electrode 150 (e.g., directly between them). In some example embodiments, electronic device 100 may be without amorphous dielectric layer 130, such that dielectric layer 140 may be on substrate 110 or directly on substrate 110 (e.g., in direct contact with a portion of the top surface 115S of the defining channel layer 115 of surface 110S). In some example embodiments, crystalline dielectric layer may be included in electronic device 100 at any of the locations described above with respect to amorphous dielectric layer 130 (e.g., electronic device 100 may include at least one crystalline dielectric layer instead of at least one amorphous dielectric layer 130). Therefore, it will be understood that an electronic device according to any example embodiment may include at least one amorphous dielectric layer (e.g., 130) or at least one crystalline dielectric layer, wherein the at least one amorphous dielectric layer (e.g., 130) or at least one crystalline dielectric layer may be between a dielectric layer (e.g., 140) and a first layer (e.g., substrate 110) on one side of the dielectric layer, between a dielectric layer (e.g., 140) and a second layer (e.g., gate electrode 150) on the opposite side of the dielectric layer, or a combination thereof (e.g., a first amorphous dielectric layer or crystalline dielectric layer between dielectric layer 140 and substrate 110 and a second amorphous dielectric layer or crystalline dielectric layer between dielectric layer 140 and gate electrode 150).

[0069] Figure 2 yes Figure 1 An enlarged cross-sectional view of the dielectric layer shown. (Refer to...) Figure 2 The dielectric layer 140 may include a plurality of grains 141 defined by grain boundaries 141a.

[0070] Here, the grains 141 constituting the dielectric layer 140 may have an alignment with a specific (or alternatively, predetermined) direction. Figure 1 The crystal orientation is 140a. In Figure 2 In the accompanying drawings, reference numeral 140b denotes a crystal plane of a grain 141 constituting (e.g., at least partially constituting) the dielectric layer 140, and typically, the crystal plane 140b may be perpendicular to the crystal direction 140a. The crystal planes 140b may be parallel to each other. The grains 141 constituting the dielectric layer 140 may have, for example... <111> Crystal orientation. <111> The Miller index represents the crystal orientation in crystallography.

[0071] here, <111> Crystal orientations include, for example,

[111] , [-111], [1-11], [11-1], [-1-11], [-11-1], [1-1-1], and / or [-1-1-1]. However, this is merely an example, and the grains 141 constituting the dielectric layer 140 may have other orientations besides

[111] , [-111], [1-1-1], [1-1-1], and / or [-1-1-1]. <111> Crystal orientations other than crystal orientations.

[0072] The dielectric layer 140 may include (for example, at least partially) a ferroelectric material.

[0073] Ferroelectric materials have a crystalline structure in which the charge distribution within a unit lattice is non-centrosymmetric, thus giving ferroelectric materials electric dipoles, i.e., spontaneous polarization.

[0074] Even in the absence of an external electric field, ferroelectric materials exhibit residual polarization caused by dipoles. Furthermore, the polarization direction can be switched in domains by an external electric field. Depending on the external electric field, the ferroelectric material may or may not have hysteresis properties. In some example embodiments, the dielectric layer 140 may not contain any ferroelectric material.

[0075] The dielectric layer 140 may include an oxide of at least one of, for example, Hf, Si, Al, Zr, Y, La, Gd, and Sr, but this is only an example. Furthermore, the dielectric layer 140 may also include a dopant, but the example embodiment is not limited thereto. Here, the dopant may include at least one of, for example, Si, Al, Zr, Y, La, Gd, Sr, and Hf. When a dopant is included in the dielectric layer 140, the dopant may be doped entirely to have the same concentration, or it may be doped to have different concentrations depending on the region of the dielectric layer 140.

[0076] Furthermore, depending on the region of the dielectric layer 140, different doping materials can be incorporated. As described below, the dielectric layer 140 can be formed by depositing an amorphous dielectric material layer on the amorphous dielectric layer 130 (e.g., directly on the top surface 130S) using deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc., and then crystallizing it. When the amorphous dielectric material layer crystallizes based on annealing, grains 141 having a crystal orientation 140a aligned in a specific (or alternatively, predetermined) direction (including, for example, aligned in a single specific direction) can be grown to form a dielectric layer 140 having a controlled crystal orientation 140a. The dielectric layer 140 can have a thickness 140T of, for example, from about 0.5 nm to about 4 nm, but the example embodiments are not limited thereto. A gate electrode 150 is provided on (e.g., on) the dielectric layer 140 (e.g., directly on the top surface 140S).

[0077] The gate electrode 150 can be positioned (e.g., configured) facing the channel layer 115 of the substrate 110 (e.g., partially or completely overlapping the channel layer 115 in the Z direction perpendicular to the top surface 110S). Such a gate electrode 150 may include a conductive metal. Here, the gate electrode 150 may have a crystal orientation different from that of the dielectric layer 140. According to some example embodiments, the electronic device 100 has a ferroelectric material constituting the dielectric layer 140, thereby reducing the subthreshold swing (SS) of the electronic device 100. Therefore, based on the fact that including this ferroelectric material can improve the performance of the electronic device 100, the ferroelectric material includes grains having aligned crystal orientations (e.g., grains oriented in a particular (e.g., a single) identical direction, grains oriented parallel to each other in a particular direction, etc.).

[0078] Figure 3 This illustrates a logic transistor according to some example implementations (e.g., Figures 1-2 The diagram shown illustrates the improved subthreshold swing (SS) characteristics of an electronic device including a dielectric layer (which comprises grains with aligned crystal orientations). Figure 3 In the diagram, curve "A" shows the operating voltage (Vg) and current (Id) characteristics of a conventional silicon-based logic transistor (e.g., a conventional silicon-based electronic device), and curve "B" shows the operating voltage (Vg) (e.g., in mV) and current (Id) (e.g., in A / μm) characteristics of a logic transistor (e.g., an electronic device) according to some exemplary embodiments of this disclosure. 2 (Unit-based) characteristics. Reference. Figure 3 Conventional silicon-based transistors have a known subthreshold swing (SS) that is limited to about 60 mV / dec at room temperature (300 K).

[0079] Logic transistors (e.g., electronic devices) according to some exemplary embodiments of this disclosure include a ferroelectric layer, thereby generating voltage amplification through a negative capacitance effect. As shown in curve "B", the subthreshold swing SS of the logic transistors including the ferroelectric layer according to some exemplary embodiments can be reduced to about 60 mV / dec or less relative to the subthreshold swing of conventional silicon-based logic transistors as shown in curve "A". Electronic device 100 according to some exemplary embodiments includes a dielectric layer 140 having a ferroelectric material, wherein the ferroelectric material has grains 141 having aligned crystal orientations 140a, thereby improving the polarization characteristics of the dielectric layer 140 and the performance of the electronic device 100. In conventional electronic devices having ferroelectric materials, the grains of the ferroelectric material are arranged in random orientations. However, in some exemplary embodiments of the electronic device 100 according to this disclosure, the dielectric layer 140 includes a ferroelectric material, wherein the ferroelectric material includes grains 141 having an aligned crystal orientation 140a, so that the dielectric layer 140 can have a relatively larger residual polarization than conventional electronic devices, thereby improving the polarization characteristics of the dielectric layer 140.

[0080] Furthermore, in the electronic device 100 according to some example embodiments, the polarization direction of the dielectric layer 140 is aligned in a specific direction, thereby increasing the depolarization field and thus increasing the negative capacitance effect. Therefore, the subthreshold swing SS of the electronic device 100 can be reduced (e.g., below about 60 mV / dec), thereby further improving the performance of the electronic device 100. Figures 1-2 In the illustrated example embodiment, an amorphous dielectric layer 130 has been described as being provided between the channel layer 115 and the dielectric layer 140 of the substrate 110. However, as described herein, in addition to or instead of the amorphous dielectric layer 130, a crystalline dielectric layer (not shown) may be provided between the channel layer 115 and the dielectric layer 140 of the substrate 110. Therefore, in Figure 1 The layer indicated by the label "130" (and in Figure 4 , Figure 5 and Figures 6B-6D The similar layers 330, 430 shown may be crystalline dielectric layers rather than amorphous dielectric layers. Here, a crystalline dielectric layer may include grains having a crystal orientation different from that of the grains of the dielectric layer 140 thereon.

[0081] Similar to the amorphous dielectric layer 130 described above, a crystalline dielectric layer can be provided between the channel layer 115 and the dielectric layer 140 of the substrate 110, thereby allowing the crystalline dielectric layer to be unaffected by the crystal structure of the substrate 110 and helping the grains of the dielectric layer 140 to have a crystal orientation 140a aligned to a specific (or alternatively, predetermined) direction. The crystalline dielectric layer can be located between the channel layer 115 and the dielectric layer 140 (e.g., directly between them), between the dielectric layer 140 and the gate electrode 150 (e.g., directly between them), or a combination thereof (e.g., multiple individual crystalline dielectric layers may exist in the electronic device 100).

[0082] The crystalline dielectric layer can include, for example, a 2D insulating material, such as hexagonal boron nitride (h-BN). However, this is just an example, and the crystalline dielectric layer can include a variety of other dielectric materials.

[0083] The foregoing only describes an amorphous dielectric layer 130 or a crystalline dielectric layer provided between the channel layer 115 and the dielectric layer 140 of the substrate 110. However, the amorphous dielectric layer 130 or the crystalline dielectric layer may additionally be provided between the dielectric layer 140 and the gate electrode 150 (e.g., directly between the dielectric layer 140 and the gate electrode 150). The amorphous dielectric layer 130 or the crystalline dielectric layer may not be provided between the channel layer 115 and the dielectric layer 140 of the substrate 110, but may instead be provided between the dielectric layer 140 and the gate electrode 150. The amorphous dielectric layer 130 or the crystalline dielectric layer may be multiple separate layers, with one layer (e.g., a first layer) between the channel layer 115 and the dielectric layer 140, and another layer (e.g., a second layer) between the dielectric layer 140 and the gate electrode 150.

[0084] In some example embodiments, the dielectric layer 140 is provided directly on the channel layer 115 of the substrate 110 (e.g., in direct contact with the top surface 115S of the channel layer 115), wherein the dielectric layer 140 includes grains 141 having a crystal orientation 140a aligned to a direction different from the crystal orientation of the grains of the substrate 110.

[0085] The aforementioned amorphous dielectric layer 130 or crystalline dielectric layer may not be provided. In other words, the dielectric layer 140, including grains 141 with aligned crystal orientation 140a, may be directly provided on the channel layer 115 of the substrate 110.

[0086] Here, the dielectric layer 140 may include grains 141 having an aligned crystal orientation 140a, which is arranged in a direction different from the crystal orientation of the substrate 110.

[0087] Figure 4 This is a cross-sectional view showing an electronic device according to some example embodiments.

[0088] The following description will focus on the differences from the example implementation described above. (Refer to...) Figure 4 The electronic device 200 includes a substrate 210, a channel layer 215, an amorphous dielectric layer 130, a dielectric layer 140, and a gate electrode 150. A source electrode 221 and a drain electrode 222 can be provided on both sides of the channel layer 215 (e.g., opposite sides).

[0089] The substrate 210 may include, but is not limited to, at least one of Si, Ge, SiGe, III-V group semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, 2D semiconductor materials, quantum dots, organic semiconductors, etc. A channel layer 215 may be provided on the top surface of the substrate 210 (e.g., as shown in the image). Figure 4 As shown, directly on it), however, the example implementation is not limited to this.

[0090] The channel layer 215 can be provided as a material layer distinct from the substrate 210, meaning that the material layer is not part of the substrate 210 (e.g., it is a separate piece of material relative to the substrate 210). The channel layer 215 can include at least one of, for example, oxide semiconductors, nitride semiconductors, oxide-oxygen nitride semiconductors, two-dimensional materials (2D materials), quantum dots, and organic semiconductors. Here, oxide semiconductors can include, for example, InGaZnO, two-dimensional materials can include, for example, transition metal dichalcogenides (TMDs) or graphene, and quantum dots can include colloidal QDs, nanocrystalline structures, etc.

[0091] However, this is merely an example, and some example implementations are not limited to this. Source electrode 221 and drain electrode 222 can be provided on both sides of channel layer 215 (e.g., opposite sides). Source electrode 221 can be connected to one side of channel layer 215, and drain electrode 222 can be connected to the other opposite side of channel layer 215.

[0092] The source electrode 221 and drain electrode 222 may be formed of a conductive material such as a metal, a metal compound, or a conductive polymer (e.g., may at least partially include said conductive material). Since the amorphous dielectric layer 130, dielectric layer 140, and gate electrode 150, which are sequentially stacked on the channel layer 215, have already been described above, their detailed description is omitted.

[0093] A crystalline dielectric layer (not shown) may be provided on (e.g., on) the channel layer 215 (e.g., directly on the top surface 215S of the channel layer 215) instead of the amorphous dielectric layer 130. Here, the crystalline dielectric layer may include grains having a different crystal orientation than the grains of the dielectric layer 140 thereon.

[0094] Figure 5This is a cross-sectional view showing an electronic device according to some example embodiments. Figure 5 The electronic device 300 shown can be, for example, a capacitor. (See reference...) Figure 5 The electronic device 300 includes a first electrode 310 and a second electrode 320 spaced apart from each other in the Z direction (e.g., spaced apart without direct contact), and an amorphous dielectric layer 330 and a dielectric layer 340 provided between the first electrode 310 and the second electrode 320 (e.g., directly between them). The Z direction may be perpendicular to the top surface (e.g., one or both top surfaces 310S and 320S) of one or both of the first electrode 310 or the second electrode 320. The amorphous dielectric layer 330 may be provided over the first electrode 310 (e.g., directly on the top surface 310S), and the dielectric layer 340 may be provided between the amorphous dielectric layer 330 and the second electrode 320 (e.g., directly between them) (e.g., such that the dielectric layer 340 can directly contact the bottom surface 320B of the second electrode 320). Here, the dielectric layer 340 may include a ferroelectric material according to any example embodiment, but the example embodiments are not limited thereto, and in some example embodiments, the dielectric layer 340 may not include any ferroelectric material. The first electrode 310 and the second electrode 320 may each include a conductive metal. In some example embodiments, the amorphous dielectric layer 330 may be absent, and the dielectric layer 340 may be between the first electrode 310 and the second electrode 320 (e.g., directly between the first electrode 310 and the second electrode 320) (e.g., in direct contact with the two surfaces 310S, 320B on opposite sides of the dielectric layer 340).

[0095] In some example embodiments, electronic device 300 may be a capacitor having a metal-ferroelectric-insulator-metal (MFIM) structure. The first electrode 310 may include a semiconductor, and the second electrode 320 may include a conductive metal. In this case, electronic device 300 may be a capacitor having a metal-ferroelectric-insulator-semiconductor (MFIS) structure.

[0096] An amorphous dielectric layer 330 is provided on (e.g., directly thereon) the top surface 310S of the first electrode 310. The amorphous dielectric layer 330 may include, but is not limited to, an oxide of at least one of Hf, Si, Al, Zr, Y, La, Gd, and Sr. Such an amorphous dielectric layer 330 may be deposited on the top surface 310S of the first electrode 310 by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc.

[0097] An amorphous dielectric layer 330 is provided between the first electrode 310 and the dielectric layer 340 (e.g., directly between them), such that the amorphous dielectric layer 330 is unaffected by the crystal structure of the first electrode 310 and can be configured to facilitate the grains of the dielectric layer 340 having a crystal orientation 340a aligned to a specific (or alternatively, predetermined) direction. The dielectric layer 340 is provided on top of the amorphous dielectric layer 330.

[0098] In some example embodiments, the dielectric layer 340 may include grains having a crystal orientation 340a aligned to a particular (or alternatively, predetermined) orientation, according to any example embodiment of the dielectric layer 140. The grains constituting the dielectric layer 340 may have, for example... <111> Crystal orientation, but not limited to this. Furthermore, the dielectric layer 340 may include grains having a crystal orientation such that the crystal orientation differs from that of the first electrode 310 and the second electrode 320. Again, the first electrode 310 and the second electrode 320 may each have grains having a crystal orientation different from the aligned crystal orientation of the grains in the dielectric layer 340.

[0099] The dielectric layer 340 may comprise an oxide of at least one of, for example, Hf, Si, Al, Zr, Y, La, Gd, and Sr, but this is only an example. The dielectric layer 340 may also comprise a dopant. Here, the dopant may comprise at least one of, for example, Si, Al, Zr, Y, La, Gd, Sr, and Hf. The dielectric layer 340 may have a thickness 340T, for example, from about 0.5 mm to about 4 nm.

[0100] In an electronic device 300 according to some example embodiments, the ferroelectric material of the dielectric layer 340 has grains having aligned crystal orientations 340a, thereby giving the dielectric layer 340 a larger remanent polarization than conventional electronic devices, which improves the polarization characteristics of the dielectric layer 340 and consequently increases its capacitance. An amorphous dielectric layer 330 provided between the first electrode 310 and the dielectric layer 340 has been described above, but a crystalline dielectric layer (not shown) may be provided between the first electrode 310 and the dielectric layer 340. Here, the crystalline dielectric layer may include grains having crystal orientations different from the aligned crystal orientations of the grains of the dielectric layer 340 thereon. For example, the crystalline dielectric layer may include a two-dimensional insulating material, such as h-BN. However, this is merely an example, and the crystalline dielectric layer may include various other dielectric materials.

[0101] As described above, an amorphous dielectric layer 330 or a crystalline dielectric layer is provided between the dielectric layer 340 and the first electrode 310. However, an amorphous dielectric layer 330 or a crystalline dielectric layer may additionally be provided between the dielectric layer 340 and the second electrode 320. The crystalline dielectric layer may be located between the channel layer 215 and the dielectric layer 340 (e.g., directly between them), between the dielectric layer 340 and the second electrode 320 (e.g., directly between them), or any combination thereof (e.g., multiple individual crystalline dielectric layers may be present in the electronic device 300). In some example embodiments, the electronic device 300 may include at least one amorphous dielectric layer 330 or a crystalline dielectric layer.

[0102] In some example embodiments, the amorphous dielectric layer 330 or the crystalline dielectric layer may not be provided between the first electrode 310 and the dielectric layer 340, but may instead be provided between the dielectric layer 340 and the second electrode 320. In this case, the dielectric layer 340 is provided directly on the top surface 310S of the first electrode 310, wherein the dielectric layer 340 includes grains having a crystal orientation 340a aligned to a direction different from the crystal orientation of the first electrode 310. Alternatively, the amorphous dielectric layer 330 or the crystalline dielectric layer described above may not be provided. In this case, the dielectric layer 340 is provided directly on the top surface 310S of the first electrode 310, wherein the dielectric layer 340 includes grains having a crystal orientation 340a aligned to a direction different from the crystal orientation of the first electrode 310. When the first electrode 310 and the second electrode 320 each include a conductive metal, a capacitor having a metal-ferroelectric-metal (MFM) structure can be provided, and when the first electrode 310 and the second electrode 320 include a semiconductor and a conductive metal, a capacitor having a metal-ferroelectric-semiconductor (MFS) structure can be provided.

[0103] Figure 6A , Figure 6B , Figure 6C and Figure 6D This is a diagram used to illustrate a method of manufacturing an electronic device according to some example embodiments.

[0104] Reference Figure 6AA substrate 410 having a channel layer 415, a source electrode S 421, and a drain electrode D 422 is prepared. The source electrode 421 and the drain electrode 422 can be formed by implanting / doping impurities into different regions of the substrate 410, wherein said regions are spaced apart from each other in the X direction (e.g., a direction parallel to the top surface 410S of the substrate 410), and the region of the substrate 410 between the source electrode 421 and the drain electrode 422 can be defined as the channel layer 415. The substrate 410 may include, for example, Si, Ge, SiGe, III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional (2D) semiconductor materials, quantum dots, or organic semiconductors, any combination thereof, etc. In some example embodiments, the channel layer 415 may include Si, Ge, SiGe, III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional (2D) semiconductor materials, quantum dots, or organic semiconductors, any combination thereof, etc. The material of the substrate 410 is not limited to the above and can be varied. Figure 6A As shown, the channel layer 415 may be a portion of the same single material as the rest of the substrate 410, such that the channel layer 415 may be defined as a region of the substrate 410 having side and bottom boundaries at least partially defined by the source 421 and drain 422 in the substrate 410 and having a top boundary that is a portion of the top surface 410S extending between the source 421 and drain 422, and this portion of the top surface 410S is referred to herein as the top surface 415S of the channel layer 415. Although the channel layer 415 and the rest of the substrate 410 may be portions of a single material, the channel layer 415 may also be referred to as being formed "on" the substrate 410.

[0105] The formation time of source 421 and drain 422 can vary.

[0106] For example, it can be formed as will be described later. Figure 6D The gate electrode 450 shown is followed by the formation of a source electrode 421 and a drain electrode 422 on the substrate 410. A channel layer 415 may be formed on the substrate 410 as a material layer that is distinct from, but not a portion of, the substrate 410 (e.g., the channel layer 415 may be a separate piece of material relative to the substrate 410). In this case, the material composition of the channel layer 415 may be varied relative to the material composition of the substrate 410. For example, the channel layer 415 may include at least one of oxide semiconductors, nitride semiconductors, oxynitride semiconductors, 2D materials, quantum dots, and organic semiconductors. Oxide semiconductors may include, for example, InGaZnO, two-dimensional materials may include, for example, TMD or graphene, and quantum dots may include colloidal quantum dots, nanocrystal structures, etc., but these are merely examples, and some exemplary embodiments are not limited thereto.

[0107] Reference Figure 6B An amorphous dielectric layer 430 is formed on (e.g., on) the channel layer 415 of the substrate 410, for example, directly on the channel layer 415 such that the amorphous dielectric layer 430 is in direct contact with the top surface 415S. Here, the amorphous dielectric layer 430 may include an oxide of at least one of Hf, Si, Al, Zr, Y, La, Gd, and Sr, but the example embodiment is not limited thereto. The amorphous dielectric layer 430 may be provided between (e.g., directly between) the channel layer 415 of the substrate 410 and the dielectric layer 440 described later, so that the amorphous dielectric layer 430 is unaffected by the crystal structure of the substrate 410 and can be configured to assist the grains of the dielectric layer 440 in having an alignment to a specific (or alternatively, predetermined) direction. Figure 6C The crystal orientation is 440a.

[0108] The amorphous dielectric layer 430 can be deposited on the channel layer 415 of the substrate 410 (e.g., directly on the top surface 415S) using deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD). The amorphous dielectric layer 430 can be formed by, for example, treating the top surface 410S of the substrate 410 with an SCl solution, or by treating the top surface 410S of the substrate 410 with oxygen and then heating the top surface 410S of the substrate 410.

[0109] In some example embodiments, the formation of the amorphous dielectric layer 430 can be omitted, and as... Figure 6C The dielectric layer 440 shown can be formed directly on the channel layer 415 (e.g., directly on the top surface 415S).

[0110] Reference Figure 6C A dielectric layer 440 is formed on (e.g., on) the amorphous dielectric layer 430. For example, as shown, the dielectric layer 440 may be formed directly on the top surface 430S of the amorphous dielectric layer 430.

[0111] Here, the dielectric layer 440 may include grains having a crystal orientation 440a aligned in a particular (or alternatively, predetermined) direction, as described with respect to any example implementation.

[0112] The grains constituting the dielectric layer 440 may have, for example, <111> Crystal orientation, but not limited thereto. Dielectric layer 440 may include ferroelectric materials, as described with respect to any example implementation.

[0113] The dielectric layer 440 may include an oxide of at least one of Hf, Si, Al, Zr, Y, La, Gd, and Sr, but this is only an example. The dielectric layer 440 may also include a dopant. Here, the dopant may include, for example, at least one of Si, Al, Zr, Y, La, Gd, Sr, and Hf. When a dopant is included in the dielectric layer 440, the dopant may be incorporated to have the same concentration throughout (e.g., the dopant concentration is uniform or substantially uniform throughout the dielectric layer 440), or it may be incorporated to have different concentrations depending on the region of the dielectric layer 440 (e.g., non-uniform dopant concentration throughout the dielectric layer 440). Different dopants may be incorporated depending on the region of the dielectric layer 440 (e.g., the dielectric layer 440 may include different dopants in different regions of the dielectric layer 440).

[0114] The dielectric layer 440 can be formed by depositing an amorphous dielectric material layer on the channel layer 415 (e.g., on the amorphous dielectric layer 430, for example, directly on the top surface 430S), and then crystallizing the amorphous dielectric material layer such that the crystallized amorphous dielectric material layer comprises grains having aligned crystal orientations, such that the crystallized amorphous dielectric material layer is the dielectric layer 440. In some example embodiments, the amorphous dielectric material layer is deposited directly on the top surface 415S of the channel layer 415 and crystallized to form the dielectric layer 440. Here, the amorphous dielectric material layer can be deposited on the amorphous dielectric layer 430 (e.g., directly on the top surface 430S) and / or on the channel layer 415 based on, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. Furthermore, the amorphous dielectric material layer can be formed as the dielectric layer 440 by crystallization via annealing. During the crystallization process of the amorphous dielectric material layer, grains having a crystal orientation 440a aligned to a specific (or alternatively, predetermined) direction can be grown to form a dielectric layer 440, such that the crystallized amorphous dielectric material layer is a dielectric layer 440.

[0115] The formation of the dielectric layer 440 can depend on the material constituting the dielectric layer 440, the type and concentration of dopants, the annealing temperature, etc. The annealing temperature of the amorphous dielectric material layer can be, for example, from about 300°C to about 1000°C, but is not limited thereto. The dielectric layer 440 can be formed with a thickness 440T of about 0.5 nm to about 4 nm, but this is only an example.

[0116] Reference Figure 6DThe electronic device 400 is completed by forming a gate electrode 450 on the dielectric layer 440 (e.g., directly on the top surface 440S). The gate electrode 450 can be formed by depositing a conductive material on the dielectric layer 440 (e.g., directly on the top surface 440S) based on methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0117] In this case, annealing can be performed separately after the gate electrode 450 is formed.

[0118] Here, the gate electrode 450 may include grains having a crystal orientation different from that of the aligned crystal orientation of the dielectric layer 440. As described above, the dielectric layer 440 is provided based on the following: an amorphous dielectric material layer is formed over an amorphous dielectric layer 430, and then the amorphous dielectric material layer is crystallized by annealing before the gate electrode 450 is formed thereon.

[0119] However, some exemplary embodiments are not limited to this, and the dielectric layer 440 may be provided based on: forming an amorphous dielectric material layer over the amorphous dielectric layer 430, then depositing a conductive material thereon to form the gate electrode 450, and then annealing. In this case, the dielectric layer 440 may be formed based on crystallizing the amorphous dielectric material layer by annealing (e.g., based on applying heat from a heat source to the amorphous dielectric material layer as described herein). Although at least one amorphous dielectric layer 430 formed over the channel layer 415 of the substrate 410 has been described above, at least one crystalline dielectric layer (not shown) may be formed instead of the amorphous dielectric layer 430, such that... Figures 6B-6D The layer “430” shown can be a crystalline dielectric layer rather than an amorphous dielectric layer 430.

[0120] Here, the crystalline dielectric layer may include grains having a crystal orientation different from that of the grains of the dielectric layer 440. Although an amorphous dielectric layer 430 or a crystalline dielectric layer formed between the channel layer 415 and the dielectric layer 440 of the substrate 410 has been described above, the amorphous dielectric layer 430 or the crystalline dielectric layer may also be additionally formed between the dielectric layer 440 and the gate electrode 450. Alternatively, the amorphous dielectric layer 430 or the crystalline dielectric layer may not be formed between the channel layer 415 and the dielectric layer 440 of the substrate 410, but may be formed only between the dielectric layer 440 and the gate electrode 450. In this case, the dielectric layer 440 is formed directly on the channel layer 415 of the substrate 410, wherein the dielectric layer 440 includes grains having a crystal orientation 440a aligned to a direction different from that of the substrate 410. The aforementioned amorphous dielectric layer 430 or crystalline dielectric layer may not be provided. In this configuration, the dielectric layer 440 is formed directly on the channel layer 415 of the substrate 410, wherein the dielectric layer 440 includes grains having a crystal orientation 440a aligned to a direction different from the crystal orientation of the substrate 410. According to the above embodiment, the subthreshold swing of the electronic device can be reduced by including a ferroelectric material within the dielectric layer.

[0121] Furthermore, ferroelectric materials can be included in the dielectric layer 440, and the ferroelectric materials can include grains with aligned crystal orientations, thereby increasing their remanent polarization and thus improving the polarization characteristics of the ferroelectric thin film. Moreover, the aligned polarization direction increases the depolarization field, thereby reducing the subthreshold swing by increasing the negative capacitance effect, further improving the performance of the electronic device. It should be understood that some of the exemplary embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each exemplary embodiment should generally be considered applicable to other similar features or aspects in other embodiments.

[0122] It will be understood that electronic devices 100, 200, and 300 can communicate with... Figures 6A-6D The method shown is similar to a method of formation (e.g., manufacturing). For example, regarding Figure 5 The electronic device 300 shown, and the method for manufacturing the electronic device 300 may include providing as described above. Figure 5 The first electrode 310 is described above. Furthermore, the method for manufacturing the electronic device 300 may include: via a method described above... Figure 6CThe process for forming dielectric layer 440 is similar or identical to the method described above, forming dielectric layer 340 on first electrode 310, wherein dielectric layer 440 comprises grains having aligned crystal orientations. Dielectric layer 340 may be formed directly on first electrode 310 (e.g., directly on its top surface 310S), or on an amorphous dielectric layer 330 or a crystalline dielectric layer formed between first electrode 310 and dielectric layer 340. In some example embodiments, forming dielectric layer 340 may include: depositing an amorphous dielectric material layer on first electrode 310 (e.g., directly on first electrode 310, on an amorphous dielectric layer 330 directly on first electrode 310, etc.), and then crystallizing the amorphous dielectric layer to form dielectric layer 340 (e.g., based on heat generated at a heat source, such that heat is applied to the amorphous dielectric material layer to achieve annealing and thus crystallization of the amorphous dielectric material layer), such that the crystallized amorphous dielectric material layer comprises grains having aligned crystal orientations 340a. Furthermore, the method for manufacturing electronic device 300 may include: via the above reference Figure 6D The process described for forming the gate electrode 450 is similar or identical to that used to form the second electrode 320 on the dielectric layer 340.

[0123] In some example embodiments, the method of forming electronic device 300 may include: via reference above. Figure 6B The process for forming the amorphous dielectric layer 430 is similar to or the same as described above, forming the amorphous dielectric layer 330 on the first electrode 310.

[0124] It will be understood that, according to some example implementations, such as Figures 1-2 , Figure 3 - The amorphous dielectric layers 130, 330, 430 shown in Figure 6 can be replaced by crystalline dielectric layers as described herein (e.g., between channel layer 115 and dielectric layer 140, as described with respect to amorphous dielectric layer 130). In some example embodiments, at least one amorphous dielectric layer 330 (and / or at least one crystalline dielectric layer) can be formed between the first electrode 310 and dielectric layer 340 (e.g. Figure 5 As shown), between the dielectric layer 440 and the second electrode 320, or a combination thereof (e.g., as described herein, multiple amorphous dielectric layers and / or crystalline dielectric layers may be formed between different groups of layers).

[0125] Figure 7 A schematic diagram of a system 1301 configured to control the formation (which may also be referred to herein as “fabrication” or “manufacturing”) of electronic devices according to some example embodiments is shown. As used herein, system 1301 may be referred to as a “set”.

[0126] Reference Figure 7 The system 1301 includes a computing device 3010 (which may also be referred to herein as an electronic device), an operating device 3040, a component (e.g., gas, fluid, etc.) source 3030-1 to 3030-N (where N is a positive integer), a heat source 3060, and a process chamber 3020.

[0127] Referring first to computing device 3010, computing device 3010 may include processing circuitry 3012 (also referred to herein as processor) connected together via bus 3011 to communication ground and / or electrical ground, memory 3014, power supply 3015 and communication interface 3016.

[0128] The computing device 3010 may be included in one or more various electronic devices (including, for example, mobile phones, digital cameras, sensor devices, etc.). In some example embodiments, the computing device 3010 may include one or more of a server, a mobile device, a personal computer (PC), a tablet computer, a laptop computer, a netbook, or some combination thereof. The mobile device may include a mobile phone, a smartphone, a personal digital assistant (PDA), or some combination thereof. The computing device 3010 may be simply referred to herein as "processing circuitry".

[0129] The memory 3014, processing circuit 3012, power supply 3015 and communication interface 3016 can communicate with each other via bus 3011.

[0130] The communication interface 3016 can transmit data to and / or from external devices using various communication protocols. In some example embodiments, the communication interface can be connected to an electronic wire (e.g., wiring) and can be configured to receive and process electrical signals from one or more external devices.

[0131] Processing circuitry 3012 can execute programs and control one or more aspects of system 1301 via communication interface 3016, such as Figure 7 As shown. The program code executed by the processing circuit 3012 can be stored in the memory 3014.

[0132] Memory 3014 can store information. Memory 3014 can be volatile or non-volatile memory. Memory 3014 can be a non-transitory computer-readable storage medium. Memory can store computer-readable instructions that, when executed, cause the execution of one or more methods, functions, processes, etc., as described herein. In some example embodiments, processing circuitry 3012 can execute one or more of the computer-readable instructions stored in memory 3014 to cause system 1301 to perform some of all the methods described herein, including... Figures 6A-6B and / or Figure 10The methods shown, and / or any methods for forming (e.g., “making”, “manufacturing”, etc.) any electronic device according to any example implementation.

[0133] In some example implementations, the communication interface 3016 may include a USB and / or HDMI interface. In some example implementations, the communication interface 3016 may include a wireless communication interface.

[0134] Still refer to Figure 7 The process chamber 3020 can be any process chamber described herein and may include a base and / or chuck 3022 configured to structurally support a substrate 3050 on which an electronic device 4000 according to any exemplary embodiment can be formed (e.g., "made", "manufactured", etc.) (which may be any of the exemplary embodiments of the electronic device according to any exemplary embodiment described herein). In some exemplary embodiments, the substrate 3050 may be at least a portion of a substrate, a first electrode, etc. (e.g., substrate 110, substrate 210, first electrode 310, substrate 410, etc.) at least partially included in the electronic device 4000 according to any exemplary embodiment. As shown, the base and / or chuck 3022 can be coupled to a motor, such that the electronic device 3010 (e.g., “processing circuitry”) can be configured to move the base and / or chuck 3022 via control signals transmitted from the communication interface 3016, for example, enabling the substrate 3050 and / or electronic device 4000 to move within, into, and / or out of the process chamber 3020.

[0135] Still refer to Figure 7 System 1301 includes a manipulation device 3040, which can be any device for manipulating a thin-film structure and / or a substrate into and / or out of a process chamber 3020. The process chamber 3020 may include an entrance 3021 (e.g., a door) through which the manipulation device 3040 can enter the interior of the process chamber 3020 to provide a substrate 3050 and / or retrieve at least some electronic devices 4000 formed therein. As shown, the manipulation device 3040 and the entrance 3021 may be controlled by an electronic device 3010 (e.g., “processing circuitry”).

[0136] Still refer to Figure 7System 1301 includes one or more component sources 3030-1 to 3030-N (N being a positive integer) that can store various materials, including any materials, dopants, and / or components described herein, or any combination thereof. The materials can be stored as gases, liquids, solids, fluids of any type, or any combination thereof. As shown, each individual component source is coupled to process chamber 3020 via a separate supply control device 3032-1 to 3032-N (e.g., a control valve), wherein each control device 3032-1 to 3032-N is configured (e.g., based on being a control valve) to control the supply of individual materials held in the separately (e.g., corresponding) coupled component sources 3030-1 to 3030-N to the process chamber. Component sources 3030-1 to 3030-N and / or control devices 3032-1 to 3032-N can be controlled by electronic device 3010 (e.g., “processing circuitry”).

[0137] Still refer to Figure 7 System 1301 includes a heat source 3060, which may be a heating device, heating element, heater, etc., for generating heat and providing the generated heat to process chamber 3020 (e.g., to heat at least a portion of process chamber 3020), for example, to achieve annealing of an amorphous dielectric material layer as described herein. As shown, heat source 3060 may be controlled by electronic device 3010 (e.g., “processing circuitry”).

[0138] like Figure 7 As shown, electronic device 3010 (e.g., "processing circuitry") can, for example, communicate with various elements of system 1301 via communication line 3018 based on the execution of an instruction program stored in memory 3014 by processing circuitry 3012, so that system 1301 forms electronic device 4000 according to any of the exemplary embodiments herein (e.g., any one of electronic devices 100, 200, 300, 400 as described herein with respect to any of the exemplary embodiments, including those referred to herein). Figures 6A-6D (Any of the methods described). It will be understood that system 1301 may be omitted. Figure 7 One or more of the components shown (e.g., heat source 3060, base or chuck 3022, etc.).

[0139] Figure 8 A schematic diagram of an electronic device according to some example embodiments is shown.

[0140] As shown, electronic device 1400 includes one or more electronic device components communicatively connected together via bus 1410, including processor (e.g., processing circuitry) 1420 and memory 1430. Electronic device 1400 may be referred to herein as a "computing device".

[0141] Processing circuitry 1420 may be included in one or more instances of processing circuitry, and may include one or more instances of processing circuitry and / or may be implemented by one or more instances of processing circuitry, such as: hardware including logic circuitry; hardware / software combination of a processor such as executing software; or combinations thereof. For example, processing circuitry 1420 may include, but is not limited to, a central processing unit (CPU), application processor (AP), arithmetic logic unit (ALU), graphics processing unit (GPU), digital signal processor, microcomputer, field-programmable gate array (FPGA), system-on-chip (SoC), programmable logic unit, microprocessor, or application-specific integrated circuit (ASIC), etc. In some example embodiments, memory 1430 may include a non-transitory computer-readable storage device storing instruction programs, such as a solid-state drive (SSD), and processing circuitry 1420 may be configured to execute instruction programs to implement the functions of electronic device 1400.

[0142] In some example embodiments, electronic device 1400 (e.g., a “computing device”) may include electronic components (e.g., logic transistors) according to any example embodiment in one or more of processing circuitry 1420 or memory 1430, wherein said electronic components include at least a dielectric layer comprising grains having aligned crystal orientations, and said electronic components including said dielectric layer are included in electronic device 1400. The electronic components included in electronic device 1400 (e.g., a “computing device”) may include ferroelectric materials. As a result, electronic device 1400 (e.g., a “computing device”) may exhibit improved operating performance, for example, based on one or more portions of electronic device 1400 with improved characteristics (e.g., processing circuitry 1420 and / or memory 1430).

[0143] Figure 9 A schematic diagram of a system 1500 configured to control electronic devices (e.g., "computing devices") according to some example embodiments is shown. Figure 10 This is a flowchart illustrating a method implemented by system 1500 for manufacturing an electronic device (e.g., a “computing device”) according to some example embodiments. As shown, system 1500 may include system 1301, which is configured to form one or more electronic devices 4000 (S1602) according to any example embodiment of the invention, including forming one or more electronic devices 4000 (which include, according to...) Figures 6A-6DThe method shown includes electronic device 400. In some example embodiments, where one or more electronic devices formed at S1602 are configured to be incorporated into a separate electronic device (e.g., a “computing device,” such as electronic device 1400), the one or more electronic devices formed at S1602 may be referred to as “sub-devices.” For example, based on the implementation of the method for forming the electronic device (e.g., as…), Figures 6A-6D The electronic device 4000 formed by the system 1301 (as shown in the method) can be a logic transistor configured to be incorporated into an electronic device, which is a computing device (e.g., such as...). Figure 8 The electronic device 1400 shown. System 1500 also includes a manufacturing assembly 1504 configured to combine electronic devices(s) (e.g., electronic device 400) formed by system 1301 with various electronic device (e.g., “computing device”) sub-components 1502 (wherein sub-components 1502 may include printed circuit boards, power supplies, buses, communication interface components, processing circuit components, memory components, any combination thereof, etc.). Manufacturing component 1504 can combine electronic devices(s) 4000, which are sub-devices, with sub-components 1502 (S1604) to manufacture (“manufacture”) electronic device (e.g., “computing device”) components (e.g., processing circuitry 1420, memory 1430, any combination thereof, etc.) and / or electronic devices (e.g., “computing devices”) themselves to manufacture (“make”) individual electronic devices(s) 1400 (e.g., “computing devices”) including one or more electronic devices (e.g., electronic devices 100, 200, 300 and / or 400) of any exemplary embodiment of the concept of the present invention (S1606). Such combination (S1604) and manufacturing (S1606) may include, for example, assembling electronic device (e.g., “computing device”) components (e.g., processing circuitry 1420 and / or memory 1430, based on combining the electronic devices(s) 4000 to one or more electronic device sub-components and connecting the electronic device components to other electronic device components (e.g., printed circuit boards or PCBs) to manufacture an electronic device (e.g., 1400).

[0144] Although some exemplary embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

[0145] This application claims the benefit of Korean Patent Application No. 10-2019-0131390, filed on October 22, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An electronic device, comprising: substrate; A dielectric layer on the substrate, the dielectric layer comprising grains having aligned crystal orientations; Gate electrode on the dielectric layer; as well as A crystalline dielectric layer, located between the substrate and the dielectric layer, between the dielectric layer and the gate electrode, or a combination thereof. The crystalline dielectric layer includes grains having a crystal orientation different from the aligned crystal orientation of the grains of the dielectric layer.

2. The electronic device according to claim 1, further comprising: A channel layer on the substrate, wherein the channel layer overlaps with the gate electrode in a direction perpendicular to the top surface of the substrate, and the source and drain electrodes are provided on opposite sides of the channel layer in a direction parallel to the top surface of the substrate.

3. The electronic device according to claim 2, wherein the channel layer comprises at least one of Si, Ge, SiGe, III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional semiconductor materials, quantum dots, and organic semiconductors.

4. The electronic device according to claim 1, wherein the dielectric layer comprises a ferroelectric material.

5. The electronic device according to claim 1, wherein the dielectric layer comprises an oxide of at least one selected from Hf, Si, Al, Zr, Y, La, Gd, and Sr.

6. The electronic device according to claim 5, wherein the dielectric layer further comprises a dopant.

7. The electronic device according to claim 1, wherein the dielectric layer has a thickness of 0.5 nm to 4 nm in a direction perpendicular to the top surface of the substrate.

8. The electronic device according to claim 1, wherein the grain has <111> Crystal orientation.

9. The electronic device according to claim 1, wherein the crystal dielectric layer comprises a two-dimensional insulating material.

10. An electronic device, comprising: The first and second electrodes are separated and do not come into direct contact with each other; A dielectric layer between the first electrode and the second electrode, wherein the dielectric layer comprises grains having aligned crystal orientations; as well as A crystalline dielectric layer, located between the first electrode and the dielectric layer, between the second electrode and the dielectric layer, or a combination thereof. The crystalline dielectric layer includes grains having a crystal orientation different from the aligned crystal orientation of the grains of the dielectric layer.

11. The electronic device of claim 10, wherein the first electrode and the second electrode comprise grains having a crystal orientation different from the aligned crystal orientation of the grains of the dielectric layer.

12. The electronic device of claim 10, wherein the dielectric layer comprises a ferroelectric material.

13. A method for manufacturing an electronic device, the method comprising: Prepare a substrate with a channel layer; A dielectric layer is formed on the channel layer, wherein the dielectric layer comprises grains having aligned crystal orientations; A gate electrode is formed on the dielectric layer; and A crystalline dielectric layer is formed between the substrate and the dielectric layer, between the dielectric layer and the gate electrode, or a combination thereof. The crystalline dielectric layer includes grains having a crystal orientation different from the aligned crystal orientation of the grains of the dielectric layer.

14. The method of claim 13, wherein forming the dielectric layer comprises: An amorphous dielectric material layer is deposited on the channel layer, and then the amorphous dielectric material layer is crystallized to form the dielectric layer, such that the crystallized amorphous dielectric material layer includes grains having the aligned crystal orientation.

15. The method of claim 13, wherein the dielectric layer comprises a ferroelectric material.

16. The method of claim 13, wherein the dielectric layer has a thickness of 0.5 nm to 4 nm.

17. A method for manufacturing a computing device, said method include: Manufacturing electronic devices according to the method of claim 14; and The computing device is formed by incorporating the electronic components into computing device components.

18. The method of claim 17, wherein the computing device component includes at least one of processing circuitry and memory.

19. A method for manufacturing an electronic device, the method comprising: A dielectric layer is formed on a first electrode, the first electrode comprising a conductive metal, and the dielectric layer comprising grains having aligned crystal orientations. A second electrode is formed on the dielectric layer, the second electrode comprising the conductive metal; as well as At least one crystalline dielectric layer is formed between the first electrode and the dielectric layer, between the dielectric layer and the second electrode, or a combination thereof. The at least one crystalline dielectric layer includes grains having a crystal orientation different from the aligned crystal orientation of the grains of the dielectric layer.

20. The method of claim 19, further comprising: At least one amorphous dielectric layer is formed between the first electrode and the dielectric layer, between the dielectric layer and the second electrode, or a combination thereof.

21. The method of claim 19, wherein forming the dielectric layer comprises: An amorphous dielectric material layer is deposited on the first electrode, and then the amorphous dielectric material layer is crystallized to form the dielectric layer, such that the crystallized amorphous dielectric material layer includes grains having the aligned crystal orientation.

22. A method for manufacturing a computing device, said method include: Manufacturing electronic devices according to the method of claim 19; and The computing device is formed by incorporating the electronic components into computing device components.

23. The method of claim 22, wherein the computing device component includes at least one of a processing circuit and a memory.

24. A system for manufacturing electronic devices, the system comprising: A process chamber, including a base or chuck configured to structurally support one or more devices or layers within the process chamber; Multiple component sources and multiple controllers, each component source being coupled to the process chamber via a separate controller, each controller configured to control the supply of a separate material held in a separate coupled component source to the process chamber; and Processing circuitry configured to control at least the plurality of controllers to manufacture the electronic device based on the following A substrate with a channel layer is prepared on the base or chuck. A dielectric layer is formed on the channel layer, wherein the dielectric layer comprises grains having aligned crystal orientations. A gate electrode is formed on the dielectric layer, and At least one crystalline dielectric layer is formed between the substrate and the dielectric layer, between the dielectric layer and the gate electrode, or a combination thereof. The at least one crystalline dielectric layer includes grains having a crystal orientation different from the aligned crystal orientation of the grains of the dielectric layer.

25. The system of claim 24, wherein the processing circuitry is further configured to control at least the plurality of controllers to At least one amorphous dielectric layer is formed between the substrate and the dielectric layer, between the dielectric layer and the gate electrode, or a combination thereof.

26. The system of claim 24, wherein the formation of the dielectric layer comprises: An amorphous dielectric material layer is deposited on the channel layer, and then the amorphous dielectric material layer is crystallized to form the dielectric layer, such that the crystallized amorphous dielectric material layer includes grains having the aligned crystal orientation.

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