Integrated device and battery / battery pack management chip

Abstract

The present disclosure provides an integrated device for detecting and controlling the charging current and discharging current of a battery / battery pack, wherein the battery / battery pack is charged and discharged through a first connection terminal and a second connection terminal. The integrated device integrates: a charge and discharge MOS transistor, which is a single MOS transistor and is connected in series on the current path between the battery / battery pack and the first connection terminal or between the battery / battery pack and the second connection terminal, and the charging and discharging are controlled by controlling the charge and discharge MOS transistor; and a current detection MOS transistor for detecting the charging current and / or discharging current flowing through the charge and discharge MOS transistor. The present disclosure also provides a battery management chip.

Description

Technical Field

[0001] The present disclosure relates to an integrated device and a battery / battery pack management chip. Background Art

[0002] In a battery system, overcharging and over-discharging of a battery not only reduce the service life of the battery, but may also cause safety accidents such as explosion and fire in severe cases. The battery is, for example, a lithium battery pack or the like.

[0003] Figure 1 A conventional overcurrent detection method according to the prior art is shown.

[0004] When the battery is discharging normally, the control signals OD and OC output by the driving unit are usually about VDD, 5V or 15V. The control signals OD and OC are respectively connected to the gates (G) of the protection switch MOS transistors M1 and M2. At this time, M1 and M2 operate in the linear region, and the drains (D) and sources (S) of M1 and M2 are equivalent to a conduction resistance, and the conduction resistance value is Ron.

[0005] The discharge current Idsg flows from the P- terminal to the B- terminal. The voltage of the P- terminal is higher. When the voltage difference (Idsg*Ron) between the P- terminal and the B- terminal is detected to reach a certain limit value, the voltage of the control signal OD changes from, for example, VDD to VB- (the voltage of the B- terminal), thereby turning off M1 and turning off the discharge path. The control signal OC may still maintain a potential such as VDD, and M2 may still be in the on state.

[0006] Similarly, when the battery is charging normally, the gate voltages of M1 and M2 are VDD. The current flows from the B- terminal to the P- terminal. The voltage of the P- terminal is lower. When the voltage difference (Ichg*Ron) between the B- terminal and the P- terminal reaches a certain limit value, the voltage of the control signal OC changes from, for example, VDD to VB-, turning off M2 and cutting off the charging path. The control signal OD may still maintain a potential such as VDD, and M1 may still be in the on state.

[0007] In Figure 1 In the circuit structure shown, during the normal charging process, the conduction resistances Ron of M1 and M2 are connected in series in the loop of the battery and the external charger. Therefore, when the system is charging, the power loss PLoss caused by the conduction resistances of M1 and M2 is Ichg*[2*Ron] 2, this power loss is directly converted into heat generation of the system. Thus, the temperature rise of the system caused by the thermal losses of M1 and M2 during charging is ΔT = PLoss / (C*m), where C is the specific heat coefficient of the system and m is the mass of the system. The safe operating temperature of the lithium battery system is usually around 45°C. Therefore, to control the system temperature rise caused by the thermal dissipation of the on-resistances of M1 and M2, the maximum charging current Ichg(max) = PLoss(max) / ([2*Ron] 2 ). In this way, the charging current becomes smaller, which will inevitably prolong the charging time of the system.

[0008] Similarly, during the discharging process, the on-resistances Ron of M1 and M2 are in series in the loop of the battery and the load. The thermal loss PLoss caused by the on-resistances of M1 and M2 is PLoss = Idsg*[2*Ron] 2 . This power loss reduces the energy utilization efficiency of the battery and also limits the maximum discharging current. The ΔT caused by the thermal losses of M1 and M2 during system discharging is ΔT = PLoss / (C*m), where C is the specific heat coefficient of the system and m is the mass of the system. The safe operating temperature of the lithium battery system is usually around 45°C. Therefore, to control the system temperature rise caused by the thermal dissipation of the on-resistances of M1 and M2, the maximum charging current Idsg(max) = PLoss(max) / ([2*Ron] 2 ). This will limit the maximum current that the battery system can output.

[0009] In addition, it is also necessary to detect the charging and discharging currents of the battery to ensure the safety of the battery. In the prior art, it can be achieved by adding a separate detection resistor, or by detecting the on-resistance of the charging and discharging MOSFETs. The method of using an external resistor will bring disadvantages such as adding pins. In the method of measuring the current by detecting the on-resistance of the MOSFET, the process and design parameters of each MOSFET are different, and it is also affected by temperature interference, etc. Therefore, how to detect the charging and discharging currents of the battery with high precision is the technical problem to be solved. Summary of the Invention

[0010] To solve one of the above technical problems, the present disclosure provides an integrated device and a battery / battery pack management chip.

[0011] According to one aspect of the present disclosure, an integrated device is used to detect and control the charging current and discharging current of a battery / battery pack. During charging and discharging of the battery / battery pack through a first connection end and a second connection end, the integrated device integrates:

[0012] A charge and discharge MOS transistor, the charge and discharge MOS transistor being a single MOS transistor and connected in series in the current path between the battery / battery pack and the first connection terminal or between the battery / battery pack and the second connection terminal, and controlling the charging and discharging by controlling the charge and discharge MOS transistor; and

[0013] A current detection MOS transistor for detecting the charging current and / or discharging current flowing through the charge and discharge MOS transistor.

[0014] According to at least one embodiment of the present disclosure, the charge and discharge MOS transistor includes a gate, a source, a drain, a substrate, a first parasitic diode, and a second parasitic diode, wherein the first parasitic diode and the second parasitic diode are connected in reverse series, one end of the series circuit of the first parasitic diode and the second parasitic diode is connected to the source, and the other end of the series circuit is connected to the drain, and the connection point of the first parasitic diode and the second parasitic diode is connected to the substrate.

[0015] According to at least one embodiment of the present disclosure, it further includes a switch, one end of the switch is connected to the connection point, the other end of the switch is connected to the source, when the charge and discharge MOS transistor is turned on and the switch is turned on, the source is connected to the substrate, when the charge and discharge MOS transistor is turned off and the switch is turned off, the source is disconnected from the substrate, and the substrate is in a floating state.

[0016] According to at least one embodiment of the present disclosure, when the charge and discharge MOS transistor is turned on and the switch is turned on so that the source is connected to the substrate, the conductive channel of the charge and discharge MOS transistor is formed, when the charge and discharge MOS transistor is turned off and the switch is turned off so that the source is disconnected from the substrate, the conductive channel of the charge and discharge MOS transistor is not formed and the substrate is in a floating state.

[0017] According to at least one embodiment of the present disclosure, the series circuit of the first parasitic diode and the second parasitic diode is arranged such that no conductive path is formed between the source and the drain through the series circuit.

[0018] According to at least one embodiment of the present disclosure, the charge and discharge MOS transistor is an NMOS transistor, and the charge and discharge MOS transistor is turned on when the gate-source voltage between the gate and the source is greater than the conduction threshold voltage of the charge and discharge MOS transistor, and the charge and discharge MOS transistor is turned off when the gate-source voltage is less than the conduction threshold voltage; or,

[0019] The charge-discharge MOS transistor is a PMOS transistor. When the gate-source voltage between the gate and the source is less than the conduction threshold voltage of the charge-discharge MOS transistor, the charge-discharge MOS transistor is turned on. When the gate-source voltage is greater than the conduction threshold voltage, the charge-discharge MOS transistor is turned off.

[0020] According to at least one embodiment of the present disclosure, when the charge-discharge MOS transistor is an NMOS transistor, the anode of the first parasitic diode is connected to the anode of the second parasitic diode, the cathode of the first parasitic diode is connected to the drain, and the cathode of the second parasitic diode is connected to the source; or

[0021] When the charge-discharge MOS transistor is a PMOS transistor, the cathode of the first parasitic diode is connected to the cathode of the second parasitic diode, the anode of the first parasitic diode is connected to the drain, and the anode of the second parasitic diode is connected to the source.

[0022] According to at least one embodiment of the present disclosure, the switch is an NMOS type and / or PMOS type transistor switch. The gate of the transistor switch is connected to the gate of the charge-discharge MOS transistor, the source of the transistor switch is connected to the connection point, and the drain of the transistor switch is connected to the source of the charge-discharge MOS transistor.

[0023] According to at least one embodiment of the present disclosure, the switch is a triode. The base of the triode is connected to the gate of the charge-discharge MOS transistor via a first resistor. The emitter / collector of the triode is connected to the connection point, and the collector / emitter of the triode is connected to the source of the field effect transistor.

[0024] According to at least one embodiment of the present disclosure, a second switch is connected between the gate and the drain of the charge-discharge MOS transistor.

[0025] The second switch is configured such that when the charge-discharge MOS transistor is turned off, the second switch ensures that the gate oxide layer of the field effect transistor is not broken down and / or the charge-discharge MOS transistor does not form a conductive channel.

[0026] According to at least one embodiment of the present disclosure, a second switch is connected between the gate and the drain of the charge-discharge MOS transistor, and the second switch is a voltage withstand diode.

[0027] When the charge-discharge MOS transistor is an NMOS transistor, the anode of the voltage withstand diode is directly or indirectly connected to the gate of the charge-discharge MOS transistor, and the cathode of the voltage withstand diode is directly or indirectly connected to the drain of the charge-discharge MOS transistor; or when the charge-discharge MOS transistor is a PMOS transistor, the cathode of the voltage withstand diode is directly or indirectly connected to the gate of the charge-discharge MOS transistor, and the anode of the voltage withstand diode is directly or indirectly connected to the drain of the charge-discharge MOS transistor.

[0028] According to at least one embodiment of the present disclosure, a triode is connected between the gate and the drain of the charge-discharge MOS transistor. The emitter / collector of the triode is connected to the gate of the charge-discharge MOS transistor, and the collector / emitter of the triode is connected to the drain of the charge-discharge MOS transistor.

[0029] According to at least one embodiment of the present disclosure, a second switch is connected between the gate and the drain of the charge-discharge MOS transistor.

[0030] When the charge-discharge MOS transistor is an NMOS transistor, the second switch is a second NMOS transistor switch. The second NMOS switch transistor has a third parasitic diode. The source of the second NMOS transistor is directly or indirectly connected to one end of the third parasitic diode and to the gate of the charge-discharge MOS transistor. The drain of the second NMOS transistor is directly or indirectly connected to the other end of the third parasitic diode and to the drain of the charge-discharge MOS transistor; or

[0031] When the charge-discharge MOS transistor is a PMOS transistor, the second switch is a second PMOS transistor switch. The second PMOS transistor switch has a third parasitic diode. The source of the second PMOS transistor switch and one end of the third parasitic diode are directly or indirectly connected to the gate of the charge-discharge MOS transistor. The drain of the second PMOS transistor and the other end of the third parasitic diode are directly or indirectly connected to the drain of the charge-discharge MOS transistor.

[0032] According to at least one embodiment of the present disclosure, the switch is replaced by a first Schottky diode and a second Schottky diode.

[0033] When the charge-discharge MOS transistor is an NMOS transistor, the cathode of the first Schottky diode is connected to the cathode of the second Schottky diode and connected to the substrate. The anode of the first Schottky diode is connected to the drain, and the anode of the second Schottky diode is connected to the source; or,

[0034] When the charge and discharge MOS transistor is a PMOS transistor, the anode of the first Schottky diode is connected to the anode of the second Schottky diode and is connected to the substrate. The cathode of the first Schottky diode is connected to the drain, and the cathode of the second Schottky diode is connected to the source.

[0035] According to at least one embodiment of the present disclosure, a second switch is connected between the gate and the drain of the charge and discharge MOS transistor.

[0036] The second switch is configured such that when the charge and discharge MOS transistor is turned off, the second switch ensures that the gate oxide layer of the field effect transistor is not broken down and / or the charge and discharge MOS transistor does not form a conductive channel.

[0037] According to at least one embodiment of the present disclosure, a second switch is connected between the gate and the drain of the charge and discharge MOS transistor, and the second switch is a voltage withstand diode.

[0038] When the charge and discharge MOS transistor is an NMOS transistor, the anode of the voltage withstand diode is directly or indirectly connected to the gate of the charge and discharge MOS transistor, and the cathode of the voltage withstand diode is directly or indirectly connected to the drain of the charge and discharge MOS transistor; or when the charge and discharge MOS transistor is a PMOS transistor, the cathode of the voltage withstand diode is directly or indirectly connected to the gate of the charge and discharge MOS transistor, and the anode of the voltage withstand diode is directly or indirectly connected to the drain of the charge and discharge MOS transistor.

[0039] According to at least one embodiment of the present disclosure, a second switch is connected between the gate and the drain of the charge and discharge MOS transistor.

[0040] When the charge and discharge MOS transistor is an NMOS transistor, the second switch is a second NMOS transistor switch. The second NMOS switch transistor has a third parasitic diode. The source of the second NMOS transistor is directly or indirectly connected to one end of the third parasitic diode and to the gate of the charge and discharge MOS transistor. The drain of the second NMOS transistor is directly or indirectly connected to the other end of the third parasitic diode and to the drain of the charge and discharge MOS transistor; or

[0041] When the charge and discharge MOS transistor is a PMOS transistor, the second switch is a second PMOS transistor switch, the second PMOS transistor switch has a third parasitic diode, the source of the second PMOS transistor switch and one end of the third parasitic diode are directly or indirectly connected to the gate of the charge and discharge MOS transistor, and the drain of the second PMOS transistor and the other end of the third parasitic diode are directly or indirectly connected to the drain of the charge and discharge MOS transistor.

[0042] According to at least one embodiment of the present disclosure, it further includes a comparison unit, a first input end of the comparison unit is connected to a voltage related to the voltage of the first end of the current detection MOS transistor, a second input end of the comparison unit is connected to a voltage related to the voltage of the first end of the charge and discharge MOS transistor, and the second end of the current detection MOS transistor is connected to the second end of the charge and discharge MOS transistor; and

[0043] a control logic unit, the control logic unit controls the charge and discharge MOS transistor according to the comparison result output by the comparison unit,

[0044] wherein, the impedance ratio between the on-resistance value of the charge and discharge MOS transistor and the on-resistance value of the current detection MOS transistor remains constant.

[0045] According to at least one embodiment of the present disclosure, the current ratio between the current flowing through the charge and discharge MOS transistor and the current flowing through the current detection MOS transistor remains constant.

[0046] According to at least one embodiment of the present disclosure, the current ratio between the current flowing through the charge and discharge MOS transistor and the current flowing through the current detection MOS transistor is independent of the system voltage and system temperature.

[0047] According to at least one embodiment of the present disclosure, the drain of the charge and discharge MOS transistor is connected to the load terminal / charger terminal and the second input end of the comparison unit, the source of the charge and discharge MOS transistor is connected to the battery / battery pack terminal, the source of the current detection MOS transistor is connected to the source of the charge and discharge MOS transistor, the drain of the current detection MOS transistor is connected to the second input end of the comparison unit and a constant current source, and the output end of the comparison unit serves as the current detection output end.

[0048] According to at least one embodiment of the present disclosure, the drain of the charge and discharge MOS transistor is connected to the load terminal / charger terminal and the drain of the current detection MOS transistor. The source of the current detection MOS transistor is connected to a constant current source. The source of the charge and discharge MOS transistor is connected to the battery / battery pack terminal and the first input terminal of the comparison unit. The source of the current detection MOS transistor is connected to the second input terminal of the comparison unit. The output terminal of the comparison unit serves as the current detection output terminal.

[0049] According to at least one embodiment of the present disclosure, the drain of the charge and discharge MOS transistor is connected to the load terminal / charger terminal and the second input terminal of the comparison unit. The source of the charge and discharge MOS transistor is connected to the battery / battery pack terminal. The source of the current detection MOS transistor is connected to the source of the charge and discharge MOS transistor. The drain of the current detection MOS transistor is connected to the second input terminal of the comparison unit. The drain of the current detection MOS transistor is connected to the drain of the first PMOS transistor. The source of the first PMOS transistor is connected to the source of the second PMOS transistor. The gates of the first PMOS transistor and the second PMOS transistor are connected and connected to the output terminal of the comparison unit. The drain of the second PMOS transistor is connected to the first input terminal of the second comparison unit and one end of a first resistor. The other end of the first resistor is grounded. The second input terminal of the second comparison unit is connected to a reference voltage. The output terminal of the second comparison unit serves as the current detection output terminal.

[0050] According to at least one embodiment of the present disclosure, the drain of the charge and discharge MOS transistor is connected to the load terminal / charger terminal and the drain of the current detection MOS transistor. The first input terminal of the comparison unit is connected to the source of the charge and discharge MOS transistor and the battery / battery pack terminal. The second input terminal of the comparison unit is connected to the source of the current detection MOS transistor. The source of the current detection MOS transistor is connected to the drain of the first PMOS transistor. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor and connected to the output terminal of the comparison unit. The source of the first PMOS transistor is connected to the source of the second PMOS transistor. The drain of the second PMOS transistor is connected to the first input terminal of the second comparison unit and one end of a first resistor. The other end of the first resistor is grounded. The second input terminal of the second comparison unit is connected to the load terminal / charger terminal. The output terminal of the second comparison unit serves as the current detection output terminal.

[0051] According to at least one embodiment of the present disclosure, the drain of the charge and discharge MOS transistor is connected to the load terminal / charger terminal and the drain of the current detection MOS transistor. The source of the current detection MOS transistor is connected to the source of the charge and discharge MOS transistor and the battery / battery pack terminal via a first resistor, and is connected to the second input terminal of the comparison unit. The first input terminal of the comparison unit is connected to a reference voltage, which is generated based on the voltage of the battery / battery pack terminal. The output terminal of the comparison unit serves as the current detection output terminal.

[0052] According to at least one embodiment of the present disclosure, the drain of the charge and discharge MOS transistor is connected to the load terminal / charger terminal and is connected to the drain of the current detection MOS transistor via a first resistor. The source of the current detection MOS transistor is connected to the source of the charge and discharge MOS transistor and the battery / battery pack terminal. The drain of the current detection MOS transistor is connected to the second input terminal of the comparison unit. The first input terminal of the comparison unit is connected to a reference voltage, which is generated based on the voltage of the load terminal / charger terminal. The output terminal of the comparison unit serves as the current detection output terminal.

[0053] According to at least one embodiment of the present disclosure, the drain of the charge and discharge MOS transistor is connected to the load terminal / charger terminal and the second input terminal of the comparison unit. The source of the charge and discharge MOS transistor is connected to the source of the current detection MOS transistor and the battery / battery pack terminal. The drain of the current detection MOS transistor is connected to the first input terminal of the comparison unit. The output terminal of the comparison unit serves as the current detection output terminal, and the output terminal of the comparison unit is connected to the first input terminal by a first resistor.

[0054] According to at least one embodiment of the present disclosure, the drain of the charge and discharge MOS transistor is connected to the load terminal / charger terminal and the drain of the current detection MOS transistor. The source of the current detection MOS transistor is connected to the second input terminal of the comparison unit. The first input unit of the comparison unit is connected to the source of the charge and discharge MOS transistor. The output terminal of the comparison unit serves as the current detection output terminal, and the output terminal of the comparison unit is connected to the second input terminal by a first resistor.

[0055] According to another aspect of the present disclosure, a battery / battery pack management chip includes the integrated device as described in any one of the above. Description of the Drawings

[0056] The drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, are used to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are included in this specification and form a part of this specification.

[0057] Figure 1 Shows a schematic diagram of battery management according to the prior art.

[0058] Figure 2 Shows a schematic diagram of a battery management system according to an embodiment of the present disclosure.

[0059] Figures 3 to 14 Shows a schematic diagram of charge and discharge switches according to different embodiments of the present disclosure.

[0060] Figures 15 to 22 Shows a schematic diagram of an integrated device according to different embodiments of the present disclosure. Detailed Embodiments

[0061] The present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the relevant content and do not limit the present disclosure. Additionally, it should be noted that for the convenience of description, only the parts related to the present disclosure are shown in the drawings.

[0062] It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. The technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings and embodiments.

[0063] Unless otherwise specified, the exemplary embodiments / Examples shown are understood to provide exemplary features of various details of some ways in which the technical concept of the present disclosure can be implemented in practice. Therefore, unless otherwise specified, without departing from the technical concept of the present disclosure, the features of various embodiments / Examples can be additionally combined, separated, interchanged, and / or rearranged.

[0064] In the drawings, cross-hatching and / or shading are generally used to make the boundaries between adjacent components clear. Thus, unless stated, the presence or absence of cross-hatching or shading does not convey or imply any preference or requirement for the specific materials, material properties, dimensions, proportions, commonalities between the components shown, and / or any other characteristics, attributes, properties, etc. of the components. Additionally, in the drawings, for clarity and / or descriptive purposes, the dimensions and relative dimensions of the components may be exaggerated. When the exemplary embodiments can be implemented differently, the specific process sequences can be performed in an order different from that described. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to that described. Furthermore, the same reference numerals denote the same components.

[0065] When a component is referred to as being “on” or “above” another component, “connected to” or “coupled to” another component, the component can be directly on the other component, directly connected to or directly coupled to the other component, or there can be intervening components. However, when a component is referred to as being “directly on” another component, “directly connected to” or “directly coupled to” another component, there are no intervening components. For this reason, the term “connected” can refer to physical connection, electrical connection, etc., and can have or not have intervening components.

[0066] For descriptive purposes, the present disclosure may use spatial relative terms such as “under”, “below”, “beneath”, “lower”, “above”, “upper”, “on”, “over”, “higher” and “side (e.g., as in “sidewall”)” etc., so as to describe the relationship of one component to another (other) component as shown in the drawings. In addition to the orientation depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device in use, operation and / or manufacture. For example, if the device in the drawings is flipped, a component described as “under” or “beneath” another component or feature will then be positioned “above” the other component or feature. Thus, the exemplary term “under” can encompass both “above” and “below” orientations. Further, the device can be otherwise positioned (e.g., rotated 90 degrees or at other orientations), and accordingly, the spatial relative descriptors used herein are to be interpreted.

[0067] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms “a”, “an” and “the” are also intended to include the plural forms. Additionally, when the terms “comprises” and / or “comprising” and their variations are used in this specification, it is specified that there are the stated features, integers, steps, operations, components, elements, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, elements, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially”, “about” and other similar terms are used as approximating terms and not as degree terms, so they are used to interpret the inherent deviations of measured values, calculated values and / or provided values that would be recognized by a person of ordinary skill in the art.

[0068] As Figure 2As shown, a battery management system 10 is provided according to the present disclosure. The battery management system can be used to manage a battery or a battery pack 20, and the battery management system can be in the form of a chip. It should be noted that in the present disclosure, the charge and discharge switch can be integrated inside the chip or arranged outside the chip. In the drawings of the present disclosure, the form in which the charge and discharge switch is arranged inside the chip is described. In addition, an external charger or an external load 30 can be connected to the positive and negative ends of the battery or the battery pack 20 to perform a charging operation or a discharging operation on the battery or the battery pack 20.

[0069] As Figure 2 shown, the battery management system 10 may include a VDD generator 100, a voltage acquisition unit 200, a logic control unit 300, a driving unit 400, and a current control detection circuit 500 (integrated device).

[0070] The VDD generator 100 generates a VDD voltage for internal use of the chip according to the highest voltage of the battery pack 20.

[0071] The voltage acquisition unit 200 is used to acquire the voltage of the battery or the battery pack 20. When it is in the form of a battery pack, the voltage acquisition unit 200 acquires the voltage of each battery, and the voltage acquisition unit 200 provides the acquired battery voltage to the control logic unit 300, and the control logic unit 300 controls the charge and discharge switch through the driving unit 400.

[0072] The current control detection circuit 500 receives a signal from the driving unit 400 to control the charge and discharge of the battery. The current control detection circuit 500 may include a charge and discharge switch 510 and a current detection unit 520.

[0073] The charge and discharge switch 510 is connected in series on the current path between the battery and the first connection terminal P- or between the battery and the second connection terminal P+.

[0074] The current detection unit 520 is used to detect the charge and discharge current flowing through the charge and discharge switch 510.

[0075] The control logic unit 300 controls the charge and discharge switch 510 according to the current value detected by the current detection unit 520, wherein the ratio between the on-impedance value of the charge and discharge switch and the on-impedance value of the current detection unit remains constant. The ratio between the current flowing through the charge and discharge switch and the current flowing through the current detection unit remains constant.

[0076] The ratio between the current flowing through the charge and discharge switch and the current flowing through the detection unit is independent of the system voltage and the system temperature.

[0077] That is to say, the ratio between the on-resistance value of the charge and discharge switch and the on-resistance value of the detection unit, as well as the ratio between the current flowing through the charge and discharge switch and the current flowing through the detection unit, are not affected by the system voltage and system temperature.

[0078] The charge and discharge switch is a MOS transistor and a single MOS transistor is used to implement the charging current control and the discharging current control.

[0079] The MOS transistor of the detection unit and the charge and discharge switch are of the same type of MOS transistor.

[0080] First, in the present disclosure, a single MOS transistor is adopted as the charge and discharge switch. The following will provide a detailed description thereof.

[0081] In the present disclosure, the MOS transistor of the charge and discharge switch and the MOS transistor of the detection unit are integrated on a single chip. In addition, other devices may also be integrated on this chip.

[0082] Figure 3 A charge and discharge switch according to the present disclosure is shown. In this embodiment, an NMOS transistor is taken as an example for illustration.

[0083] As Figure 3 shown, the charge and discharge switch includes a field effect transistor M4 and a switch M5.

[0084] The field effect transistor M4 includes a gate G, a source S, a drain D, a substrate B, a first parasitic diode D41 and a second parasitic diode D42, wherein the first parasitic diode D41 and the second parasitic diode D42 are connected in reverse series. One end of the series circuit of the first parasitic diode D41 and the second parasitic diode D42 is connected to the source S, and the other end of the series circuit is connected to the drain D. The connection point of the first parasitic diode D41 and the second parasitic diode D42 is connected to the substrate B.

[0085] The anode of the first parasitic diode D41 is connected to the anode of the second parasitic diode D42. The cathode of the first parasitic diode D41 is connected to the drain, and the cathode of the second parasitic diode D42 is connected to the source.

[0086] The series circuit of the first parasitic diode D41 and the second parasitic diode D42 is arranged such that no conductive path is formed between the source S and the drain D of the field effect transistor M4 through the series circuit.

[0087] One end of the switch is connected to the connection point, and the other end of the switch is connected to the source. As an example, the field-effect transistor is an NMOS transistor and the switch is an NMOS transistor. The gate G of the NMOS transistor M5 of the switch is connected to the gate G of the NMOS transistor M4 of the field-effect transistor, the source S of the NMOS transistor M5 of the switch is connected to the connection point B, and the drain D of the NMOS transistor M5 is connected to the source S of the NMOS transistor M4 of the field-effect transistor.

[0088] When the gate-source voltage V between the gate G and the source S of the field-effect transistor M4 GS is greater than the on-threshold voltage V of the field-effect transistor TH , the field-effect transistor M4 is turned on, and the switch is turned on so that the source S of the field-effect transistor M4 is connected to the substrate B. When the gate-source voltage V GS is less than the on-threshold voltage V TH , the field-effect transistor M4 is turned off, and the switch is turned off so that the source S of the field-effect transistor M4 is disconnected from the substrate B, and the substrate B is in a floating state.

[0089] The source S of the field-effect transistor M4 is connected to the substrate B through the switch and the field-effect transistor M4 is turned on, a conductive channel of the field-effect transistor M4 is formed, and when the source S of the field-effect transistor M4 is disconnected from the substrate B through the switch, the conductive channel of the field-effect transistor M4 is not formed.

[0090] A second switch DZ is connected between the gate G and the drain D of the field-effect transistor M4. The second switch is set such that when the field-effect transistor is turned off, the second switch ensures that the gate oxide layer of the field-effect transistor is not broken down and / or the field-effect transistor does not form a conductive channel.

[0091] In some cases, when the voltage of the drain D of the field-effect transistor M4 ≤ 0, for example, in the range of 0V to 40V, the second switch DZ is turned on to connect the gate G and the drain D of the field-effect transistor M4. When the voltage of the drain D of the field-effect transistor M4 > 0, the second switch DZ is turned off to disconnect the gate G and the drain D of the field-effect transistor M4. Or in some cases, if the drain voltage is greater than the gate voltage, the second switch is turned off, while if the drain voltage is less than or equal to the gate voltage, the second switch is turned on. Or in some cases, if the drain voltage is less than or equal to the gate voltage minus the on-voltage of the second switch, the second switch is turned on.

[0092] The second switch DZ is a voltage-resistant diode. The anode of the voltage-resistant diode is directly or indirectly connected to the gate G of the field-effect transistor M4, and the cathode of the voltage-resistant diode is directly or indirectly connected to the drain of the field-effect transistor M4. In the case of direct connection, one end of the voltage-resistant diode is connected to the gate G of the field-effect transistor M4, and the other end is connected to the drain D of the field-effect transistor M4. In the case of indirect connection, the second switch DZ can form a series circuit with the resistor R. One end of the series circuit is connected to the gate G of the field-effect transistor M4, and the other end is connected to the drain D of the field-effect transistor M4. It should be noted that the series order of the second switch DZ and the resistor R is not limited.

[0093] In Figure 3 it is shown that the second switch DZ is in the form of a Zener diode. The second switch DZ can also be a Schottky diode or the like.

[0094] According to other examples, the second switch can be an NMOS transistor. For example Figure 4 as shown, the NMOS transistor M6 has a parasitic diode D6. The source of the NMOS transistor M6 and one end of the parasitic diode D6 are directly or indirectly connected to the gate of the field-effect transistor M6, and the drain of the NMOS transistor and the other end of the parasitic diode D6 are directly or indirectly connected to the drain of the field-effect transistor. In the case of direct connection, one end of the field-effect transistor M6 is connected to the gate G of the field-effect transistor M4, and the other end is connected to the drain D of the field-effect transistor M4. In the case of indirect connection, the field-effect transistor M6 can form a series circuit with the resistor R. One end of the series circuit is connected to the gate G of the field-effect transistor M4, and the other end is connected to the drain D of the field-effect transistor M4. It should be noted that the series order of the field-effect transistor M6 and the resistor R is not limited.

[0095] When using the NMOS transistor as the second switch, the parasitic diode D6 of the NMOS transistor M6 is used as the voltage-resistant diode, so that it can play the role of the second switch.

[0096] By using the second switch, the high voltage at the drain terminal D of the NMOS transistor M4 can be prevented from damaging the NMOS transistor M4, such as breaking down the gate oxide layer.

[0097] When the circuit is normally charged, the conductive channel of the NMOS transistor M4 is formed, and the NMOS transistor M4 is turned on, so that the substrate Bulk region of the NMOS transistor M4 is connected to the source S of the NMOS transistor M4.

[0098] When the circuit is overcharged, the conductive channel of the NMOS transistor M4 will not be formed, and the channel of the NMOS transistor M4 is in the off state. The Bulk region of the NMOS transistor M4 is disconnected from the source S, and the Bulk region is in a floating state.

[0099] Since the parasitic diodes D41 and D42 are connected in reverse series, the series circuit of the parasitic diodes D41 and D42 cannot conduct, so there is no current path from the source S to the drain D of the NMOS transistor M4. According to the present disclosure, the gate oxide layer of the NMOS transistor M4 will not be broken down.

[0100] As Figure 5 shown, when the battery discharges to an external load, the direction of current flow in the loop is: the discharge current I dsg flows from the P- terminal to the B- terminal, and the voltage at the B- terminal is higher than the voltage at the P- terminal. When the voltage difference (I dsg *R on ) between the P- terminal and the B- terminal reaches a certain threshold, the MOS transistor M4 is turned off, and the discharge path is turned off. The reverse series-connected parasitic diodes D41 and D42 will not form a current path.

[0101] Figure 6 Another embodiment according to the present disclosure is provided. As Figure 6 shown, the charge-discharge switch includes a field-effect transistor M4, where the field-effect transistor M4 is an NMOS transistor.

[0102] The field-effect transistor M4 includes a gate G, a source S, a drain D, a substrate B, a first parasitic diode D41, and a second parasitic diode D42, where the first parasitic diode D41 and the second parasitic diode D42 are connected in reverse series. One end of the series circuit of the first parasitic diode D41 and the second parasitic diode D42 is connected to the source S, and the other end of the series circuit is connected to the drain D. The connection point of the first parasitic diode D41 and the second parasitic diode D42 is connected to the substrate B.

[0103] The anode of the first parasitic diode D41 is connected to the anode of the second parasitic diode D42. The cathode of the first parasitic diode D41 is connected to the drain, and the cathode of the second parasitic diode D42 is connected to the source.

[0104] The series circuit of the first parasitic diode D41 and the second parasitic diode D42 is arranged such that no conductive path is formed through the series circuit between the source S and the drain D of the field-effect transistor M4.

[0105] The anode of the first Schottky diode D61 is connected to the anode of the second Schottky diode 62. The cathode of the first Schottky diode D61 is connected to the drain of the field-effect transistor M4, and the first Schottky diode D61 is connected to the source of the field-effect transistor M4. The connection point of the anode of the first Schottky diode D61 and the anode of the second Schottky diode 62 is connected to the substrate B.

[0106] In this embodiment, since the conduction voltage of the Schottky diode is less than the voltage of the parasitic diode, the parasitic diode will not conduct when the Schottky diode conducts.

[0107] When the circuit is charging normally, the conductive channel of the NMOS transistor M4 is formed, and the NMOS transistor M4 conducts, causing the substrate Bulk region of the NMOS transistor M4 to be connected to the source S of the NMOS transistor M4.

[0108] When the circuit is overcurrent during charging, the conductive channel of the NMOS transistor M4 will not be formed, and the channel of the NMOS transistor M4 is in the off state. The Bulk region of the NMOS transistor M4 is disconnected from the source S, and the Bulk region is in a floating state. Since the parasitic diodes D41 and D42 are connected in reverse series, the series circuit of the parasitic diodes D41 and D42 cannot conduct, so there is no current path from the source S to the drain D of the NMOS transistor M4. Moreover, the gate oxide layer of the NMOS transistor M4 will not be broken down.

[0109] When the battery discharges to an external load, the parasitic diodes D41 and D42 connected in reverse series will not form a current path.

[0110] The above description of the control method is described with reference to the NMOS transistor, but for the PMOS transistor, the principle is the same, and the situation of the PMOS transistor will be described in detail below.

[0111] Figure 7 A charge and discharge switch according to the present disclosure is shown. In this embodiment, the PMOS transistor is taken as an example for illustration.

[0112] As Figure 7 shown, the charge and discharge switch includes a field-effect transistor M4 (PMOS transistor) and a switch M5.

[0113] The field-effect transistor M4 includes a gate G, a source S, a drain D, a substrate B, a first parasitic diode D41, and a second parasitic diode D42, where the first parasitic diode D41 and the second parasitic diode D42 are connected in reverse series. One end of the series circuit of the first parasitic diode D41 and the second parasitic diode D42 is connected to the source S, and the other end of the series circuit is connected to the drain D. The connection point of the first parasitic diode D41 and the second parasitic diode D42 is connected to the substrate B.

[0114] The cathode of the first parasitic diode D41 is connected to the cathode of the second parasitic diode D42. The anode of the first parasitic diode D41 is connected to the drain, and the anode of the second parasitic diode D42 is connected to the source.

[0115] The series circuit of the first parasitic diode D41 and the second parasitic diode D42 is arranged such that no conductive path is formed through the series circuit between the source S and the drain D of the field-effect transistor M4.

[0116] One end of the switch M5 is connected to the connection point of the first parasitic diode D41 and the second parasitic diode D42, and the other end of the switch is connected to the source.

[0117] As an example, the field-effect transistor is a PMOS transistor and the switch M5 is a PMOS transistor. The gate G of the PMOS transistor M5 is connected to the gate G of the PMOS transistor M4 of the field-effect transistor. The drain D of the PMOS transistor M5 is connected to the connection point B (the substrate (Bulk, B terminal) of the MOS transistor M4), and the source S of the PMOS transistor M5 is connected to the source S of the PMOS transistor M4 of the field-effect transistor.

[0118] When the gate-source voltage V between the gate G and the source S of the field-effect transistor M4 GS is less than the conduction threshold voltage V of the field-effect transistor TH the field-effect transistor M4 conducts, and the switch conducts to connect the source S of the field-effect transistor M4 to the substrate B. When the gate-source voltage V GS is greater than the conduction threshold voltage V TH the field-effect transistor M4 turns off, and the switch turns off to disconnect the source S of the field-effect transistor M4 from the substrate B, and the substrate B is in a floating state.

[0119] When the source S of the field-effect transistor M4 is connected to the substrate B through the switch and the field-effect transistor M4 conducts, the conductive channel of the field-effect transistor M4 is formed. When the source S of the field-effect transistor M4 is disconnected from the substrate B through the switch, the conductive channel of the field-effect transistor M4 is not formed.

[0120] A second switch DZ is connected between the gate G and the drain D of the field-effect transistor M4. The second switch is configured such that when the field-effect transistor is turned off, the second switch ensures that the gate oxide layer of the field-effect transistor is not broken down and / or a conductive channel is not formed in the field-effect transistor. When the voltage of the drain D of the field-effect transistor M4 > 0, the second switch DZ conducts to connect the gate G and the drain D of the field-effect transistor M4. When the voltage of the drain D of the field-effect transistor M4 ≤ 0, the second switch DZ turns off to disconnect the gate G and the drain D of the field-effect transistor M4. Or in some cases, when the drain voltage is less than or equal to the gate voltage, the second switch is turned off, and when the drain voltage is greater than the gate voltage, the second switch is turned on. Or in some cases, when the drain voltage is greater than the gate voltage plus the conduction voltage of the second switch, the second switch is turned on.

[0121] The second switch DZ is a voltage-resistant diode. The anode of the voltage-resistant diode is directly or indirectly connected to the gate G of the field-effect transistor M4, and the cathode of the voltage-resistant diode is directly or indirectly connected to the drain of the field-effect transistor M4. In the case of direct connection, one end of the voltage-resistant diode is connected to the gate G of the field-effect transistor M4, and the other end is connected to the drain D of the field-effect transistor M4. In the case of indirect connection, the second switch DZ can form a series circuit with the resistor R. One end of the series circuit is connected to the gate G of the field-effect transistor M4, and the other end is connected to the drain D of the field-effect transistor M4. It should be noted that the series connection order of the second switch DZ and the resistor R is not limited.

[0122] In Figure 7 it is shown that the second switch DZ is in the form of a Zener diode. The second switch DZ can also be a Schottky diode or the like.

[0123] According to other examples, the second switch can be a PMOS transistor. For example Figure 8 as shown, the PMOS transistor M6 has a parasitic diode D6. The source of the PMOS transistor M6 and one end of the parasitic diode D6 are directly or indirectly connected to the gate of the field-effect transistor M6, and the drain of the PMOS transistor M6 and the other end of the parasitic diode D6 are directly or indirectly connected to the drain of the field-effect transistor. In the case of direct connection, one end of the field-effect transistor M6 is connected to the gate G of the field-effect transistor M4, and the other end is connected to the drain D of the field-effect transistor M4. In the case of indirect connection, the field-effect transistor M6 can form a series circuit with the resistor R. One end of the series circuit is connected to the gate G of the field-effect transistor M4, and the other end is connected to the drain D of the field-effect transistor M4. It should be noted that the series connection order of the field-effect transistor M6 and the resistor R is not limited.

[0124] When using a PMOS transistor as the second switch, the parasitic diode D6 of the PMOS transistor M6 is used as a voltage withstand diode, thereby playing the role of the second switch.

[0125] By using the second switch, high voltage at the drain terminal D of the PMOS transistor M4 can be prevented from damaging the PMOS transistor M4.

[0126] When the circuit is charging normally, a conductive channel of the PMOS transistor M4 is formed, the PMOS transistor M4 is turned on, and the substrate Bulk region of the PMOS transistor M4 is connected to the source S of the PMOS transistor M4.

[0127] When the circuit is overcurrent during charging, a conductive channel of the PMOS transistor M4 is not formed, and the channel of the PMOS transistor M4 is in the off state. As a result, the Bulk region of the PMOS transistor M4 is disconnected from the source S, and the Bulk region is in a floating state. Since the parasitic diodes D41 and D42 are connected in reverse series, the series circuit of the parasitic diodes D41 and D42 cannot conduct, so there is no current path from the source S to the drain D of the PMOS transistor M4. Moreover, the gate oxide layer of the PMOS transistor M4 will not be broken down.

[0128] As Figure 9 shown, when the battery discharges to an external load, the direction of current flow in the loop is: the discharge current I dsg flows from the B+ terminal to the P+ terminal. The voltage of the P+ terminal is higher than that of the B+ terminal. When the voltage difference (I dsg *R on ) between the B+ terminal and the P+ terminal reaches a certain threshold, the MOS transistor M4 is turned off, that is, the discharge path is turned off. The reverse series-connected parasitic diodes D41 and D42 do not form a current path.

[0129] Figure 10 Another embodiment according to the present disclosure is provided. As Figure 10 shown, the charge and discharge switch includes a field effect transistor M4, where the field effect transistor M4 is an NMOS transistor.

[0130] The field effect transistor M4 includes a gate G, a source S, a drain D, a substrate B, a first parasitic diode D41, and a second parasitic diode D42, where the first parasitic diode D41 and the second parasitic diode D42 are connected in reverse series, one end of the series circuit of the first parasitic diode D41 and the second parasitic diode D42 is connected to the source S, and the other end of the series circuit is connected to the drain D, and the connection point of the first parasitic diode D41 and the second parasitic diode D42 is connected to the substrate B.

[0131] The cathode of the first parasitic diode D41 is connected to the cathode of the second parasitic diode D42. The anode of the first parasitic diode D41 is connected to the drain, and the anode of the second parasitic diode D42 is connected to the source.

[0132] The series circuit of the first parasitic diode D41 and the second parasitic diode D42 is arranged such that no conductive path is formed through the series circuit between the source S and the drain D of the field effect transistor M4.

[0133] The cathodes of the first Schottky diode D61 and the second Schottky diode 62 are connected. The anode of the first Schottky diode D61 is connected to the drain of the field effect transistor M4, and the first Schottky diode D61 is connected to the source of the field effect transistor M4. The connection point of the cathodes of the first Schottky diode D61 and the second Schottky diode 62 is connected to the substrate B.

[0134] In this embodiment, since the turn-on voltage of the Schottky diode is less than the voltage of the parasitic diode, the parasitic diode does not turn on when the Schottky diode turns on.

[0135] When the circuit is charging normally, the conductive channel of the PMOS transistor M4 is formed, and the PMOS transistor M4 is turned on, causing the substrate Bulk region of the PMOS transistor M4 to be connected to the source S of the PMOS transistor M4.

[0136] When the circuit has an overcurrent during charging, the conductive channel of the PMOS transistor M4 is not formed, and the channel of the PMOS transistor M4 is in the off state. As a result, the Bulk region of the PMOS transistor M4 is disconnected from the source S, and the Bulk region is in a floating state. Since the parasitic diodes D41 and D42 are connected in reverse series, the series circuit of the parasitic diodes D41 and D42 cannot conduct, so there is no current path from the source S to the drain D of the PMOS transistor M4. Moreover, the gate oxide layer of the PMOS transistor M4 will not be broken down.

[0137] When the battery discharges to an external load, the parasitic diodes D41 and D42 connected in reverse series do not form a current path.

[0138] In the above description, the switch is described by taking the NMOS transistor M5 as an example, but other types of switches can also be used in the present disclosure, such as triodes. Figures 11 to 14 An embodiment using a triode is shown. The base B of the triode is connected to the gate of the field effect transistor M4 through a resistor RT, and the collector or emitter of the triode can be connected to the Bulk terminal, while the emitter or collector of the triode can be connected to the source of the field effect transistor M4. Additionally, the second switch M6 / DZ can also be in the form of a triode, for exampleFigure 13 and 14 As shown, the collector or emitter of the triode can be directly or indirectly connected to the gate of the field effect transistor M4, and the emitter or collector of the triode can be directly or indirectly connected to the drain of the field effect transistor M4.

[0139] In addition, for the case where the field effect transistor M4 is in the form of a PMOS transistor, the situation of using a triode is the same as that of Figures 11 to 14 the case of

[0140] In the present disclosure, the current detection unit and the charge and discharge switch are integrated in one chip, for example, they can be arranged in one wafer.

[0141] Next, the charge and discharge switch shown in Figure 3 will be taken as an example for illustration. For other forms in Figures 4 to 14 , reference can be made to the description relative to Figure 3 . Specifically, the charge and discharge switch in Figure 3 is replaced with a charge and discharge switch of other forms. Next, various implementation manners of the current control detection circuit 500 will be described in detail with reference to Figures 15 to 22 . Among them, the components in the dashed box shown in Figures 15 to 22 can be integrated in one wafer, so as to form a single device.

[0142] Figure 15 shows a schematic diagram according to the first embodiment of the present disclosure. This first embodiment is used to control overcurrent during battery discharge.

[0143] The charge and discharge control unit may include a detection unit and a comparison unit. The first input terminal of the comparison unit is connected to a voltage related to the voltage at the first end of the detection unit, the second input terminal of the comparison unit is connected to a voltage related to the voltage at the first end of the charge and discharge switch, and the second end of the detection unit is connected to the second end of the charge and discharge switch. The charge and discharge switch is M4. The detection unit is an NMOS transistor 531a.

[0144] The drain of the transistor 531a is connected to the first input terminal of the comparison unit, the drain of the transistor M4 is connected to the external negative terminal P- and is connected to the second input terminal of the comparison unit, the source of the transistor 531a is connected to the source of the transistor M4 and is connected to the battery negative terminal B-. The gate of the transistor 531a can be connected to the gate of the transistor M4 and receive the drive control signal IN of the drive unit to conduct and disconnect. Or the gate of the transistor M4 is connected to the drive control signal IN, and the gate of the transistor 531a can also receive other control signals to at least keep it conducting when detecting. In addition, the Bulk (substrate) of the transistor 531a and the transistor M4 can be connected together or not connected together (for Figures 16 to 22In the embodiment, the transistor 531* and M4 can also adopt this method). The drain of the NMOS transistor 531a of the detection unit is connected to a constant current Idc, which is independent of the voltage and temperature of the system.

[0145] And the discharge current Idsg flows from the first end of the charge and discharge switch (the negative end connected to the external charger or the external load 300 is shown in the figure, that is, the P- end) to the second end. When the voltage at the first end of the charge and discharge switch is greater than the voltage at the drain side of the NMOS transistor of the detection unit, the comparison result of the comparison unit flips, and the control logic unit controls the disconnection of the discharge control switch.

[0146] Specifically, a constant current Idc can be generated inside the chip, which is independent of the voltage and temperature of the system. The constant current generates a voltage Va (the voltage at the drain end of the NMOS transistor 531a) on the NMOS transistor 531a. Since the NMOS transistors M4 and 531a are of the same type, even if the temperature or voltage of the system changes, the sum of the equivalent on-resistances of the NMOS transistor 531a and the NMOS transistor M4 can be maintained at a constant value K:1 (correspondingly, the size ratio is 1:K).

[0147] The comparison unit 532a is used to compare the voltage Va and the voltage VP- (the voltage at the P- end). When VP- is greater than Va, the output signal of the comparison unit 532a flips, and after the control logic unit 300 receives the flip signal, it outputs a control signal OD through the driving unit 400 to turn off the charge and discharge switch.

[0148] Figure 16 The figure shows a schematic diagram according to the second embodiment of the present disclosure. This second embodiment is used to control the overcurrent during battery charging. The charge and discharge control unit may include a detection unit and a comparison unit. The second input terminal of the comparison unit is connected to a voltage related to the voltage at the second end of the detection unit, the first input terminal of the comparison unit is connected to a voltage related to the voltage at the second end of the charge and discharge switch, and the first end of the detection unit is connected to the first end of the charge and discharge switch. The charge and discharge switch is the charge and discharge switch M4. The detection unit is an NMOS transistor 531b. One input terminal of the comparison unit 532b is connected to the voltage at the B- end, the other input terminal is connected to the source of the transistor 531b, and its drain is connected to the P- end.

[0149] Specifically, a constant current Idc can be generated inside the chip. This constant current Idc is independent of the voltage and temperature of the system. The constant current generates a voltage Vb (the voltage at the drain terminal of the NMOS transistor 531b) across the NMOS transistor 531b. Since the NMOS transistors M4 and 531b are of the same type, even if the temperature or voltage of the system changes, the sum of the equivalent conduction impedances of the NMOS transistor 531b and the NMOS transistor M4 can be maintained at a constant value K: 1.

[0150] The comparison unit 532b is used to compare the voltage Vb and the voltage VB- (the voltage at the B- terminal). When VB- is greater than Vb, the output signal of the comparison unit 532b flips. After the control logic unit 300 receives the flip signal, it outputs a control signal through the drive unit 400 to turn off the charge and discharge switch. For the connection method of the gates of the NMOS transistors 531b and M4, reference can be made to the description of the first embodiment, and the connection methods in the following embodiments can also refer to the description of the first embodiment.

[0151] Figure 17 A schematic diagram showing a third embodiment according to the present disclosure is presented. This third embodiment is used to control overcurrent during battery discharge. The discharge current Idsg flows from the P- terminal to the B- terminal.

[0152] In this embodiment, the detection unit is an NMOS transistor 531c. The source of the NMOS transistor 531c is connected to the second terminal of the charge and discharge switch M4 (the right end of the discharge switch is shown in the figure, which is the negative terminal B- of the battery).

[0153] The drain of the NMOS transistor 531c is connected to a mirror circuit. This mirror circuit includes PMOS transistors 533c and 534c. The drain of the NMOS transistor 531c can be connected to the drain of the PMOS transistor 533c. And the source of the PMOS transistor 533c can be connected to the system voltage (such as VDD). And the gate of the PMOS transistor 533c is connected to the gate of the PMOS transistor 534c. The source of the PMOS transistor 534c can be connected to the system voltage.

[0154] The source of the NMOS transistor 531c is connected to the B- terminal, and its gate can be connected to the system voltage VDD. One input terminal of the comparison unit 532c is connected to the drain of the NMOS transistor 531c, and the other input terminal of the comparison unit 532c is connected to the first terminal of the charge and discharge switch (the negative terminal connected to the external charger or the external load 300 is shown in the figure, which is the P- terminal).

[0155] The output of the comparison unit 532c is connected to the gates of the PMOS transistors 533c and 534c, and the drain of the PMOS transistor 534c is connected to the resistor 535c.

[0156] A comparator 536c is further included. One input terminal of the comparator 536c is connected to the drain of the PMOS transistor 534c so as to input the voltage generated by the resistor 535c to one input terminal of the comparator 536a, and the other input terminal of the comparator 536c is connected to the reference voltage Vref.

[0157] In this embodiment, the comparison unit 532c can make the voltage Vc on the drain side of the NMOS transistor 531c the same as the voltage VP- on the P-side.

[0158] Wherein, the NMOS transistor 531c and M4 are NMOS transistors of the same type. Therefore, even if the temperature and voltage change, the comparison between the equivalent on-resistance of the NMOS transistor 531c and the equivalent on-resistance of the NMOS transistor M4 will remain a constant value K:1. Thus, since Vc = VP-, the current flowing through the NMOS transistor 531c and the current flowing through the NMOS transistor M4 remain 1:K.

[0159] The PMOS transistor 533c and the PMOS transistor 534c are PMOS transistors of the same type and operate in the saturation region. Thus, the current flowing through the NMOS transistor 531c can be mirrored to the path where the resistor 535c is located, and a voltage will be generated on the resistor 535c (assuming the resistance value is Rc). By comparing this voltage Vr with the reference voltage Vref, when Vr is greater than Vref, the comparator 536c flips. In this way, the logic control unit 300 can control the drive unit 400 according to this flip signal, and output a control signal through the drive unit 400 to turn off the NMOS transistor M4.

[0160] Since when the discharge NMOS transistor 520 is turned off, the current flowing through the NMOS transistor M4 is Vref / Rc*K. And Vref and Rc are fixed values, and K is a constant ratio. When the system voltage and temperature change, these three values will not change. Thus, the current flowing through the NMOS transistor M4 will not change, that is, the detected discharge overcurrent will not change with the voltage or temperature.

[0161] Figure 18 A schematic diagram showing a fourth embodiment according to the present disclosure is shown.

[0162] This fourth embodiment is used to control the overcurrent during battery charging. The charging current Ichg flows from the B-terminal to the P-terminal.

[0163] In this embodiment, the detection unit is an NMOS transistor 531d. The source of the NMOS transistor 531d is connected to the first end of the charge and discharge switch (in the figure, it is shown as being connected to the negative terminal of the external charger or the external load 300, that is, the P- terminal).

[0164] The drain of the NMOS transistor 531d is connected to a mirror circuit. The mirror circuit includes PMOS transistors 533d and 534d. The drain of the NMOS transistor 531d can be connected to the drain of the PMOS transistor 533d. And the source of the PMOS transistor 533d can be connected to the system voltage (such as VDD). And the gate of the PMOS transistor 533d is connected to the gate of the PMOS transistor 534d. The source of the PMOS transistor 534d can be connected to the system voltage.

[0165] The source of the NMOS transistor 531d is connected to the P- terminal, and its gate can be connected to the system voltage VDD. One input terminal of the comparison unit 532d is connected to the drain of the NMOS transistor 531d, and the other input terminal of the comparison unit 532d is connected to the second end of the charge and discharge switch (in the figure, it is shown as the right end of the discharge switch, that is, the negative terminal B- of the battery).

[0166] The output of the comparison unit 532d is connected to the gates of the PMOS transistors 533d and 534d, and the drain of the PMOS transistor 534d is connected to the resistor 535d.

[0167] It further includes a comparator 536d. One input terminal of the comparator 536d is connected to the drain of the PMOS transistor 534d so as to input the voltage generated by the resistor 535d to one input terminal of the comparator 536d. The other input terminal of the comparator 536d is connected to the reference voltage Vref.

[0168] In this embodiment, the comparison unit 532d can make the voltage Vc on the drain side of the NMOS transistor 531d the same as the voltage VB- on the B- side.

[0169] Among them, the NMOS transistor 531d and M4 are NMOS transistors of the same type. Therefore, even when the temperature and voltage change, the comparison between the equivalent on-resistance of the NMOS transistor 531d and the equivalent on-resistance of the NMOS transistor M4 will remain a constant value K:1. In this way, since Vc = VB-, the current flowing through the NMOS transistor 531d and the current flowing through the NMOS transistor M4 remain 1:K.

[0170] The PMOS transistor 533d and the PMOS transistor 534d are PMOS transistors of the same type and operate in the saturation region. In this way, the current flowing through the NMOS transistor 531d can be mirrored to the path where the resistor 535d is located, and a voltage will be generated across the resistor 535d (assuming the resistance value is Rd). By comparing this voltage Vr with the reference voltage Vref, when Vr is greater than Vref, the comparator 536c toggles. In this way, the logic control unit 300 can control the driving unit 400 according to this toggle signal, and the driving unit 400 outputs a control signal to turn off the transistor M4.

[0171] When the transistor M4 is turned off, the current flowing through the NMOS transistor M4 is Vref / Rd*K. Since Vref and Rd are fixed values and K is a constant ratio, these three values will not change when the system voltage and temperature change. Thus, the current flowing through the NMOS transistor 5M4 will not change, that is, the detected charging overcurrent will not change with voltage or temperature.

[0172] Figure 19 A schematic diagram showing a fifth embodiment according to the present disclosure is shown.

[0173] This fifth embodiment is used to control the overcurrent during battery discharge. The discharge current Idsg flows from the P - terminal to the B - terminal. The charge - discharge switch is the transistor M4. The detection unit includes a series - connected resistor 533e and an NMOS transistor 531e.

[0174] The resistance value of the resistor 533e is much smaller than the on - resistance of the NMOS transistor 531e. The drain of the transistor 531e is connected to the P - terminal, the source is connected to one end of the resistor 533e, and the other end of the resistor 533e is connected to the B - terminal.

[0175] The connection point of the NMOS transistor 531e and the resistor 533e is connected to one input terminal of the comparison unit 534e, and the other input terminal of the comparison unit 534e is connected to the reference voltage Vref generated based on VB - (the voltage at the B - terminal). The generation of this reference voltage Vref can be generated by a voltage generation unit 535e based on VB - (for example, a voltage with VB - as the reference zero potential, which can be generated inside the chip).

[0176] The NMOS transistor 531e and the NMOS transistor M4 are NMOS transistors of the same type. The ratio of the on-resistance of the NMOS transistor 531e to the on-resistance of the NMOS transistor M4 is constantly K:1. At the same time, to ensure accuracy, the resistance value Re of the resistor 533e is set to be much smaller than the on-resistance of the NMOS transistor 531e. In this way, by comparing the voltage Ve at the connection point of the NMOS transistor 532e and the resistor 533e with Vref, when Ve is greater than Vref, the comparator 534e flips. Thus, the logic control unit 300 can control the drive unit 400 according to this flip signal, and output a control signal through the drive unit 400 to turn off the discharge NMOS transistor M4.

[0177] When the NMOS transistor is turned off, the current flowing through the NMOS transistor M4 is Vref / Re*K. Since Vref and Re are fixed values and K is a constant ratio, these three values will not change when the system voltage and temperature change. Thus, the current flowing through the NMOS transistor M4 will not change, that is, the detected discharge overcurrent will not change with voltage or temperature.

[0178] Figure 20 A schematic diagram according to the sixth embodiment of the present disclosure is shown.

[0179] This sixth embodiment is used to control the overcurrent during battery charging. The charging current Ichg flows from the B- terminal to the P- terminal. The charge and discharge control unit may include a detection unit and a comparison unit. The first input terminal of the comparison unit is connected to a voltage related to the voltage at the second terminal of the detection unit, the first input terminal of the comparison unit is connected to a voltage related to the voltage at the first terminal of the charge and discharge switch, and the first terminal of the detection unit is connected to the first terminal of the charge and discharge switch.

[0180] The charge and discharge switch is the NMOS transistor M4.

[0181] The detection unit includes a resistor 533f and an NMOS transistor 531f connected in series. In the case of controlling the charging current, one end of the resistor of the detection unit is connected to the first terminal of the charge and discharge switch, the other end is connected to one end of the NMOS transistor of the detection unit, and the other end is connected to the second terminal of the charge and discharge switch. And the connection point of the resistor and the NMOS transistor of the detection unit is connected to the first input terminal of the comparison unit. The second input terminal of the comparison unit is connected to a reference voltage generated based on the voltage at the second terminal of the charge and discharge switch. When the voltage at the first input terminal of the comparison unit is greater than the voltage at the second input terminal, the comparison result of the comparison unit flips, and the control logic unit controls the disconnection of the charging control switch. The resistance value of the resistor of the detection unit is much smaller than the on-resistance of the NMOS transistor of the detection unit.

[0182] The source of the NMOS transistor 531f is connected to the B-terminal, the drain is connected to one end of the resistor 533f, and the other end of the resistor 533f is connected to the P-terminal. The connection point between the NMOS transistor 531f and the resistor 533f is connected to one input terminal of the comparison unit 534f, and the other input terminal of the comparison unit 534f is connected to the reference voltage Vref generated based on VP- (the voltage of the P-terminal). The generation of the reference voltage Vref can be generated by a voltage generation unit based on VP- (for example, a voltage with VP- as the reference zero potential, which can be generated inside the chip).

[0183] The NMOS transistor 531f and the NMOS transistor M4 are of the same type of NMOS transistor. The ratio of the on-resistance of the NMOS transistor 531f to the on-resistance of the NMOS transistor M4 is constantly K:1. At the same time, to ensure accuracy, the resistance value Rf of the resistor 533f is set to be much smaller than the on-resistance of the NMOS transistor 531f. In this way, the voltage Vf at the connection point between the NMOS transistor 532f and the resistor 533f is compared with Vref. When Vf is greater than Vref, the comparator 534f flips, and thus the logic control unit 300 can control the driving unit 400 according to this flip signal, and output a control signal through the driving unit 400 to turn off the switch M4.

[0184] Since when the switch M4 is turned off, the current flowing through the NMOS transistor M4 is Vref / Rf*K. And Vref and Rf are fixed values, and K is a constant ratio. When the system voltage and temperature change, these three values will not change, so the current flowing through the NMOS transistor M4 will not change, that is, the detected charging overcurrent will not change with voltage or temperature.

[0185] Figure 21 A schematic diagram according to the seventh embodiment of the present disclosure is shown.

[0186] The seventh embodiment is used to control the charging overcurrent of the battery. The discharge current Idsg flows from the P-terminal to the B-terminal. The charge and discharge control unit may include a detection unit and a comparison unit. The first input terminal of the comparison unit is connected to a voltage related to the voltage at the second terminal of the detection unit, the first input terminal of the comparison unit is connected to a voltage related to the voltage at the first terminal of the charge and discharge switch, and the first terminal of the detection unit is connected to the first terminal of the charge and discharge switch. The charge and discharge switch is the charging M4.

[0187] In this embodiment, the comparison unit is an operational amplifier. A detection resistor is connected in series between the second input terminal and the output terminal of the operational amplifier. One end of the NMOS transistor of the comparison unit is connected to the second input terminal of the operational amplifier, and the other end of the NMOS transistor of the comparison unit is connected to the second end of the charge and discharge switch. The first input terminal of the operational amplifier is connected to the first end of the charge and discharge switch.

[0188] The current value of the charging current or the discharging current is obtained through the voltage generated by the detection resistor and the resistance value of the detection resistor.

[0189] The following will refer to Figure 21 for a detailed description. The detection unit may include an NMOS transistor 531g. The NMOS transistor 531g may be an NMOS transistor of the same type as the NMOS transistor M4.

[0190] The source electrode of the NMOS transistor 531g is connected to the B- terminal, and its drain electrode is connected to one input terminal of the operational amplifier 533g. The other input terminal of the operational amplifier 533g is connected to the P- terminal.

[0191] The principle of this embodiment will be described in detail below.

[0192] When charging, an external load is connected. The external load is connected between the positive output terminal P+ and the negative output terminal P- of the battery, and its resistance value is R Load , so the discharging current Idsq of the battery is [V(P+)-V(P-)] / R Load .

[0193] The operational amplifier 533g can make the source terminal voltage of the NMOS transistor 531g the same as the voltage of the negative terminal P- of the battery output. The NMOS transistor 531g and the NMOS transistor M4 are NMOS transistors of the same type. Therefore, even if the temperature or voltage changes, the ratio of the on-resistance of the NMOS transistor 531g to the on-resistance of the NMOS transistor M4 always remains a constant value K:1. Thus, the current flowing through the NMOS transistor 531g and the current flowing through the NMOS transistor M4 are constantly maintained at 1:K.

[0194] Due to the negative feedback effect of the operational amplifier 533g, the negative input terminal of the operational amplifier 533g, that is, the source terminal voltage of the NMOS transistor 531g, is the same as the voltage of the negative terminal P- of the battery output.

[0195] Since the input impedance of the operational amplifier 533g is approximately infinite, all the current of the NMOS transistor 531g flows into the sampling resistor 534g (the resistance value is Rg).

[0196] Thus, the output voltage V of the operational amplifier 533g sns = Rg * Idsg / k + V(P-). V(P-) is the voltage at the P- terminal.

[0197] V(P-) = V(B-) + Idsg * (R on ). V(B-) is the voltage at the B- terminal, and R on1 is the equivalent resistance of the NMOS transistor M4.

[0198] The B- terminal is the ground terminal of the battery. Therefore, V(B-) can be considered as the "ground" potential of the system, so V(B-) = 0.

[0199] Thus, V(P-) = Idsg * (R on ).

[0200] V sns = Rg * Idsg / K + V(P-) = Rg * Idsg / K + Idsg * (R on )

[0201] = Idsg * [(Rg / K + (R on )].

[0202] Usually, Rg / K >> (R on ), so the above formula can be equivalent to V sns = Idsg * Rg / K, Idsg = K * V sns / Rg.

[0203] V sns value can be obtained by the subsequent voltage sampling circuit. Rg is the pre-designed value of the circuit, so as to accurately obtain the magnitude of the discharge current Idsg flowing through the charge and discharge switch, and thus will not be affected by the voltage or temperature of the system.

[0204] Figure 22 Shows a schematic diagram according to the eighth embodiment of the present disclosure.

[0205] The eighth embodiment is used to control the overcurrent charging of the battery. The charging current Ichg flows from the B- terminal to the P- terminal. The charge and discharge control unit may include a detection unit and a comparison unit. The first input terminal of the comparison unit is connected to a voltage related to the voltage at the second terminal of the detection unit, the first input terminal of the comparison unit is connected to a voltage related to the voltage at the first terminal of the charge and discharge switch, and the first terminal of the detection unit is connected to the first terminal of the charge and discharge switch. The charge and discharge switch is the charging M4.

[0206] In this embodiment, the comparison unit is an operational amplifier. A detection resistor is connected in series between the second input terminal and the output terminal of the operational amplifier. One end of the NMOS transistor of the comparison unit is connected to the second input terminal of the operational amplifier, and the other end of the NMOS transistor of the comparison unit is connected to the second end of the charge and discharge switch. The first input terminal of the operational amplifier is connected to the first end of the charge and discharge switch.

[0207] The current value of the charging current or the discharging current is obtained through the voltage generated by the detection resistor and the resistance value of the detection resistor.

[0208] The detection unit may include an NMOS transistor 531h. The NMOS transistor 531h may be an NMOS transistor of the same type as the NMOS transistor M4.

[0209] The drain of the NMOS transistor 531h is connected to the P-terminal, and its source is connected to one input terminal of the operational amplifier 533h. The gate of the NMOS transistor 531h is connected to the control signal IN. The other input terminal of the operational amplifier 533h is connected to the B-terminal.

[0210] The principle of this embodiment will be described in detail below.

[0211] The NMOS transistor 531h and the NMOS transistor M4 are NMOS transistors of the same type. Therefore, even if the temperature or voltage changes, the ratio of the on-resistance of the NMOS transistor 531h to the on-resistance of the NMOS transistor M4 always remains a constant value K:1. Thus, the current flowing through the NMOS transistor 531h and the current flowing through the NMOS transistor M4 are constantly maintained at 1:K.

[0212] During charging, an external charger is connected between the output positive electrode (P+) and the output negative electrode (P-) of the battery. The magnitude of the charging current from the external charger to the battery pack is Ichg*(1 + 1 / K). The current flowing through the NMOS transistor M4 is Ichg, and the current flowing through the NMOS transistor 531h is Ichg / K.

[0213] The operational amplifier 533h can make the source voltage of the NMOS transistor 531h the same as the voltage of the negative electrode B- of the battery. The voltage of the negative electrode B- of the battery pack is the system "ground" potential. Therefore, V(B-) = 0.

[0214] Due to the negative feedback effect of the operational amplifier 533h, the negative input terminal of the operational amplifier 533h, that is, the source voltage of the NMOS transistor 531h, is the same as the voltage of the negative output terminal P- of the battery.

[0215] Also, since the input impedance of the operational amplifier 533h is approximately infinite, all the current of the NMOS transistor 531h flows into the sampling resistor 534h (with a resistance value of Rh).

[0216] In this way, the output voltage V of the operational amplifier 533h sns = Rh * Ichg / K + V(B-) = Rh * Ichg / K. Since the V sns value can be obtained by the subsequent voltage sampling circuit, and Rh is a pre-designed value of the circuit, the magnitude of the charging current Ichg flowing through the charge and discharge switch can be accurately obtained, and thus it will not be affected by the voltage or temperature of the system.

[0217] In addition, although in the drawings and the written description, the NMOS transistor is taken as an example for illustration, other types of MOS transistors, such as PMOS transistors, can also be used.

[0218] Through the embodiments of the present disclosure, it is possible to be not affected by the system temperature or voltage, and it is also possible to avoid being affected by the transistor itself. Thus, according to the technical solution of the present disclosure, high-precision detection of the charge and discharge current can be achieved.

[0219] According to a further technical solution of the present disclosure, the present disclosure provides a battery management chip 10, wherein the battery management chip can be integrated with the above-mentioned current control and detection circuit; the battery management chip can be integrated with the current control and detection circuit and the charge and discharge switch. In addition, the battery management chip can also be integrated with a voltage acquisition unit, a VDD generator, a driving unit, etc. as shown in the figure.

[0220] The present disclosure also provides an electrical device, which includes a battery or a battery pack and a battery management chip. The battery is used to supply power to other devices of the electrical device, and the battery management chip is used to manage the battery.

[0221] In the description of this specification, the description with reference to terms such as "one embodiment / way", "some embodiments / ways", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment / way or example are included in at least one embodiment / way or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment / way or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments / ways or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments / ways or examples described in this specification and the features of different embodiments / ways or examples.

[0222] In addition, the terms "first" and "second" are used for descriptive purposes only, and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0223] Those skilled in the art should understand that the above embodiments are merely for clearly explaining the present disclosure, rather than limiting the scope of the present disclosure. For those skilled in the art, other changes or variations can be made based on the above disclosure, and these changes or variations are still within the scope of the present disclosure.

Claims

1. An integrated device, characterized in that, The integrated device is used to detect and control the charging current and discharging current of a battery / battery pack, wherein the battery / battery pack is charged and discharged through a first connection terminal and a second connection terminal, and the integrated device integrates: A charge-discharge MOS transistor, which is a single MOS transistor and is connected in series on the current path between the battery / battery pack and the first connection terminal or between the battery / battery pack and the second connection terminal, and the charging and discharging are controlled by controlling the charge-discharge MOS transistor; A current detection MOS transistor, which is used to detect the charging current and / or discharging current flowing through the charge-discharge MOS transistor; A comparison unit, where the first input terminal of the comparison unit is connected to a voltage related to the voltage at the first end of the current detection MOS transistor, the second input terminal of the comparison unit is connected to a voltage related to the voltage at the first end of the charge-discharge MOS transistor, and the second end of the current detection MOS transistor is connected to the second end of the charge-discharge MOS transistor; The drain of the charge-discharge MOS transistor is connected to the load terminal / charger terminal and the second input terminal of the comparison unit, the source of the charge-discharge MOS transistor is connected to the battery / battery pack terminal, the source of the current detection MOS transistor is connected to the source of the charge-discharge MOS transistor, the drain of the current detection MOS transistor is connected to the second input terminal of the comparison unit, the drain of the current detection MOS transistor is connected to the drain of the first PMOS transistor, the source of the first PMOS transistor is connected to the source of the second PMOS transistor, the gates of the first PMOS transistor and the second PMOS transistor are connected and connected to the output terminal of the comparison unit, the drain of the second PMOS transistor is connected to the first input terminal of the second comparison unit and one end of a first resistor, the other end of the first resistor is grounded, the second input terminal of the second comparison unit is connected to a reference voltage, and the output terminal of the second comparison unit serves as the current detection output terminal.

2. The integrated device according to claim 1, wherein The charge-discharge MOS transistor includes a gate, a source, a drain, a substrate, a first parasitic diode, and a second parasitic diode, wherein the first parasitic diode and the second parasitic diode are connected in reverse series, one end of the series circuit of the first parasitic diode and the second parasitic diode is connected to the source, and the other end of the series circuit is connected to the drain, and the connection point of the first parasitic diode and the second parasitic diode is connected to the substrate.

3. The integrated device according to claim 2, wherein It further includes a switch, one end of the switch is connected to the connection point, the other end of the switch is connected to the source, when the charge-discharge MOS transistor is turned on and the switch is turned on, the source is connected to the substrate, when the charge-discharge MOS transistor is turned off and the switch is turned off, the source is disconnected from the substrate, and the substrate is in a floating state.

4. The integrated device according to claim 3, wherein, When the charge-discharge MOS transistor is turned on and the switch is turned on so that the source is connected to the substrate, the conductive channel of the charge-discharge MOS transistor is formed. When the charge-discharge MOS transistor is turned off and the switch is turned off so that the source is disconnected from the substrate, the conductive channel of the charge-discharge MOS transistor is not formed and the substrate is in a floating state.

5. The integrated device according to claim 4, wherein, The series circuit of the first parasitic diode and the second parasitic diode is arranged such that no conductive path is formed between the source and the drain through the series circuit.

6. The integrated device according to claim 5, wherein the charge-discharge MOS transistor is an NMOS transistor, and the charge-discharge MOS transistor is turned on when the gate-source voltage between the gate and the source is greater than the turn-on threshold voltage of the charge-discharge MOS transistor, and the charge-discharge MOS transistor is turned off when the gate-source voltage is less than the turn-on threshold voltage; or the charge-discharge MOS transistor is a PMOS transistor, and the charge-discharge MOS transistor is turned on when the gate-source voltage between the gate and the source is less than the turn-on threshold voltage of the charge-discharge MOS transistor, and the charge-discharge MOS transistor is turned off when the gate-source voltage is greater than the turn-on threshold voltage.

7. The integrated device according to claim 6, wherein when the charge-discharge MOS transistor is an NMOS transistor, the anode of the first parasitic diode is connected to the anode of the second parasitic diode, the cathode of the first parasitic diode is connected to the drain, and the cathode of the second parasitic diode is connected to the source; or when the charge-discharge MOS transistor is a PMOS transistor, the cathode of the first parasitic diode is connected to the cathode of the second parasitic diode, the anode of the first parasitic diode is connected to the drain, and the anode of the second parasitic diode is connected to the source.

8. The integrated device according to claim 7, wherein, The switch is an NMOS type and / or PMOS type transistor switch. The gate of the transistor switch is connected to the gate of the charge-discharge MOS transistor, the source of the transistor switch is connected to the connection point, and the drain of the transistor switch is connected to the source of the charge-discharge MOS transistor.

9. The integrated device according to claim 7, wherein, The switch is a triode. The base of the triode is connected to the gate of the charge-discharge MOS transistor via a first resistor, the emitter / collector of the triode is connected to the connection point, and the collector / emitter of the triode is connected to the source of the charge-discharge MOS transistor.

10. The integrated device according to claim 7, characterized in that, A second switch is connected between the gate and the drain of the charge-discharge MOS transistor. The second switch is arranged such that when the charge-discharge MOS transistor is turned off, the second switch ensures that the gate oxide layer of the charge-discharge MOS transistor is not broken down and / or the charge-discharge MOS transistor does not form a conductive channel.

11. The integrated device according to claim 4, wherein A second switch is connected between the gate and the drain of the charge-discharge MOS transistor, and the second switch is a voltage-resistant diode. When the charge-discharge MOS transistor is an NMOS transistor, the anode of the voltage withstand diode is directly or indirectly connected to the gate of the charge-discharge MOS transistor, and the cathode of the voltage withstand diode is directly or indirectly connected to the drain of the charge-discharge MOS transistor; or when the charge-discharge MOS transistor is a PMOS transistor, the cathode of the voltage withstand diode is directly or indirectly connected to the gate of the charge-discharge MOS transistor, and the anode of the voltage withstand diode is directly or indirectly connected to the drain of the charge-discharge MOS transistor.

12. The integrated device according to claim 7, wherein A triode is connected between the gate and the drain of the charge-discharge MOS transistor. The emitter / collector of the triode is connected to the gate of the charge-discharge MOS transistor, and the collector / emitter of the triode is connected to the drain of the charge-discharge MOS transistor.

13. The integrated device according to claim 4, wherein A second switch is connected between the gate and the drain of the charge-discharge MOS transistor. When the charge-discharge MOS transistor is an NMOS transistor, the second switch is a second NMOS transistor switch. The second NMOS transistor switch has a third parasitic diode. The source of the second NMOS transistor is directly or indirectly connected to one end of the third parasitic diode and to the gate of the charge-discharge MOS transistor. The drain of the second NMOS transistor is directly or indirectly connected to the other end of the third parasitic diode and to the drain of the charge-discharge MOS transistor; or When the charge-discharge MOS transistor is a PMOS transistor, the second switch is a second PMOS transistor switch. The second PMOS transistor switch has a third parasitic diode. The source of the second PMOS transistor switch and one end of the third parasitic diode are directly or indirectly connected to the gate of the charge-discharge MOS transistor. The drain of the second PMOS transistor and the other end of the third parasitic diode are directly or indirectly connected to the drain of the charge-discharge MOS transistor.

14. The integrated device according to claim 4, characterized in that, The switch is replaced by a first Schottky diode and a second Schottky diode. When the charge-discharge MOS transistor is an NMOS transistor, the cathode of the first Schottky diode is connected to the cathode of the second Schottky diode and connected to the substrate. The anode of the first Schottky diode is connected to the drain, and the anode of the second Schottky diode is connected to the source. Or, When the charge-discharge MOS transistor is a PMOS transistor, the anode of the first Schottky diode is connected to the anode of the second Schottky diode and connected to the substrate. The cathode of the first Schottky diode is connected to the drain, and the cathode of the second Schottky diode is connected to the source.

15. The integrated device according to claim 14, characterized in that, A second switch is connected between the gate and the drain of the charge-discharge MOS transistor. The second switch is set such that when the charge-discharge MOS transistor is turned off, the second switch ensures that the gate oxide layer of the charge-discharge MOS transistor will not be broken down and / or the charge-discharge MOS transistor does not form a conductive channel.

16. The integrated device according to claim 13, wherein A second switch is connected between the gate and the drain of the charge and discharge MOS transistor, and the second switch is a voltage withstand diode. When the charge and discharge MOS transistor is an NMOS transistor, the anode of the voltage withstand diode is directly or indirectly connected to the gate of the charge and discharge MOS transistor, and the cathode of the voltage withstand diode is directly or indirectly connected to the drain of the charge and discharge MOS transistor; or when the charge and discharge MOS transistor is a PMOS transistor, the cathode of the voltage withstand diode is directly or indirectly connected to the gate of the charge and discharge MOS transistor, and the anode of the voltage withstand diode is directly or indirectly connected to the drain of the charge and discharge MOS transistor.

17. The integrated device according to claim 13, wherein, A second switch is connected between the gate and the drain of the charge and discharge MOS transistor. When the charge and discharge MOS transistor is an NMOS transistor, the second switch is a second NMOS transistor switch, and the second NMOS transistor switch has a third parasitic diode. The source of the second NMOS transistor is directly or indirectly connected to one end of the third parasitic diode and the gate of the charge and discharge MOS transistor, and the drain of the second NMOS transistor is directly or indirectly connected to the other end of the third parasitic diode and the drain of the charge and discharge MOS transistor; or When the charge and discharge MOS transistor is a PMOS transistor, the second switch is a second PMOS transistor switch, and the second PMOS transistor switch has a third parasitic diode. The source of the second PMOS transistor switch and one end of the third parasitic diode are directly or indirectly connected to the gate of the charge and discharge MOS transistor, and the drain of the second PMOS transistor and the other end of the third parasitic diode are directly or indirectly connected to the drain of the charge and discharge MOS transistor.

18. The integrated device according to any one of claims 4 to 17, characterized in that, It further includes: A control logic unit, and the control logic unit controls the charge and discharge MOS transistor according to the comparison result output by the comparison unit.

19. The integrated device according to claim 18, wherein, The current ratio between the current flowing through the charge and discharge MOS transistor and the current flowing through the current detection MOS transistor remains constant.

20. The integrated device according to claim 19, characterized in that, The current ratio between the current flowing through the charge and discharge MOS transistor and the current flowing through the current detection MOS transistor is independent of the system voltage and the system temperature.

21. The integrated device according to claim 1, characterized in that, Alternatively, the drain of the charge / discharge MOS transistor is connected to the load terminal / charger terminal and the drain of the current detection MOS transistor. The first input terminal of the comparison unit is connected to the source of the charge / discharge MOS transistor and to the battery / battery pack terminal. The second input terminal of the comparison unit is connected to the source of the current detection MOS transistor. The source of the current detection MOS transistor is connected to the drain of the first PMOS transistor. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor and to the output terminal of the comparison unit. The source of the first PMOS transistor is connected to the source of the second PMOS transistor. The drain of the second PMOS transistor is connected to the first input terminal of the second comparison unit and to one end of the first resistor. The other end of the first resistor is grounded. The second input terminal of the second comparison unit is connected to the load terminal / charger terminal. The output terminal of the second comparison unit serves as the current detection output terminal.

22. A battery / battery pack management chip, characterized in that, Comprising the integrated device according to any one of claims 1 to 21.

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