Quantum circuit design specific to an application or algorithm

Abstract

Techniques are presented for designing application or algorithm specific quantum computing circuits for a particular application or algorithm. Design components can include an extractor component that can extract pairs of qubits determined to meet a defined threshold potential that necessitates direct connections between one another to be used in the quantum circuit design based on an analysis of the application or algorithm; a design management component (DMC) can determine a circuit design for a quantum circuit for the application or algorithm based on a feature analysis related to the pairs of qubits. The DMC can classify the pairs of qubits by a weighting scheme and features including a number of downstream qubits that are affected, a number of two-qubit gate operations between the pairs of qubits, and / or whether the pairs of qubits affect a measurement. Based on the classification, the DMC can select the highest ranked pairs of qubits to assign direct connections.

Description

BACKGROUND

[0001] The present disclosure relates to quantum circuits, such as quantum circuit design. Quantum computing employs quantum physics to encode and process information, as opposed to transistor-based binary digital technology. Quantum computing devices employ quantum bits (also known as qubits) that operate according to the laws of quantum physics, and can exhibit phenomena such as superposition and entanglement. The superposition principle of quantum physics allows a qubit to be in a state that represents both a “1” and a “0” value at the same time. The entanglement principle of quantum physics causes qubits to be correlated with each other such that the state of a qubit cannot be resolved into individual qubit states. For example, the state of a first qubit can depend on the state of a second qubit. In this way, quantum circuits can employ qubits to encode and process information in a manner that is significantly different from transistor-based binary digital technology. However, the design of quantum circuits can generally be relatively difficult and / or time consuming.

[0002] With respect to quantum circuit design, a conventional approach can be to employ a universal quantum computing circuit that can be used for almost all types of algorithms, and that has varying and / or limited performance levels. The universal quantum computing circuit design can be used for algorithms to create a superconducting quantum computing circuit to perform superconducting quantum circuit operations. The universal quantum computing circuit can generally have qubits that can be connected to all of their neighboring qubits, and can generally run all or almost all types of algorithms, albeit with varying and / or limited performance levels due at least in part to, for example, resource limitations and design constraints, as well as the universality of the connectivity of the qubits in the universal quantum computing circuit. For a universal quantum computing circuit, for operations on qubits that are not directly connected, a number of swap gates can generally be used. However, there can be a number of problems with using a universal quantum computing circuit for algorithms, particularly using the universal quantum computing circuit on a non-ideal quantum processor. For example, certain quantum processors can be considered non-ideal because they can include non-ideal qubits (e.g., shorter coherence times) and / or non-ideal gates (e.g., gate errors). Due to these and / or other non-idealities, the number of gate operations that can be employed can be limited, under the premise that a reasonable fidelity of the final result can still be obtained. These types of circuits are often referred to as shallow. In principle, a universal quantum computing circuit can implement an arbitrary algorithm that is conventionally connected thereto. However, when a universal quantum computing circuit is used for an algorithm, there can be an undesirable and / or unacceptably high cumulative error rate, in part due to the relatively high number of gate operations used because gate fidelities are not 100%. These and other deficiencies of conventional quantum computing circuit designs, such as universal quantum computing circuit designs, can result in inefficient and / or ineffective circuits and / or inefficient quantum circuit designs. SUMMARY

[0003] The following presents a summary to provide a basic understanding of one or more embodiments of the disclosed subject matter. This summary is not intended to identify key or critical elements, or delineate any scope of particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, a system, device, structure, computer- implemented method, apparatus, and / or computer program product can facilitate determining a circuit design for a quantum circuit for an application based on an analysis of characteristics associated with pairs of qubits.

[0004] According to one embodiment, a system includes a memory storing computer executable components; a processor operatively coupled to the memory to execute the computer executable components. The computer executable components can include an extractor component that extracts pairs of qubits determined to satisfy a defined threshold potential that must use direct connections between each other based on an analysis of an application. The computer executable components can also include a design management component that determines a circuit design for a quantum circuit to use. The analysis of the application is based on an analysis of characteristics related to the pairs of qubits. The system can have many advantages, including that the system can enhance performance of a quantum circuit and an application or related algorithm when the application or algorithm is run using the quantum circuit.

[0005] In some embodiments, the design management component can analyze the characteristics associated with the pairs of qubits and can classify the pairs of qubits based on the characteristics associated with the pairs of qubits and a weight value associated with the characteristics. In certain implementations, the design management component can determine a subset of the pairs of qubits based on the classification that have a higher ranking than other pairs of qubits in the pairs of qubits and a subset of the pairs of qubits based on a defined circuit design criteria (which can indicate a maximum number of pairs of qubits that are allowed direct connections) can be assigned direct connections to the pairs of qubits. These embodiments of the system can provide many advantages, including that the system can reduce a number of gates used in a quantum circuit for running an application or related algorithm and reduce connections used in a quantum circuit for running an application or related algorithm.

[0006] Another embodiment relates to a computer-implemented method that includes extracting, by a system operatively coupled with a processor, pairs of qubits determined to satisfy a defined threshold potential that must utilize a direct connection between one another by an analysis. One application. The computer-implemented method can further include determining, by the system, a circuit design for a quantum circuit to be used for the application based on the analysis of characteristics of the pairs of qubits. The computer-implemented method can have a number of advantages, including that the method can enhance the performance of the quantum circuit and the application or related algorithm when the application or related algorithm is run using the quantum circuit.

[0007] In certain embodiments, the computer-implemented method can further include analyzing, by the system, characteristics associated with the pairs of qubits; and, classifying, by the system, the pairs of qubits based on the characteristics associated with the pairs of qubits and weight values associated with the characteristics. In other embodiments, the computer-implemented method can include determining, by the system, a subset of the pairs of qubits that has a higher ranking than one other of the pairs of qubits based on the classifying of the pairs of qubits; and assigning a direct connection to pairs of qubits of the subset of the pairs of qubits, where a maximum number of qubits that can exist in the subset of the pairs of qubits is determined based on defined circuit design criteria. Such embodiments of the method can provide a number of advantages, including that the method can reduce the number of gates used in a quantum circuit for running the application or related algorithm and reduce the connectivity used in a quantum circuit for running the application or algorithm.

[0008] Another embodiment relates to a computer program product that facilitates determining a circuit design for a quantum circuit, the computer program product including a computer readable storage medium having program instructions stored therein. The program instructions can be executable by a processor to cause the processor to extract, based on an analysis of an application, pairs of qubits determined to satisfy a defined threshold potential that must utilize a direct connection between one another. The program instructions can also be executable by the processor to determine a circuit design for a quantum circuit to be used for the application based on the analysis of characteristics of the pairs of qubits. The computer program product can have a number of advantages, including that the computer program product can enhance the performance of the quantum circuit and the application or related algorithm when the application or related algorithm is run using the quantum circuit.

[0009] In some embodiments, the program instructions can be executed by the processor to cause the processor to perform operations of analyzing characteristics associated with the pair of qubits, and classifying the pair of qubits based on the characteristics associated with the pair of qubits and weight values associated with the characteristics, where the characteristics can be selected from a set of characteristics including a number of affected downstream qubits associated with one of the pair of qubits, a number of two-qubit gate operations between the pair of qubits, a measurement affected by the pair of qubits, and determining that no measurement result is affected by the pair of qubits. These embodiments of the computer program product can provide a number of advantages, including that the computer program product can reduce the number of gates used in a quantum circuit for running an application or related algorithm, and reduce the connectivity used in a quantum circuit for running the application or algorithm.

[0010] According to another embodiment, a system includes a memory that stores computer executable components, and a processor that is operatively coupled to the memory to execute the computer executable components. The computer executable components can include an extractor component that extracts pairs of qubits determined to satisfy a defined threshold potential based on an analysis of an algorithm associated with an application for use with direct connections between each other. The computer executable components can also include a design management component that determines a quantum computing circuit design for the algorithm based on an analysis of characteristics associated with the pairs of qubits and weight values associated with the characteristics. The system can have a number of advantages, including that the system can enhance the performance of the quantum computing circuit design and the algorithm when the algorithm is run using the quantum computing circuit design.

[0011] In certain embodiments, the design management component can analyze characteristics associated with the pairs of qubits, and can rank the pairs of qubits based on the characteristics associated with the pairs of qubits and based on weight values associated with the characteristics. In other embodiments, the design management component can determine a subset of the pairs of qubits that have a higher rank than one other of the pairs of qubits based on the ranking of the pairs of qubits, and can assign direct connections to pairs of qubits of the subset of the pairs of qubits based on a defined circuit design criteria that can indicate a number of pairs of qubits that can have direct connections. Such embodiments of the system can provide a number of advantages, including that the system can reduce the number of gates in a quantum circuit for running the algorithm, and reduce the connectivity in a quantum circuit for running the algorithm.

[0012] Another embodiment relates to a computer program product that facilitates determining a quantum computing circuit design, the computer program product including a computer readable storage medium having program instructions embedded therein. The program instructions are executable by a processor to cause the processor to extract a pair of qubits determined to satisfy a defined threshold potential to use a direct connection between each other based on an analysis of an algorithm associated with an application. The program instructions are also executable by the processor to determine a quantum computing circuit design for the algorithm based on an analysis of a characteristic associated with the pair of qubits and based on a weight associated with the characteristic. The computer program product can have a number of advantages, including that the computer program product can enhance performance of the quantum computing circuit design and the application or related algorithm when the application or related algorithm is run using the quantum computing circuit design.

[0013] In some example embodiments, the program instructions can be executable by the processor to cause the processor to analyze the characteristic associated with the pair of qubits; rank the pair of qubits based on a result of the analysis of the characteristic associated with the pair of qubits and based on a weight value associated with the characteristic, where the characteristic can be selected from a group of characteristics including a number of affected downstream qubits associated with one of the pair of qubits, a number of two-qubit gate operations between the pair of qubits, a measurement affected by the pair of qubits, and a determination that no measurement result is affected by the pair of qubits. These embodiments of the computer program product can provide a number of advantages, including that the computer program product can reduce a number of gates used in a quantum circuit for running an application or related algorithm and reduce connectivity used in a quantum circuit for running an application or algorithm.

[0014] These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 A block diagram of an exemplary, non-limiting system that can be effectively used for a design application or algorithm that is specific to quantum computing circuit design is shown in accordance with various aspects and embodiments of the disclosed subject matter.

[0016] Figure 2 A diagram of an exemplary, non-limiting algorithm for which a desired customized quantum computing circuit design subject (e.g., a quantum computing circuit design for a particular algorithm) can be determined is shown in accordance with various aspects and embodiments of the disclosed subject matter.

[0017] Figure 3Example algorithm diagrams generated for example algorithms for desired quantum computing circuit design specific principles of the example algorithms are shown, and corresponding schematic diagrams of the desired quantum computing circuit designs are constructed in accordance with various aspects and embodiments of the disclosed subject matter.

[0018] Figure 4 A diagram of an example quantum computing circuit is shown in accordance with various aspects and embodiments of the disclosed subject matter.

[0019] Figure 5 A block diagram of an example design component is shown in accordance with various aspects and embodiments of the disclosed subject matter.

[0020] Figure 6 A flowchart of an example non-limiting method for determining application or algorithm specific quantum computing circuit designs for applications or algorithms is shown in accordance with various aspects and embodiments of the disclosed subject matter.

[0021] Figure 7 A flowchart of another example non-limiting method for determining application or algorithm specific quantum computing circuit designs for applications or algorithms is depicted in accordance with various aspects and embodiments of the disclosed subject matter.

[0022] Figure 8 A flowchart of an example non-limiting method is shown in accordance with various aspects and embodiments of the disclosed subject matter. The flowchart determines that an application or algorithm specific quantum computing circuit design for one of the quantum computing circuit designs for a particular plurality of applications or algorithms is used for that application or algorithm.

[0023] Figure 9 An example non-limiting block diagram is shown that illustrates an operating environment in which one or more embodiments described herein can be implemented.

[0024] Figure 10 A diagram of an example Toffoli gate for a quantum computing circuit is shown. DETAILED DESCRIPTION

[0025] The following detailed description is merely illustrative and is not intended to limit embodiments and / or the application or uses of embodiments. Furthermore, there is no intention to be bound by any expressed or implied information provided in the preceding "SUMMARY" or the "ABSTRACT".

[0026] One or more embodiments will now be described, by way of example, with reference to the accompanying drawings, in which like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding. It will be apparent, however, that one or more embodiments can be practiced without these specific details.

[0027] Superconducting quantum computing circuit operations can rely on resonant coupler (e.g., "bus") connections or capacitive coupler connections to directly couple qubits (also referred to as quantum bits) that can be used in quantum computing circuit designs. A universal quantum computing circuit can generally have qubits that can be connected to all of their neighboring qubits, and can generally run almost any type of algorithm. With respect to universal quantum computing circuits, for operations on qubits that are not directly connected, a number of swap gates can generally be used. Due to non-ideal conditions, the number of gate operations that can be employed during operation of the circuit (e.g., a "shallow" quantum computing circuit) can be limited.

[0028] A coherence time can characterize an amount of time that a qubit can maintain its quantum state (including entangled states) before being affected by its external environment. Currently, coherence times can be relatively short, e.g., less than 500 microseconds (ms) in superconducting qubits. It can be difficult to extend coherence times, which can be a consequence of "shallow" quantum computing circuits where the number of gate operations can be limited.

[0029] There can be advantages to using quantum circuits even before quantum error correction and logical qubits with long effective coherence times are implemented. Certain applications (e.g., quantum dynamics) can employ relatively complex algorithms and / or can utilize relatively large amounts of computing power when run on classical computers, which can make use of classical computers for such applications undesirable and inefficient. Also, applications can include or utilize specialized (e.g., specific) algorithms where the algorithms can include or employ specialized sequential gate operations, each of which is arranged on a subset of qubits when using quantum circuits. In running such applications (e.g., applications that use complex algorithms, such as quantum dynamics applications), using quantum circuits can generally result in better performance than classical computing, even before quantum error correction and logical qubits with long effective coherence times are implemented.

[0030] In a superconducting quantum computing circuit, connectivity issues can be overcome by certain gate operations. For example, in a superconducting quantum computing circuit, connectivity issues can be overcome by gate decomposition and use of swap gates. In theory, any application or algorithm can be run on a universal quantum computing circuit. However, there can be costs or trade-offs when running an application or algorithm on a universal quantum computing circuit that can result in inefficiencies in the algorithm. These inefficiencies can negatively impact (e.g., reduce) the performance of the application or algorithm using the universal quantum computing circuit. For example, when running an application or algorithm using a universal quantum computing circuit, some of the costs and trade-offs can include a relatively excessive and disproportionate increase in the number of gate operations, which is limited by the coherence time when using a universal quantum computing circuit. When running an application or algorithm using a universal quantum computing circuit, the cumulative error rate can also be relatively high due to gate fidelities that are not 100%. The more qubits involved in the application or algorithm, the higher the costs or trade-offs can be when running the application or algorithm using a universal quantum computing circuit.

[0031] For example, in Linke, N. M. et al., Experimental comparison of two quantum computing architectures, Proc. Natl. Acad. Sci., vol. 114, No. 13, 3305-3310 (2017), the negative impact of using excessive gate operations has been illustrated by comparing experimental results of quantum computing circuit architectures. Figure 10 An example Toffoli gate 1000 of a quantum computing circuit is shown. When a quantum computing circuit contains a gate (e.g., Toffoli gate 1000) between two disconnected pairs of qubits, system overhead can be incurred due to the use of an extra two-qubit gate to implement a swap operation for, e.g., a star circuit. In Experimental comparison of two quantum computing architectures (Linke et al.), four algorithms were run on circuits with gates (e.g., Toffoli gate 1000) using a star-connected architecture with a superconducting hardware system and a fully connected architecture with an ion-trap system, and the experimental results were as follows in Table 1:

[0032]

[0033] Table 1

[0034] wherein Table 1 is a summary of success probabilities expressed in percentage values for the circuits, characterized in that the observed (Obs) values represent the observed probabilities, the first estimate assumes random (RAND) error propagation with total error (1-E g )√N, and the second estimate is based on having an overall error (1-E gcoherent over-rotations and under-rotations of the system (Sys) of N gates, where N is the number of gates, where E g is a gate error parameter.

[0035] Thus, conventional quantum computing circuits, such as general-purpose quantum computing circuits, can suffer from many problems such as those described above, including excessive or unnecessary connectivity between qubits, an excessive number of gate operations, which can be limited by the coherence time associated with the qubits and an excessively high cumulative error rate due to the fidelity of the gates not being 100%. The disclosed subject matter can be implemented to produce solutions to all or at least some of all of these problems and / or other problems of conventional quantum computing circuits by determining and / or designing a custom (e.g., application or algorithm specific) quantum computing circuit (e.g., a superconducting quantum computing circuit) in the form of a quantum computing circuit (e.g., a superconducting quantum computing circuit) for use with an application or algorithm. By determining and / or designing a custom quantum computing circuit for use with an application or algorithm, the disclosed subject matter can, for example, reduce the number of gates in the quantum computing circuit for running the application or algorithm, reduce the connectivity utilized in the quantum computing circuit to run the application or algorithm, and enhance the performance of the quantum computing circuit and the application or algorithm when the quantum computing circuit is used to run the application or algorithm.

[0036] To this end, various embodiments herein relate to techniques for designing an application or algorithm specific quantum computing circuit (e.g., a superconducting quantum computing circuit). The disclosed subject matter can employ such techniques, for example, to engineer (as the term “engineer” is used herein, the term includes manufacture and / or construction) a physical layout scheme (e.g., a physical layout of a quantum computing circuit) that is application or algorithm specific, where the physical layout scheme can employ a reduced number of gates utilized on the quantum computing circuit to run the application or algorithm specific (e.g., as compared to a general-purpose quantum computing circuit). The disclosed subject matter can generate a quantum computing circuit for a particular application or algorithm that can achieve a desired (e.g., optimal, enhanced, suitable, or acceptable) performance of the application or algorithm (e.g., a quantum algorithm) and a desired performance of the corresponding quantum computing circuit (e.g., as compared to a general-purpose quantum computing circuit).

[0037] The disclosed subject matter can include a design component that can be used to design a specific quantum computing circuit (e.g., a custom or tailor-made quantum computing circuit) that is specific to an application or algorithm for a particular application or algorithm. The design component can include an extractor component that can extract pairs of qubits that are determined to satisfy a defined threshold potential for which direct connections between the pairs of qubits (e.g., direct connections between qubits within a pair of qubits) must be used in the quantum circuit. The design is made based at least in part on analysis results of the application or algorithm, according to the application or algorithm. According to the application or algorithm, the pairs of qubits can be, for example, pairs of qubits for which direct connections between qubits in the pairs of qubits can be ideal (e.g., particularly useful, beneficial, and / or preferred) in terms of the application or algorithm and a defined circuit design standard (and a related defined threshold potential that can be based at least in part on (e.g., indicated or specified by) the defined circuit design standard). The design component can also include a design management component that can determine a circuit design for a quantum circuit to be used for the application or algorithm based at least in part on analysis results of characteristics associated with the pairs of qubits. As part of determining the quantum circuit design for the application or algorithm, the design management component can determine, for example, which of the pairs of qubits (e.g., the extracted pairs of qubits) to directly assign based at least in part on analysis results of characteristics associated with the pairs of qubits and applicable process and design constraints related to the quantum circuit design, where such analysis can include, for example, as more fully described herein, applying a weighting scheme to the characteristics and ranking and / or ordering the pairs of qubits according to the weighted characteristics.

[0038] The design management component can rank the pairs of qubits by the weighting scheme and the characteristics associated with the pairs of qubits. The characteristics can include, for example, a number of affected downstream qubits relative to a pair of qubits in the pair of qubits, a number of two-qubit gate operations between the pair of qubits, a determination that there are no measurements that can be affected by the pair of qubits, and / or a determination that there are measurements that will be affected by the pair of qubits. Based at least in part on the results of the ranking, the design management component can select a subset of the pairs of qubits that are determined to be higher ranked according to the defined circuit design standard, which can relate to and / or be based at least in part on process and / or design specifications that can limit or dictate (e.g., dictate a defined threshold for) a maximum number of direct connections to be assigned to the pairs of qubits. The design management component can assign the direct connections to those higher ranked pairs of qubits.

[0039] If the design management component determines or creates more than one circuit design that can satisfy defined circuit design criteria related to process and / or design specifications and / or application or algorithm, the design management component can analyze such circuit designs to determine a most suitable circuit design compared to other circuit designs according to applicable circuit design criteria (e.g., other circuit design criteria related to determining a most suitable circuit design).

[0040] These and other aspects and embodiments of the disclosed subject matter will now be described with reference to the drawings.

[0041] Based on the various aspects and embodiments of the disclosed subject matter, Figure 1 A block diagram of an example, non-limiting system 100 in accordance with the present disclosure is shown that can be used to efficiently design application or algorithm specific quantum computing circuit designs (e.g., superconducting quantum computing circuit designs). The system 100 can be used to design application or algorithm specific quantum computing circuits for a particular application or algorithm.

[0042] The system 100 can include a design component 102 that can be used to design a quantum computing circuit for an application or algorithm. The design component 102 can employ various techniques, as described herein, for designing an application or algorithm specific quantum computing circuit for the application or algorithm. The design component 102 can employ such techniques to, for example, provide an engineer with a physical layout (e.g., a physical layout of a quantum computing circuit) for a particular application or algorithm, where the physical layout scheme can employ a reduced number of gates in the quantum computing circuit to run (e.g., to more efficiently run) the particular application or algorithm (e.g., as compared to a general purpose quantum computing circuit). The design component 102 can generate an application or algorithm specific quantum computing circuit for the application or algorithm (e.g., a quantum algorithm) that can achieve a desired (e.g., optimal, enhanced, suitable, or acceptable) performance of the application or algorithm and a corresponding desired performance of the quantum computing circuit (e.g., as compared to a general purpose quantum computing circuit).

[0043] The design component 102 can include an extractor component 104 and a design management component 106. The design management component 106 can analyze an application or algorithm. For example, the design management component 106 can analyze features, functions, and / or characteristics of the application or algorithm. As part of the analysis of the application or algorithm, the design management component 106 can identify or determine qubits and / or qubit pairs for the application or algorithm.

[0044] In some embodiments, the design management component 106 can determine, based at least in part on the analysis results of an application or algorithm in the quantum circuit design according to defined circuit design criteria, and the extractor component 104 can extract from the application or algorithm qubit pairs that satisfy a defined threshold potential that requires the use of direct connections between them (e.g., direct connections between qubits within a qubit pair). More fully described herein, the design management component 106 can determine the quantum computing circuit design to be used for the application or algorithm based at least in part on the analysis results of characteristics associated with the qubit pairs according to defined circuit design criteria.

[0045] Reference Figure 2 (together) Figure 1 Based on the various aspects and embodiments of the disclosed subject matter, Figure 2 A schematic diagram of an exemplary non-limiting algorithm 200 is depicted, for which design component 102 can determine an ideal custom quantum computing circuit design (e.g., an algorithm-specific quantum computing circuit design). For example, based at least in part on the analysis results of algorithm 200 (e.g., features, functionality, and / or characteristics of algorithm 200) (e.g., by design management component 106), design management component 106 can determine qubits with respect to algorithm 200 that satisfy the requirement to use defined threshold potentials that are directly interconnected with each other, according to defined circuit design criteria. For example, based at least in part on the analysis results of algorithm 200, design management component 106 can identify or determine a set of qubit pairs with respect to algorithm 200 that satisfy the requirement to use defined threshold potentials that are directly interconnected with each other in the quantum circuit design, wherein the set of qubit pairs may include, for example, qubit pairs 12 202. Quantum Bit Pair 13 204. Quantum Bit Pair 23 206. Quantum Bit Pairs 34 208, qubit pairs 45 210. Quantum Bit Pair 46 212 and qubit pairs 56 214. From Figure 2 As can be seen from algorithm 200, at least one of the set of qubit pairs (e.g., qubit pairs 202 to 214) can potentially utilize direct connections.

[0046] The extractor component 104 can extract the pairs of qubits from the algorithm 200. The design management component 106 can determine a desired (e.g., conventional or custom) quantum computing circuit design for the algorithm 200 (or application) based at least in part on results of an analysis of characteristics (e.g., properties) associated with pairs of qubits in the set of pairs of qubits (e.g., pairs of qubits 202-214) according to defined circuit design criteria. To facilitate determining a desired (e.g., custom or tailored) quantum computing circuit design, the design management component 106 can analyze pairs of qubits in the set of pairs of qubits (e.g., pairs of qubits 202-214) of the algorithm 200 to identify or determine characteristics associated with the pairs of qubits and can analyze the characteristics associated with the pairs of qubits. For example, the design management component 106 can identify and analyze a first set of characteristics associated with a first pair of qubits, a second set of characteristics associated with a second pair of qubits, a third set of characteristics associated with a third pair of qubits, and so on. The characteristics can include, for example, a number of affected downstream qubits associated with a pair of qubits (e.g., pairs of qubits 202-214), a number of two-qubit gate operations between a pair of qubits, a measurement capable of being affected by a pair of qubits, and / or a confirmation of an absence of a measurement to be affected by a pair of qubits.

[0047] For example, based at least in part on results of the analysis of the pairs of qubits and characteristics of the pairs of qubits for the algorithm 200, the design management component 106 can determine that the pair of qubits 34 208 has the highest number of affected downstream qubits compared to other pairs of qubits (e.g., pairs of qubits 202, 204, 206, 210, 212, and 214) because the pair of qubits 34 (when considering the pairs of qubits in the algorithm 200 from left to right, it is the leftmost and applied earliest in the algorithm 200) affects all downstream other qubits, which is greater than the number of qubits affected by any other pair of qubits. The design management component 106 can also determine that the pair of qubits 23 206 and the pair of qubits 45 210 each have a second highest number of affected downstream qubits compared to other pairs of qubits.

[0048] As another example, the design management component 106 can determine that, for the algorithm 200, the pair of qubits 23 206 and the pair of qubits 45 210 have the highest number of two-qubit gate operations compared to other pairs of qubits (e.g., pairs of qubits 202, 204, 208, 212, and 214). For example, the design management component 106 can determine that, for the algorithm 200, the pair of qubits 23 206 and the pair of qubits 45210 each is used three times, and other pairs of qubits in the set of pairs of qubits can be determined, and pairs of qubits 23 206 and pairs of qubits 45 210 have the highest number of two-qubit gate operations.

[0049] According to the defined circuit design criteria, the design management component 106 can classify the pairs of qubits in the set of pairs of qubits based at least in part on results of analysis of characteristics associated with the pairs of qubits in the set of qubits (e.g., pairs of qubits 202-214) and weight values associated with the set of qubit-related characteristics (e.g., which can be assigned or determined). The design management component 106 can determine and assign weight values to characteristics (e.g., types of characteristics). For example, the design management component 106 can determine and assign a first weight to a first (e.g., a first type of) characteristic related to a pair of qubits (e.g., a number of downstream qubits related to a pair of qubits), assign a second weight to a second characteristic related to a pair of qubits (e.g., a number of two two-qubit gate operations between the pair of qubits), and / or assign a third weight to a third characteristic related to a pair of qubits (e.g., a measure of likely impact of a pair of qubits on a measurement or a confirmation that a measurement is not impacted by a pair of qubits), etc.

[0050] It should be appreciated and understood that while certain characteristics associated with pairs of qubits and certain numbers of characteristics are disclosed herein, the disclosed subject matter is not limited to this matter, and other types of characteristics of pairs of qubits can exist and / or a desired number of characteristics of pairs of qubits can be considered, which can be greater than three, equal to three, or less than three, in addition to or in addition to the characteristics disclosed herein.

[0051] According to the defined circuit design criteria, the design management component 106 can determine an ordering of the pairs of qubits in the set of pairs of qubits based at least in part on results of classification of the pairs of qubits in the set of pairs of qubits (e.g., pairs of qubits 202-214). For example, with respect to the algorithm 200, if the design management component 106 determines that the pair of qubits 34 208 has the highest weighted score of the pairs of qubits in the set of pairs of qubits compared to the weighted scores of the other pairs of qubits (e.g., pairs of qubits 202, 204, 206, 210, 212, and 214), the design management component 106 can determine that the pair of qubits 34208 has the highest ranking. If the design management component 106 determines the weighted scores of other qubit pairs (e.g., qubit pairs 202, 204, 208, 212, and 214), the qubit pair... 23 206 and / or qubit pairs 45 210 has the second highest weighted score among the qubit pairs in this group, and the design management component 106 can determine the ranking of the qubit pair compared to other qubit pairs. 23 206 and / or qubit pairs 45 210 is the second highest (or tied for second highest).

[0052] For example, regarding Algorithm 200, if applicable circuit design criteria result in assigning weight values ​​to characteristics relating to the number of downstream qubits affected by a pair of qubits, such weight values ​​are sufficiently higher than the weight values ​​assigned and applied to characteristics relating to the number of two-qubit gate operations between the qubit pair and the weight values ​​assigned and applied to characteristics relating to measurements that may be affected by the pair of qubits (or confirmations that no measurement will be affected by the pair of qubits), the qubit pair... 34 The weighted score of 208 can be higher than that of qubit pairs. 23 206 and qubit pairs 45 The weighted score of 210 (and other qubit pairs), even if the qubit pairs 23 206 and qubit pairs 45 Each of 210 has the second highest number of downstream qubits with influence and the highest number of two-qubit gate operations between each qubit. However, if the applicable circuit design criteria differ with respect to algorithm 200, and accordingly, the weight values ​​assigned to the characteristics related to the number of downstream qubits with influence associated with a pair of qubits are not sufficiently higher or lower than the weight values ​​already assigned and applied to the characteristics regarding the number of two-qubit gate operations between a pair of qubits, and are not greater or lower than the weight values ​​already assigned and applied to the characteristics regarding measurements that may be affected by a pair of qubits (or confirmations that no measurement will be affected by a pair of qubits), the qubit pair 34 208, qubit pairs 34 The weighted score of 208 can also be lower than that of a qubit pair. 23 206 and qubit pairs 45 Each weighted score is 210. Even for qubit pairs 34 208 has the largest number of downstream qubits that affect the design, which may also lead to the design management component 106 pairing qubits with... 23 206 and qubit pairs 45 210 ranks higher than qubit pairs 34 The location of 208.

[0053] According to defined circuit design standards, based at least in part on the ranking of pairs of qubits in the set of pairs of qubits (e.g., pairs of qubits 202-214), the design management component 106 can select a subset of pairs of qubits in the set of pairs of qubits (e.g., pairs of qubits 202-214) that are determined to have a higher ranking than other pairs of qubits in the set of pairs of qubits. With respect to a desired (e.g., custom or custom-designed) quantum computing circuit design for an algorithm (e.g., algorithm 200) or application, the design management component 106 can assign a direct connection to each of one or more pairs of qubits in the subset of pairs of qubits that are determined to have a higher ranking (e.g., a higher weighted score) than other pairs of qubits in the set of pairs of qubits. The design management component 106 can determine a number (e.g., 1, 2, 3, or more) of pairs of qubits in the subset of pairs of qubits based at least in part on defined circuit design standards that can be related to processes and / or design specifications. The circuit design standards can limit or dictate (e.g., dictate a defined threshold) a maximum number of direct connections. The direct connections can be assigned to pairs of qubits for a quantum computing circuit design of an algorithm (e.g., algorithm 200) or application.

[0054] Depending in part on the application or algorithm for which a quantum computing circuit is to be designed and / or defined circuit design standards, the number of pairs of qubits in the subset of pairs of qubits can be the maximum number of direct connections that can be assigned to pairs of qubits or can be less than the maximum number of direct connections that can be assigned to pairs of qubits. For example, if applicable defined circuit design standards related to applicable processes and / or design specifications indicate or dictate that a pair of qubits can have four direct connections in a desired quantum computing circuit design, the design management component 106 can identify and select the four highest ranked pairs of qubits in the set of pairs of qubits to the subset of pairs of qubits and can assign direct connections to the four highest ranked pairs of qubits that make up the subset of pairs of qubits. The design management component 106 can determine other connections (e.g., non-direct connections) for the remaining pairs of qubits that are not in the subset of pairs of qubits in a desired (e.g., custom or custom-designed) quantum computing circuit design for an application or algorithm (e.g., algorithm 200). For example, according to defined circuit design standards, based at least in part on characteristics and / or specifications of an application or algorithm (e.g., algorithm 200), the design management component 106 can determine single swap gate connections and / or two swap gate connections between qubits.

[0055] As another example, if the applicable circuit design standards indicate that a maximum number of pairs of qubits that can have direct connections in a desired quantum computing circuit design in connection with the applicable process and / or design specifications indicate or specify, the design management component 106 can determine that in the desired quantum computing circuit design, a direct connection can be allocated to each qubit in a set of pairs of qubits. In this case, in response to determining that the number of extracted pairs of qubits is less than or equal to the maximum number of pairs of qubits that can be allocated a direct connection in the quantum computing circuit design, the design management component 106 can bypass the partial analysis of pairs of qubits, can bypass the determination of the weighted score. Pairs of qubits, and / or can bypass the ranking of pairs of qubits (as a direct connection can be allocated to all extracted pairs of qubits).

[0056] In some cases, the design management component 106 can determine or create (e.g., generate) more than one desired (e.g., custom or tailored) quantum computing circuit design for a particular application or algorithm (e.g., algorithm 200) that is capable of meeting (e.g., matching or meeting or exceeding) the defined circuit design standards (e.g., initial or first level circuit design standards). In this case, the design management component 106 can analyze such desired quantum computing circuit designs. The design management component 106 can determine the quantum computing circuit design of those circuit designs that can be the most desired (e.g., most enhanced, effective or suitable) circuit. The design is made in accordance with the applicable defined circuit design standards based at least in part on the results of the analysis of such desired quantum computing circuit designs. The applicable defined circuit design standards can relate to, indicate and / or specify, for example, which of the plurality of quantum computing circuit designs is considered the most ideal quantum computing circuit design. For example, the design management component 106 can analyze such quantum computing circuit designs and can determine the total number of gate operations (e.g., the total number of single-qubit gate operations and / or two-qubit gate operations) of the quantum computing circuit designs. The desired quantum computing circuit design is based at least in part on the results of analyzing the desired quantum computing circuit designs. In some embodiments, the design management component 106 can determine the quantum computing circuit design of such desired quantum computing circuit designs that can have the lowest total number of gate operations (e.g., the lowest total number of single-qubit gate operations and / or two-qubit gate operations) as compared to other total numbers of gate operations of other quantum computing circuit designs of such quantum computing circuit designs. The design management component 106 can determine the quantum computing circuit design that is determined to have the lowest total number of gate operations as the most desired quantum computing circuit design employable with respect to the particular application or algorithm (e.g., algorithm 200). And can select the most ideal quantum computing circuit design to be employed with respect to the particular application or algorithm in accordance with the (e.g., applicable) defined circuit design standards.

[0057] It should be appreciated and understood that, according to various other embodiments, the applicable design circuitry criteria can involve determining and selecting a (most) desirable (e.g., custom or bespoke) quantum computing circuit design for an application. An "or" algorithm among multiple eligible quantum computing circuit designs for an application program or algorithm can specify or dictate different design circuitry criteria for determining and selecting a (most) ideal quantum computing circuit design as a supplement or alternative to the specified design circuitry criteria or as an indication to select a quantum computing circuit design with the least total number of gate operations as the (most) ideal (e.g., custom or bespoke) quantum computing circuit design for the application program or algorithm.

[0058] After the desired quantum computing circuit design is determined, the design management component 106 can construct a schematic of a quantum computing circuit layout for the desired quantum computing circuit design. For example, the design management component 106 can determine and construct a schematic of a desired (e.g., optimal, efficient, suitable, or acceptable) quantum computing circuit layout for the desired quantum computing circuit design, which can correspond to the characteristics of the qubits and pairs of qubits, connections between qubits (e.g., direct connections, single swap gate connections, or two swap gate connections). The design component 102 can represent this schematic as an output and / or can employ this schematic to facilitate fabricating a desired (e.g., custom or bespoke) quantum computing circuit for the application program or algorithm based at least in part on this schematic.

[0059] With respect to other aspects and embodiments of the disclosed subject matter, the design component 102 can employ certain other techniques to facilitate determining a desired (e.g., custom or bespoke) quantum computing circuit design (e.g., an algorithm- or application-specific quantum computing circuit design) for an algorithm or application program according to the defined circuit design criteria. With brief reference to Figure 3 (and Figure 1 ), Figure 3 An example algorithm-specific schematic generation 300 for a desired quantum computing circuit design for an example algorithm is shown according to various aspects and embodiments of the disclosed subject matter, and a corresponding schematic of the desired quantum computing circuit design is constructed. In the algorithm-specific schematic generation 300, there can be an algorithm 302 for which a desired (e.g., custom or bespoke) quantum computing circuit design and corresponding schematic can be desired.

[0060] The design management component 106 can analyze the algorithm 302. For example, the design management component 106 can analyze the features, functionality, and / or characteristics of the algorithm 302. Based at least in part on the results of the analysis of the features, functionality, and / or characteristics of the algorithm 302, the design management component 106 can determine a number of qubits of a set of qubits to be used in the algorithm 302 and can determine, according to the defined circuit design criteria, a connectivity of each of the individual qubits of the set of qubits to be used in the algorithm 302.

[0061] In some embodiments, based at least in part on the results of the analysis of the features, functionality, and / or characteristics of the algorithm 302, the design management component 106 can determine one or more qubits of the set of qubits that are the most connected qubits (e.g., the qubits that have the highest number or a relatively high number of connections to other qubits) compared to the connectivity of the other qubits of the set of qubits. For example, depending in part on the particular defined circuit design criteria that are applicable, the applicable circuit design criteria can indicate or specify that only the most connected qubits are to be considered, or the applicable circuit design criteria can indicate or specify that two of the most connected qubits are to be considered, or the applicable circuit design criteria can indicate or specify that three of the most connected qubits are to be considered, and so on. The design management component 106 can determine, based at least in part on the qubits of the set of qubits that are determined to be the most connected qubits, a configuration of the desired (e.g., custom or custom-designed) quantum computing circuit design for the algorithm 302. For example, the qubits that are determined to be the most connected qubits of the set of qubits. The design management component 106 can determine, based at least in part, a configuration of the desired (e.g., custom or custom-designed) quantum computing circuit design for the algorithm 302 to address the connectivity of the qubits that are determined to be the most connected qubits of the set of qubits.

[0062] In certain embodiments, the design management component 106 can determine or decide whether certain qubits, for example like ancilla qubits, are to be used or not in the algorithm 302 of the desired quantum computing circuit design for the required quantum computation based at least in part on the results of the analysis of the features, functionality, and / or characteristics of the algorithm 302. If it is determined that one or more ancilla qubits are to be used in such a design, the design management component 106 can determine whether the ancilla qubits are to be used in part or in whole in the desired quantum computing circuit design for the algorithm 302.

[0063] According to defined circuit design criteria, the design management component 106 can confirm, for the algorithm 302, a desired quantum computing circuit design based at least in part on the algorithm analysis results, a confirmation regarding the most connected qubit(s) in the set of qubits, a confirmation regarding ancilla qubits, and / or other factors or confirmations. The design management component 106 can also determine a schematic 304 of a quantum computing circuit layout of the desired quantum computing circuit design. For example, the design management component 106 can determine or produce one example schematic 304 that can include nine qubits (e.g., qubits 306, 308, 310, 312, 314, 316, 318, 320, and 322). The design management component 106 can determine and arrange the nine qubits according to the ideal quantum computing circuit design. Connections between the qubits (e.g., qubits 306-322), such as connection 324 between qubits 314 and 318, can also be determined and arranged.

[0064] It should be understood and appreciated that the example schematic 304 of a quantum computing circuit layout of a desired quantum computing circuit design is merely one example of a schematic that can be determined or produced. According to various embodiments, the design component 102 employing the design management component 106 can determine different algorithm-specific quantum computing circuit designs and related example schematics 304 for the same algorithm and / or can determine algorithm-specific quantum computing circuit designs for a particular (e.g., different) algorithm and related example schematics for other algorithms.

[0065] With respect to other aspects and embodiments of the disclosed subject matter, in developing a desired (e.g., custom or bespoke) quantum computing circuit design for an application or algorithm, the disclosed subject matter (e.g., employing the design component 102) can operate to increase the circuit depth of the quantum computing circuit. For example, there can be an example algorithm in which it can be desirable to entangle one qubit with as many other qubits as possible. However, there can be a constraint (e.g., a processing or design constraint) that no more than four qubits can be connected to one qubit. To facilitate increasing the circuit depth, the design component 102 can determine a quantum computing circuit design for the algorithm that can entangle with entanglement between one qubit and as many qubits as possible in as few steps as possible while adhering to the constraint as much as possible.

[0066] Briefly referring to Figure 4 (Along with Figure 1 ), Figure 4A diagram illustrating an example quantum computing circuit system 400 in accordance with various aspects and embodiments of the disclosed subject matter is shown. The example quantum computing circuit system 400 can include a conventional square quantum computing circuit design 402 for an example algorithm. The example quantum computing circuit 400 can also include an example custom quantum computing circuit design 404 (e.g., an algorithm or application-specific quantum computing circuit design) for the example algorithm, where the custom quantum computing circuit design 404 can be designed by the design component 102 using the techniques 102 described herein in accordance with defined circuit design criteria.

[0067] As can be observed in Figure 4 In accordance with the constraint that the conventional square quantum computing circuit design 402 can include various qubits, including qubit 406 that can be directly connected to the four qubits 408, 410, 412, and 414. Due to the square layout of the quantum computing circuit design 402, the four qubits 408, 410, 412, and 414 can each be connected to three other qubits, where, for example, qubit 408 can be connected to qubits 416, 418, and 420, qubit 410 can be connected to qubits 420, 422, and 424, qubit 412 can be connected to qubits 424, 426, and 428, and qubit 414 can be connected to qubits 428, 430, and 416. Thus, there can be four direct connections (e.g., to the central qubit, qubit 406), and eight connections (e.g., to the central qubit, qubit 406) for entanglement. Qubits with a single swap gate. It can be observed that certain qubits associated with a single swap gate (e.g., qubits 416, 420, 424, and 428) can be connected to multiple qubits (e.g., qubit 416 can be connected to qubits 408 and 414; qubit 420 can be connected to qubits 408 and 410; qubit 424 can be connected to qubits 410 and 412; and qubit 428 can be connected to qubits 412 and 414). It can also be observed that there can be 12 qubit pairs in the conventional square quantum computing circuit design 402 that can be entangled with the central qubit 406 after the application of two swap gates.

[0068] With respect to the example custom quantum computing circuit design 404 for the example algorithm, the design component 102 can design the custom quantum computing circuit design 404 to include various qubits, including qubit 440, which can also be referred to as the central qubit of this custom quantum computing circuit design 404. In some embodiments, the design component 102, employing the techniques described herein, can remove or not include some of the connections of the circuit (e.g., delete or not include unnecessary connections) to construct or configure the custom quantum computing circuit design 404 so that the custom quantum computing circuit design 404 can entangle more qubits with the central qubit 440 using a smaller number of gates than the conventional square quantum computing circuit design 402.

[0069] The design component 102 can connect the qubit 440 directly to four qubits 442, 444, 446, and 448 in accordance with the constraints. The design component 102 can connect these four qubits 442, 444, 446, and 448 to three other qubits each, where, for example, qubit 442 can be connected to qubits 450, 452, and 454, qubit 444 can be connected to qubits 456, 458, and 460, qubit 446 can be connected to qubits 462, 464, and 466, and qubit 448 can be connected to qubits 468, 470, and 472. Thus, there can be four direct connections (e.g., to the central qubit 440) and twelve connections (e.g., to the central qubit 440) to entangle qubit pairs with a single swap gate. As can also be observed, there can be up to thirty-six qubit pairs in the custom quantum computing circuit design 404 that can be entangled with the central qubit 440 after applying two swap gates.

[0070] Thus, as can be seen from the example custom quantum computing circuit design 404, in comparison to the conventional quantum computing circuit design 402, and more generally in accordance with the design component 102, a custom (e.g., algorithmic or application-specific) quantum computing circuit design can be determined or created for a particular algorithm or application, which, in comparison to a conventional quantum computing circuit design that can be determined for the algorithm or application, even though the custom quantum computing circuit design (e.g., 404) and the conventional quantum computing circuit design (e.g., 402) each have the same number of qubits connected to a central qubit, the custom quantum computing circuit design (e.g., 404) can have a greater number (e.g., twelve) of pairs of qubits that can be entangled with the central qubit by applying a single swap gate than the number (e.g., eight pairs) of qubit pairs that can be entangled with the central qubit by applying a single swap gate for the conventional quantum computing circuit design (e.g., 402); and the custom quantum computing circuit design (e.g., 404) can have a significantly higher number (e.g., thirty-six) of two swap gates that entangle pairs of qubits with the central qubit than the number (e.g., twelve) of two swap gates that entangle pairs of qubits with the central qubit in the conventional quantum computing circuit design (e.g., 402). The custom quantum computing circuit design (e.g., 404) can also reduce, remove, and / or not include undesired (e.g., unnecessary) connectivity in the circuit design in comparison to the conventional quantum computing circuit design (e.g., 402); and the custom quantum computing circuit design (e.g., 404) can have a significantly higher efficiency than the conventional quantum computing circuit design (e.g., 402) because the quantum computing circuit design that is custom to such a particular algorithm can use circuit area more efficiently (e.g., can reduce area usage due to removal or not including portions of undesired connectivity) and / or can achieve enhancements (e.g., improved, better) for performing one particular algorithm in comparison to aspects of the conventional quantum computing circuit design.

[0071] It should be appreciated that system 100 can provide various advantages in designing quantum computing circuits for an application or related algorithm as compared to conventional techniques, such as using a general-purpose quantum computing circuit design. For example, system 100 can extract, based at least in part on an analysis of an application or related algorithm, pairs of qubits that can be determined to satisfy a defined threshold point of having to use a direct connection between each other, and can determine, based at least in part on results of an analysis of characteristics associated with the pairs of qubits, a quantum computing circuit design to be used for the application or related algorithm, advantageously, can reduce a number of gates in a quantum computing circuit for one or more qubits used to run the application or related algorithm, reduce connectivity of a quantum circuit used to run the application or related algorithm, enhance use of area for the quantum computing circuit design (e.g., reduce area used), and enhance performance of the quantum circuit and the application or related algorithm when the application or related algorithm is run with the quantum circuit design as compared to running the application or related algorithm using a general-purpose quantum computing circuit design.

[0072] Figure 5 A block diagram illustrating an example design component 500 is shown in accordance with various aspects and embodiments of the disclosed subject matter. Design component 500 can include an extractor component 502 and a design management component 504, each of which can be the same or similar to various components (e.g., the components named respectively) and / or can include the same or similar functionality, as more fully described herein.

[0073] Design component 500 can include an operations manager component 506, which can control (e.g., manage) operations associated with design component 500. For example, operations manager component 506 can facilitate generating instructions for components of design component 500 to perform operations, and can communicate the instructions to the components of design component 500 (e.g., extractor component 502, design management component 504 (or components thereof), processor component 522, data store 524, etc.) to facilitate performance of operations by components of design component 500 based at least in part on the instructions, in accordance with defined circuit design criteria, defined circuit design algorithms (e.g., circuit design algorithms disclosed, defined, recited, embodied, or indicated by the methods, systems, and techniques described herein). Operations manager component 506 can also facilitate controlling data flow between components of design component 500 and controlling data flow between design component 500 and another or more other components or devices (e.g., computers, laptops, or other types) associated with (e.g., connected to) design component 500.

[0074] The design management component 504 can include, for example, an analyzer component 508, a qubit identifier component 510, a weight component 512, a classifier component 514, a connection assignment component 516, a design selector component 518, and a schematic generator component 520. The analyzer component 508 can be used to analyze information in order to determine a desired (e.g., custom or tailored) quantum computing circuit design for an algorithm or application. For example, the analyzer component 508 can analyze characteristics, functions, and / or features of an algorithm or application (e.g., an algorithm of an application).

[0075] Based at least in part on results of the analysis of the characteristics, functions, and / or features of the algorithm or application, the qubit identifier component 510 can identify or determine qubits or pairs of qubits to be used for the algorithm or application. In some embodiments, based at least in part on results of the analysis of the application or algorithm, the qubit identifier component 510 can identify or determine pairs of qubits (e.g., a set of pairs of qubits) of the algorithm or application that are determined to satisfy a defined threshold potential for direct connections between one another to be utilized in a quantum circuit design for the algorithm or application according to defined circuit design criteria.

[0076] The extractor component 502 can extract pairs of qubits from an algorithm or application. For example, the extractor component 502 can extract information related to pairs of bits from an algorithm or application. In some embodiments, the analyzer component 508 can analyze pairs of qubits to facilitate determining characteristics associated with the pairs of qubits. The qubit identifier component 510 can determine characteristics associated with the pairs of qubits based at least in part on results of such analysis of the pairs of qubits. Characteristics can include, for example, a number of pairs of qubits that influence downstream pairs of qubits, a number of pairs of qubits that are influenced by a pair of qubits, and a measure of influence of a pair of qubits through a two-qubit gate operation between the pair of qubits (or without a measurement on the pair of qubits).

[0077] The weight component 512 can determine and / or assign weights (e.g., weight values) to characteristics associated with the pairs of qubits. For example, the weight component 512 can determine and / or assign a first weight to a first characteristic associated with a pair of qubits, a second weight to a second characteristic associated with the pair of qubits, and / or a third weight to a third characteristic associated with the pair of qubits, and so on, according to defined circuit design criteria. In some embodiments, the weight component 512 can determine (e.g., calculate) a weighted score related to characteristics associated with a pair of qubits based at least in part on results of analyzing the characteristics and assigning weights to the characteristics.

[0078] The classifier component 514 can classify or rank pairs of qubits based at least in part on the features and the weights assigned to the features. For example, the classifier component 514 can classify or rank a pair of qubits based at least in part on the weighted score associated with the pair of qubits, where the classifier component 514 can determine the weighted score associated with the pair of qubits based at least on the features related to the pair of qubits and the weights assigned to the features.

[0079] The connection assignment component 516 can determine and / or assign connections to the qubits and / or pairs of qubits based at least in part on analyzing the qubits, the pairs of qubits (e.g., the features related to the pairs of qubits), classifying / ranking the pairs of qubits, and / or other features, functions, or characteristics of the algorithm or application according to defined circuit design criteria. The connections can include, for example, direct connections (e.g., direct connections between a particular pair of qubits) or indirect connections (e.g., single swap gates or double swap gates) between qubits. For example, according to applicable defined circuit design criteria (e.g., circuit design criteria related to process and / or design limitations of the quantum computing circuit), the connection assignment component 516 can determine / select a number of pairs of qubits with higher rankings based at least in part on the rankings of the pairs of qubits in the set of pairs of qubits and / or a defined number (e.g., a maximum number) of pairs of qubits to which direct connections can be assigned. The connection assignment component 516 can assign direct connections to the pairs of qubits with higher rankings to facilitate determining or generating a desired quantum computing circuit design for the algorithm or application. The connection assignment component 516 can also determine and / or assign connections (e.g., indirect connections) between other qubits (e.g., primary qubits and / or ancilla qubits) and / or pairs of qubits according to defined circuit design criteria in order to determine or generate a required quantum computing circuit design for the algorithm or application.

[0080] In some cases, the design management component 504 can target a defined circuit design criteria (e.g., an initial or first stage circuit design criteria). In some embodiments, the design selector component 518 can determine and / or select a desired (e.g., most desired) quantum computing circuit design of a plurality of desired quantum computing circuit designs that can be the most desired (e.g., most enhanced, effective, or suitable) quantum computing circuit design based, at least in part, on results of the plurality of analyses to determine the desired quantum computing circuit design according to the defined circuit design criteria (e.g., other (e.g., second order) applicable circuit design criteria related to determining which of the plurality of desired quantum computing circuit designs is the most desired quantum computing circuit design). In some embodiments, the design selector component 518 can analyze the plurality of desired (e.g., at least potentially desired) quantum computing circuit designs based, at least in part, on results of such analyses and can determine a total number of gate operations (e.g., a total number of single-qubit gate operations and / or two-qubit gate operations) of the desired quantum computing circuit design. The design selector component 518 can determine the desired quantum computing circuit design of the quantum computing circuit designs that has the lowest total number of gate operations (e.g., a total number of single-qubit gate operations and / or two-qubit gate operations) as compared to other total numbers of gate operations of the other desirable quantum computing circuit designs. The design selector component 518 can determine the quantum computing circuit design determined to have the lowest total number of gate operations as the most desired quantum computing circuit design to employ with respect to the algorithm or application according to the defined circuit design criteria (e.g., the applicable defined circuit design criteria), and can select such quantum computing circuit design as the most ideal quantum computing circuit design for the algorithm or application.

[0081] The schematic generator component 520 can be used to determine and / or establish an algorithm or application usage of a desired quantum computing circuit layout based, at least in part on (e.g., corresponding to) the desired (e.g., custom or tailored quantum computing circuit design (e.g., the most ideal quantum computing circuit design). For example, the schematic generator component 520 can determine and arrange qubits and / or qubit pairs relative to each other in the quantum computing circuit layout and can determine and arrange connections between qubits and / or qubit pairs in the quantum computing circuit layout according to the quantum computing circuit design required by the algorithm or application.

[0082] The processor component 522 can work with other components (e.g., the extractor component 502, the design management component 504, the operation manager component 506, and / or the data store 524,...) to facilitate performance of various functions of the design component 500. The processor component 522 can employ one or more processors, microprocessors, or controllers that can process data, such as information related to algorithms or applications, qubits or pairs of qubits, weights (e.g., weights to be assigned to characteristics associated with pairs of qubits), defined circuit design criteria, defined circuit design algorithms, traffic flows, policies, protocols, interfaces, tools, and / or other information to facilitate operation of the design component 500 (as more fully disclosed herein) and control data flow between the design component 500 and other components (e.g., computers, laptops, or other computing or communication devices) associated with (e.g., connected to) the design component 500.

[0083] The data store 524 can store data structures (e.g., user data, metadata), code structures (e.g., modules, objects, hashes, classes, procedures), or instructions, information related to algorithms or applications, qubits or pairs of qubits, weights (e.g., weights to be assigned to characteristics associated with pairs of qubits), defined circuit design criteria, defined circuit design algorithms, traffic flows, policies, protocols, interfaces, tools, and / or other information to facilitate control operation associated with the design component 500. In an aspect, the processor component 522 can be functionally coupled (e.g., by a memory bus) to the data store 524 to store and retrieve information desired to at least partially operate and / or impart functionality to the extractor component 502, the design management component 504, the operation manager component 506, and / or the data store 524, etc., and / or substantially any other operational aspect of the design component 500.

[0084] Systems and / or devices have been (or will be) described herein with respect to interactions between a number of components. It should be understood that such systems and components can include those components specified therein, some of the specified components, and / or other components. Subcomponents can also be implemented as components that are communicatively coupled to other components rather than being included within a parent component. Furthermore, one or more components and / or subcomponents can be combined into a single component that provides aggregate functionality. These components can also interact with one or more other components not specifically described herein but known to those skilled in the art.

[0085] Figure 6A flowchart illustrating an exemplary, non-limiting method 600 for determining an application- or algorithm-specific quantum computing circuit design (e.g., a superconducting quantum computing circuit design) for an application or algorithm is shown in accordance with aspects of the disclosed subject matter. The method 600 can be performed by, for example, a design component and / or a processor component. The design component can include an extractor component and a design management component. Repetitive description of like elements employed in other embodiments described herein can be omitted or can be omitted for the sake of brevity.

[0086] At 602, a pair of qubits determined to satisfy a defined threshold potential that must utilize a direct connection between one another can be extracted based at least in part on analyzing the application. The design management component can analyze the application (or an algorithm of the application or associated therewith). The design management component can identify, based at least in part on results of the analysis of the application (or the associated algorithm), pairs of qubits associated with the application (or the associated algorithm). Moreover, based at least in part on such results of the analysis, the design management component can determine, in accordance with defined circuit design criteria, pairs of qubits that satisfy a quantum threshold potential that must utilize a direct connection between one another (e.g., a direct connection between individual qubits within a pair of qubits) in a quantum computing circuit design (e.g., a custom or tailored quantum computing circuit design). The extractor component can extract the pairs of qubits to form a set of pairs of qubits.

[0087] At 604, a circuit design for a quantum circuit for the application can be determined based at least in part on analyzing characteristics of the pairs of qubits. The design management component can analyze characteristics of the pairs of qubits in the set of qubits associated with the application (or the associated algorithm). The design management component can determine, based at least in part on results of analyzing the characteristics of the pairs of qubits, a circuit design (e.g., a custom or tailored quantum computing circuit design) for a quantum circuit for the application (or the associated algorithm).

[0088] In accordance with various embodiments, to facilitate determining the circuit design, the design management component can assign weights (e.g., weight values) to characteristics associated with the pairs of qubits, determine weighted scores for the pairs of qubits, rank and order the pairs of qubits, select a subset of the pairs of qubits that can be assigned a direct connection, in accordance with defined circuit design criteria, as more fully described herein. If there are multiple quantum computing circuit designs that can satisfy such defined circuit design criteria, the design management component can determine which of the multiple quantum computing circuit designs is the most desirable quantum computing circuit design (e.g., select the most desirable quantum computing circuit design from multiple potential quantum computing circuit designs with respect to other circuit design criteria) in accordance with defined circuit design criteria, as more fully described herein.

[0089] Figure 7 A flow diagram of a non-exemplary method 700 is depicted in accordance with another example of various aspects and embodiments, the method discloses subject matter that can be used to determine quantum computing circuit designs (e.g., superconducting quantum computing circuit designs) that are specific to an application or algorithm. The method 700 can be performed by, for example, a design component and / or a processor component. The design component can include an extractor component and a design management component. Repetitive description of like elements employed in other embodiments described herein can be omitted or can be omitted for the sake of brevity.

[0090] At 702, an application or algorithm can be analyzed. The design management component can analyze the application or algorithm in order to determine or identify qubits and qubit pairs of the application or algorithm, determine or identify qubit pairs of the application or algorithm that satisfy a defined threshold potential that must utilize direct connections between one another (e.g., direct connections between qubits within a qubit pair), and / or determine characteristics of qubit pairs (or multiple qubits), etc.

[0091] At 704, qubit pairs of the application or algorithm that satisfy a defined threshold potential that must use direct connections between one another can be determined based at least in part on results of the analysis of the application or algorithm. The design management component can determine qubit pairs of the application or algorithm that satisfy a defined threshold potential that must utilize direct connections between one another based at least in part on results of the analysis of the application or algorithm.

[0092] At 706, qubit pairs can be extracted from the application or algorithm. The extractor component can extract qubit pairs from the application or algorithm. For example, the extractor component can extract information about qubit pairs from the application or algorithm.

[0093] At 708, characteristics associated with the qubit pairs can be analyzed. The design management component can analyze characteristics associated with the qubit pairs, for example, in order to identify characteristics associated with the qubit pairs and determine or identify differences between characteristics associated with the qubit pairs. The characteristics associated with the qubit pairs can include characteristics associated with the qubit pairs, for example, as more fully described herein.

[0094] At 710, weights can be assigned to features. The design management component can assign weights to features associated with pairs of qubits according to defined circuit design criteria. For example, according to certain applicable circuit design criteria, the design management component can assign a first weight (e.g., a first weight value) to a first feature associated with a pair of qubits that can be higher than a second weight that can be assigned to a second feature associated with the pair of qubits. A second feature associated with the pair of qubits that can be higher than a third weight that can be assigned to a third feature associated with the pair of qubits, and so on.

[0095] At 712, a weight score for a pair of qubits can be determined based at least in part on results of analyzing features associated with the pair of qubits and the weights. The design management component can determine (e.g., calculate) a weight score for a pair of qubits based at least in part on results of analyzing features associated with the pair of qubits and the weights assigned to the features.

[0096] At 714, the pairs of qubits can be ranked based at least in part on the weight scores for the pairs of qubits. The design management component can rank and / or order the pairs of qubits based at least in part on the weight scores for the pairs of qubits. For example, in response to the design management component determining that a first weight score for a first pair of qubits is higher than a second weight score for a second pair of qubits, the design management component can give the first pair of qubits in the pair of qubits a higher ranking and / or ordering than the second pair of qubits in the second pair of qubits.

[0097] At 716, a defined number of pairs of qubits with higher rankings can be selected for assignment of direct connections for the quantum computing circuit design according to the defined circuit design criteria. The defined circuit design criteria can specify or indicate a maximum number of pairs of qubits that can be directly connected in the quantum computing circuit design. The design management component can determine what the defined number of pairs of qubits with higher rankings is based at least in part on the maximum number of pairs of qubits that can be assigned direct connections in the quantum computing circuit design, where the defined number can be equal to or higher than the maximum number. The design management component can select the defined number of pairs of qubits with higher rankings in the pairs of qubits for assignment of direct connections in the quantum computing circuit design.

[0098] At 718, direct connections can be assigned to the higher ranked pairs of qubits that are part of the defined number of higher ranked pairs of qubits. The design management component can assign direct connections to the higher ranked pairs of qubits that are part of the defined number of higher ranked pairs of qubits.

[0099] At 720, a desired (e.g., custom or bespoke) quantum computing circuit design for an application or algorithm can be determined based at least in part on the allocation of direct connections of higher-ranked pairs of qubits in the desired quantum computing circuit design, according to defined circuit design criteria. The design management component can determine a desired (e.g., custom or bespoke) quantum computing circuit design for an application or algorithm based at least in part on the allocation of direct connections of higher-ranked pairs of qubits in the desired quantum computing circuit design. Based at least in part on such direct connection allocation, the design management component can determine other connections (e.g., connections other than direct connections) between qubits or pairs of qubits to complete the remaining connections (e.g., quantum circuit connections) to complete the configuration that constructs the desired quantum computing circuit design. As described more fully herein, if more than one quantum computing circuit design can satisfy the defined circuit design criteria, the design management component can determine which of the multiple quantum computing circuit designs is the most desirable quantum computing circuit design according to other circuit design criteria related to selecting the most desirable quantum computing circuit design from the multiple potential quantum computing circuit designs.

[0100] Figure 8 A flow diagram of an example non-limiting method 800 is presented that determines that an application or algorithm specific quantum computing circuit design of a plurality of application or algorithm specific quantum computing circuit designs for an application or algorithm of the plurality of application or algorithm specific quantum computing circuit designs is used for the application or algorithm, in accordance with various aspects and embodiments of the disclosed subject matter. The method 800 can be performed by, for example, a design component and / or a processor component. The design component can include an extractor component and a design management component. Repetitive description of like elements employed in other embodiments described herein can be omitted or can be omitted for the sake of brevity.

[0101] At 802, a quantum computing circuit design for an application or algorithm can be analyzed. In some cases, the design management component can determine, with respect to an application or algorithm, that multiple quantum computing circuit designs can satisfy defined circuit design criteria (e.g., initial or first stage circuit design criteria). The design management component can determine a quantum computing circuit design for an application or algorithm by employing various techniques described herein to determine a desired (e.g., custom or bespoke) quantum computing circuit design for the application or algorithm (e.g., application or algorithm specific). The design management component can analyze a quantum computing circuit design for the application or algorithm.

[0102] At 804, a total number of gate operations of the quantum computing circuit design can be determined based at least in part on the analysis results. The design management component can determine (e.g., compute) the total number of gate operations (e.g., the total number of single-qubit gate operations and / or two-qubit gate operations) of the quantum computing circuit design based at least in part on the results of the quantum computing circuit design analysis.

[0103] At 806, a quantum computing circuit design having a lowest total number of gate operations compared to other total numbers of gate operations of other quantum computing circuit designs can be determined. The design management component can determine the quantum computing circuit design having the lowest total number of gate operations (e.g., the lowest total number of single-qubit gate operations and / or two-qubit gate operations) compared to other total numbers of gate operations of other quantum computing circuit designs.

[0104] At 808, the quantum computing circuit design having the lowest total number of gate operations can be selected as the desired (e.g., custom or custom-made) quantum computing circuit design for the application or algorithm according to the defined circuit design criteria. In some embodiments, the defined design circuit criteria can specify or indicate that, among the quantum computing circuit designs, the quantum computing circuit design having the lowest total number of gate operations is to be selected as the (most) ideal (e.g., custom or custom-made) quantum computing circuit design for the application or algorithm. The design management component can select the quantum computing circuit design having the lowest total number of gate operations as the (most) ideal (e.g., custom or custom-made) quantum computing circuit design for the application or algorithm according to the defined circuit design criteria.

[0105] For simplicity of explanation, methods and / or computer-implemented methods are depicted and described as a series of acts. It is to be understood and appreciated that the disclosed subject matter is not limited by the acts illustrated and / or by the order of acts. For example acts can occur in various orders and / or concurrently, and with other acts not presented and described herein. Furthermore, not all illustrated acts can be required to implement the computer-implemented methods in accordance in the disclosed subject matter. In addition, those skilled in the art will understand and appreciate the contexts of the computer-implemented methods disclosed and described herein are susceptible to

[0106] In order to provide a context for the various aspects of the disclosed subject matter, Figure 9 and the following discussion are intended to provide a general description of a suitable environment in which various aspects of the disclosed subject matter can be implemented. Figure 9A block diagram showing one example of a non-limiting operating environment in which one or more embodiments described herein can be implemented. Repetitive description of like elements employed in other embodiments described herein can be omitted or can be omitted for the sake of brevity. Reference is made to Figure 9 A suitable operating environment 900 for implementing various aspects of this disclosure can also include the computer 912. The computer 912 can also include a processing unit 914, a system memory 916, and a system bus 918. The system bus 918 can couple the system components including, but not limited to, the system memory 916 to the processing unit 914. The processing unit 914 can be any of various available processors. Dual microprocessors and other multi-processor architectures can also be employed as the processing unit 914. The system bus 918 can be any of several types of bus structures including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of a variety of bus architectures including, but not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (IEEE 1394), and Small Computer Systems Interface (SCSI). The system memory 916 can also include volatile memory 920 and nonvolatile memory 922. The nonvolatile memory 922 can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or nonvolatile random-access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). The volatile memory 920 can also include random-access memory (RAM), which acts as external cache memory. By way of illustration, and not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), and Rambus dynamic RAM (RDRAM).

[0107] The computer 912 can also include removable / non-removable, volatile / non-volatile computer storage media. Figure 9A disk storage 924 is illustrated. A disk storage 924 can also include, without limitation, a floppy disk drive, a flexible disk drive, a hard disk drive, a magnetic tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a mem stick. A disk storage 924 can also include other storage media, including, without limitation, a magnetic or optical disc, such as a CD-ROM, a CD-RW, a DVD-ROM, a DVD-RAM, a DVD- RW, or a plurality of DVD-ROMs, DVD-RWs, or other optical and / or nonvolatile storage media. To facilitate connection of the disk storage 924 to the system bus 918, a removable or non-removable interface is typically used, such as interface 926. Figure 9 Software is also depicted as being used in a suitable operating environment 900. The software can also include, for example, an operating system 928. The operating system 928, which can be stored on the disk storage 924, acts to control and allocate resources of the computer system 912. System applications 930 take advantage of the management of the resources by the operating system 928 and utilize program modules 932 and program data 934, such as stored on system memory 916 or the disk storage 924. It is to be appreciated that this disclosure can be implemented with various operating systems or operating systems combinations. A user enters commands or information into the computer 912 through input device(s) 936. Input devices 936 include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to the processing unit 914 through the system bus 918 via interface port(s) 938. Interface port(s) 938 include, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). Output devices 940 use some of the same type of ports as input devices 936. Thus, for example, a USB port can be used to provide input to and output from computer 912, and can be used to input and output digital information between computer 912 and an output device 940. Output adapters 942 are provided to illustrate that there are some output devices 940 like monitors, speakers, and printers, among other output devices 940, which require special adapters. The output adapters 942 include, by way of illustration and not limitation, video and sound cards that provide a means of connection between the output device 940 and the system bus 918. It should be noted that other devices and / or systems of devices provide both input and output capabilities such as remote computer 944.

[0108] The computer 912 can operate in a networked environment using logical connections to one or more remote computers, such as a remote computer(s) 944. The remote computer(s) 944 can be a computer, a server, a router, a network PC, a workstation, a microprocessor based appliance, a peer device or other common network node, and typically can also include many or all of the elements described relative to the computer 912, although, for purposes of brevity, not each of the remote computer(s) 944 is shown. The logical connections depicted include wire / wireless connectivity to a network 956 that can be utilized by the remote computer(s) 944 to communicate with the computer 912 and / or other remote computer(s) 944. The network 956 is a wired and / or wireless network with other devices connected to it. Such networking environments are commonplace in enterprises, so the computer 912 might be coupled to a LAN, WAN, or other types of networks through a network interface 948. The network interface 948 encompasses wire / wireless communication technology to provide connectivity to each network. Wired media suitable for implementing wired / wireless varieties of the network 956 include wire / wireless technologies that are used for connecting devices to the Internet, such as digital subscriber line (DSL), cable modem, Tl, T2, T3, and T4, which are used in

[0109] The present disclosure can be embodied as a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure. The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire cable, as these do not carry program instructions for execution by a processor.

[0110] The computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to external computers or external storage devices via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device. Computer readable program instructions for carrying out operations of the present disclosure can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computing / processing device, partly on the user's computing / processing device, as a stand-alone software package, partly on the user's computing / processing device and partly on a remote computing / processing device or entirely on the remote computing / processing device or server. In the latter scenario, the remote computing / processing device can be connected to the user's computing / processing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to perform aspects of the present disclosure.

[0111] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored

[0112] The flow diagrams and block diagrams in the drawings are illustrative of possible architectures, functions, and operations for systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams or block diagrams can represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations of blocks in the block diagrams and / or flow diagrams, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

[0113] While the above has been described in the general context of computer-executable instructions of a computer program product that runs on one and / or more computers, those skilled in the art will recognize that the disclosure also can be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the computer-implemented methods disclosed herein can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, minicomputers, mainframe computers, as well as computers, hand-held computing devices (e.g., PDA, phone), microprocessor-based or programmable consumer or industrial electronics, and the like. The illustrated aspects can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. However, some, if not all, aspects of this disclosure can be practiced on stand-alone computers. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

[0114] As used herein, the terms “component,” “system,” “platform,” “interface,” and the like may refer to and / or include a computer-related entity or an operable machine having one or more specific functions. Entities disclosed herein may be hardware, a combination of hardware and software, software, or software being executed. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As an illustration, an application may run on both a server and a server as a component. One or more components may reside in an executing process and / or thread, and a component may reside on a single computer and / or be distributed across two or more computers. In another example, individual components may be executable from various computer-readable media on which various data structures are stored. These components can interact with other components via local communication and / or remote processes, for example, based on signals having one or more data packets (e.g., data from one component) and connections to other systems via signals in a local system, a distributed system, and / or through a network, such as the Internet. As another example, a component can be a device with a specific function provided by a mechanical part operated by electrical or electronic circuitry, which is operated by a software or firmware application executed by a processor. In this case, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application. As yet another example, a component can be a means of providing a specific function through an electronic component that does not have mechanical parts, wherein the electronic component can include a processor or other methods to execute software or firmware that at least partially endows the electronic component with function. In one aspect, a component can simulate an electronic component via a virtual machine component, for example, within a cloud computing system.

[0115] Furthermore, the term "or" is intended to indicate an inclusive "or" rather than an exclusive "or". That is, unless otherwise stated or clearly understood from the context, "X uses A or B" is intended to indicate any natural inclusive arrangement. That is, if X uses A; X uses B; or X uses both A and B, then the above condition "X uses A or B" is satisfied under any of the following conditions. Additionally, the articles "a" and "an" used in the subject matter description and figures should generally be interpreted as meaning "one or more" unless otherwise stated or clearly understood from the context to be in the singular form. As used herein, the terms "example" and / or "exemplary" are used to indicate that something is used as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to these examples. Furthermore, any aspect or design described herein as "exemplary" and / or "exemplary" is not necessarily to be construed as a preferred or advantageous alternative to other aspects or designs, nor does it exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0116] As employed in the subject specification, the term "processor" can refer generally to any computing processing unit or device comprising, but not limited to, single-core processors; single-processors with software multithread execution capability; multi- core processors; multi-core processors with software multithread execution capability; multi-core processors with hardware multithread technology; parallel platforms; and parallel platforms with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, processors can utilize nano- scale architectures such as, but not limited to, molecular and quantum-dot based transistors, switches and gates, in order to optimize space usage or enhance performance of user equipment. Processors can also be implemented as a combination of computing processing units. In the present disclosure, terms such as "memory," "storage device," "data storage," "data storage," "database," and substantially any other information storage component relevant to operation and functionality of a component are utilized to refer to "memory components" and entities embodied in a "memory," or component containing the memory. It is to be appreciated that memory and / or memory components described herein can be volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of illustration, and not limitation, nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory can include RAM, which can be used as external cache memory. By way of illustration, and not limitation, RAM is available in many forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), and Rambus dynamic RAM (RDRAM). Additionally, the memory components of a system or computer-implemented method disclosed herein are intended to comprise, without being limited to, these and any other suitable types of memory.

[0117] What has been described above includes examples of systems and computer-implemented methods. Of course, it is not possible to describe every conceivable combination of components or computer-implemented methods for purposes of describing the present application, but one of ordinary skill in the art can recognize that many further combinations and permutations of the present application are possible. Additionally, the description above is intended to cover any and all modifications and variations in the herein described embodiments, including the use of alternative and / or equivalent means for practicing the embodiments. Furthermore, the terms "comprise", "have", "with", and the like, when used in the description above, are used to specify the presence of stated features, integers, steps or components but do not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. The description of various embodiments of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the disclosure to the embodiments described. Numerous modifications and changes will be readily apparent to those skilled in the art, without departing from the scope of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application of the technology found in the market, or the technical improvements over the technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A computer system comprising: a memory storing computer executable components; and a processor operatively coupled to the memory, executing the computer executable components, the computer executable components comprising: an extractor component extracting pairs of qubits determined to satisfy a defined threshold potential that must use direct connections between one another based on an analysis of an application; and a design management component analyzing features related to the pairs of qubits, classifying the pairs of qubits based on the features related to the pairs of qubits and weight values associated with the features, and determining a circuit design for a quantum circuit of the application based on the feature analysis and classification related to the pairs of qubits.

2. The computer system of claim 1, wherein, the application is associated with a defined quantum algorithm from which the pairs of qubits are extracted.

3. The computer system of claim 1, wherein the features are selected from a set of features including a number of influence downstream qubits associated with a pair of qubits of the pairs of qubits, a number of two-qubit gate operations between the pair of qubits, a measurement affected by the pair of qubits, a measurement not determined to be affected by the pair of qubits.

4. The computer system of claim 1, wherein the design management component determines a subset of the pairs of qubits based on the classification, the subset having a higher ranking than other pairs of qubits of the pairs of qubits, and assigns direct connections to the pairs of qubits of the subset of the pairs of qubits based on a defined circuit design standard indicating a maximum number of pairs of qubits allowed to have direct connections.

5. The computer system of claim 1, wherein the design management component further determines that the circuit design satisfies a portion of defined circuit design standards based on the analysis of the features associated with the pairs of qubits.

6. The computer system of claim 5, wherein, the design management component determines a total number of single-qubit gate operations and two-qubit gate operations associated with the circuit design, and determines that the circuit design is to be used for the quantum circuit based on one confirmation that the circuit design has a minimum number of two-qubit gate operations relative to other total numbers of two-qubit gate operations of other circuit designs of the circuit design.

7. The computer system of claim 1, wherein, the design management component determines a number of qubits to be used for the application to satisfy defined circuit design standards related to defined algorithmic specifications associated with the application, determines connectivity of qubits to be used for the qubits, and includes the defined circuit design based on the connectivity of qubits to be used for qubits in accordance with defined circuit design standards determining the circuit design based on the connectivity of qubits to be used for qubits.

8. The computer system of claim 7, wherein, the design management component determines a subset of the qubits that satisfy a number of connections more than other qubits of the qubits.

9. The computer system of claim 7, wherein, the design management component determines one or more ancilla qubit features that ancilla qubits of the qubits are to have based on defined circuit design standards.

10. The computer system of claim 1, wherein, the design management component constructs a schematic of the circuit design.

11. A computer-implemented method comprising: extracting, by a system operatively coupled to a processor, pairs of qubits determined to meet a defined threshold potential that must use a direct connection between each other based on an analysis of an application; analyzing, by the system, features related to the pairs of qubits; classifying, by the system, the pairs of qubits based on the features related to the pairs of qubits and weight values associated with the features; and determining, by the system, a circuit design for a quantum circuit of the application based on the analysis and classification of the features of the pairs of qubits.

12. The computer-implemented method of claim 11, wherein the features are selected from a set of features including a number of influence downstream qubits associated with one of the pairs of qubits, a number of two-qubit gate operations between the one of the pairs of qubits, a measurement affected by the one of the pairs of qubits, no measurement affected by the one of the pairs of qubits.

13. The computer-implemented method of claim 11, further comprising: determining, by the system, a subset of the pairs of qubits based on the classification of the qubits, the subset having a higher ranking than other pairs of qubits of the pairs of qubits; and allocating a direct connection to pairs of qubits in the subset of the pairs of qubits, wherein a maximum number of pairs of qubits in the subset of the pairs of qubits is determined based on defined circuit design criteria that are able to be connected.

14. The computer-implemented method of claim 11, further comprising: determining, by the system, that the circuit design meets at least one defined circuit design criterion of defined circuit design criteria based on the analysis of the features associated with the pairs of qubits.

15. The computer-implemented method of claim 14, further comprising: determining, by the system, a total number of single-qubit gate operations and two-qubit gate operations associated with the circuit design; determining, by the system, that the circuit design of the circuit designs has a least number of two-qubit gate operations in the circuit design compared to other circuit designs of the circuit designs based on comparing the total number of two-qubit gate operations; and determining, by the system, that the circuit design is to be used for the quantum circuit based on determining that the circuit design has the least number of two-qubit gate operations. constructing, by the system, a schematic of the circuit design.

16. The computer-implemented method of claim 11, further comprising:

17. A computer program product that facilitates determining a circuit design for a quantum circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform: extracting pairs of qubits determined to meet a defined threshold potential that must use a direct connection between each other based on an analysis of an application; analyzing features related to the pairs of qubits; classifying the pairs of qubits based on the features related to the pairs of qubits and weight values associated with the features, and determining the circuit design for the quantum circuit of the application based on the analysis and classification of the features of the pairs of qubits. ​ 18. The computer program product of claim 17, wherein the features are selected from a group of features including a number of downstream qubits affected by a pair of qubits of the pair of qubits, a number of two-qubit gate operations between the pair of qubits, a measurement affected by the pair of qubits, no measurement determined to be affected by the pair of qubits.

19. A computer system comprising: a memory that stores computer executable components; and a processor, operatively coupled to the memory, that executes the computer executable components, the computer executable components comprising: an extractor component that extracts pairs of qubits determined to satisfy a defined threshold potential based on an analysis of an algorithm associated with an application to use direct connections between pairs of qubits to each other; and a design management component that analyzes features related to the pairs of qubits, classifies the pairs of qubits based on the features related to the pairs of qubits and weight values associated with the features, and determines a quantum computing circuit design for the algorithm based on the analysis and classification of the features related to the pairs of qubits.

20. The computer system of claim 19, wherein the design management component determines a subset of the pairs of qubits based on a ranking, the subset having a higher ranking than other pairs of qubits of the pairs of qubits, and assigns direct connections to the pairs of qubits of the subset of the pairs of qubits based on a defined circuit design standard indicating a maximum number of pairs of qubits allowed to have direct connections.

21. A computer program product that facilitates determining a quantum computing circuit design, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to: extract pairs of qubits determined to satisfy a defined threshold potential to use direct connections between pairs of qubits to each other based on an analysis of an algorithm associated with an application; analyze features related to the pairs of qubits; classify the pairs of qubits based on the features related to the pairs of qubits and weight values associated with the features; and determine the quantum computing circuit design for the algorithm based on the analysis and classification of the features related to the pairs of qubits.

22. The computer program product of claim 21, wherein the features are selected from a group of features including a number of downstream qubits affected by a pair of qubits of the pair of qubits, a number of two-qubit gate operations between the pair of qubits, a measurement affected by the pair of qubits, no measurement determined to be affected by the pair of qubits.

23. A method of engineering a physical layout of a quantum computing circuit using a circuit design of a quantum circuit generated by the system of any of claims 1-10 or 19-20, comprising: running the application on the quantum circuit with a reduced number of gates.

24. A method of engineering a physical layout of a quantum computing circuit using a circuit design of a quantum circuit generated by the computer-implemented method of any one of claims 11 to 16, comprising: running the application on the quantum circuit with a reduced number of gates.

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