Memory array and method for forming a memory array including memory cell strings

Abstract

The present application relates to a memory array and a method for forming a memory array including a string of memory cells. A memory array including a string of memory cells includes laterally spaced memory blocks, each of which includes a vertical stack, the vertical stack including alternating insulating layers and conductive layers. The operational channel material string of the memory cell extends through the insulating layer and the conductive layer. Intermediate material is laterally located between laterally adjacent memory blocks in the memory block and longitudinally along the laterally adjacent memory blocks. The intermediate material includes a first region and a second region that alternate longitudinally, each of the first region and the second region having a vertically elongated seam therein. The top of the vertically elongated seam is higher in the first region than in the second region. The top of the seam in the second region vertically coincides with the bottom of the uppermost portion of the conductive layer or is below the bottom of the uppermost portion of the conductive layer.

Description

Technical Field

[0001] Embodiments disclosed herein relate to memory arrays and methods for forming memory arrays including strings of memory cells. Background Art

[0002] A memory is an integrated circuit and is used in computer systems to store data. The memory may be fabricated in one or more arrays of individual memory cells. The memory cells may be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). The sense lines may interconnect the memory cells in a conductive manner along the columns of the array, and the access lines may interconnect the memory cells in a conductive manner along the rows of the array. Each memory cell may be uniquely addressable by a combination of the sense lines and the access lines.

[0003] Memory cells can be volatile, semi-volatile or non-volatile. Non-volatile memory cells can store data for a long period of time without power. Non-volatile memory is usually specified as a memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of several milliseconds or less. In any case, the memory cell is configured to retain or store storage content in at least two different selectable states. In a binary system, the state is considered to be "0" or "1". In other systems, at least some of the individual memory cells can be configured to store information of more than two bits or states.

[0004] Field effect transistors are electronic components that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconductive channel region between them. A conductive gate is adjacent to the channel region and is separated from the channel region by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory that is used extensively in modern computers and devices. For example, a modern personal computer may store the BIOS on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in the form of solid-state drives in place of conventional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and to provide the ability to remotely upgrade devices for enhanced features.

[0006] NAND can be the basic architecture of integrated flash memory. A NAND cell component includes at least one selection device coupled in series to a series combination of memory cells (wherein the series combination is generally referred to as a NAND string). The NAND architecture can be configured in a three-dimensional arrangement, including vertically stacked memory cells that individually include reversibly programmable vertical transistors. Control circuitry or other circuitry can be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures can also include vertically stacked memory cells that individually include transistors.

[0007] The memory array may be arranged in memory pages, memory blocks, and partial blocks (e.g., sub-blocks), and memory planes, such as shown and described in any of U.S. Patent Application Publications No. 2015 / 0228659, No. 2016 / 0267984, and No. 2017 / 0140833, which are hereby fully incorporated by reference herein, and aspects thereof may be used in some embodiments of the invention disclosed herein. The memory blocks may at least partially define the longitudinal profiles of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines may occur in a so-called "staircase structure" at the ends or edges of the array of vertically stacked memory cells. The staircase structure includes individual "steps" (alternatively referred to as "steps" or "stairs") that define contact areas for individual word lines, on which vertically extending conductive vias contact to provide electrical access to the word lines. Summary of the invention

[0008] In one aspect, the present application provides a memory array including a string of memory cells, comprising: laterally spaced memory blocks, each of which includes a vertical stack, the vertical stack including alternating insulating layers and conductive layers, and an operational channel material string of the memory cell extends through the insulating layers and the conductive layers; and an intermediate material, which is laterally located between laterally adjacent memory blocks in the memory blocks and longitudinally along the laterally adjacent memory blocks, the intermediate material including longitudinally alternating first and second regions, the first and second regions each having a vertically elongated seam therein, the top of the vertically elongated seam being higher in the first region than in the second region, the top of the seam in the second region vertically coinciding with the bottom of the uppermost portion of the conductive layer or being below the bottom of the uppermost portion of the conductive layer.

[0009] In another aspect, the present application provides a memory array comprising a string of memory cells, comprising: laterally spaced memory blocks, each of which comprises a vertical stack comprising alternating insulating layers and conductive layers, through which strings of operative channel materials of memory cells extend; and an intervening material laterally located between and longitudinally along laterally adjacent memory blocks in the memory blocks, the intervening material comprising a vertically elongated seam therein, the vertically elongated seam having a top that vertically coincides with or is below an uppermost portion of the insulating layer.

[0010] In another aspect, the present application provides a method for forming a memory array including a memory cell string, comprising: forming a stack including a first layer and a second layer that are vertically alternating; forming horizontally elongated trenches in the stack to form laterally spaced memory blocks; forming a sacrificial material in the trenches to completely fill the trenches; forming vertical recesses in the sacrificial material, the vertical recesses extending across the trenches, the trenches extending laterally between laterally adjacent memory blocks in the memory blocks and being longitudinally spaced apart along the laterally adjacent memory blocks, the vertical recesses Each has a bottom below the top of the uppermost portion of the second layer; forming a bridging material in the vertical recess to form a bridge extending across the groove, the groove being laterally between the laterally adjacent memory block areas and spaced apart longitudinally along the laterally adjacent memory block areas, the bridges each having a bottom below the top of the uppermost second layer, the bridges each having a planar top coplanar with the top of the uppermost second layer; and replacing the sacrificial material in the groove with an intermediate material directly below the bridge and longitudinally between the bridges.

[0011] In another aspect, the present application provides a method for forming a memory array including a memory cell string, comprising: forming a stack including a vertically alternating first layer and a second layer, the first layer including a first sacrificial material; forming horizontally elongated grooves in the stack to form laterally spaced memory blocks; forming a second sacrificial material in the grooves to completely fill the grooves; forming vertical recesses in the second sacrificial material, the vertical recesses extending across the grooves, the grooves extending laterally between laterally adjacent memory blocks in the memory blocks and spaced longitudinally along the laterally adjacent memory blocks, the vertical recesses each having a bottom below a top of an uppermost portion of the second layer; forming a bridge in the vertical recess material to form a bridge extending across the groove, the groove being laterally between the laterally adjacent memory blocks and spaced apart longitudinally along the laterally adjacent memory blocks, the bridges each having a bottom below the top of the uppermost second layer, and the bridges each having a planar top coplanar with the top of the uppermost second layer; selectively isotropically etching away the second sacrificial material relative to the bridge and the second layer; isotropically etching away the first sacrificial material in the first layer and replacing it with conductive material of individual conductive lines; and forming an intermediate material in the groove, the intermediate material being directly below the bridge between the laterally adjacent memory blocks and longitudinally between the bridges. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It passes through Figure 2 A diagrammatic cross-sectional view of a portion of a substrate under processing according to an embodiment of the present invention, taken along line 1 - 1 in FIG.

[0013] Figure 2 It passes through Figure 1 A diagrammatic cross-sectional view taken along line 2-2 in FIG.

[0014] Figure 3-31 is a process according to some embodiments of the present invention Figure 1 and 2 Diagrammatical representations of the structure or parts thereof in sequential cross-sectional and / or enlarged views.

[0015] Figure 32-38 Alternative example methodological and / or structural embodiments of the present invention are shown. DETAILED DESCRIPTION

[0016] Some aspects of the invention are directed to overcoming problems associated with so-called "block bow" (sideways tipping / tilting of a block stack relative to its longitudinal orientation during manufacture), but the invention is not limited thereto.

[0017] Embodiments of the present invention encompass methods for forming a memory array, such as an array of NAND or other memory cells with peripheral control circuitry beneath the array (e.g., CMOS-under-array). Embodiments of the present invention encompass so-called "gate-last" or "replacement-gate" processes, so-called "gate-first" processes, and other processes, whether existing or developed in the future, that are independent of when the transistor gates are formed. Embodiments of the present invention also encompass a memory array (e.g., a NAND architecture) that is independent of the method of manufacture. Reference may be made to what may be considered a "gate-last" or "replacement-gate" process. Figure 1-23 A first example method embodiment is described.

[0018] Figure 1 and 2 A construction 10 is shown having an array or array region 12 in which vertically extending strings of transistors and / or memory cells are to be formed. Construction 10 includes a base substrate 11 having any one or more of conductive / conductive / conductive, semiconductive / semiconductive / semiconductive, or insulating / insulator / insulating (i.e., electrically herein) materials. Various materials are formed vertically over base substrate 11. The materials may be Figure 1 and 2 1. The base substrate 11 may be provided with a plurality of subarrays or arrays of memory cells. For example, other partially fabricated or fully fabricated components of the integrated circuit may be provided somewhere above, around, or within the base substrate 11. Control circuitry and / or other peripheral circuitry for operating components within an array of vertically extending memory cell strings (e.g., array 12) may also be fabricated, and may or may not be completely or partially within an array or subarray. In addition, multiple subarrays may also be fabricated and operated independently, sequentially, or otherwise relative to one another. As used herein, a "subarray" may also be considered an array.

[0019] A conductor layer 16 including conductive material 17 is formed above substrate 11. Conductor layer 16 may include portions of control circuitry (e.g., peripheral under-array circuitry and / or common source lines or plates) for controlling read and write access to transistors and / or memory cells to be formed within array 12. A stack 18 including vertically alternating insulating layers 20 and conductive layers 22 is formed above conductor layer 16. An example thickness for each of layers 20 and 22 is 22 to 60 nanometers. Only a small number of layers 20 and 22 are shown, with stack 18 more likely to include tens, a hundred, or more (etc.) layers 20 and 22. Other circuitry that may or may not be part of peripheral and / or control circuitry may be between conductor layer 16 and stack 18. For example, multiple vertically alternating layers of conductive and insulating material of such circuitry may be below a lowermost conductive layer 22 and / or above an uppermost conductive layer 22. For example, one or more select gate layers (not shown) may be between conductor layer 16 and lowermost conductive layer 22, and one or more select gate layers may be above uppermost conductive layer 22. Regardless, conductive layer 22 (alternatively referred to as a first layer) may not include conductive material, and insulating layer 20 (alternatively referred to as a second layer) may not include insulating material or may be insulating when processed in conjunction with the "gate last" or "replacement gate" example method embodiments initially described herein. Example conductive layer 22 includes a first material 26 (e.g., silicon nitride) that may be fully or partially sacrificial. Example insulating layer 20 includes a second material 24 (e.g., silicon dioxide) that has a composition different from that of first material 26 and that may be fully or partially sacrificial. Uppermost insulating layer 20 may be considered to have a top surface 21.

[0020] A channel opening 25 is formed through the insulating layer 20 and the conductive layer 22 to the conductor layer 16 (e.g., by etching). In some embodiments, the channel opening 25 may partially enter the conductive material 17 of the conductor layer 16 as shown, or may stop at the top (not shown). Alternatively, as an example, the channel opening 25 may stop atop or inside the lowermost insulating layer 20. The reason for extending the channel opening 25 at least to the conductive material 17 of the conductor layer 16 is to ensure that the subsequently formed channel material (not shown) is directly electrically coupled to the conductor layer 16 when such connection is desired without using alternative processes and structures to achieve this. An etch stop material (not shown) may be within or atop the conductive material 17 of the conductor layer 16 to help stop etching of the channel opening 25 relative to the conductor layer 16 when such a connection is desired. Such an etch stop material may be sacrificial or non-sacrificial. By way of example and for simplicity only, channel openings 25 are shown arranged in groups or columns of staggered rows of four and five openings 25 per row, and arranged in laterally spaced memory block regions 58, which in a finished circuit system configuration will include laterally spaced memory blocks 58. In this document, a "block" generally includes a "sub-block". Memory block regions 58 and resulting memory blocks 58 (not yet shown) may be considered to be longitudinally elongated and oriented, for example, along direction 55. It is possible that memory block regions 58 are not discernible at this processing point. Any alternative existing or future developed arrangements and configurations may be used.

[0021] The transistor channel material may be formed vertically in individual channel openings along the insulating layer and the conductive layer, thus including individual channel material strings that are directly electrically coupled to the conductive material in the conductor layer. Individual memory cells of the formed example memory array may include a gate region (e.g., a control gate region) and a memory structure that is laterally located between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge transfer material. The storage material (e.g., a floating gate material, such as doped or undoped silicon, or a charge trapping material, such as silicon nitride, metal dots, etc.) of the individual memory cell is vertically along the individual charge blocking region. The insulating charge transfer material (e.g., a bandgap engineered structure having a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulator oxides (e.g., silicon dioxide) is laterally located between the channel material and the storage material.

[0022] Figure 3 , 3A, 4 and 4A show an embodiment in which charge blocking material 30, storage material 32 and charge transfer material 34 are formed vertically in individual channel openings 25 along insulating layer 20 and conductive layer 22. Transistor materials 30, 32 and 34 (e.g., memory cell materials) can be formed by, for example, depositing respective thin layers of the transistor materials over stack 18 and within individual channel openings 25 and then planarizing such transistor materials back to at least the top surface of stack 18. Channel material 36 is also formed vertically in channel openings 25 along insulating layer 20 and conductive layer 22, thus comprising individual operative channel material strings 53. Due to the proportions, materials 30, 32, 34 and 36 are formed vertically in individual channel openings 25. Figure 3 and 4 37. Example channel material 36 includes appropriately doped crystalline semiconductor materials, such as one or more of silicon, germanium, and so-called Group III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness of each of materials 30, 32, 34, and 36 is 25 to 100 angstroms. As shown, a stamp etch may be performed to remove materials 30, 32, and 34 from the base of the channel opening 25 to expose the conductor layer 16 so that the channel material 36 is directly against the conductive material 17 of the conductor layer 16. Such a stamp etch may occur individually with respect to each of the materials 30, 32, and 34 (as shown), or may occur collectively with respect to all materials after deposition of material 34 (not shown). Alternatively and by way of example only, a stamp etch may not be performed, and the channel material 36 may be directly electrically coupled to the conductive material 17 of the conductor layer 16 through a separate conductive interconnect (not shown). The channel opening 25 is shown to include a radially central solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively and by way of example only, the radially central portion within the channel opening 25 may include void space (not shown) and / or be free of solid material (not shown). A conductive plug (not shown) may be formed atop the channel material string 53 for better conductive connection to the upper circuitry (not shown).

[0023] refer to Figure 5 and 6 , horizontally elongated trenches 40 are formed in stack 18 (e.g., by anisotropic etching) to form laterally spaced apart memory block regions 58. Horizontally elongated trenches 40 may have respective bottoms directly against (e.g., on top or inside) conductive material 17 of conductive layer 16 (as shown), or may have respective bottoms above conductive material 17 of conductive layer 16 (not shown).

[0024] The above process shows that the channel opening 25 is formed and filled before the trench 40 is formed. This process can be reversed. Alternatively, the trench 40 can be formed between forming and filling the channel opening 25 (not ideal).

[0025] refer to Figure 7 and 8 , sacrificial material 31 is formed in trench 40 to completely fill trench 40. Example techniques for doing so include depositing sacrificial material 31 to overfill trench 40, followed by planarizing such sacrificial material back to at least top surface 21 of uppermost insulating layer 20. In some embodiments, such sacrificial material is referred to as second sacrificial material 31. In one embodiment and as shown, sacrificial material 31 is formed to have a top surface 19 that vertically coincides with top surface 21 of stack 18. In one embodiment and as shown, top surfaces 19 and 21 are individually flat and coplanar together. Example sacrificial materials include at least one of spin-on carbon, boron and / or phosphorus doped silicon dioxide, silicon nitride, aluminum oxide, and tungsten in elemental form. In one embodiment, conductive layer 22 includes first sacrificial material 26, and sacrificial material 31 includes second sacrificial material, in one embodiment, the sacrificial materials have different compositions relative to each other, and in another embodiment, have the same composition relative to each other.

[0026] refer to Figure 9-11 , a masking material 23 (e.g., photoresist) is formed atop stack 18 and is patterned as shown to provide longitudinally spaced mask openings 46 directly above sacrificial material 31 in trenches 40. Example patterned masking material 23 is shown as blanket covering over memory block region 58. Alternatively and by way of example only, masking material 23 may be patterned as Fig. 9 A series of horizontal lines (not shown) with grooves therebetween and having the same width as openings 46 in direction 55 .

[0027] refer to Figure 12-14 , a patterned masking material 23 (not shown) is used to form vertical recesses 41 in sacrificial material 31 and is then removed. Vertical recesses 41 extend across trenches 40 that are laterally between and longitudinally spaced apart along laterally adjacent memory blocks 58. Vertical recesses 41 each have a bottom 43 below top 21 of uppermost insulating layer 20. The use of patterned masking material 23 is an example method by which example vertical recesses 41 may be formed, and any alternative existing or future developed means may be used. As will become apparent in the continued discussion, vertical recesses 41 may be formed deeper into stack 18 than shown.

[0028] refer to Fig.15 and 16, bridging material 35 is formed in vertical recesses 41 and, in one example, overfills such recesses as shown and is on top 21 of memory block region 58. In one embodiment and as shown, bridging material 35 is directly against insulating material 24 of the uppermost insulating layer 20 of stack 18 and, in one such embodiment, is of the same composition as insulating material 24 (e.g., silicon dioxide). In another embodiment, bridging material 35 is of a different composition than all materials (e.g., 24, 26) of the vertically alternating insulating layers 20 and conductive layers 22 (whether or not directly against the top insulating layer 20 of stack 18), with one example material being carbon-doped silicon nitride. In embodiments where bridging material 35 remains in the finished construction of the integrated circuit, such bridging material is formed so that at least the material external thereto is insulating (whereby bridge 39 formed therefrom is in turn insulating).

[0029] refer to Figure 17-19 , the bridging material 35 is planarized (e.g., by polishing) back to at least the top 21 of the outermost insulating layer 20 to form a bridge 39 extending across the trench 40, which is laterally between and longitudinally spaced apart along the laterally adjacent memory block areas 58. The planarization back of the bridging material 35 can be performed to inherently stop on the sacrificial material 31, such as providing a hard stop in the case where the material 31 includes carbon. The example bridges 39 each have a bottom 44 below the top 21 of the uppermost insulating layer 20 and each have a planar top 45 coplanar with the old or new top 21 of the uppermost insulating layer 20. The space 42 is longitudinally between the bridges 39 and is occupied by the sacrificial material 31. In one embodiment, the bridges 39 are insulating, which include / encompass any combination of bridging materials at least its outermost insulating or partially insulating.

[0030] The sacrificial material 31 in the groove 40 is replaced by the intervening material directly below and longitudinally between the bridges 39. Figure 20-31 Describe an example of such a method. First refer to Figure 20-22 , for example, by isotropically etching away sacrificial material 31 (not shown) selectively relative to bridge 39 and insulating layer 20, and selectively relative to conductive layer 22 in one embodiment as shown. Practitioners can select appropriate etching chemistries to selectively etch one material relative to other materials. In one embodiment and as shown, in Figure 20-22 All remaining sacrificial material 31 is removed during the process.

[0031] refer to Figure 23-26And in one embodiment, material 26 (not shown) of conductive layer 22 is removed, for example, by isotropically etching away through spaces 42, ideally selectively relative to other exposed materials (e.g., using liquid or gaseous H3PO4 as the primary etchant, where material 26 is silicon nitride, and other materials include one or more oxides or polysilicon). In an example embodiment, material 26 (not shown) in conductive layer 22 is sacrificial and replaced by conductive material 48 and thereafter removed from spaces 42 and trenches 40, thus forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56.

[0032] A thin insulating liner (such as Al2O3 and not shown) may be formed prior to forming the conductive material 48. The approximate location of the transistor and / or memory cell 56 is Fig.26 Indicated by brackets in Fig.23 and 24 4 and 5. The conductive material 48 may be shown as having ends 50 ( 51 ) corresponding to the control gate regions 52 of the individual transistors and / or memory cells 56. The conductive material 48 may be shown as having ends 50 ( 52 ) corresponding to the control gate regions 52 of the individual transistors and / or memory cells 56. The conductive material 48 may be shown as having ends 50 ( 51 ) corresponding to the control gate regions 52 of the individual transistors and / or memory cells 56. The conductive material 48 may be shown as having ends 50 ( 51 ) corresponding to the control gate regions 52 of the individual transistors and / or memory cells 56. Fig.26 ). In the depicted embodiment, control gate region 52 includes individual portions of individual conductive lines 29. Materials 30, 32, and 34 may be viewed as a memory structure 65 laterally located between control gate region 52 and channel material 36. In one embodiment and as shown with respect to an example "gate last" process, conductive material 48 of conductive layer 22 is formed after forming bridge 39. Alternatively, for example with respect to a "gate first" process, conductive material of the conductive layer may be formed prior to forming upper bridge 39 and / or prior to forming trench 40 (not shown).

[0033] A charge blocking region (e.g., charge blocking material 30) is between the storage material 32 and each control gate region 52. The charge blocking member may have the following functions in a memory cell: in a programming mode, the charge blocking member may prevent charge carriers from flowing out of the storage material (e.g., floating gate material, charge trapping material, etc.) toward the control gate, and in an erase mode, the charge blocking member may prevent charge carriers from flowing from the control gate into the charge storage material. Thus, the charge blocking member may be used to block charge migration between the control gate region and the storage material of each memory cell. The example charge blocking region as shown includes an insulator material 30. By way of further example, the charge blocking region may include a lateral (e.g., radially) outer portion of the storage material (e.g., material 32) where such storage material is insulating (e.g., in the absence of any material of different composition between the insulating storage material 32 and the conductive material 48). Regardless, as an additional example, the interface of the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region in the absence of any single-composition insulator material 30. Furthermore, the interface of conductive material 48 and material 30 (if present) in conjunction with insulator material 30 may together act as a charge blocking region and alternatively or additionally may act as a lateral outer region of insulating storage material such as silicon nitride material 32. Example material 30 is one or more of hafnium oxide and silicon dioxide.

[0034] refer to Figure 27-31 And in one embodiment, the intervening material 57 is formed in the trench 40 directly below the bridge 39 between the laterally adjacent memory blocks 58 and longitudinally between the bridges 39. For clarity, Fig.30 In Figure 27-29 The ratio is three times the ratio of Fig.31 yes Fig.30 . Intermediate material 57 may provide lateral electrical isolation (insulation) between laterally adjacent memory block regions 58 and final memory blocks 58. This may include one or more of insulating, semiconducting, and conducting materials, and in any event, may facilitate shorting of conductive layers 22 relative to each other in the finished circuit system construction. Example insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. In one embodiment, intermediary material 57 includes a laterally outermost insulating material (e.g., silicon nitride and / or silicon dioxide and not shown) and a laterally inner material (e.g., undoped polysilicon and not shown) having a different composition than the laterally outermost insulating material. In one such embodiment, the laterally inner material is insulating. In one embodiment, intermediary material 57 is insulating everywhere between laterally adjacent memory blocks.

[0035] In one embodiment, the intervening material 57 includes a vertically elongated seam 61 therein. The intervening material 57 can be considered to include first and second regions 60, 64, respectively, that alternate longitudinally. In one embodiment and as shown, the vertically elongated seam 61 is higher longitudinally between the bridges 39 than directly below the bridges 39. Alternatively or additionally, and as shown, the vertically elongated seam 61 has a seam top 33 ( Fig.30 ), which is longitudinally higher between the bridges 39 than directly below the bridges 39. In one embodiment, the vertically elongated seam 61 includes at least one void space, and in one such embodiment and as shown ( Fig.31 ) includes a plurality of vertically spaced apart void spaces 63. For example, as shown, at least some of the plurality of void spaces 63 can each be vertically elongated. In another example embodiment, the vertically elongated seam 61a includes only one void space 63a (e.g., extending downward from the top of the intervening material 57 in the groove 40), such as with respect to Fig.32 10a in FIG. 10a. The same reference numerals of the embodiments described above are used where appropriate, with the suffix "a" indicating certain construction differences. Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0036] The bridge 39 may be thinner or thicker vertically than shown. For example, Fig.33 Shown with a ratio Fig.30 10b with thicker bridges 39b than shown in FIG. 10b. The same reference numerals as the embodiments described above are used where appropriate, with the suffix "b" indicating certain construction differences. In some embodiments, the top of the seam in the second region is vertically coincident with or lower than the bottom of the uppermost portion of the conductive layer. Fig.33 An example is shown in which seam top 33 in second region 64 vertically coincides with bottom 90 of uppermost conductive layer 22 . Fig.34 Shown is Fig.30 and 33 The same reference numerals as in the embodiments described above are used where appropriate, with the suffix "c" indicating certain construction differences. Fig.34 The top 33 of the seam in the second region 64 in the embodiment is lower than the bottom 90 of the uppermost conductive layer 22. Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used for reference Fig.33 and 34 The embodiments shown and described.

[0037] Figure 27-30, 33 and 34 show example embodiments in which the seam top 33 in the second zone 64 is in the uppermost half of the stack 18. Alternatively, such a seam top may be right at the interface between the uppermost and lowermost halves of the stack 18 or in the lowermost half of the stack. Fig.35 An example configuration 10d is shown with bridges 39d where the seam tops 33 in the second region 64 are in the lowermost half of the stack 18. Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0038] refer to Figure 36-38 An alternative example method and resulting construction 10f is shown and described. Like reference numerals from the above described embodiments are used where appropriate, with certain construction differences indicated by a suffix "f" or by a different reference numeral. Figure 36-38 An example embodiment is shown in which the intervening material between memory blocks / block regions is not uniform. Specifically, the example intervening material 57f is formed to include a laterally outer material 67 and a laterally inner material 68 having a composition different from that of the laterally outer material 67. The vertically elongated seams 61 are in the laterally inner material 68. By way of example only, the example laterally outer material 67 includes silicon dioxide, and the example laterally inner material 68 includes undoped polysilicon. Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0039] In one embodiment where the bridges 39 / 39b / 39c / 39d are insulating / insulating, at least some of the insulating material has the same composition as the intervening material 57 / 57f. In one embodiment where the bridges 39 / 39b / 39c / 39d are insulating / insulating, at least some of the insulating material has a different composition than the intervening material 57 / 57f, and in one embodiment, only some of the insulating material has a different composition than the intervening material 57 / 57f.

[0040] In some method embodiments, all of the bridges are removed sometime after replacing the sacrificial material in the trench with intervening material directly below and longitudinally between the bridges (not shown). Alternatively, at least some material of the bridges may remain extending across the trench in a finished configuration of the memory array, including, for example, reducing the vertical thickness of the bridges (not shown) sometime after the act of forming the bridge material, and, for example, whereby at least some material of the bridges remains extending across the trench in a finished configuration of the memory array.

[0041] Alternative embodiment configurations may result from the method embodiments described above or in other ways. Regardless, embodiments of the present invention encompass memory arrays that are independent of the method of manufacture. However, such memory arrays may have any of the properties described herein in the method embodiments. Likewise, the method embodiments described above may incorporate, form, and / or have any of the properties described with respect to the device embodiments.

[0042] Embodiments of the present invention include a memory array (e.g., 12) comprising strings (e.g., 49) of memory cells (e.g., 56). The memory array comprises laterally spaced memory blocks (e.g., 58), each of which comprises a vertical stack (e.g., 18) comprising alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). A string (e.g., 53) of operative channel materials of the memory cells extends through the insulating layers and the conductive layers. Intermediate materials (e.g., 57, 57f) are laterally located between and longitudinally along laterally adjacent memory blocks in the memory blocks. The intermediary materials comprise longitudinally alternating first and second regions (e.g., 60 and 64, respectively), each of which has a vertically elongated seam (e.g., 61, 61a) therein. The seam tops (e.g., 33) of the vertically elongated seams in the first regions are higher than the seam tops of the vertically elongated seams in the second regions. The top of the seam in the second region vertically coincides with or is below the bottom of the uppermost portion of the conductive layer (eg, 90).Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0043] Embodiments of the present invention include a memory array (e.g., 12) comprising strings (e.g., 49) of memory cells (e.g., 56). The memory array comprises laterally spaced memory blocks (e.g., 58), each of which comprises a vertical stack (e.g., 18) comprising alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). The operational channel material strings (e.g., 53) of the memory cells extend through the insulating layers and the conductive layers. Intermediate materials (e.g., 57, 57f) are laterally located between and longitudinally along the laterally adjacent memory blocks in the memory blocks. The intermediary materials include a vertically elongated seam (e.g., 61, 61a) therein, the vertically elongated seam having a seam top (e.g., 33) that is vertically coincident with the uppermost portion of the insulating layer (i.e., somewhere between and including the top and bottom of the uppermost insulating layer) or below the uppermost portion of the insulating layer. In one embodiment, the seam top is vertically coincident with the top of the uppermost insulating layer. In one embodiment, the top of the seam is below the uppermost insulating layer.Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0044] The above-described processing or construction may be considered to be associated with an array of components formed as a single stack or single stack of such components above or as part of an underlying base substrate or within the single stack or single stack (although the single stack / stack may have multiple layers). Control and / or other peripheral circuits for operating or accessing such components within the array may also be formed at any location as part of the final construction, and in some embodiments may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / stacks may be provided or manufactured above and / or below the stacks / stacks shown in the en route or described above. In addition, the arrays of components may be the same or different in different stacks / stacks relative to each other, and different stacks / stacks may have the same thickness or different thicknesses relative to each other. Intermediate structures may be provided between vertically adjacent stacks / stacks (e.g., additional circuits and / or dielectric layers). Also, different stacks / stacks may be electrically coupled relative to each other. Multiple stacks / stacks may be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / stacks may be manufactured substantially simultaneously.

[0045] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0046] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "top", "bottom", "above", "below", "below...", "under...", "upward" and "downward" generally refer to the vertical direction. "Horizontal" refers to the general direction along the surface of the main substrate (i.e., within 10 degrees) and can be relative to the substrate processed during manufacturing, and vertical is a direction generally orthogonal thereto. Reference to "just horizontal" refers to the direction along the surface of the main substrate (i.e., not forming a degree with the surface) and can be referenced to the substrate during manufacturing. In addition, "vertical" and "horizontal" as used herein are generally perpendicular directions relative to each other and have nothing to do with the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to a direction that deviates from the just horizontal by at least 45°. In addition, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending", etc., relative to a field effect transistor, are references to the orientation of the channel length of the transistor, and the current flows along the said orientation between the source / drain regions in operation. For bipolar junction transistors, "extending vertically", "extending vertically", "extending horizontally", "extending horizontally", etc. are reference to the orientation of the substrate length along which current flows between the emitter and the collector in operation. In some embodiments, any component, feature and / or region extending vertically extends vertically or within 10° of vertical.

[0047] In addition, "directly above," "directly below," and "directly below" require at least some lateral overlap (i.e., horizontally) of the two stated areas / materials / components relative to each other. Moreover, the use of "above" without a preceding "directly" requires only that some portion of the stated area / material / component that is above another stated area / material / component is vertically outward of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap of the two stated areas / materials / components). Similarly, the use of "below" and "beneath" without a preceding "directly" requires only that some portion of the stated area / material / component that is below / beneath another stated area / material / component is vertically inward of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap of the two stated areas / materials / components).

[0048] Any of the materials, regions, and structures described herein may be uniform or non-uniform, and in any case may be continuous or discontinuous over any material overlying it. When one or more example compositions are provided for any material, the material may comprise, consist essentially of, or consist of the one or more compositions. Furthermore, unless otherwise indicated, each material may be formed using any suitable existing or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0049] In addition, "thickness" (without a directional adjective in front) used alone is defined as the average straight-line distance perpendicularly passing through a given material or region from the closest surface of an adjacent material or adjacent region with different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a certain minimum thickness and a certain maximum thickness due to the variable thickness. As used herein, "different compositions" only require that those parts of the two stated materials or regions that can directly abut against each other are chemically and / or physically different, such as when such materials or regions are not uniform. If the two stated materials or regions are not directly against each other, then in the case of such materials or regions being not uniform, "different compositions" only require that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, when the stated materials, regions or structures are in at least some physical contact relative to each other, the material, region or structure "directly abuts" another material, region or structure. In contrast, "over," "on," "adjacent," "along," and "against" without being preceded by "directly" encompass "directly against" as well as configurations in which intervening materials, regions, or structures result in no physical touching contact of the stated materials, regions, or structures relative to one another.

[0050] As used herein, regions / materials / components are "electrically coupled" relative to one another if, in normal operation, electrical current is able to flow continuously from one region / material / component to another, and flows primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between and electrically coupled to the region-material-components. In contrast, when region-material-components are referred to as "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0051] "Rows" and "columns" are used in this document for convenience in distinguishing features of one series or orientation from features of another series or orientation, and components have been or may be formed along said "rows" and "columns". "Rows" and "columns" are used synonymously with respect to any series of regions, components and / or features, regardless of function. Regardless, rows can be straight and / or curved and / or parallel and / or non-parallel relative to each other, and columns can be the same. In addition, rows and columns can intersect at 90° or at one or more other angles relative to each other.

[0052] The composition of any one of the conductive / conductor / conductive materials herein can be a metallic material and / or a conductively doped semiconductive / semiconductive / semiconductive material. "Metallic material" is any one or combination of an elemental metal, a mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0053] As used herein, any use of "selective" with respect to etching, removing, depositing, forming, and / or shaping is such action performed on one stated material relative to another stated material being acted upon in a volume ratio of at least 2:1. Additionally, any use of selectively depositing, selectively growing, or selectively forming is deposition, growth, or forming of one material relative to another stated material or materials for at least the first 75 angstroms in a volume ratio of at least 2:1.

[0054] Unless otherwise indicated, the use of "or" herein includes either and both.

[0055] in conclusion

[0056] In some embodiments, a memory array including a string of memory cells includes laterally spaced memory blocks, each of which includes a vertical stack, the vertical stack including alternating insulating layers and conductive layers. The operational channel material string of the memory cell extends through the insulating layer and the conductive layer. The intermediate material is laterally located between the laterally adjacent memory blocks in the memory block and longitudinally along the laterally adjacent memory blocks. The intermediate material includes a first region and a second region that alternate longitudinally, each of the first region and the second region having a vertically elongated seam therein. The top of the vertically elongated seam is higher in the first region than in the second region. The top of the seam in the second region vertically coincides with the bottom of the uppermost portion of the conductive layer or is below the bottom of the uppermost portion of the conductive layer.

[0057] In some embodiments, a memory array including strings of memory cells includes laterally spaced memory blocks, each of which includes a vertical stack, the vertical stack including alternating insulating layers and conductive layers. The operational channel material strings of the memory cells extend through the insulating layers and the conductive layers. Intermediate materials are laterally between and longitudinally along the laterally adjacent memory blocks in the memory blocks. Intermediate materials are laterally between and longitudinally along the laterally adjacent memory blocks in the memory blocks. The intermediary materials include a vertically elongated seam therein, the vertically elongated seam having a top that vertically coincides with or is below the uppermost portion of the insulating layer.

[0058] In some embodiments, a method for forming a memory array including a memory cell string includes forming a stack including a first layer and a second layer that alternate vertically. A horizontally elongated groove is formed in the stack to form a memory block area that is spaced apart laterally. A sacrificial material is formed in the groove to completely fill the groove. A vertical recess is formed in the sacrificial material. The vertical recess extends across the groove, and the groove extends laterally between the memory blocks that are adjacent to each other in the memory block area and is spaced apart longitudinally along the memory blocks that are adjacent to each other in the memory block area. Each of the vertical recesses has a bottom below the top of the uppermost portion of the second layer. A bridging material is formed in the vertical recess to form a bridge extending across the groove, and the groove is laterally between the memory blocks that are adjacent to each other in the memory block area and is spaced apart longitudinally along the memory blocks that are adjacent to each other in the memory block area. Each of the bridges has a bottom below the top of the uppermost second layer. Each of the bridges has a planar top that is coplanar with the top of the uppermost second layer. The sacrificial material in the groove is replaced with intervening material directly beneath and longitudinally between the bridges.

[0059] In some embodiments, a method for forming a memory array including a memory cell string includes forming a stack including a vertically alternating first layer and a second layer. The first layer includes a first sacrificial material. A horizontally elongated groove is formed in the stack to form a laterally spaced memory block area. A second sacrificial material is formed in the groove to completely fill the groove. A vertical recess is formed in the second sacrificial material. The vertical recess extends across the groove, the groove extends laterally between the laterally adjacent memory blocks in the memory block area and is longitudinally spaced along the laterally adjacent memory blocks. The vertical recesses each have a bottom below the top of the uppermost portion of the second layer. A bridging material is formed in the vertical recess to form a bridge extending across the groove, the groove is laterally between the laterally adjacent memory blocks and is longitudinally spaced along the laterally adjacent memory blocks. The bridges each have a bottom below the top of the uppermost second layer. The bridges each have a planar top coplanar with the top of the uppermost second layer. The second sacrificial material is selectively isotropically etched away relative to the bridge and the second layer. The first sacrificial material in the first layer is isotropically etched away and replaced with conductive material of the individual conductive lines. Intermediate material is formed in the trench, the trench being directly below the bridge between the laterally adjacent memory block regions and longitudinally between the bridges.

[0060] As specified, the subject matter disclosed herein has been described in language more or less specific in terms of structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes example embodiments. Therefore, the claims have the full scope as written and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A memory array comprising a memory cell string, comprising: laterally spaced memory blocks each comprising a vertical stack of alternating insulating and conductive layers through which strings of operative channel material of memory cells extend; and An intermediate material is laterally located between the laterally adjacent memory blocks in the memory block and longitudinally along the laterally adjacent memory blocks, the intermediate material including first and second zones alternating longitudinally, the first and second zones each having a vertically elongated seam therein, the top of the vertically elongated seam being higher in the first zone than in the second zone, the top of the seam in the second zone vertically coinciding with the bottom of the uppermost portion of the conductive layer or being below the bottom of the uppermost portion of the conductive layer. 2 . The memory array of claim 1 , wherein a top of the seam in the second region vertically coincides with the bottom of the uppermost conductive layer. 3 . The memory array of claim 1 wherein a top of the seam in the second region is below the bottom of the uppermost conductive layer.

4. The memory array of claim 3 wherein the seam top in the second region is in an uppermost half of the stack.

5. The memory array of claim 3 wherein the seam top in the second region is in a lowermost half of the stack.

6. The memory array of claim 1 wherein the vertically elongated seams in the first region are taller than the vertically elongated seams in the second region.

7. The memory array of claim 1 wherein the vertically elongated seams in the first and second regions each include at least one void space.

8. The memory array of claim 7 wherein the vertically elongated seams in the first and second regions each comprise a plurality of vertically spaced apart void spaces.

9. The memory array of claim 7 wherein the vertically elongated seams in the first and second regions each include only one void space.

10. The memory array of claim 1 wherein the intervening material comprises a laterally outermost insulating material and a laterally inner material having a composition different from that of the laterally outermost insulating material, the vertically elongated seams in the first and second regions being in the laterally inner material.

11. The memory array of claim 10 wherein the lateral inner material is insulating.

12. The memory array of claim 1 wherein the intervening material is insulating throughout between the laterally adjacent memory blocks.

13. The memory array of claim 1 , comprising insulating bridges within the stack extending laterally between and longitudinally spaced apart from laterally adjacent ones of the memory blocks, the insulating bridges spaced apart above the seam tops in the second region, the insulating bridges each having a planar top coplanar with a planar top of an uppermost portion of the insulating layer.

14. The memory array of claim 13 wherein insulating material is beneath the insulating bridges, the insulating material of the insulating bridges having a composition different than a composition of the insulating material beneath the insulating bridges.

15. A memory array comprising a memory cell string, comprising: laterally spaced memory blocks each comprising a vertical stack of alternating insulating and conductive layers through which strings of operative channel material of memory cells extend; an intervening material laterally between and longitudinally along laterally adjacent ones of the memory blocks, the intervening material including a vertically elongated seam therein, the vertically elongated seam having a top that vertically coincides with or is below a top of an uppermost insulating layer; and Insulating bridges within the stack, the insulating bridges extending laterally between laterally adjacent memory blocks in the memory blocks and spaced longitudinally along the laterally adjacent memory blocks, the insulating bridges spaced above the top of the seam, the insulating bridges each having a planar top that is coplanar with the planar top of the uppermost portion of the insulating layer.

16. A method for forming a memory array comprising strings of memory cells, comprising: forming a stack comprising vertically alternating first and second layers; forming horizontally elongated trenches in the stack to form laterally spaced memory block regions; forming a sacrificial material in the trench to completely fill the trench; forming vertical recesses in the sacrificial material, the vertical recesses extending across the trench, the trench extending laterally between and longitudinally spaced apart along laterally adjacent ones of the memory blocks, the vertical recesses each having a bottom below a top of an uppermost portion of the second layer; forming a bridging material in the vertical recess to form bridges extending across the trenches, the trenches being laterally between and longitudinally spaced apart along the laterally adjacent memory blocks, the bridges each having a bottom below the top of the uppermost second layer, the bridges each having a planar top coplanar with the top of the uppermost second layer; and The sacrificial material in the groove is replaced with intervening material directly beneath and longitudinally between the bridges. The method of claim 16 , wherein the replacing removes all remaining portions of the sacrificial material.

18. The method of claim 16, wherein the bridge is insulating.

19. The method of claim 16, wherein the insulating material of the bridge has the same composition as the composition of the second layer.

20. The method of claim 16, wherein the bottom of the bridge is below the bottom of the uppermost second layer.

21. A method for forming a memory array comprising strings of memory cells, comprising: forming a stack comprising vertically alternating first and second layers, the first layers comprising a first sacrificial material; forming horizontally elongated trenches in the stack to form laterally spaced memory block regions; forming a second sacrificial material in the trench to completely fill the trench; forming vertical recesses in the second sacrificial material, the vertical recesses extending across the trench, the trench extending laterally between and longitudinally spaced apart along laterally adjacent ones of the memory blocks, the vertical recesses each having a bottom below a top of an uppermost portion of the second layer; forming a bridging material in the vertical recess to form bridges extending across the trenches, the trenches being laterally between and longitudinally spaced apart along the laterally adjacent memory blocks, the bridges each having a bottom below the top of the uppermost second layer, the bridges each having a planar top coplanar with the top of the uppermost second layer; selectively isotropically etching away the second sacrificial material relative to the bridge and the second layer; isotropically etching away the first sacrificial material in the first layer and replacing with conductive material of individual conductive lines; and An intervening material is formed in the trench directly beneath the bridges between the laterally adjacent memory block regions and longitudinally between the bridges.

22. The method of claim 21, wherein the first and second sacrificial materials have different compositions relative to each other.

23. The method of claim 21, wherein the first sacrificial material and the second sacrificial material have the same composition relative to each other.

24. The method of claim 21, wherein the isotropically etching away the second sacrificial material selectively with respect to the bridge and the second layer is also performed selectively with respect to the first layer.

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