Apparatus comprising a level shifter

Abstract

An apparatus, the apparatus comprising: a first voltage domain circuit comprising a first circuit component configured to provide a first digital output signal; a second voltage domain circuit comprising a second circuit component; a level shifter arrangement configured to receive the first digital output signal and to generate a second digital output signal at an elevated high state voltage level based on the first digital output signal and to provide the second digital output signal to the second circuit component; wherein the level shifter arrangement comprises at least one stage, the at least one stage comprising an arrangement of one or more diode-connected PMOS transistors coupled to a CMOS inverter arrangement, a CMOS inverter arrangement of a first stage of the at least one stage being configured to receive the first digital output signal and a CMOS inverter arrangement of a last stage of the at least one stage being configured to output the second digital output signal.

Description

Technical Field

[0001] This disclosure relates to an apparatus having circuit components that operate in different voltage domains. Specifically, this disclosure relates to an apparatus having a level shifter for receiving a digital signal from one voltage domain and shifting its voltage level to control a second voltage domain. Background Technology

[0002] The circuit layout may have one or more components operating in a first power supply voltage domain and one or more components operating in a second power supply voltage domain different from the first power supply voltage domain. Ensuring that digital signals can cross from the first power supply voltage domain to the second power supply voltage domain while ensuring that the components in the domain operate within the desired operating parameter range may be difficult. Summary of the Invention

[0003] According to a first aspect of this disclosure, an apparatus is provided, the apparatus comprising:

[0004] A first voltage domain circuit, the first voltage domain circuit including a first circuit component configured to provide a first digital output signal, wherein the first voltage domain circuit is configured to receive a first power supply voltage, and wherein the first digital output signal has a high state and a low state, and the voltage of the high state is based on the first power supply voltage.

[0005] A second voltage domain circuit, the second voltage domain circuit including a second circuit component, wherein the second voltage domain circuit is configured to receive a second power supply voltage greater than the first power supply voltage;

[0006] A level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal at an elevated voltage level based on the first digital output signal, wherein the level shifter arrangement is configured to provide the second digital output signal for input to the second circuit component;

[0007] The level shifter arrangement includes at least one stage, the at least one stage including an arrangement of one or more diode-connected PMOS transistors, the source terminal of at least one of the one or more diode-connected PMOS transistors being configured to be coupled to the second power supply voltage, and the drain terminal of at least one of the one or more diode-connected PMOS transistors being coupled to a CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference.

[0008] The CMOS inverter arrangement of the first stage in the at least one stage is configured to receive the first digital output signal, and the CMOS inverter arrangement of the last stage in the at least one stage is configured to output the second digital output signal.

[0009] In one or more examples, the one or more CMOS inverter arrangements of the level shifter include a PMOS transistor, wherein the first terminal includes a source terminal of the PMOS transistor, a drain terminal directly or indirectly connected to the drain terminal of an NMOS transistor, and wherein the source terminal of the NMOS transistor is used for direct or indirect coupling to a reference voltage, the CMOS inverter arrangement having an input including gate terminals of both PMOS and NMOS transistors and an output including a node between the drain terminals of the PMOS transistor and the drain terminals of the NMOS transistor.

[0010] In one or more examples, the CMOS inverter arrangement of the last stage in the at least one stage is configured to output the second digital output signal from a node between the PMOS transistor and the NMOS transistor of the CMOS inverter arrangement.

[0011] In one or more examples, the CMOS inverter arrangement at any stage preceding the last stage is configured to provide an output from a node between the PMOS transistors and NMOS transistors of the CMOS inverter arrangement.

[0012] In one or more embodiments, the level shifter arrangement includes at least two stages, the at least two stages including a first stage and a second stage;

[0013] The first stage includes a first arrangement of one or more diode-connected PMOS transistors, wherein the source terminal of at least one of the one or more diode-connected PMOS transistors is configured to be coupled to the second power supply voltage, and the drain terminal of at least one of the one or more diode-connected PMOS transistors is coupled to a first CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference; and

[0014] The second stage includes a second arrangement of one or more diode-connected PMOS transistors, wherein the source terminal of at least one of the one or more diode-connected PMOS transistors is configured to be coupled to the second power supply voltage, and the drain terminal of at least one of the one or more diode-connected PMOS transistors is coupled to a second CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal coupled to a voltage reference.

[0015] The first CMOS inverter arrangement is configured to receive the first digital output signal and provide a first intermediate digital output signal to the second CMOS inverter arrangement of the second stage, wherein the second CMOS inverter arrangement is configured to receive the intermediate digital output signal and provide a second digital output signal to the second circuit component; and

[0016] The first and second arrangements of the diode-connected PMOS transistor are configured such that the voltage drop provided by the first arrangement is greater than the voltage drop provided by the second arrangement.

[0017] In one or more examples, the level shifter arrangement includes at least one additional stage following the at least one stage, the at least one additional stage including a CMOS inverter arrangement without one or more diode-connected PMOS transistor arrangements, the CMOS inverter arrangement of the additional stage including a PMOS transistor having a source terminal for coupling to receive the second power supply voltage, a drain terminal directly or indirectly connected to a drain terminal of an NMOS transistor, and wherein the source terminal of the NMOS transistor is for direct or indirect coupling to the reference voltage, the CMOS inverter arrangement of the additional stage having an input including the gate terminals of the PMOS transistor and the NMOS transistor, and an output including a node between the drain terminals of the PMOS transistor and the drain terminals of the NMOS transistor.

[0018] In one or more examples, the first intermediate output signal is output from the node between the PMOS transistor and the NMOS transistor arranged in the CMOS inverter.

[0019] In one or more examples, there is an even number of stages. In one or more examples, each stage is configured, through the arrangement of one or more diode-connected PMOS transistors in each stage, to raise the trip voltage level of the CMOS inverter arrangement of the corresponding stage relative to the CMOS inverter arrangement of the preceding stage to the second supply voltage.

[0020] In one or more embodiments, the arrangement of one or more diode-connected PMOS transistors includes one of the following:

[0021] Multiple diode-connected PMOS transistors connected in series; and

[0022] A PMOS transistor with multiple diodes connected in parallel.

[0023] In one or more embodiments, the arrangement includes a plurality of diode-connected PMOS transistors connected in series, and wherein at least one or more of the diode-connected PMOS transistors have individual n-wells.

[0024] In one or more embodiments, the first arrangement includes a plurality of diode-connected PMOS transistors connected in series, and the second arrangement includes one or more diode-connected PMOS transistors connected in series, and the voltage drop difference is provided by a greater number of diode-connected PMOS transistors connected in series in the first arrangement than the number of diode-connected PMOS transistors connected in series in the second arrangement.

[0025] In one or more embodiments, the first arrangement includes one or more diode-connected PMOS transistors connected in parallel, and the second arrangement includes a plurality of diode-connected PMOS transistors connected in parallel, and the voltage drop difference is provided by a greater number of diode-connected PMOS transistors connected in parallel in the second arrangement than the number of diode-connected PMOS transistors connected in parallel in the first arrangement.

[0026] Generally, and in one or more examples, each arrangement of one or more diode-connected PMOS transistors in each stage includes a diode-connected PMOS transistor chain, wherein a first diode-connected PMOS transistor in the chain or a plurality of first parallel-connected diode-connected PMOS transistors in the chain has one or more source terminals for coupling to the second power supply voltage, and one or more drain terminals for coupling to zero, one or more subsequent diode-connected PMOS transistors in the chain or a plurality of subsequent parallel-connected diode-connected PMOS transistors in the chain, and then connected to one or more drain terminals of the first terminal of the CMOS inverter arrangement.

[0027] In one or more embodiments, the level shifter arrangement includes at least three stages, and the voltage drop of the diode-connected PMOS transistor arrangement in each of the at least three stages gradually and monotonically decreases from the first stage that receives the first digital output signal to the last of the at least three stages that provides the second digital output signal for the second circuit component.

[0028] In one or more embodiments, each of the diode-connected PMOS transistors in the first arrangement and the second arrangement has the same unit size.

[0029] In one or more embodiments, the level shifter arrangement includes:

[0030] A high trigger level first stage, the high trigger level first stage including an arrangement of one or more diode-connected PMOS transistors, the source terminal of at least one of the one or more diode-connected PMOS transistors being configured to be coupled to the second power supply voltage, and the drain terminal of at least one of the one or more diode-connected PMOS transistors being coupled to a high trigger level CMOS inverter arrangement, the high trigger level CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference;

[0031] The high-trigger-level CMOS inverter arrangement of the first stage of the high-trigger-level is configured to receive the first digital output signal and provide a high-trigger-level output signal;

[0032] A low trigger level first stage, the low trigger level first stage comprising an arrangement of one or more diode-connected PMOS transistors, wherein the source terminal of at least one of the one or more diode-connected PMOS transistors is configured to be coupled to the second power supply voltage, and the drain terminal of at least one of the one or more diode-connected PMOS transistors is coupled to a low trigger level CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference;

[0033] The low-trigger-level CMOS inverter arrangement of the first stage of the low-trigger-level is also configured to receive the first digital output signal and provide a low-trigger-level output signal;

[0034] Both the high-trigger-level CMOS inverter arrangement and the low-trigger-level CMOS inverter arrangement include a PMOS transistor, the PMOS transistor having a source terminal for direct or indirect coupling to a corresponding arrangement of one or more diode-connected PMOS transistors, and a drain terminal for direct or indirect connection to a drain terminal of an NMOS transistor, wherein the source terminal of the NMOS transistor is used for direct or indirect coupling to the reference voltage.

[0035] In the high-trigger-level CMOS inverter arrangement, the aspect ratio of the PMOS transistor is greater than that of the NMOS transistor, and in the low-trigger-level CMOS inverter arrangement, the aspect ratio of the NMOS transistor is greater than that of the PMOS transistor.

[0036] A latch, configured to receive the high-trigger level output signal and the low-trigger level output signal, and to combine the high-trigger level output signal and the low-trigger level output signal to generate a combined digital signal; and

[0037] The final stage includes a CMOS logic inverter configured to receive the combined digital signal and output the second digital signal.

[0038] In one or more embodiments, the first stage includes a switch configured to short-circuit one of the diode-connected PMOS transistors in the first arrangement, the switch being controlled by the output of the second stage.

[0039] In one or more embodiments, the switch includes a transistor, the source and drain terminals of which are coupled to short-circuit one of the diode-connected PMOS transistors in the first arrangement, and the gate terminal of the transistor is coupled to the second CMOS inverter arrangement to receive the second digital output signal.

[0040] In one or more embodiments, the first CMOS inverter arrangement includes a PMOS transistor connected in series with an NMOS transistor, and wherein the PMOS transistor of the first CMOS inverter arrangement has a connection between its source terminal and its back gate terminal.

[0041] In one or more embodiments, the level shifter arrangement includes an NMOS transistor for high-voltage protection, the NMOS transistor having a drain terminal for receiving the first digital output signal and a source terminal for providing the first digital output signal to the CMOS inverter arrangement of the first stage of the at least one stage, wherein the gate of the NMOS transistor for high-voltage protection is coupled to receive the second power supply voltage.

[0042] In one or more embodiments, the NMOS transistor for high-voltage protection includes a double-diffused metal-oxide-semiconductor (DMOS) transistor.

[0043] According to a second aspect of this disclosure, a wireless communication device is provided, the wireless communication device including the device described above. The wireless communication device may include a portion of a communication device, such as a mobile phone or a base station.

[0044] While this disclosure allows for various modifications and alternatives, their particularities have been illustrated by way of example in the drawings and will be described in detail. However, it should be understood that other embodiments beyond the specific embodiments described are also possible. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of this disclosure are also covered.

[0045] The foregoing discussion is not intended to represent every example embodiment or implementation within the scope of the present or future disclosure. Various example embodiments are illustrated in the figures and the following detailed description. A more comprehensive understanding of these various example embodiments can be gained by considering the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0046] One or more embodiments will now be described with reference to the accompanying drawings, by way of example only, in which:

[0047] Figure 1 An example embodiment is shown, illustrating a first voltage domain circuit and a second voltage domain circuit, and a first digital output signal to be transmitted therebetween.

[0048] Figure 2 A first example embodiment illustrating the use of a first example arrangement of diode-connected PMOS transistors to receive a first digital output signal is shown;

[0049] Figure 3 A second example embodiment illustrating the use of a second example arrangement of diode-connected PMOS transistors to receive a first digital output signal is shown;

[0050] Figure 4 Showing based on Figure 2 and Figure 3 A third example embodiment of any of the arrangements has an additional stage for implementing hysteresis;

[0051] Figure 5 Showing based on Figure 2 and Figure 3 A fourth example embodiment of any of the arrangements has an alternative arrangement for implementing hysteresis in the absence of a separate level;

[0052] Figure 6 A fifth example embodiment illustrating the addition of high-voltage protection that can be applied in any other embodiment is shown;

[0053] Figure 7 A sixth example embodiment illustrating the increased high-voltage protection that can be applied in any other embodiment is shown; and

[0054] Figure 8 The apparatus shown is a device included in any of the preceding embodiments, such as a wireless communication device. Detailed Implementation

[0055] In some electronic devices, digital signaling must traverse from a first power domain to a second power domain. Therefore, digital signaling generated by a first circuit component powered by the first power domain needs to be effectively received by a second digital circuit component powered by the second power domain. It may also be important that the voltage level of the digital signaling does not cause undesirable characteristics of the second circuit component. In other words, it may be desirable that the voltage level of the digital signaling complements the logic high and / or logic low trigger levels of the digital logic of the second circuit component.

[0056] Figure 1 A device 100 is illustrated, including a first voltage domain circuit 101, which includes a first circuit component 102 configured to provide a first digital output signal at an output terminal 103. The first voltage domain circuit 101 includes: a voltage supply terminal 104 for receiving a first power supply voltage from a power supply line 105; and a voltage reference terminal 106 for coupling to a reference voltage, such as ground, on a line 107. The first circuit component 102 includes a digital logic component, shown in this example as a logic inverter. It should be understood that the first circuit component 102 may include any single digital logic component or an arrangement of multiple digital logic components (e.g., AND, OR, NOT, NOR, etc., or combinations thereof). In one or more examples, the first circuit component 102 includes a CMOS-based digital logic component. It should be understood that the first digital output signal provided at the output terminal 103 has a high state and a low state, and the voltage of the high state is based on (e.g., substantially equal to) the first power supply voltage. Therefore, although the first circuit component 102 can be configured to generate logic high and logic low signals using the first power supply voltage, losses and voltage drops may occur across the logic. Consequently, the first digital output signal has logic high and logic low states, the voltages of which depend on the first power supply voltage of the first power domain circuit 101.

[0057] Figure 1A second voltage domain circuit 108, including a second circuit component 109, is also shown. The second voltage domain circuit 108 includes: a voltage supply terminal 110 for receiving a second power supply voltage from a power supply line 111; and a voltage reference terminal 112 for coupling to a reference voltage, such as ground, on line 107. The second circuit component 109 includes digital logic components, which are shown in this example as logic inverters. In one or more examples, the second circuit component 109 includes CMOS-based digital logic components. It should be understood that the second circuit component 109 may include any single digital logic component or arrangement of multiple digital logic components (e.g., AND, OR, NOT, NOR, etc., or combinations thereof). The second voltage domain circuit 108 includes an input terminal 113 for receiving a first digital output signal. The second circuit component 109 can be configured to operate based on a logic high or logic low received at input terminal 113. The second power supply voltage configured to power the digital logic of the second circuit component 109 is greater than the first power supply voltage powering the digital logic of the first circuit component 102. Therefore, there may be a difference between the voltage range considered logic high in the first voltage domain circuit 101 and the voltage range considered logic high in the second voltage domain circuit 108. In one or more examples, an undesirable result of this difference may be the appearance of cross currents from the second voltage supply to ground through the digital logic of the second circuit component 109, as indicated by arrow 114.

[0058] Generally, the second circuit assembly 109 includes an arrangement of one or more transistors configured to form a digital logic circuit, such as the aforementioned logic inverter. The logic inverter may include a PMOS transistor having a source terminal for direct or indirect coupling to a second power supply voltage, a drain terminal for direct or indirect connection to the drain terminal of an NMOS transistor, and wherein the source terminal of the NMOS transistor is for direct or indirect coupling to a reference voltage. The first circuit assembly is configured to provide a first digital output signal to the gate terminals of both the PMOS and NMOS transistors, and the output signal of the second circuit assembly is provided from a node between the drain terminals of the PMOS and NMOS transistors.

[0059] Generally, the first circuit assembly 102 includes an arrangement of one or more transistors configured to form a digital logic circuit, such as the aforementioned logic inverter. The logic inverter may include a PMOS transistor having a source terminal for direct or indirect coupling to a first power supply voltage, a drain terminal for direct or indirect connection to the drain terminal of an NMOS transistor, and wherein the source terminal of the NMOS transistor is for direct or indirect coupling to a reference voltage, wherein the first circuit assembly is configured to provide a first digital output signal from a node between the drain terminals of the PMOS transistor and the NMOS transistor.

[0060] Figure 2 A second voltage domain circuit 108 is shown in more detail, including a first example embodiment in which the second voltage domain circuit 108 includes a level shifter arrangement 200. The level shifter arrangement 200 is configured to receive a first digital output signal at input 113 and to provide or generate a second digital output signal at output 201 for reception by a second circuit component 109. The second circuit component 109 is shown as a CMOS inverter arrangement. The second digital output signal can be considered a modified version of the first digital output signal.

[0061] Regarding the data content of the regenerated logic high and logic low signals, the second digital output signal is based on the first digital output signal, but the voltage levels representing logic high and logic low in the second digital output signal may be different. Specifically, the second digital output signal may have an elevated (e.g., average) voltage level for high states compared to the high state (e.g., average) voltage level in the first digital output signal.

[0062] Therefore, the level shifter arrangement 200 can be configured to provide the second digital output signal for input to the second circuit component 109, and in one or more instances, the occurrence of cross current 114 can be overcome or reduced.

[0063] The level shifter arrangement 200 includes at least one stage. (Example) Figure 2The diagram illustrates three stages 201, 202, and 203. In this example, the first stage of one or more stages 201, 202, and 203, including the first stage 201, is configured to receive a first digital output signal from input 113. This first digital output signal is then sequentially passed from stage 201 to stage 202, where the first digital output signal in the first stage 201 can be referred to as the first intermediate digital output signal; then from the second stage to the third stage 203, where the first digital output signal in the second stage can be referred to as the second intermediate digital output signal; and finally, a second digital output signal is output from the last stage of one or more stages 201, 202, and 203, including the third stage 203 in this example. It should be understood that in examples where the level shifter arrangement 200 comprises a single stage, the first stage and the last stage comprise the same single stage.

[0064] Generally, the similarity in the structure included in each of stages 201, 202, and 203 lies in that the stage includes one or more diode-connected PMOS transistor arrangements 204, 205, and 206 series-coupled between voltage supply terminal 110 and voltage reference terminal 112, and CMOS inverter arrangements 207, 208, and 209. Thus, in one or more examples, the source terminal 210 of one of the one or more diode-connected PMOS transistors 220, 240, or 260, referred to as the first diode-connected PMOS transistor, is coupled to receive a second supply voltage from power line 111. In one or more examples, the drain terminal 211 of one of the one or more diode-connected PMOS transistors 224, 242, or 260, referred to as the last diode-connected PMOS transistor, is coupled to the corresponding CMOS inverter arrangement 207, 208, or 209. Therefore, the CMOS inverter arrangements 207, 208, 209 have a first terminal 212 coupled to the drain terminal 211 and a second terminal 213 coupled to the voltage reference terminal 112 to receive a reference voltage.

[0065] In one or more examples, it is the CMOS inverter arrangement 207 of the first stage 201 that receives the first digital output signal from the input terminal 113. Then, the first digital output signal is passed between the CMOS inverter arrangements 207, 208, and 209 of each stage to the last CMOS inverter arrangement 209 of the third stage 203, thereby outputting the second digital output signal.

[0066] In one or more examples, each stage 201, 202, 203 of the level shifter 200 includes CMOS inverter arrangements 207, 208, 209 comprising a PMOS transistor 214, 215, or 216 and an NMOS transistor 217, 218, or 219 coupled through their respective drain terminals. A first terminal 212 includes the source terminal of the PMOS transistor 214, 215, or 216, and a second terminal 213 includes the source terminal of the NMOS transistor 217, 218, or 219.

[0067] CMOS inverter arrangements 207, 208, and 209 each have inputs 225, 245, and 265 for receiving a first digital signal from input 113 or the preceding stages 201, 202, and 203. Inputs 225, 245, and 265 are separately coupled to the gates of the respective PMOS transistors 214, 215, or 216 and NMOS transistors 217, 218, or 219 of the CMOS inverter arrangement. CMOS inverter arrangements 207, 208, and 209 have outputs 226, 246, and 266, which comprise nodes between the drain terminals of the respective PMOS transistors 214, 215, or 216 and the drain terminals of the respective NMOS transistors 217, 218, or 219.

[0068] Therefore, generally, the CMOS inverter arrangement 207 includes PMOS and NMOS transistors with drain terminals connected, and a first stage 201 of at least one stage is configured to receive a first digital output signal at the gate terminals of the PMOS and NMOS transistors. The CMOS inverter arrangement 209 of the last stage 203 of at least one stage is configured to output the second digital output signal from an output 266, said output 266 comprising a node between the PMOS 216 and NMOS transistor 219 of the CMOS inverter arrangement.

[0069] Referring now to arrangements 204, 205, 206 of one or more diode-connected PMOS transistors, as those skilled in the art will understand, the diode-connected PMOS transistors include p-channel MOSFETs having a connection between their gate and drain terminals. Generally, arrangements 204, 205, 206 each comprise a chain of diode-connected PMOS transistors, wherein a first diode-connected PMOS transistor in the chain has a source terminal for coupling to a second power supply voltage, and a drain terminal for coupling to zero, one or more subsequent diode-connected PMOS transistors in the chain, and then to the first terminal 212 of the corresponding CMOS inverter arrangement. It should be understood that in other examples, arrangements 204, 205, 206 may have additional connections, for example, from a second power supply 111, and / or may have other components coupled to said arrangements.

[0070] The first arrangement 204 of diode-connected PMOS transistors includes three diode-connected PMOS transistors 220, 222, and 224 connected in series. The second arrangement 205 of diode-connected PMOS transistors includes two diode-connected PMOS transistors 240 and 242 connected in series. The third arrangement 206 of diode-connected PMOS transistors includes one diode-connected PMOS transistor 260.

[0071] In one or more examples, the first arrangement 204 and the second arrangement 205 of the diode-connected PMOS transistor are configured such that the voltage drop provided by the first arrangement 204 is greater than the voltage drop provided by the second arrangement 205. Similarly, the second arrangement 205 and the third arrangement 206 of the diode-connected PMOS transistor can be configured such that the voltage drop provided by the second arrangement 205 is greater than the voltage drop provided by the third arrangement 206.

[0072] In this example, the voltage drop difference is provided by a greater number of diode-connected PMOS transistors 220, 222, 224 (three) connected in series in the first arrangement 204 than the number of diode-connected PMOS transistors 240, 242 (two) connected in series in the second arrangement 205. Similarly, the voltage drop difference is provided by a greater number of diode-connected PMOS transistors 240, 242 (two) connected in series in the second arrangement 205 than the number of diode-connected PMOS transistors 260 (one) connected in series in the third arrangement 206.

[0073] By using diode-connected PMOS transistor arrangements 204, 205, 206 on top of the respective CMOS inverter arrangements 207, 208, 209, the stage effectively reduces the power supply voltage of the CMOS inverter arrangements to a threshold voltage (e.g., V for each diode-connected PMOS transistor used in the stage). thThis effectively reduces the trip voltage level of the CMOS inverter arrangement. It should be understood that the trip voltage level is a characteristic of the CMOS inverter arrangement that defines the point at which the CMOS inverter arrangement switches states. Thus, the different stages 201, 202, 203 gradually increase the supply voltage. This "diode-based gradient" can be used to perform a level shift from the lower supply domain 101 to the higher supply domain 108. In one or more examples, each stage is configured to increase the trip voltage level of the CMOS inverter arrangement of the corresponding stage relative to the CMOS inverter arrangement of the previous stage to the second supply voltage through the arrangement of one or more diode-connected PMOS transistors in each stage. This arrangement can also reduce the DC current in at least the second circuit component. The one or more arrangements of diode-connected PMOS transistors arranged in a gradient manner reduce the effective local voltage across each corresponding CMOS inverter arrangement, and thereby reduce or minimize quiescent current consumption.

[0074] Figure 2 The embodiment illustrates a “series transition”. The number of diode-connected PMOS transistors required to transition from the first power supply voltage at input 113 to the second power supply voltage of the second circuit 108 can be determined by dividing the voltage difference (i.e., first power supply voltage - second power supply voltage) by a threshold voltage, which, as those skilled in the art will know, includes the voltage at which the inversion layer of the diode-connected PMOS transistor is formed, or in other words, the voltage at which the transistor is turned on.

[0075] In one or more examples, two or more of the diode-connected PMOS transistors may have individual n-wells. This has been found to reduce body effects. Individual n-wells can be used to lower the threshold voltage of the corresponding diode-connected PMOS transistors arranged 204, 205, 206, thereby raising the trip voltage level of the corresponding CMOS inverter arrangements 207, 208, 209. It should be understood that the voltage present between the n-well and the source terminal affects the threshold voltage, and thus affects the trip voltage level (in conjunction with the width / length specification dimensions of the diode-connected PMOS transistor).

[0076] In one or more examples, there are an even number of levels. In one or more examples, there are an odd number of levels.

[0077] The use of a diode-connected PMOS transistor arrangement may be advantageous because it is unaffected by receptor effects. For example, if an NMOS transistor were used instead, a large Vgs voltage might occur. Furthermore, the level shifter in this embodiment, or any other embodiment, may only require a second supply voltage, thereby simplifying the layout.

[0078] exist Figure 2In the example, the diode-connected PMOS transistor arrangements 204, 205, 206 include diode-connected PMOS transistors connected in series. Figure 3 The example embodiment shows an arrangement of diode-connected PMOS transistors including diode-connected PMOS transistors connected in parallel.

[0079] Example Figure 3 Showing similar Figure 2 A level shifter 300 with three stages (stage 301, stage 302, and stage 303). (See example) Figure 2 Similarly, the first stage includes a first arrangement 304 of diode-connected PMOS transistors connected in series between the second voltage supply 111 and the reference voltage 107 to the CMOS inverter arrangement 307. The second stage includes a second arrangement 302 of diode-connected PMOS transistors connected in series between the second voltage supply 111 and the reference voltage 107 to the second CMOS inverter arrangement 308. The third and final stages include a third arrangement 306 of diode-connected PMOS transistors connected in series between the second voltage supply 111 and the reference voltage 107 to the CMOS inverter arrangement 309. As in the previous example, the first CMOS inverter arrangement 307 receives a first digital output signal from input 113, and the final CMOS inverter arrangement 308 outputs a second digital control signal to the second circuit component 109 at output 201. The structure and operation of the CMOS inverter arrangements 307, 308, and 309 are the same as in the previous example embodiment.

[0080] In the example Figure 3 In the example, the layout of 304, 305, and 306 differs from the example. Figure 2 Each arrangement 304, 305, 306 has a different number of diode-connected PMOS transistors connected in parallel. Specifically, the later stage has a greater number of diode-connected PMOS transistors connected in parallel compared to the previous stage. These parallel arrangements of different sizes therefore have different current capacities, and thus the voltage drop across the arrangements can vary across stages 301, 302, 303. In one or more examples, the first arrangement 304 and the second arrangement 305 are configured such that the voltage drop provided by the first arrangement 304 is greater than the voltage drop provided by the second arrangement 305. Similarly, the second arrangement 205 and the third arrangement 206 are configured such that the voltage drop provided by the second arrangement 205 is greater than the voltage drop provided by the third arrangement 206.

[0081] In the example Figure 3It should be understood that the source terminals of the parallel-connected diode-connected PMOS transistor arrays will be configured to be coupled to power line 111. Similarly, the drain terminals of the parallel-connected diode-connected PMOS transistor arrays will be configured to be coupled to the first terminals of the corresponding CMOS inverter arrangements 307, 308, and 309.

[0082] Using multiple parallel diode-connected PMOS transistors effectively doubles the width, and thus doubles the total current capacity of the diode-connected PMOS transistors. This, in turn, reduces the required overdrive voltage, causing the trip level of the corresponding CMOS inverter arrangement to rise. Those skilled in the art will understand that overdrive voltage includes an additional voltage (overdrive voltage) higher than the threshold voltage required to maintain a predetermined current.

[0083] In the example Figure 3 In this example, multiple unit-sized diode-connected PMOS transistors (W / L = 1 / 5) are used in parallel. Each stage of the CMOS inverter arrangement 307, 308, and 309 uses diode-connected PMOS arrangements 304, 305, and 306 of different sizes. In this example, the first arrangement 304 may include a single unit-sized diode-connected PMOS transistor with a W / L ratio of 1 / 5. Therefore, diode-connected PMOS transistor 320 represents a single unit-sized diode-connected PMOS transistor. The second arrangement 305 may consist of five unit-sized diode-connected PMOS transistors (W / L ratio of 1 / 5) connected in parallel. Therefore, diode-connected PMOS transistor 340 represents a parallel connection group of five unit-sized diode-connected PMOS transistors. The third arrangement 306 may consist of twenty-five unit-sized diode-connected PMOS transistors (W / L ratio of 1 / 5) connected in parallel. Therefore, diode-connected PMOS transistor 360 represents a parallel connection group of twenty-five unit-sized diode-connected PMOS transistors. Using unit-sized PMOS diodes allows for simplified back-end layout design. It should be understood that different numbers of parallel-connected diode-connected PMOS transistors can be used in other examples. Although in this example, the parallel connections 304, 305, 306 are embodied by different numbers of parallel-connected diode-connected PMOS transistors, it should be understood that it is possible to provide an arrangement with an increased W / L ratio from the first stage 301 to each subsequent stage 302, 303.

[0084] In one or more examples, level shifters 200, 300 may include different combinations of parallel-connected diode-connected PMOS transistor groups and series-connected diode-connected PMOS transistor chains. Regardless of the layout of diode-connected PMOS transistors used in each of arrangements 204, 205, 206, 304, 305, 306, said arrangements can be selected to provide a reduced voltage drop and a raised trip voltage level for the associated CMOS inverter arrangements spanning stages 201, 202, 203.

[0085] In other embodiments, the principles of the first and second example embodiments may be applied. Figure 4 Example implementations include instances of adding hysteresis. Hysteresis is typically added to the input buffers of digital logic circuits to suppress interference caused by noise superimposed on slowly changing signals.

[0086] To implement the hysteresis, two different voltage levels are required, where a first level defines the transition from a low state to a high state, and a second level defines the transition from a high state to a low state, wherein the hysteresis includes the difference. These levels can be implemented using two separate CMOS inverter arrangements, both connected to receive a first digital signal.

[0087] Example Figure 4 The level shifter arrangement 400 includes two first stages 401A and 401B. The two first stages include a high-trigger level first stage 401A and a low-trigger level first stage 401B. In this example, a second stage 402A is present for the high-trigger level first stage 401A. There is no second stage associated with the low-trigger level first stage 401B. However, in other embodiments, the high-trigger level stage may have at least one, two, or more stages, and the low-trigger level stage may have at least one, two, or more stages.

[0088] The high-trigger level first stage 401A includes an arrangement 404A of one or more diode-connected PMOS (DPMOS) transistors, in this example, including first and second DPMOS transistors 420, 421 connected in series (but other arrangements are also possible). The source terminal of the first DPMOS 420 is configured to be coupled to a second supply voltage, and the drain terminal of the second DPMOS transistor 421 is coupled to a high-trigger level CMOS inverter arrangement 407A. As in the previous example, the high-trigger level CMOS inverter arrangement 407A has a first terminal coupled to the drain terminal of the second DPMOS 421 and a voltage reference terminal for coupling to voltage reference line 107. The high-trigger level CMOS inverter arrangement 407A of the high-trigger level first stage 401A is configured to receive a first digital output signal at input 113 and provide a high-trigger level output signal at 410. According to the principles herein, one or more stages may be included through which the first digital output signal is passed before becoming a second digital output signal provided by the second component 109.

[0089] In this example, the high-trigger-level CMOS inverter arrangement 407A of the first high-trigger-level stage 401A provides an intermediate high-trigger-level signal at 411, which is passed to the second high-trigger-level CMOS inverter arrangement 408A of the second high-trigger-level stage 402A. Therefore, the second high-trigger-level CMOS inverter arrangement 408A outputs a high-trigger-level output signal at 410.

[0090] The level shifter 400 includes a low-trigger level first stage 401B, consistent with all embodiments, which includes an arrangement 404B of one or more DPMOS transistors 422 and a low-trigger level CMOS inverter arrangement 407B. The source terminals of the DPMOS transistors 422 are configured to be coupled to a second supply voltage 111, and the drain terminals of the DPMOS transistors 422 (because there is only one transistor in this stage, rather than a chain of two or more transistors) are coupled to the low-trigger level CMOS inverter arrangement 407B. The low-trigger level CMOS inverter arrangement 407B has a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference.

[0091] The low-trigger-level CMOS inverter arrangement 407B of the low-trigger-level first stage 401B is also configured to receive a first digital output signal from input 113 and provide a low-trigger-level output signal as an output at 412.

[0092] The high-trigger-level and low-trigger-level CMOS inverter arrangements 407A, 408A, and 407B may each include PMOS transistors 413 and 415, each having a source terminal for direct or indirect coupling to a corresponding arrangement 404A, 405A, and 404B of one or more DPMOS transistors, and a drain terminal for direct or indirect connection to the drain terminals of NMOS transistors 414 and 416, wherein the source terminal of the NMOS transistor is used for direct or indirect coupling to a reference voltage at 107. As in the previous example, the inputs to the high-trigger-level and low-trigger-level CMOS inverter arrangements 407A, 408A, and 407B may include the gate terminals of the configured PMOS and NMOS transistors, and the outputs include nodes between the connected drain terminals.

[0093] In the high-trigger-level CMOS inverter arrangement 407A of at least the first stage 401A, the aspect ratio of the PMOS transistor 413 (e.g., 10 / 1) is greater than that of the NMOS transistor 414 (e.g., 2 / 2). Therefore, the PMOS 413 can be considered strong, while the NMOS 414 can be considered weak.

[0094] In the low-trigger-level CMOS inverter arrangement 407B, the aspect ratio of the NMOS transistor 416 (e.g., 10 / 1) is greater than that of the PMOS transistor 415 (e.g., 2 / 2). Therefore, the PMOS 415 can be considered weak, while the NMOS 416 can be considered strong.

[0095] The strength difference between the PMOS and NMOS transistors in the low-trigger-level CMOS inverter arrangement 407B and the high-trigger-level CMOS inverter arrangement 407A provides different trip voltage levels for implementing hysteresis. Furthermore, the DPMOS transistors in arrangements 404A and 404B can be proportionally adjusted to support different trigger levels. Therefore, the aspect ratio of the DPMOS transistor in arrangement 404A can be greater than that of the DPMOS transistor in arrangement 404B.

[0096] The level shifter 400 further includes a latch 417 to combine a high-trigger level output signal at 410 with a low-trigger level output signal at 412, thereby providing a combined digital signal at 418. The combined digital signal at 418 is received by a logic inverter 419, which is also configured to output an inverted version of the combined digital signal, including a second digital signal for reception by the second circuit component 109. In other examples, the second circuit component 109 may be connected to output 437, and two or more inverters may be proportionally adjusted to drive a specific load at 437. In this example, two inverters with increased current drive capability or "strength" may be used.

[0097] In this example and one or more examples, the level shifter arrangement includes a high-trigger level second stage 402A. However, in one or more examples, the second stage can be replaced by a logic inverter, such as a CMOS logic inverter. Therefore, whether implemented as a stage (and thus including a CMOS inverter arrangement with DPMOS transistors connected in series and a second power supply and a reference voltage) or implemented as a CMOS logic inverter, Figure 4 All embodiments can achieve logic inversion of the output of the high-trigger-level first stage 401A. Therefore, the second stage 402A or an alternative logic inverter is used to invert the polarity of the signal output from the high-trigger-level CMOS inverter arrangement 407A, so that the high-trigger-level signal is in phase with the first digital output signal at terminal 113, while the low-trigger-level output signal from the low-trigger-level CMOS inverter arrangement 407B is out of phase with the first digital output signal at terminal 113.

[0098] exist Figure 4 In this example, latch 417 includes a first branch 430 and a second branch 431. Each branch includes a terminal coupled at one end to a second voltage supply at line 111 and at the other end to a voltage reference at line 107. The first branch 430 includes a PMOS transistor 432, and the second branch includes a PMOS transistor 433. Because the gate of PMOS 432 is coupled to the drain of PMOS 433, and the gate of PMOS 433 is coupled to the drain of PMOS 432, the PMOS transistors 432 and 433 in each branch are cross-coupled.

[0099] Branches 430 and 431 each include an NMOS transistor. A first NMOS transistor 434 is provided in the first branch 430 to receive a low trigger level output signal at its gate, and a second NMOS transistor 435 is provided in the second branch 431 to receive a high trigger level output signal at its gate. A combined digital signal is provided from a node 436 of one of the first and second branches; in this case, the branch is the second branch 431. Thus, node 436 is between one of the cross-coupled PMOS transistors 432 or 431 and a corresponding one of the first or second NMOS transistors 434 or 436 in the same branch 430, 431.

[0100] Because latch 417 not only combines two signals into a single output, but also generates a full-swing output signal to reduce the need for multiple stages such as those providing the aforementioned variation, it may be advantageous to use latch 417.

[0101] In one or more embodiments, one or more of the first series-connected DPMOS 420, the second series-connected DPMOS 421, and the PMOS in the CMOS inverter arrangement 407A may have a back gate coupled to receive a second power supply voltage. It should be understood that in Figure 4 In this configuration, connection 438 provides a second power supply voltage to the back gate terminals of the second DPMOS 421 and PMOS transistor 413. In one or more embodiments, one or more of the first series-connected DPMOS 423, the second series-connected DPMOS 424, and the PMOS 415 in the CMOS inverter arrangement 407B may have a back gate terminal coupled to receive the second power supply voltage.

[0102] Example Figure 4 The embodiments can advantageously provide hysteresis. However, through Figure 5 Example implementations can achieve hysteresis without the complexity of high and low trigger level stages.

[0103] Example Figure 5 A level shifter 500 with three stages is shown, comprising a first stage 501, a second stage 502, and a third stage 503. Each stage 501-503 includes an arrangement 508, 512, 514 of one or more DPMOS transistors, which are coupled in series with CMOS inverter arrangements 516, 517, 518 between a second voltage supply 111 and a reference voltage (i.e., ground 107). The level shifter 500 also optionally includes one or more CMOS logic inverters—in this example, three CMOS logic inverters, including 504, 505, and 506—before providing a second output signal at output 507.

[0104] Generally speaking, it should be understood that Figure 5 The level shifter 500 may have at least two stages 501, 502, 503 and zero, and at least one or at least two CMOS logic inverters 504, 505, 506.

[0105] The DPMOS arrangement 508 of the first stage 501 includes a first DPMOS transistor 510 and a second DPMOS transistor 511 (which may indicate multiple DPMOS transistors connected in parallel as in the previous example). The DPMOS arrangement 512 of the second stage 502 includes a single DPMOS transistor 513 (or multiple DPMOS transistors connected in parallel). The DPMOS arrangement 514 of the third stage 503 includes a single DPMOS transistor 515 (or multiple DPMOS transistors connected in parallel).

[0106] In this example, hysteresis is provided by the presence of switch 520, which is configured to short-circuit one or more diode-connected PMOS transistors 510, 511 of the first arrangement 508 by selectively providing an alternative current path that can be turned on and off. In this example, switch 520 is configured to selectively short-circuit the second DPMOS 511. The switch is controlled by the output of the CMOS inverter arrangement of the second stage 502. This arrangement can advantageously provide hysteresis while reducing complexity.

[0107] Switch 520 may include a transistor, such as a PMOS transistor, whose source terminal is coupled to the source terminal of one of the DPMOS transistors 511, and whose drain terminal is coupled to the drain terminal of the same DPMOS transistor 511. Depending on the provided stage, the gate terminal of switch 510 is coupled at 521 to the output of the second CMOS inverter arrangement 517 to receive a second digital output signal or an intermediate digital output signal between the second and third stages.

[0108] In one or more examples, the back gate of the second DPMOS transistor 511 (i.e., one or more transistors shorted by the switch) can be coupled to the second power supply voltage at line 111. In one or more examples, the back gate of the switch 520 can be coupled to the second power supply voltage at line 111. A connection 528 providing the back gate connection is shown.

[0109] Generally, in any embodiment, the back gate of at least one of the DPMOS transistors can be coupled to a second power supply voltage at 111, which can be advantageously used to control the trigger level of the CMOS inverter arrangements 516, 517, 518.

[0110] In one or more examples, the first CMOS inverter arrangement 516 includes a PMOS transistor 522 connected in series with an NMOS transistor 523, wherein the PMOS transistor 522 has a connection 524 between its source terminal and its back gate terminal. This connection 524 can be provided to reduce the effects of body effects.

[0111] Therefore, in use, the first CMOS inverter arrangement 516 receives the first digital output signal at the gates of its constituent PMOS and NMOS transistors 522, 523. The output from the node between the connected drain terminals is used to drive the second CMOS inverter arrangement 517. The second CMOS inverter arrangement 517 in turn drives the third CMOS inverter arrangement 518. In this example, the third CMOS inverter arrangement is the last stage and provides its output to drive three CMOS inverters 504, 505, 506, whose sizes are set appropriately to drive a specific load connected at 507 (which can be considered an additional stage of a level shifter). As mentioned, hysteresis is achieved using a switch 520, which shorts the DPMOS 511 and drives it with the output of the second CMOS inverter arrangement 517. Therefore, when the voltage of the first output signal at 525 begins to be low, the DPMOS transistor 511 is shorted, and the provided trigger or trip level is higher than the trigger or trip level when the first output signal at 525 is high. In the second state, when the first output signal at 525 is high, switch 520 is open and DPMOS 511 is not short-circuited, thus providing a lower trigger or trip level.

[0112] Therefore, the selective short circuit of the first DPMOS arrangement 508 provides hysteresis.

[0113] Example Figure 6 Another embodiment is shown, comprising a stage 601 and three CMOS inverters 602, 603, and 604. Stage 601 has the same general structure as in the previous embodiment.

[0114] However, in Figure 6 In this example, the level shifter arrangement 600 includes an NMOS transistor 605 for high-voltage protection. The NMOS transistor 605 has a drain terminal 606 for receiving a first digital output signal and a source terminal 607 for providing the first digital output signal to the CMOS inverter arrangement 608 of the first stage 601 after the first digital output signal has passed through the NMOS 605. The gate terminal 609 of the NMOS transistor 605 is coupled to receive a second supply voltage at line 111.

[0115] The NMOS transistor 605 for high-voltage protection may include a double-diffused metal-oxide-semiconductor (DMOS) transistor. In one or more examples, the NMOS transistor includes one of a VDMOS (vertical double-diffused metal-oxide-semiconductor) and an LDMOS (lateral double-diffused metal-oxide-semiconductor) transistor.

[0116] It should be understood that any of the embodiments described herein may include the NMOS transistor 605 for high-voltage protection. Using the NMOS transistor 605 can generate a very large input voltage range. The NMOS transistor 605 will limit the voltage at the gate terminals of the PMOS and NMOS of the first CMOS inverter arrangement 608, thereby preventing damage to the gate oxide of these components. It should be understood that due to the threshold voltage of the NMOS transistor 605, the voltage at the gate terminals of the PMOS and NMOS of the first CMOS inverter arrangement 608 will remain well below the second supply voltage. In one or more examples, for example by using series-connected DPMOS in the first DPMOS arrangement 610, additional components or arrangements may be added to prevent quiescent current from flowing in the first stage 601.

[0117] Example Figure 7 With example Figure 6 They are essentially the same; however, in this example, two stages 701 and 702 are provided, as well as two CMOS inverters 703 and 704.

[0118] It has been found that using the NMOS transistor 605 does not prevent operation under small input voltages, and the series-connected DPMOS transistor 710 effectively prevents quiescent current consumption during such operating conditions. Therefore, a level shifter 600 with an NMOS transistor for high voltage protection and at least two stages 601, 701, 702 can provide an “input buffer” with a truly wide input voltage range.

[0119] It should be understood that level shifters 200, 300, 400, 500, 600, and 700 can be considered as “input buffers” that facilitate the passage of digital signaling from different voltage domains and provide modification of the voltage level of the digital signaling.

[0120] Example Figure 8 A wireless communication device 800 is shown, comprising any one of embodiments 108, 300, 400, 500, and 600 as described herein.

[0121] It should be understood that any components that are alleged to be coupled can be coupled or connected directly or indirectly. In the case of indirect coupling, an additional component may be placed between the two components that are alleged to be coupled.

[0122] In this specification, exemplary embodiments have been presented with respect to a selected set of details. However, those skilled in the art will understand that many other exemplary embodiments, including different selected sets of these details, can be practiced. It is intended that the appended claims cover all possible exemplary embodiments.

Claims

1. A device including a level shifter, characterized in that, include: A first voltage domain circuit, the first voltage domain circuit including a first circuit component configured to provide a first digital output signal, wherein the first voltage domain circuit is configured to receive a first power supply voltage, and wherein the first digital output signal has a high state and a low state, and the voltage of the high state is based on the first power supply voltage. A second voltage domain circuit, the second voltage domain circuit including a second circuit component, wherein the second voltage domain circuit is configured to receive a second power supply voltage greater than the first power supply voltage; A level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal at an elevated voltage level based on the first digital output signal, wherein the level shifter arrangement is configured to provide the second digital output signal for input to the second circuit component; The level shifter arrangement includes at least one stage, the at least one stage including an arrangement of one or more diode-connected PMOS transistors, the source terminal of at least one of the one or more diode-connected PMOS transistors being configured to be coupled to the second power supply voltage, and the drain terminal of at least one of the one or more diode-connected PMOS transistors being coupled to a CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference. The CMOS inverter arrangement of the first stage in the at least one stage is configured to receive the first digital output signal, and the CMOS inverter arrangement of the last stage in the at least one stage is configured to output the second digital output signal.

2. The device including a level shifter according to claim 1, characterized in that, The level shifter arrangement includes at least two stages, the at least two stages including a first stage and a second stage; The first stage includes a first arrangement of one or more diode-connected PMOS transistors, at least one of the diode-connected PMOS transistors having its source terminal configured to be coupled to the second power supply voltage, and at least one of the diode-connected PMOS transistors having its drain terminal coupled to a first CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference. and The second stage includes a second arrangement of one or more diode-connected PMOS transistors, wherein the source terminal of at least one of the one or more diode-connected PMOS transistors is configured to be coupled to the second power supply voltage, and the drain terminal of at least one of the one or more diode-connected PMOS transistors is coupled to a second CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal coupled to a voltage reference. The first CMOS inverter arrangement is configured to receive the first digital output signal and provide a first intermediate digital output signal to the second CMOS inverter arrangement of the second stage, wherein the second CMOS inverter arrangement is configured to receive the intermediate digital output signal and provide the second digital output signal to the second circuit component; and The first and second arrangements of the diode-connected PMOS transistor are configured such that the voltage drop provided by the first arrangement is greater than the voltage drop provided by the second arrangement.

3. The device including a level shifter according to any of the preceding claims, characterized in that, The arrangement of the one or more diode-connected PMOS transistors includes one of the following: Multiple diode-connected PMOS transistors connected in series; and A PMOS transistor with multiple diodes connected in parallel.

4. The device including a level shifter according to claim 3, characterized in that, The arrangement includes a plurality of diode-connected PMOS transistors connected in series, and at least one or more of the diode-connected PMOS transistors have individual n-wells.

5. The device including a level shifter according to claim 2, characterized in that, The first arrangement includes a plurality of diode-connected PMOS transistors connected in series, and the second arrangement includes one or more diode-connected PMOS transistors connected in series, and the voltage drop difference is provided by a greater number of diode-connected PMOS transistors connected in series in the first arrangement than the number of diode-connected PMOS transistors connected in series in the second arrangement.

6. The device including a level shifter according to claim 2, characterized in that, The first arrangement includes one or more diode-connected PMOS transistors connected in parallel, and the second arrangement includes a plurality of diode-connected PMOS transistors connected in parallel, and the voltage drop difference is provided by a greater number of diode-connected PMOS transistors connected in parallel in the second arrangement than the number of diode-connected PMOS transistors connected in parallel in the first arrangement.

7. The device including a level shifter according to claim 2, characterized in that, The level shifter arrangement includes at least three stages, and the voltage drop of the diode-connected PMOS transistor arrangement in each of the at least three stages gradually and monotonically decreases from the first stage that receives the first digital output signal to the last of the at least three stages that provides the second digital output signal for the second circuit component.

8. The device including a level shifter according to claim 6, characterized in that, Each of the diode-connected PMOS transistors in the first and second arrangements has the same unit size.

9. The device including a level shifter according to claim 1 or 2, characterized in that, The level shifter arrangement includes: A high trigger level first stage, the high trigger level first stage including an arrangement of one or more diode-connected PMOS transistors, the source terminal of at least one of the one or more diode-connected PMOS transistors being configured to be coupled to the second power supply voltage, and the drain terminal of at least one of the one or more diode-connected PMOS transistors being coupled to a high trigger level CMOS inverter arrangement, the high trigger level CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference; The high-trigger-level CMOS inverter arrangement of the first stage of the high-trigger-level is configured to receive the first digital output signal and provide a high-trigger-level output signal; A low trigger level first stage, the low trigger level first stage comprising an arrangement of one or more diode-connected PMOS transistors, wherein the source terminal of at least one of the one or more diode-connected PMOS transistors is configured to be coupled to the second power supply voltage, and the drain terminal of at least one of the one or more diode-connected PMOS transistors is coupled to a low trigger level CMOS inverter arrangement having a first terminal coupled to the drain terminal and a voltage reference terminal for coupling to a voltage reference; The low-trigger-level CMOS inverter arrangement of the first stage of the low-trigger-level is also configured to receive the first digital output signal and provide a low-trigger-level output signal; Both the high-trigger-level CMOS inverter arrangement and the low-trigger-level CMOS inverter arrangement include a PMOS transistor, the PMOS transistor having a source terminal for direct or indirect coupling to a corresponding arrangement of one or more diode-connected PMOS transistors, and a drain terminal for direct or indirect connection to an NMOS transistor, wherein the source terminal of the NMOS transistor is used for direct or indirect coupling to a reference voltage. In the high-trigger-level CMOS inverter arrangement, the aspect ratio of the PMOS transistor is greater than that of the NMOS transistor, and in the low-trigger-level CMOS inverter arrangement, the aspect ratio of the NMOS transistor is greater than that of the PMOS transistor. A latch, configured to receive the high-trigger level output signal and the low-trigger level output signal, and to combine the high-trigger level output signal and the low-trigger level output signal to generate a combined digital signal; and The final stage includes a CMOS logic inverter configured to receive the combined digital signals and output the second digital output signal.

10. A wireless communication device, characterized in that, Includes the device comprising a level shifter as described in any of the preceding claims.

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