Apparatus and method for driving a display panel

Abstract

A processing system includes a first IC chip and a second IC chip. The first IC chip includes first image processing circuitry, first display panel driver circuitry, and first communication circuitry. The first image processing circuitry is configured to generate a first overlaid image by overlapping a first partial input image with a first image element based on first partial input image data representing the first partial input image and first image element data representing the first image element. The first display panel driver circuitry is configured to drive a display panel based on the first overlaid image. The first communication circuitry is configured to output second image element data representing a second image element to the second IC chip.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 62 / 915001, filed on October 14, 2019, which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments disclosed herein generally relate to electronic devices, and more specifically to devices for driving display panels. Background Technology

[0004] A processing system configured to drive a display panel (such as an organic light-emitting diode (OLED) panel or a liquid crystal panel) may include multiple integrated circuit (IC) chips. Summary of the Invention

[0005] This invention is provided to introduce, in a simplified form, the selection of concepts further described below in the detailed description. This invention is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0006] A processing system is disclosed. In one or more embodiments, the processing system includes a first IC chip and a second IC chip. The first IC chip includes a first image processing circuit system, a first display panel driver circuit system, and a first communication circuit system. The first image processing circuit system is configured to generate a first overlapping image by overlaying the first partial input image with first image elements based on first partial input image data representing a first partial input image and first image element data representing first image elements. The first display panel driver circuit system is configured to drive a display panel based on the first overlapping image. The first communication circuit system is configured to output second image element data representing second image elements to the second IC chip.

[0007] In one or more embodiments, an IC chip is disclosed. The IC chip includes an image processing circuit system, a display panel driver circuit system, and a communication circuit system. The image processing circuit system is configured to generate an overlapping image by overlaying the partial input image with a first image element based on partial input image data representing a partial input image and first image element data representing a first image element. The display panel driver circuit system is configured to drive a display panel based on the overlapping image. The communication circuit system is configured to output second image element data representing a second image element to a first IC chip in a first operating mode, and to receive first image element data from a second IC chip.

[0008] A method for driving a display panel is also disclosed. In one or more embodiments, the method includes generating, by a first IC chip, a first overlay image, the first overlay image including a first portion of input images overlaid with first image elements; and driving, by the first IC chip, the display panel using the first overlay image. The method further includes outputting, by the first IC chip, second image element data representing second image elements to a second IC chip. The method further includes generating, by the second IC chip, a second overlay image, the second overlay image including a second portion of input images overlaid with the second image elements; and driving, by the second IC chip, the display panel using the second overlay image. BRIEF DESCRIPTION OF DRAWINGS

[0009] Thus, a more particular description of the disclosure, for purposes of exemplification, of specific embodiments thereof, but not limitation, will be given with reference to certain embodiments in the accompanying drawings. However, it is noted that the drawings are for purposes of exemplification only and, therefore, are not to be considered as limiting the scope in any manner, since the disclosure can admit other equally effective embodiments.

[0010] Figure 1 An exemplary configuration of a display apparatus according to one or more embodiments is described.

[0011] Figure 2 An exemplary structure of overlay control information according to one or more embodiments is described.

[0012] Figure 3 An exemplary configuration of a display apparatus according to one or more embodiments is described.

[0013] Figure 4 An exemplary data stored in an external memory according to one or more embodiments is described.

[0014] Figure 5 An exemplary configuration of a processing system according to one or more embodiments is described.

[0015] Figure 6 An exemplary operation of a processing system according to one or more embodiments is described.

[0016] Figure 7 An exemplary method of transferring image element data according to one or more embodiments is described.

[0017] Figure 8 An exemplary transmission of individual control information and global control information according to one or more embodiments is described.

[0018] Figure 9 An exemplary configuration of a processing system according to one or more embodiments is described.

[0019] Figure 10 An exemplary configuration of a processing system according to one or more embodiments is described.

[0020] Figure 11 An exemplary configuration of a display apparatus according to one or more embodiments is described.

[0021] For the purposes of promoting an understanding of the principles of the application, reference will now be made to the embodiments illustrated in the drawings, which are described below. It will be readily understood that the principles of the present application, as taught by the DETAILED DESCRIPTION

[0022] The following detailed description is merely illustrative in nature and is not intended to limit the disclosure or the application and uses of the disclosure. Furthermore, there is no intention that the application be limited in its application to the details set forth in the following description, or that it recite a complete list of all the possible embodiments of the application. Rather, the detailed description is intended to present embodiments of the application by illustrating some possible aspects of it. The principles and applications discussed can be employed in various ways.

[0023] A processing system configured to drive a display panel can include multiple integrated circuit (IC) chips. Synchronization among these IC chips can improve the efficiency of such a system.

[0024] Figure 1 An exemplary configuration of a display system according to one or more embodiments is described. In the illustrated embodiment, a processing system 110 is configured to drive a display panel 30 based on an input image 11 and one or more image elements 21, which can each include an icon to display a desired image. An external apparatus 10 disposed outside the processing system 110 can supply input image data representing the input image 11 to the processing system 110, and an external memory 20 can supply image element data representing the image elements 21 to the processing system 110. In one or more embodiments, the external apparatus 10 is configured to output overlap control information 12 to the processing system 110, the overlap control information 12 indicating whether each of the image elements 21 is to be displayed. In such embodiments, the processing system 110 can be configured to generate an overlap image 111 in which the input image 11 overlaps at least one of the image elements 21 specified by the overlap control information 12 at a desired location based on the overlap control information 12. The generated overlap image 111 can be displayed on the display panel 30.

[0025] Figure 2Exemplary contents of the overlap control information 12 are described. In the illustrated embodiment, the overlap control information 12 includes first image element control data 510-1 to third image element control data 510-3. The first image element control data 510-1 to the third image element control data 510-3 respectively indicate whether the input image 11 is to overlap with a first image element to a third image element among the image elements 21. For example, the first image element control data 510-1 can include an identifier to identify the first image element and a status value indicating whether the input image 11 is to overlap with the first image element. The second and third image element control data 510-2 to 510-3 can be configured similarly to the first image element control data 510-1.

[0026] Figure 3 An exemplary configuration of the display panel 30 and the processing system 110 according to one or more embodiments is described. In the illustrated embodiment, the display panel 30 includes pixel circuits 31, source lines 32, and gate lines 33. The source lines 32 are connected to the processing system 110, and the gate lines 33 are connected to gate driver circuitry (not illustrated) configured to select the gate lines 33. Each pixel circuit 31 is connected to a corresponding source line 32 and gate line 33. The pixel circuits 31 are driven based on an input to the source line 32 and a selection of the gate line 33. Examples of the display panel 30 include an organic light-emitting diode (OLED) display panel, a liquid crystal display (LCD) panel, or the like. The display panel 30 can be installed in an automobile, but is not limited thereto.

[0027] In one or more embodiments, the processing system 110 includes a plurality of IC chips 200, including, for example, a master chip 200-M, a first slave chip 200-S1, and a second slave chip 200-S2. In the illustrated embodiment, the display panel 30 is segmented into a number of partial areas 35, each of which corresponds to an IC chip 200 that can be configured to drive the pixel circuits 31 in the corresponding partial area 35. The partial areas 35 can be segmented depending on the number of source lines 32 that each IC chip 200 is capable of driving. The partial areas 35 can be defined such that the same number of source lines 32 are merged, but are not limited thereto. The partial areas 35 can be segmented with boundaries that are parallel to the direction in which the source lines 32 of the display panel 30 extend. For example, the master chip 200-M can drive the pixel circuits 31 in a partial area 35-M; the first slave chip 200-S1 can drive the pixel circuits 31 in a partial area 35-S1; and the second slave chip 200-S2 can drive the pixel circuits 31 in a partial area 35-S2. Each IC chip 200 can control the input to the associated source lines 32, and at least one of the IC chips 200 can control the selection of the gate lines 33. In embodiments in which the display panel 30 includes sensor electrodes (which are used to detect contact or proximity of an input object with the display panel 30), the processing system 110 can be configured to detect the position of the input object based on signals from the sensor electrodes.

[0028] In one or more embodiments, the external device 10 is configured to output the overlap control information 12 and input image data representing the input image 11 to each IC chip 200. In such embodiments, each IC chip 200 can be configured to extract, from the input image data, partial input image data corresponding to the partial area 35 to which the IC chip 200 is assigned, and to drive the display panel 30 based on the extracted partial input image data. The input image data can describe the gray scale values of the respective colors (e.g., red, green, and blue) of each pixel included in the input image 11.

[0029] In one or more embodiments, the external memory 20 is configured to output image element data representing the image elements 21 to at least one of the IC chips 200. For example, the external memory 20 can be configured to output all of the image elements 21 to the master chip 200-M, to output a subset of the image elements 21 to a selected IC chip 200, and so on. The image element data can include the gray scale values of the respective colors of each pixel included in the image elements 21. In other embodiments, the master chip 200-M can include an internal memory that stores the image element data.

[0030] Figure 4An example data stored in the external memory 20 according to one or more embodiments is illustrated. In the illustrated embodiment, the external memory 20 is configured to store image element data 420 representing the image elements 21 and index data 410 including attribute information of each image element 21. The attribute information of each image element 21 indicates, for example, a data size of the corresponding image element data 420 and a position at which the image element 21 is to be displayed. The main chip 200-M can be configured to receive the index data 410 from the external memory 20 and transfer the image element data 420 to another IC chip 200 based on the index data 410.

[0031] In one or more embodiments, the index data 410 includes main chip index data 412, first slave chip index data 414, and second slave chip index data 416. The main chip index data 412 can include attribute information of each image element 21 to be displayed in the partial area 35-M assigned to the main chip 200-M. The first slave chip index data 414 can include attribute information of each image element 21 to be displayed in the partial area 35-S1 assigned to the first slave chip 200-S1. The second slave chip index data 416 can include attribute information of each image element 21 to be displayed in the partial area 35-S2 assigned to the second slave chip 200-S2.

[0032] In one or more embodiments, the image element data 420 includes main chip image element data 422, first slave chip image element data 424, and second slave chip image element data 426. The main chip image element data 422 can include image element data representing each image element 21 to be displayed on the partial area 35-M assigned to the main chip 200-M. The first slave chip image element data 424 can include image element data representing each image element 21 to be displayed on the partial area 35-S1 assigned to the first slave chip 200-S1. The second slave chip image element data 426 can include image element data representing each image element 21 to be displayed in the partial area 35-S2 assigned to the second slave chip 200-S2.

[0033] Figure 5An exemplary configuration of the master chip 220-M is illustrated in accordance with one or more embodiments. In the illustrated embodiment, the master chip 200-M includes a first interface (I / F) 300, a second interface (I / F) 310, communication circuitry 320, internal memory 330, image processing circuitry 340, and display panel driver circuitry 350. In one or more embodiments, the first slave chip 200-S1 and the second slave chip 200-S2 have the same configuration as the configuration of the master chip 200-M. In other embodiments, the first slave chip 200-S1 and the second slave chip 200-S2 can have a different configuration than the configuration of the master chip 200-M.

[0034] In one or more embodiments, the first interface 300 is configured to transfer the overlap control information 12 and input image data representing the input image 11 from the external device 10 to the image processing circuitry 340. In other embodiments, the first interface 300 can be configured to extract partial input image data representing a partial input image from the input image data, the partial input image data corresponding to a partial region 35-M to which the master chip 200-M is assigned, and output the extracted partial input image data to the image processing circuitry 340. The first interface 300 can include a low voltage differential signaling (LVDS) interface, a serial peripheral interface (SPI), an inter-integrated circuit (I2C) interface, or another suitable interface. The LVDS interface can be configured to receive the input image data from the external device 10. The first interface 300 can include multiple LVDS interfaces (e.g., two LVDS interfaces) configured to receive the input image data from the external device 10 and an SPI or I2C interface configured to receive the overlap control information 12.

[0035] In one or more embodiments, the second interface 310 of the master chip 220-M is configured to transfer the index data 410 and the image element data 420 from the external memory 20 to the communication circuitry 320 when the processing system 110 is started. The second interface 310 can include an SPI, an I2C, or another suitable interface or a combination of these interfaces. In embodiments in which the first slave chip 200-S1 and the second slave chip 200-S2 have the same configuration as the configuration of the master chip 200-M, the first slave chip 200-S1 and the second slave chip 200-S2 can also include the second interface 310. In such embodiments, the second interface 310 of the first slave chip 200-S1 and the second interface 310 of the second slave chip 200-S2 can be disabled and disconnected from the external memory 20.

[0036] In one or more embodiments, the communication circuitry 320 includes control circuitry 322, first inter-chip communication circuitry 324, and second inter-chip communication circuitry 326. The control circuitry 322 is configured to transfer the index data 410 and the image element data 420 from the second interface 310 to the internal memory 330. The control circuitry 322 can be configured to transfer only the image element data 420 and the index data 410 associated with the image elements 21 that are to be displayed on the partial area 35 that is assigned to the master chip 200-M. In other embodiments, the control circuitry 322 can be configured to transfer the image element data 420 and the index data 410 associated with all of the image elements 21.

[0037] The control circuitry 322 can be further configured to control inter-chip communication between the communication circuitry 320 and one or more different IC chips 200, which can be adjacent IC chips 200. In one or more embodiments, the different IC chips 200 can include a first slave chip 200-S1 and a second slave chip 200-S2. The inter-chip communication with the different IC chips 200 can be used to transfer image element data. Additionally or alternatively, the inter-chip communication can be used to synchronize image processing in the IC chips 200.

[0038] The first inter-chip communication circuitry 324 and the second inter-chip communication circuitry 326 can be electrically connected to the communication circuitry 320 of the different IC chips 200. For example, as illustrated in Figure 7 The first inter-chip communication circuitry 324-M of the master chip 200-M can be connected to the second inter-chip communication circuitry 326-S1 of the first slave chip 200-S1, and the second inter-chip communication circuitry 326-M of the master chip 200-M can be connected to the first inter-chip communication circuitry 324-S2 of the second slave chip 200-S2. The IC chips 200 connected to the first inter-chip communication circuitry 324 can be different from the IC chips 200 connected to the second inter-chip communication circuitry 326.

[0039] Referring back to Figure 5 In one or more embodiments, the internal memory 330 is configured to store the image element data transferred from the control circuitry 322, and to output the image element data upon request from the image processing circuitry 340. The internal memory 330 includes, for example, a long horizontal blanking period (LHB) memory.

[0040] The image processing circuitry 340 can include overlap circuitry 342, an image intellectual property (IP) core 344, and register circuitry 346. In various embodiments, the overlap circuitry 342 is configured to generate an overlaid image 111 to be displayed on the display panel 30 based on the image elements 21, the input image 11, and the overlap control information 12. The overlap circuitry 342 can be configured to receive the overlap control information 12 and partial input image data representing a partial input image, which is a portion of the input image 11, from the first interface 300. The overlap circuitry 342 can be further configured to select one or more image elements 21 with which the partial input image is to be overlaid based on the overlap control information 12, and receive image element data representing the selected image elements 21 from the internal memory 330. In one or more embodiments, the overlap circuitry 342 is further configured to generate an overlaid image 111 in which the partial input image is overlaid with the selected image elements 21 based on the received image element data. The overlap circuitry 342 can be configured to output overlaid image data representing the generated overlaid image 111 to the image IP core 344. In other embodiments, the overlap circuitry 342 of each IC chip 200 can receive input image data, and extract partial input image data from the received input image data. In still other embodiments, the first interface 300 of each IC chip 200 can receive partial input image data corresponding to a partial area 35 assigned to that IC chip 200 from the external device 10, and transfer the received partial input image data to the overlap circuitry 342.

[0041] In one or more embodiments, the image IP core 344 is configured to generate a partial output image based on the overlaid image 111, which is to be displayed in a corresponding partial area 35 of the display panel 30. The image IP core 344 can be configured to receive overlaid image data representing the overlaid image 111 from the overlap circuitry 342, and generate partial output image data representing a partial output image by performing various types of image processing, such as gamma correction, on the received overlaid image data. The image IP core 344 can be configured to output the partial output image data representing the partial output image to the display panel driver circuitry 350.

[0042] The register circuitry 346 can be configured to store various types of setting information of the image processing circuitry 340. In various embodiments, the register circuitry 346 is configured to store the overlap control information 12 received from the external device 10 via the first interface 300, and output the stored overlap control information 12 to the overlap circuitry 342. The register circuitry 346 can store the image element control data 510 corresponding to all image elements 21 based on the overlap control information 12. The overlap control information 12 stored in the register circuitry 346 of each IC chip 200 can be the same.

[0043] In one or more embodiments, the display panel driver circuitry 350 is configured to drive the display panel 30 based on the partial output image generated by the image IP core 344. The display panel driver circuitry 350 can be configured to receive the partial output image data from the image IP core 344, and drive the display panel 30 based on the partial output image data. For example, the display panel driver circuitry 350 can be configured to drive the pixel circuits 31 in the partial area 35 corresponding to the IC chip 200 in which the display panel driver circuitry 350 is integrated. In one or more embodiments, the partial output image is displayed in each of the partial areas 35 of the display panel 30 by this operation, thereby displaying the complete output image on the display panel 30.

[0044] In one or more embodiments, each IC chip 200 includes a display driver section 360 configured to drive the display panel 30, and a touch detection section 370 configured to detect input to the display panel 30. The display driver section 360 can integrate the first interface 300, the communication circuitry 320, the internal memory 330, the image processing circuitry 340, and the display panel driver circuitry 350. The second interface 310 can be provided in the touch detection section 370 or the display driver section 360. In other embodiments, each circuitry of the processing system 110 can be provided in the display driver section 360 or the touch detection section 370.

[0045] Figure 6 An exemplary operation of the processing system 110 to drive the display panel 30 according to one or more embodiments is described. It should be noted that the order of the steps can be different from the described order. In the described embodiment, in step S110, the processing system 110 prepares to start image processing. The preparation can include, for example, preparation for generating the overlap image 111 from the input image 11 and the image elements 21 based on the overlap control information 12.

[0046] Reference Figure 7In one embodiment, the master chip 200-M receives the image element data 420 from the external memory 20 and transfers the received image element data 420 associated with other IC chips 200 to the other IC chips 200. For example, the master chip 200-M transfers first slave chip image element data 424 included in the received image element data 420 to the first slave chip 200-S1 and second slave chip image element data 426 to the second slave chip 200-S2.

[0047] The control circuitry 322-M of the master chip 200-M can determine a total data size based on the index data 410 stored in the external memory 20 by adding data sizes of the image element data corresponding to the IC chips 200. The control circuitry 322-M can fetch the index data 410 from the external memory 20 and extract data sizes of the image element data associated with each of the IC chips 200 from the index data 410. The control circuitry 322-M can determine a total data size of the image element data associated with each IC chip 200 based on the extracted data sizes.

[0048] The control circuitry 322-M of the master chip 200-M can further fetch the master chip image element data 422 from the external memory 20 and transfer the master chip image element data 422 to the internal memory 330-M. Fetching the master chip image element data 422 from the external memory 20 can be based on the total data size of the image element data corresponding to the master chip 200-M, i.e., based on the data size of the master chip image element data 422. In one or more embodiments, the internal memory 330-M stores the master chip image element data 422 received from the external memory 20. The control circuitry 322-M can transfer the master chip index data 412 to the internal memory 330-M.

[0049] In one or more embodiments, the control circuitry 322-M further retrieves the first slave chip image element data 424 from the external memory 20 and outputs the first slave chip image element data 424 to the first slave chip 200-S1. The control circuitry 322-M can retrieve the first slave chip image element data 424 from the external memory 20 based on a total data size of image element data corresponding to the first slave chip 200-S1 (i.e., based on a data size of the first slave chip image element data 424). The control circuitry 322-M can transfer the first slave chip image element data 424 to the control circuitry 322-S1 of the first slave chip 200-S1 via the first inter-chip communication circuitry 324-M of the master chip 200-M and the second inter-chip communication circuitry 326-S1 of the first slave chip 200-S1. In one or more embodiments, the control circuitry 322-S1 of the first slave chip 200-S1 transfers the first slave chip image element data 424 to the internal memory 330-S1, and the internal memory 330-S1 stores the first slave chip image element data 424.

[0050] The control circuitry 322-M of the master chip 200-M can transfer the first slave chip index data 414 to the control circuitry 322-S1 of the first slave chip 200-S1. In such embodiments, the control circuitry 322-S1 can transfer the first slave chip index data 414 to the internal memory 330-S1, and the internal memory 330-S1 can store the first slave chip index data 414.

[0051] In one or more embodiments, the control circuitry 322-M further retrieves the second slave chip image element data 426 from the external memory 20 and outputs the second slave chip image element data 426 to the second slave chip 200-S2. The control circuitry 322-M can retrieve the second slave chip image element data 426 from the external memory 20 based on a total data size of image element data corresponding to the second slave chip 200-S2 (i.e., based on a data size of the second slave chip image element data 426). The control circuitry 322-M can transfer the second slave chip image element data 426 to the control circuitry 322-S2 of the second slave chip 200-S2 via the second inter-chip communication circuitry 326-M of the master chip 200-M and the first inter-chip communication circuitry 324-S2 of the second slave chip 200-S2. In one or more embodiments, the control circuitry 322-S2 of the second slave chip 200-S2 transfers the second slave chip image element data 426 to the internal memory 330-S2, and the internal memory 330-S2 stores the second slave chip image element data 426.

[0052] The control circuitry 322-M of the master chip 200-M can additionally transfer the second slave chip index data 416 to the control circuitry 322-S2 of the second slave chip 200-S2. In such embodiments, the control circuitry 322-S2 can transfer the second slave chip index data 416 to the internal memory 330-S2, and the internal memory 330-S2 can store the second slave chip index data 416.

[0053] In one or more embodiments, in step S120 described in Figure 6 In step S120 described in

[0054] Figure 8 An exemplary operation of the respective IC chip 200 in which the individual control information is generated is described. In Figure 8 In the illustrated embodiment, the control circuitry 322 of each of the IC chips 200 determines that the preparation for generating the overlay image 111 by the overlay circuitry 342 is completed based on completion of storing the image element data in the internal memory 330. The control circuitry 322 of each of the IC chips 200 can determine that the preparation for generating the overlay image 111 by the overlay circuitry 342 is completed at the time of completion of storing the image element data in the internal memory 330. In Figure 8 In the illustrated embodiment, the control circuitry 322-S1 of the first slave chip 200-S1 completes the preparation for image processing in frame 5, and sends the individual control information to the control circuitry 322-M of the master chip 200-M, as indicated by the arrow 600. Also, the control circuitry 322-S2 of the second slave chip 200-S2 completes the preparation for image processing in frame 8, and sends the individual control information to the control circuitry 322-M of the master chip 200-M, as indicated by the arrow 601. The control circuitry 322-M of the master chip 200-M completes the preparation for image processing in frame 8, and generates the individual control information. The individual control information can be sent, for example, in the front porch period.

[0055] Referring back to Figure 6 In step S130, the master chip 200-M can generate the global control information using the individual control information generated by each of the IC chips 200, and then send the global control information to the other IC chips 200. In Figure 8In the embodiment illustrated in FIG. 6, the control circuitry 322-M of the master IC chip 200-M receives the individual control information from the first slave IC chip 200-S1 in frame 5 and the individual control information from the second slave IC chip 200-S2 in frame 8. The master IC chip 200-M completes the preparation for the image processing in frame 8 and generates its individual control information. Then, the master IC chip 200-M generates the global control information represented by arrow 610 in frame 9 and transmits the global control information to the first slave IC chip 200-S1 and the second slave IC chip 200-S2. The global control information can be transmitted, for example, in the front porch period.

[0056] In Figure 6 Step S140, the IC chip 200 can perform the image processing using the global control information from the master IC chip 200-M. For example, the control circuitry 322 of each IC chip 200 can transmit a start instruction to the image processing circuitry 340, thereby enabling the generation of the partial output image. In one embodiment, as illustrated in FIG. 6, the start instruction can be transmitted during the front porch period. Figure 8

[0057] In one or more embodiments, in step S140 of FIG. 4, the overlap circuitry 342 in each IC chip 200 starts the image processing based on the start instruction. The image processing can include generating the overlap image 111 from the input image 11 and the image elements 21 based on the overlap control information 12. When the state value of the first image element control data 510-1 included in the overlap control information 12 is, for example, “1”, the corresponding portion of the overlap image 111 is generated by overlapping the partial input image with the first image element. When the state value of the first image element control data 510-1 is “0”, the overlap circuitry 342 generates the portion of the overlap image 111 without overlapping the partial input image with the first image element. The state values “0” and “1” of the first image element control data 510-1 are merely examples, and any values can be used instead. The overlap circuitry 342 can further extract the position at which the partial input image is to be overlapped with the first image element from the index data 410. Figure 6

[0058] In one or more embodiments, the overlap circuitry 342 selectively fetches from the register circuitry 346 only the image element control data 510 corresponding to the one or more image elements 21 that are to be displayed in the corresponding partial area 35. For example, when the second image element corresponding to the second image element control data 510-2 is not to be displayed in the corresponding partial area 35, the overlap circuitry 342 generates the corresponding portion of the overlap image 111 without fetching the second image element control data 510-2.

[0059] ​​In one or more embodiments, after the superimposed image 111 is generated, the image IP core 344 of each IC chip 200 generates a partial output image for driving the display panel 30 by performing image processing on the superimposed image 111 in step S150. The image IP core 344 can output partial output image data representing the partial output image to the display panel driver circuitry 350.

[0060] In one or more embodiments, in step S160, the display panel driver circuitry 350 of each IC chip 200 drives the display panel 30 based on the partial output image. In various embodiments, the display panel 30 displays the partial output image on the partial area 35, thereby displaying a complete output image in which the input image 11 overlaps with the desired one or more of the image elements 21.

[0061] In embodiments in which the processing system 110 is configured to detect an abnormality in communication with the external device 10, the processing system 110 can be configured to generate a superimposed image 111 in which an abnormality image, such as a solid black image, is superimposed on an image element 21 indicating detection of an abnormality (which image element 21 can be referred to hereinafter as an “abnormality-indicating image element”). The abnormality in communication can arise from noise applied to the communication line, desynchronization between the external device 10 and the processing system 110, or other causes. Figure 9 An exemplary configuration of the processing system 110 suitable for abnormality detection is described. Each IC chip 200 can include detection circuitry 380 configured to detect an abnormality in communication between the external device 10 and the IC chip 200. The detection circuitry 380 can be configured to output abnormality detection information to the register circuitry 346 when the detection circuitry 380 detects an abnormality in communication with the external device 10. The abnormality detection information can include information indicating that an abnormality was detected and / or information indicating the type of abnormality. The register circuitry 346 can be configured to store the abnormality detection information as part of the image element control data 510.

[0062] The overlay circuitry 342 can be configured to receive the anomaly image and the anomaly indication image element data representing the anomaly indication image element, and generate the overlay image 111 in which the anomaly image is overlaid with the anomaly indication image element. The anomaly image can be stored in the internal memory 330. In other embodiments, the circuitry integrated in each IC chip 200, such as the first interface 300 or the image processing circuitry 340, can be configured to generate the anomaly image. As with other image element data, the anomaly indication image element data can be transferred from the external memory 20 to the internal memory 330 at the start of the IC chip 200. The overlay circuitry 342 can be configured to receive the image element control data 510 indicating the anomaly detection from the register circuitry 346, and fetch the anomaly indication image element data from the internal memory 330 based on the received image element control data 510. The overlay circuitry 342 can be configured to generate the overlay image 111 in which the anomaly image is overlaid with the anomaly indication image element.

[0063] In such embodiments, the image IP core 344 can be configured to generate a partial output image based on the overlay image 111, and output partial output image data representing the generated partial output image to the display panel driver circuitry 350, and the display panel driver circuitry 350 can be configured to drive the display panel 30 based on the thus generated partial output image data. This results in the display panel 30 displaying an image indicating that an anomaly is detected.

[0064] In one or more embodiments, an image indicating that an anomaly is detected can be displayed on the display panel 30 based on the anomaly being detected by the IC chip 200 as described above. The detection circuitry 380 can be configured to detect any type of anomaly. For example, the detection circuitry 380 can be configured to detect a failure of the circuitry integrated in the IC chip 200. In such embodiments, the detection circuitry 380 can be configured to output anomaly detection information corresponding to the type of anomaly detected, and the external memory 20 can be configured to store anomaly indication image element data for each type of anomaly. This can allow the processing system 110 to display the type of anomaly on the display panel 30 based on the anomaly indication image element data corresponding to the anomaly detected being stored in the external memory 20.

[0065] In one or more embodiments, the detection circuitry 380 may be configured to output anomaly detection information to a register circuitry 346 integrated in different IC chips 200. In such embodiments, the anomaly detection information may be sent from a first inter-chip communication circuitry 324 of the communication circuitry 320 or from a second inter-chip communication circuitry 326 of the communication circuitry 320 to different IC chips 200. This allows the processing system 110 to display an image based on an anomaly detected by one of the IC chips 200, the image indicating an anomaly in a portion 35 corresponding to a different IC chip 200.

[0066] Figure 10 An exemplary configuration of the processing system 110 according to other embodiments is described. In the described embodiment, at least one IC chip 200 may include a third interface 390 electrically connected to the second interface 310. The third interface 390 may be configured to receive... Figure 3 The image element data 420 and index data 410 described herein are transferred to external memory 20 via a second interface 310. A third interface 390 may include, for example, an SPI, I2C interface, or the like. This facilitates the storage of image element data in external memory 20. The third interface 390 may be located in a touch detection section 370 or a display driver section 360.

[0067] Figure 11 Exemplary configurations of display systems according to other embodiments are described. In the described embodiments, each IC chip 200 is configured to directly receive image element data representing image element 21 from external memory 20. In such embodiments, external memory 20 may be connected to a second interface 310 of each IC chip 200. External memory 20 may be configured to output all image element data to each IC chip 200 or to output image element data representing one or more image elements 21 to each IC chip 200, which will be displayed in a partial area 35 allocated to the IC chip 200.

[0068] For example, the control circuitry 322-M of the master IC chip 200-M can be configured to receive, from the external memory 20 via the second interface 310-M, master chip image element data 422 representing one or more image elements 21 to be displayed on the partial area 35-M corresponding to the master IC chip 200-M, and store the received master chip image element data 422 in the internal memory 330-M. The control circuitry 322-S1 of the first slave IC chip 200-S1 can be configured to receive, from the external memory 20 via the second interface 310-S1, first slave chip image element data 424 representing one or more image elements 21 to be displayed on the partial area 35-S1 corresponding to the first slave IC chip 200-S1, and store the received first slave chip image element data 424 in the internal memory 330-S1. The control circuitry 322-S2 of the second slave IC chip 200-S2 can be configured to receive, from the external memory 20 via the second interface 310-S2, second slave chip image element data 426 representing one or more image elements 21 to be displayed on the partial area 35-S2 corresponding to the second slave IC chip 200-S2, and store the received second slave chip image element data 426 in the internal memory 330-S2.

[0069] In other embodiments, the control circuitry 322 of each IC chip 200 can be configured to receive, from the external memory 20, image element data 420 representing all image elements 21. The control circuitry 322 can be configured to store, in the internal memory 330, image element data representing one or more image elements 21 to be displayed on the corresponding partial area 35.

[0070] In one or more embodiments, each IC chip 200 is configured to switch operation modes by a predetermined setting. For example, the IC chip 200 can operate as the master IC chip 200-M in a first operation mode. The IC chip 200 can operate as the first slave IC chip 200-S1 in a second operation mode. The IC chip 200 can operate as the second slave IC chip 200-S2 in a third operation mode. The IC chip 200 can operate in one of the first to third operation modes depending on the setting. The setting of the IC chip 200 can be determined during assembly of the display system incorporating the IC chip 200 depending on the partial area corresponding to the IC chip 200.

[0071] The following is also an embodiment of the present disclosure.

[0072] In one or more embodiments, a processing system is provided. The processing system includes a first IC chip and a second IC chip. The first IC chip includes first image processing circuitry configured to generate a first partial output image by first image processing, first display panel driver circuitry configured to drive a display panel based on the first partial output image, and first communication circuitry. The second IC chip includes second image processing circuitry configured to generate a second partial output image by second image processing, second display panel driver circuitry configured to drive the display panel based on the second partial output image, and second communication circuitry configured to generate individual control information based on completion of preparation for initiating the second image processing. The first communication circuitry is configured to generate overall control information based on receiving the individual control information from the second communication circuitry and completion of preparation for initiating the first image processing. The first image processing circuitry is further configured to initiate the first image processing based on the overall control information. The second image processing circuitry is further configured to initiate the second image processing based on the overall control information.

[0073] The first image processing can generate a first overlay image as the first partial output image in which the first partial input image overlaps with first image elements.

[0074] The second image processing can generate a second overlay image as the second partial output image in which the second partial input image overlaps with second image elements.

[0075] In one or more embodiments, an IC chip is provided. The IC chip includes image processing circuitry configured to generate a partial output image by first image processing, display panel driver circuitry configured to drive a display panel based on the partial output image, and communication circuitry configured to generate overall control information based on receiving first individual control information and completion of preparation for the first image processing by the image processing circuitry, the first individual control information being generated based on completion of preparation for second image processing in a different IC chip. The image processing circuitry is further configured to initiate the first image processing based on the overall control information.

[0076] Generating the overall control information can include generating the overall control information based on receiving the first individual control information and completion of preparation for the first image processing in a first operating mode. The communication circuitry can be further configured to generate second individual control information based on completion of preparation for the first image processing in the image processing circuitry, and output the second individual control information to the different IC chip in a second operating mode.

[0077] The communication circuitry can be configured to output the global control information to the different IC chips.

[0078] The first image processing generates an overlap image as a partial output image in which the partial input image overlaps with image elements.

[0079] A method for driving a display panel is also provided. In one or more embodiments, the method includes sending individual control information to the first IC chip based on completion of preparation for starting the second image processing in the second IC chip; generating, by the first IC chip, global control information based on receiving the individual control information from the second IC chip and completion of preparation for starting the first image processing in the first IC chip; starting, by the second IC chip, the second image processing based on the global control information; starting, by the first IC chip, the first image processing based on the global control information; and driving the display panel based on a first partial output image generated by the first image processing and a second partial output image generated by the second image processing.

[0080] The first image processing can generate a first overlap image as a first partial output image in which the first partial input image overlaps with first image elements. The second image processing can generate a second overlap image as a second partial output image in which the second partial input image overlaps with second image elements.

[0081] Although various embodiments of the present disclosure are specifically described above, examples of various modifications of the present disclosure can be implemented by changing the technology described in the specification.

[0082] Reference Signs

[0083] frame 5 frame 8 frame 9 external device 10 input image 11 superimposition control information 12 external memory 20 image element(s) 21 image element 21 display panel 30 pixel driving circuit 31 source line 32 gate line 33 partial area 35 partial area(s) 35 processing system 110 superimposed image 111 IC chip 200 first interface 300 second interface 310 communication circuit system 320 control circuit system 322 chip communication circuit system 324 chip communication circuit system 326 internal memory 330 image processing circuit system 340 superimposition circuit system 342 image IP core 344 register circuit system 346 display panel driver circuit system 350 display driver section 360 touch detection section 370 detection circuit system 380 third interface 390 index data 410 master chip index data 412 first slave chip index data 414 second slave chip index data 416 image element data 420 master chip image element data 422 first slave chip image element data 424 second slave chip image element data 426 image element control data 510

Claims

1. A processing system comprising: a first integrated circuit (IC) chip; and a second IC chip, wherein the first IC chip comprises: a first interface configured to receive first image element data and second image element data from an external memory located outside the processing system, wherein the first image element data represents first image elements; first communication circuitry configured to transfer the first image element data to first image processing circuitry and the second image element data to the second IC chip based on attribute information of the first image element data and the second image element data received from the external memory, wherein the first image processing circuitry is configured to generate a first overlaid image by overlapping a first partial input image extracted from a first input image with the first image elements based on the first image element data; first display panel driver circuitry configured to drive a display panel based on the first overlaid image, wherein the first IC chip further comprises a third interface configured to receive first partial input image data representing the first partial input image and overlap control information indicating whether the first image elements are to be displayed, and wherein the first image processing circuitry is further configured to: receive the first partial input image data and the overlap control information from the third interface; and generate the first overlaid image further based on the overlap control information. the first IC chip further comprises detection circuitry configured to detect an anomaly, 2. The processing system of claim 1, wherein, wherein the first image processing circuitry is further configured to generate a second overlaid image based on the detection of the anomaly, the second overlaid image including an anomaly image overlaid with an anomaly indication image element indicating the anomaly; and wherein the first display panel driver circuitry is further configured to drive the display panel based on the second overlaid image. the second IC chip comprises:

3. The processing system of claim 1, wherein, second communication circuitry configured to receive the second image element data from the first IC chip; second image processing circuitry configured to generate a second overlaid image by overlapping a second partial input image with second image elements based on the second image element data; and second display panel driver circuitry configured to drive the display panel based on the second overlaid image, wherein the second IC chip further comprises an interface configured to receive second partial input image data and overlap control information indicating whether the second image elements are to be displayed, and wherein the second image processing circuitry is further configured to: receive the overlap control information and the second partial input image data representing the second partial input image from the interface; and generate the second overlaid image based on the overlap control information. the second communication circuitry is configured to generate individual control information based on completion of preparation for generating the second overlaid image by the second image processing circuitry, 4. The processing system of claim 3, wherein, ​ wherein the first communication circuitry is configured to generate overall control information based on receiving the individual control information and the first image processing circuitry being ready to generate the first overlay image, wherein the first image processing circuitry is further configured to generate the first overlay image using the overall control information, and wherein the second image processing circuitry is configured to generate the second overlay image using the overall control information.

5. The processing system of claim 4, wherein, The first IC chip further includes an internal memory, and the first communication circuitry is further configured to: store the first image element data in the internal memory; and determine that the first image processing circuitry is ready to generate the first overlay image in response to completing storing the first image element data into the internal memory.

6. The processing system of claim 4, wherein, The second IC chip further includes an internal memory, and wherein the second communication circuitry is further configured to: store the second image element data in the internal memory, and determine that the second image processing circuitry is ready to generate the second overlay image in response to completing storing the second image element data into the internal memory.

7. The processing system of claim 3, wherein, The first IC chip further includes detection circuitry configured to detect an anomaly and generate anomaly detection information based on the detection of the anomaly, wherein the second image processing circuitry is further configured to generate a third overlay image based on the anomaly detection information, the third overlay image including an anomaly image overlaid with an anomaly indication image element indicating the anomaly, and wherein the second display panel driver circuitry is further configured to drive the display panel based on the third overlay image.

8. An integrated circuit (IC) chip, comprising: a first interface configured to receive first image element data and second image element data from an external memory located outside of a processing system, wherein the first image element data represents first image elements; first communication circuitry configured to transfer the first image element data to first image processing circuitry and the second image element data to a second IC chip based on attribute information of the first image element data and the second image element data received from the external memory, wherein the first image processing circuitry is configured to generate a first overlay image by overlaying a first partial input image extracted from a first input image with the first image elements based on the first image element data; and first display panel driver circuitry configured to drive a display panel based on the first overlay image, wherein the IC chip further includes a third interface configured to receive first partial input image data representing the first partial input image and overlay control information indicating whether the first image elements are to be displayed, and wherein the first image processing circuitry is further configured to: receive the first partial input image data and the overlay control information from the third interface; and generating the first overlay image further based on the overlap control information.

9. The IC chip of claim 8, wherein, the IC chip further includes detection circuitry configured to detect an anomaly, wherein the first image processing circuitry is further configured to generate a second overlay image based on the detection of the anomaly, the second overlay image including an anomaly image overlaid with an anomaly indication image element indicating the anomaly; and wherein the first display panel driver circuitry is further configured to drive the display panel based on the second overlay image.

10. The IC chip of claim 8, wherein, the IC chip further includes internal memory, and the first communication circuitry is further configured to: store the first image element data in the internal memory; and determine that the first image processing circuitry is ready to generate the first overlay image in response to completion of storing the first image element data into the internal memory.

11. A method comprising: receiving, by a first integrated circuit (IC) chip, first image element data and second image element data from an external memory, wherein first image element data represents first image elements; generating, by the first IC chip, a first overlay image, the first overlay image including first partial input images extracted from a first input image overlaid with the first image elements; driving, by the first IC chip, a display panel using the first overlay image; outputting, by the first IC chip, the second image element data representing second image elements to a second IC chip; generating, by the second IC chip, a second overlay image using the second image element data, the second overlay image including second partial input images overlaid with the second image elements; and driving, by the second IC chip, the display panel using the second overlay image, further comprising receiving, by the first IC chip, the first partial input images and overlap control information indicating whether the first image elements are to be displayed, wherein generating the first overlay image includes generating the first overlay image based on the overlap control information, further comprising: generating, by the second IC chip, individual control information based on completion of preparation for generating the second overlay image; and generating, by the first IC chip, overall control information based on receiving the individual control information from the second IC chip and completion of preparation for generating the first overlay image, wherein generating the first overlay image includes generating the first overlay image based on the overall control information, and wherein generating the second overlay image includes generating the second overlay image based on the overall control information.

12. The method of claim 11, further comprising storing first image element data representing the first image elements in a first internal memory of the first IC chip, wherein generating the overall control information includes determining the completion of the preparation for generating the first overlay image based on storing the first image element data in the first internal memory.

13. The method of claim 11, further comprising storing the second image element data in a second internal memory of the second IC chip, wherein generating the individual control information includes determining completion of preparation for generating the second overlaid image.

Images