Semiconductor package and method of manufacturing the same

Abstract

Embodiments of the present disclosure relate to a semiconductor package including a substrate, a conductive post, and a metal layer. The substrate has a first surface, a second surface opposite the first surface, and an opening extending from the first surface to the second surface. The opening has a sidewall, and the conductive post is disposed in the opening. The metal layer is disposed in the substrate. The metal layer is substantially at the same level as the conductive post. Another embodiment of the present disclosure relates to a method of manufacturing a semiconductor package.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor packages and methods of manufacturing the same, and more particularly, to semiconductor packages having a metal layer and an insulating layer encapsulating the metal layer. BACKGROUND

[0002] As the demand for higher circuit density per unit volume increases, reducing line width / space (L / S) is one way to increase circuit density per unit volume. However, as line width / space is reduced, solder bridges can be created due to unavoidable drum-side effects during soldering, which can cause short circuits. This problem is often overlooked in older wider pitch (e.g., line width greater than 20 microns) structures. SUMMARY

[0003] Embodiments of the present disclosure relate to a semiconductor package. The semiconductor package includes a substrate, a conductive post, and a metal layer. The substrate has a first surface, a second surface opposite the first surface, and an opening extending from the first surface to the second surface. The opening has sidewalls, and the conductive post is disposed in the opening. The metal layer is disposed in the substrate. The metal layer is substantially at the same horizontal level as the conductive post.

[0004] Embodiments of the present disclosure relate to a semiconductor package. The semiconductor package includes a substrate, an insulating layer, and a metal layer. The substrate has a first surface, a second surface opposite the first surface, and an opening extending from the first surface to the second surface. The opening has sidewalls. The insulating layer has a first surface substantially coplanar with the first surface of the substrate. The metal layer is disposed in the substrate and in contact with the insulating layer.

[0005] Embodiments of the present disclosure relate to a method of manufacturing a semiconductor package. The method includes providing a carrier; forming an insulating layer on the carrier; forming a metal layer on the insulating layer; forming a substrate on the carrier covering the insulating layer and the metal layer; and forming a first opening in the substrate to expose a portion of a surface of the carrier. BRIEF DESCRIPTION OF DRAWINGS

[0006] Various aspects of at least one embodiment are discussed in the following reference to the accompanying drawings, in which:

[0007] Figure 1 A cross-sectional view of a semiconductor package according to some embodiments of the present application is shown;

[0008] Figure 2 A perspective view of a semiconductor package according to some embodiments of the present application is shown;

[0009] Figure 3 A cross-sectional view of a semiconductor package according to some embodiments of the present application is shown;

[0010] Figure 4 A cross-sectional view of a semiconductor package according to some embodiments of the present application is shown;

[0011] Figures 5A to 5M One or more stages in a method of manufacturing a semiconductor package according to some embodiments of the present application are shown; and

[0012] Figure 6A And 6B Various types of semiconductor packages according to some embodiments of the present application are shown. DETAILED DESCRIPTION

[0013] According to some embodiments, the present application provides a semiconductor package incorporating fine pitch interconnect structures embedded within a single dielectric layer and separated by insulating layers and conductive contacts. Thus, tin bridging can be avoided. Furthermore, using only a single dielectric layer, increased circuit density per unit volume can be achieved without the need for multi-layer structures, which would reduce the thickness and manufacturing cost of the semiconductor package device, and avoid warpage due to increased thickness.

[0014] Referring to Figure 1 , Figure 1FIG. 1 shows a cross-sectional view of a semiconductor package 1 according to some embodiments. The semiconductor package 1 includes a substrate 10, a conductive contact 11, a seed layer 12, a metal layer 13, a conductive pillar 14, a metal layer 15, an electrical connection 16, an electronic component 17, an underfill 18, an encapsulant 19, and an insulating layer 101.

[0015] In some embodiments, the substrate 10 can include, but is not limited to, a solder mask, a Polyimide (PI), an Ajinomoto Build-Up Film (ABF), a molding compound, a pre- impregnated composite fiber (e.g., a prepreg), a borophosphosilicate glass (BPSG), a silicon oxide, a silicon nitride, a silicon oxynitride, an undoped silicate glass (USG), and combinations thereof, or other similar materials. Examples of the molding compound can include, but are not limited to, an epoxy resin including fillers dispersed therein. Examples of the prepreg can include, but are not limited to, a multi-layer structure formed by stacking or laminating multiple prepregs and / or sheets.

[0016] The substrate 10 has a surface 10a, a surface 10b opposite to the surface 10a, and a surface 10s connecting the surface 10a and the surface 10b. The surface 10a and the surface 10s form an inner recessed angle 10c. In some embodiments, the inner recessed angle 10c is between 0 degree and 90 degree. In some embodiments, the inner recessed angle 10c is less than 80 degree. In some embodiments, the inner recessed angle 10c is less than 70 degree. In some embodiments, the inner recessed angle 10c is less than 65 degree. The substrate 10 has an opening from the surface 10a to the surface 10b, and the surface 10s forms a sidewall of the opening. In some embodiments, the surface 10s has a single slope, for example, the surface 10s has substantially equal slope from the surface 10a to the surface 10b. In some embodiments, the opening tapers from the surface 10b to the surface 10a. For example, the opening width of the surface 10b is greater than the opening width of the surface 10a. In some embodiments, the substrate 10 can have a thickness of about 2.5 micrometers to about 10 micrometers.

[0017] A conductive post 14 is disposed in the opening of the substrate 10. For example, the conductive post 14 is located between the surface 10a and the surface 10b, in contact with and surrounded by the surface 10s. The conductive post 14 is spaced apart from the surface 10a. In a direction from the surface 10b to the surface 10a, the conductive post 14 includes layers 14a, 14b, and 14c. In some embodiments, any of the layers 14a, 14b, and 14c can include, but are not limited to, copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), or other metals or alloys. For example, the layer 14a can be a connection layer including copper, gold, silver, or aluminum. The layer 14b can be a buffer layer including nickel, titanium, or tungsten. The layer 14c can be a soldering layer including tin, copper, gold, silver, or aluminum.

[0018] A conductive contact 11 is formed on the surface 10a and electrically connected with the conductive post 14. The conductive contact 11 includes a portion 11a and a portion 11b. The portion 11a is surrounded by the substrate 10 and in contact with the sidewall 10s, and the portion 11b protrudes from the surface 10a and the portion 11a. The conductive contact 11 is surrounded by and in contact with the inner recessed corner 10c. In some embodiments, the conductive contact 11 can include, but is not limited to, a solder ball or a land grid array (LGA).

[0019] A metal layer 15 is located in the substrate 10 and substantially at the same horizontal level as the conductive post 14. For example, the metal layer 15 and the conductive post 14 are located between the surface 10a and the surface 10b. The metal layer 15 is spaced apart from the surface 10a. The metal layer 15 and the conductive post 14 are surrounded by the substrate 10 (e.g., the same substrate 10, a single substrate 10) and spaced apart from each other. For example, a portion of the substrate 10 is located between the metal layer 15 and the conductive post 14. In a direction from the surface 10b to the surface 10a, the metal layer 15 includes layers 15a and 15b. In some embodiments, any of the layers 15a and 15b can include, but are not limited to, copper, gold, silver, aluminum, nickel, titanium, tungsten, tin, or other metals or alloys. In some embodiments, the pitch (e.g., L / S) of the metal layer 15 is smaller than the pitch of the seed layer 12 and the metal layer 13 embedded in the package 19. In some embodiments, the pitch (e.g., L / S) of the metal layer 15 is smaller than 7 / 7 microns, smaller than 2 / 2 microns, or smaller. In some embodiments, the metal layer 15 can form a redistribution layer (RDL).

[0020] An insulating layer 101 is between the surface 10a of the substrate 10 and the metal layer 15. The insulating layer 101 and the substrate 10 enclose the metal layer 15. The insulating layer 101 insulates and separates the metal layer 15 from the conductive pads 11. The insulating layer 101 has a surface 101a that is substantially coplanar with the surface 10a of the substrate 10 and a surface 101b opposite the surface 101a. The metal layer 15 is in contact with the surface 101b. The metal layer 15 is between the surface 101b and the surface 10b of the substrate 10. In some embodiments, the insulating layer 101 can have materials as listed above for the substrate 10, such as an epoxy resin including fillers, which can be, for example, particulate, network, cross-grid, etc.

[0021] The insulating layer 101 can have the same or different materials as the substrate 10. In some embodiments, an interface 101i is formed between the insulating layer 101 and the substrate 10, which is substantially coplanar with one side surface of the metal layer 15. For example, the insulating layer 101 is substantially equal in width to the metal layer 15. In some embodiments, the insulating layer 101 can have a thickness of about 1 micron to about 3 microns. In some embodiments, the insulating layer 101 and the metal layer 15 can have a thickness of about 1 micron to about 3 microns.

[0022] Continuing to refer to Figure 1 The seed layer 12 and the metal layer 13 are on the surface 10b and electrically connected to the conductive posts 14. In some embodiments, the seed layer 12 and the metal layer 13 can have materials as listed above for the metal layer 15. The seed layer 12 and the metal layer 13 can be completely covered or encapsulated by the encapsulant 19, as shown in Figure 1 In some embodiments, portions of the seed layer 12 and the metal layer 13 can be exposed from the encapsulant 19, which exposed portions can be further connected to other electronic components or other circuitry.

[0023] The electronic component 17 is disposed on the surface 10b of the substrate 10. The electronic component 17 can be an active component, a passive component, or a combination thereof. The active component can be an integrated chip (IC) or a die. The passive component can be a capacitor, a resistor, or an inductor. The electronic component 17 can be electrically connected to one or more of the remaining electronic components, the substrate 10 (e.g., a connection RDL), or the conductive posts 14. The electrical connection can be achieved by flip chip or wire bonding techniques. For example, the electrical connections 16 electrically connect the electronic component 17 and the metal layer 13. The electronic component 17 is electrically connected to the conductive posts 14 through the electrical connections 16 and the metal layer 13.

[0024] One or more electrical connectors 16 are attached to the surface of the electronic component 17. The electrical connectors 16 may be, for example, conductive pads, solder balls, copper pillars, microbumps (μBump), other feasible electrical connectors, or combinations thereof. The electrical connectors 16 may be covered or encapsulated by an underfill 18.

[0025] The underfill 18 may include (but is not limited to) epoxy resin, molding compound (e.g., epoxy molding compound or other molding compound), PI, phenolic compound or material, material containing silicone dispersed therein, non-conductive paste (NCP), or non-conductive film (NCF).

[0026] Electronic component 17 is covered or encapsulated by package 19. Electronic component 17 may have its sidewalls covered or encapsulated by package 19, while its top is exposed from package 19, such as... Figure 2 As shown. In some embodiments, electronic component 17 may be completely covered or encapsulated by package 19, with its top not exposed from package 19.

[0027] In some embodiments, the encapsulation 19 comprises epoxy resin, molding compound (e.g., epoxy molding compound or other molding compound), PI, phenolic compound or material, material containing silicone dispersed therein, NCP, or NCF. In some embodiments, the encapsulation 19 has the same material as the underfill 18. In some embodiments, the encapsulation 19 and the underfill 18 have different materials.

[0028] Although the figures disclosed herein depict a single dielectric layer (e.g., a single-layer substrate 10), the semiconductor package of the present invention may also have more than one dielectric layer, such as an interposer between the substrate 10 and the package 19, and the interposer may contain any number of RDL layers.

[0029] Reference Figure 2 , Figure 2 The diagram shown is a perspective view of a semiconductor package 2 according to certain embodiments of this invention. In the drawings disclosed herein, identical or similar components are designated by the same component symbols, and detailed descriptions of these components will not be repeated.

[0030] like Figure 1 As shown, substrate 10 has a surface 10a and a surface 10b opposite to surface 10a. Substrate 10 has an upper layer and a lower layer. Metal layer 15 is located in the lower layer of substrate 10 and covers or encapsulates insulating layer 101 and substrate 10. Conductor 21w is located on surface 10b of substrate 10 and connects to contacts 21a and 21b. Contacts 21a and / or 21b can be further electrically connected to other electronic components (e.g., Figure 2electronic components 17 are not shown in Figure 2 and conductive contacts 11.

[0031] The metal layer 15 forms a line (e.g., RDL) in the substrate 10, and the insulating layer 101 extends together with the metal layer 15, e.g., the insulating layer 101 covers the bottom of the metal layer 15.

[0032] The metal layer 15 extends in the relatively lower layer and has an end point connected to the contact 21a through a conductive via, and the contact 21a is connected to the contact 21b through a line 21w. Figure 3 The configuration of the lines and components shown is merely an exemplary example, and the present application is not limited thereto. The configuration of the insulating layer 101 and the metal layer 15 can be changed according to requirements and device specifications. For example, in other embodiments, the metal layer 15 can be directly connected to the contact 21b in the relatively lower layer. In other embodiments, the metal layer 15 can be directly connected to the conductive contact 11 in the relatively lower layer.

[0033] Referring to Figure 3 , Figure 3 Fig. 4 shows a cross-sectional view of a semiconductor package 4 according to some embodiments of the present application. Figure 1 The semiconductor package 4 is similar to the semiconductor package 1 of Figure 1 Fig. 1, with the difference that Figure 3 The inner corner 10c of the semiconductor package 1 is an acute angle, Figure 4 The inner corner 10c of the semiconductor package 3 has a rounded or rounded-like shape. For example, the portion thereof contacting the conductive contact 11 is arc-shaped, or has an arc-shaped end point. The design of the rounded corner helps to avoid stress concentration at the tip of the inner corner 10c, and improves the ability to resist lateral stress. The inner corner 10c of the semiconductor package 3 can be shaped by dry etching, ion bumping, or other feasible means.

[0034] Referring to Figure 4 , Figure 4 Fig. 4 shows a cross-sectional view of a semiconductor package 4 according to some embodiments of the present application. Figure 1 The semiconductor package 4 is similar to the semiconductor package 1 of Figure 1 Fig. 1, with the difference that Figure 4 The metal layer 15 of the semiconductor package 1 is a relatively small-sized line, Figures 5A to 5MThe metal layer 15 of the semiconductor package 4 is a relatively large pad. The size of the metal layer 15 can vary depending on the requirements and device specifications. Since the metal layer 15 disclosed herein is isolated from the conductive contact 11 by the insulating layer 101, a short circuit between the metal layer 15 and the conductive contact 11 can be avoided. Therefore, the distance between the metal layer 15 and the conductive contact 11 can be smaller, and the size design of the metal layer 15 has greater flexibility.

[0035] Reference Figures 5A to 5M , Figure 5A The illustration shows one or more stages in a method for manufacturing a semiconductor package according to certain embodiments of this case.

[0036] Reference Figure 5B A carrier 20 is provided, and an insulating layer 101 is formed on the carrier 20. The carrier 20 may be a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate. In some embodiments, the carrier 20 may be a copper plate or other conductive carrier. In some embodiments, the carrier 20 may be non-conductive but has a metal foil on its upper surface. In some embodiments, the carrier 20 may include internal interconnection structures, such as RDLs.

[0037] Reference Figure 5C Metal layers 15, including layers 15a (e.g., seed layers) and 15b, are formed on insulating layer 101. In some embodiments, layer 15a may be formed by sputtering titanium and copper (Ti / Cu) or TiW. In some embodiments, layer 15a may be formed by electroless plating of Ni or Cu. Layer 15b is formed on layer 15a. In some embodiments, layer 15b may be formed by plating Ni, Cu, Ag, Au, or other metals. In some embodiments, layer 15b may be formed by electroless plating of Ni, Pb, or other metals. In some embodiments, layer 15b may be formed by printing Cu, Ag, Au, or other metals.

[0038] Reference Figure 5DThe patterned metal layer 15 and the insulating layer 101 are patterned and the substrate 10 is coated to cover or encapsulate the patterned metal layer 15 and the insulating 101. The surface 10a of the substrate 10 contacts the carrier 20. In some embodiments, the metal layer 15 and the insulating layer 101 can be patterned through a photoresist and using lithography techniques.

[0039] Referring to Figure 5E An opening 10r1 is formed in the substrate 10 to expose a portion of the carrier 20. In some embodiments, the opening 10r1 can be formed through a photoresist and using lithography techniques. The opening 10r1 is spaced apart from the patterned metal layer 15 and the insulating 101 by a distance. The opening 10r1 tapers from the surface 10b to the surface 10a. In some embodiments, the exposed portion of the carrier 20 surface is a conductive surface. The opening 10r1 is formed Figure 5E Before the sacrificial layer 14d in the substrate 10 is formed, a seed layer is not formed along the exposed portion of the carrier 20 surface and the opening 10r1 sidewall to facilitate the subsequent formation of the horizontal stack of the sacrificial layer 14d and the conductive pillar 14 of the layer 14a, the layer 14b, and the layer 14c. Referring to Figure 5F A sacrificial layer 14d is formed on the exposed portion of the carrier 20 in the opening 10r1, and a conductive pillar 14 is formed on the sacrificial layer 14d in the opening 10r1. In some embodiments, the sacrificial layer 14d can include, but is not limited to, copper, gold, silver, aluminum, nickel, titanium, or other metals or alloys. The conductive pillar 14 includes the layer 14a, the layer 14b, and the layer 14c. In some embodiments, the conductive pillar 14 can be formed by electroplating a conductive material in the opening 10r1 by applying a voltage to the carrier 20.

[0040] Referring to Figure 5G A seed layer 12 is formed on the conductive pillar 14 and the carrier 20. The seed layer 12 is conformally deposited on the conductive pillar 14 and the carrier 20. In some embodiments, the seed layer 12 can be formed using the same manner as the layer 15a of the metal layer 15.

[0041] Referring to Figure 5H A photoresist 13p is formed on the seed layer 12.

[0042] Referring to Figure 5I The photoresist 13p is patterned such that portions of the seed layer 12 are exposed from the photoresist 13p. A metal layer 13 is formed on the exposed portions of the seed layer 12. In some embodiments, the metal layer 13 can be formed using the same manner as the layer 15b of the metal layer 15.

[0043] Referring to Figure 5J The photoresist 13p is removed.

[0044] Referring to Figure 5Kelectrical connections are formed on the exposed metal layer 13. In some embodiments, the electrical connections are formed through the photoresist and using a lithography technique.

[0045] Referring to Figure 5L electronic components 17 are connected to the portions 16a and 16b with the electrical connections 16 formed therebetween. An underfill 18 is formed to encapsulate the electrical connections 16. An encapsulant 19 is formed on the substrate 10 to encapsulate the electronic components 17. In some embodiments, the encapsulant 19 and the underfill 18 are integrally formed, e.g., using the same material in the same process step using the same process technique. In some embodiments, the encapsulant 19 and the underfill 18 are formed in different process steps using the same or different process techniques. The underfill 18 can be formed by capillary action. The encapsulant 19 can be formed using a molding technique, such as transfer molding or compression molding.

[0046] Referring to Figure 5M the carrier 20 and the sacrificial layer 14d are removed to form an aperture 10r2 and a concave corner 10c, and the conductive posts 14 are exposed from the substrate 10. In some embodiments, the aperture 10r2 can be formed by an etching technique, a drilling technique, or a laser drilling technique.

[0047] Referring to Figure 6A conductive contacts 11 are formed on the conductive posts 14 in the aperture 10r2, the conductive contacts 11 including portions 11a and 11b. The portions 11a are surrounded by the substrate 10. A singulation step is performed to singulate individual semiconductor packages. That is, the singulation step is through the encapsulant 19 and the substrate 10. The singulation step can be accomplished by a dicing saw, a laser, or other suitable dicing techniques.

[0048] Referring to Figure 6A and 6B , Figure 6A and 6B various types of semiconductor packages according to some embodiments of the present application are shown.

[0049] As shown in Figure 1 multiple chips 60 and / or dies are disposed on a square carrier 61. In some embodiments, the chips 60 can include Figure 2 , Figure 3 , Figure 4 , and Figure 6BSemiconductor packages 1 to 4 are shown. In some embodiments, the carrier 61 may contain organic materials (e.g., BT resin, polypropylene (PP), ABF) or inorganic materials (e.g., glass, silicon, ceramics, metals, etc.).

[0050] like Legend of symbols As shown, a plurality of chips 60 and / or dies are disposed on a circular carrier 62. In some embodiments, the carrier 62 may comprise organic materials (e.g., BT resin, polypropylene (PP), ABF) or inorganic materials (e.g., glass, silicon, ceramics, metals, etc.).

[0051] It will be understood that embodiments of the methods and apparatus discussed herein are not limited to the details of the construction and configuration of the components set forth in the following description or illustrated in the accompanying drawings. The methods and apparatus can be implemented in other embodiments and can be practiced or performed in various ways. Examples of specific embodiments are provided herein for illustrative purposes only and are not intended to be limiting. Specifically, the actions, elements, and features discussed in connection with any one or more embodiments are not intended to exclude similar roles from any other embodiments.

[0052] Furthermore, the wording and terminology used herein are for descriptive purposes and should not be considered limiting. Any reference to an embodiment, element, or action of the system and method herein, when referred to in the singular, may also include embodiments comprising multiple such elements, and any reference to any embodiment, element, or action herein, when referred to in the plural, may also include embodiments comprising only a single element. References in the singular or plural form are not intended to limit the system or method, its components, actions, or elements as disclosed herein. The use of variations of “comprising,” “including,” “having,” “containing,” “involving,” and the like herein is intended to cover the items listed thereafter and their equivalents, as well as additional items. References to “or” are to be considered inclusive such that any use of “or” indicates a single, more than, or all of the described items. Any references to front and rear, left and right, top and bottom, upper and lower, and vertical and horizontal are intended for ease of description and do not limit the system and method or its components to any particular location or spatial orientation.

[0053] Therefore, given that several aspects of at least one embodiment have been described, it should be understood that various changes, modifications, and improvements will readily occur to those skilled in the art. Such changes, modifications, and improvements are intended to be part of and within the scope of this invention. Therefore, the above description and figures are merely by way of example, and the scope of the invention should be determined by the proper construction of the appended claims and their equivalents.

[0054] ​

[0055] 1 semiconductor package

[0056] 2 semiconductor package

[0057] 3 semiconductor package

[0058] 4 semiconductor package

[0059] 10 substrate

[0060] 10a surface

[0061] 10b surface

[0062] 10c interior reentrant corner

[0063] 10r1 opening

[0064] 10r2 aperture

[0065] 10s surface

[0066] 11 conductive contact

[0067] 11a portion

[0068] 11b portion

[0069] 12 seed layer

[0070] 13 metal layer

[0071] 13p photoresist

[0072] 14 conductive post

[0073] 14a layer

[0074] 14b layer

[0075] 14c layer

[0076] 14d sacrificial layer

[0077] 15 metal layer

[0078] 15a portion

[0079] 15b portion

[0080] 16 electrical connection

[0081] 16a portion

[0082] 16b portion

[0083] 17 electronic assembly

[0084] 18 underfill

[0085] 19 package

[0086] 20 carrier

[0087] 21a contact

[0088] 21b contact

[0089] 21w wire

[0090] 60 chip

[0091] 61 carrier

[0092] 62 carrier

[0093] 101 insulating layer

[0094] 101a surface

[0095] 101b surface

[0096] 101i interface

Claims

1. A semiconductor package comprising: The substrate has a first surface, a second surface opposite to the first surface, and an opening extending from the first surface to the second surface, wherein the opening tapers from the second surface to the first surface; A conductive post is disposed in the opening; Solder balls are disposed in the opening and contact the bottom surface of the conductive post; and A metal layer is disposed in the substrate, wherein the bottom surface of the metal layer and the bottom surface of the conductive pillar are substantially at the same horizontal level relative to the second surface, wherein the sidewall of the opening forms an acute angle with the first surface, the acute angle surrounding the solder ball.

2. The semiconductor package according to claim 1, further comprising: An insulating layer that covers the bottom surface of the metal layer, and the insulating layer having a surface substantially coplanar with the first surface.

3. The semiconductor package of claim 2, wherein the insulating layer has an interface with the substrate, the interface being substantially coplanar with the side surface of the metal layer, and the insulating layer and the metal layer being substantially the same width.

4. The semiconductor package of claim 2, wherein the metal layer and the conductive pillar are surrounded by a single substrate and spaced apart from each other by a distance, the insulating layer separates the metal layer from the solder ball, and the width of the metal layer is greater than the width of the conductive pillar.

5. The semiconductor package of claim 1, wherein the width of the solder ball tapers from the bottom surface of the conductive post to the first surface.

6. The semiconductor package of claim 1, further comprising: The seed layer is in contact with the second surface and the top surface of the conductive pillar.

7. The semiconductor package of claim 1, wherein the conductive pillar and the substrate do not include a seed layer.

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