Method for making a light emitting diode or a light receiving diode

Abstract

The present invention provides a method for manufacturing a light emitting diode or a light receiving diode (102), comprising: manufacturing a first semiconductor layer and a second semiconductor layer with opposite doping and a third intrinsic semiconductor layer on a first substrate (104); etching a groove, the groove surrounding the second layer and the third layer and the remaining part (126, 128, 130) of the first part of the first layer; manufacturing a dielectric spacer (132) covering the side wall of the remaining part in the groove; performing etching to extend the groove to the first substrate; laterally etching a part of the dielectric spacer to expose a contact surface (136) of the second part of the first layer; and manufacturing a first electrode in the groove in contact with the contact surface of the second part of the first layer and the side surface of the second part of the first layer.

Description

Technical Field

[0001] The invention relates to the field of light-emitting diodes or light-emitting diodes, called LEDs or micro-LEDs or μLEDs with a size of a few micrometers or tens of micrometers, and to the field of light-receiving diodes or photodiodes. The invention is particularly applicable to the field of devices illuminated by LEDs, light-emitting electronic devices including LED matrices (such as screens, projectors, car headlights or image walls), and to the field of light-receiving electronic devices or microelectronic devices including photodiode matrices (such as image sensors). The invention particularly relates to the production of LED matrices or μLED matrices from GaN / InGaN semiconductor stacks for the production of display screens or matrix lighting. Background Art

[0002] The production of diodes (for example in the production of photodiode matrices or LED matrices forming a matrix of pixels) is usually based on the implementation of standard microelectronic methods commonly used in so-called planar technology, during which each element of the diode is produced by a deposition step and a subsequent photolithography step and a subsequent etching step. With this type of method, the production of each pattern of diode material requires the implementation of at least three different steps. In addition, each pattern produced must be consistent with the previously produced pattern. Finally, the definition of each pattern must take into account the performance of the relevant equipment, with regard to both the achievable dimensions and the alignment performance relative to the previous pattern.

[0003] Furthermore, in order to obtain adequate performance under standard microelectronics techniques, planarization of the fabricated components is necessary to control the lithography steps performed on these components, since the resolution that can be achieved by the lithography steps is directly related to the topography on which the lithography is performed, and the depth of field of optical lenses with very large apertures used in lithography isolation equipment decreases as the resolution increases.

[0004] Document FR3042913A1 describes a method for automatically aligning the production of LED matrices or μLED matrices. In this method, pixels are made in an automatically aligned manner, that is, the various LEDs are physically separated by a single photolithography layer while producing a mesa structure of the LED. The grooves made also make it possible to make electrical contact on one of the n-doped or p-doped parts of the LED simply by contacting the side of the n-doped or p-doped part of the LED. These optical isolation grooves between pixels are etched into the growth substrate of the semiconductor forming the pn junction of the LED and then filled with a material that forms a reflective metal electrode, which enables the pixels to be properly optically isolated from each other, because the light emitted by the pixel is then extracted directly below the pixel and is not directed to adjacent pixels in the semiconductor (crosstalk phenomenon). Therefore, this pixel matrix structure provides the pixels with optimal optical contrast and good optical clarity.

[0005] However, from an electrical point of view, it is preferred that the electrical contact between the semiconductor of the n-doped part or the p-doped part located on the substrate and the electrode providing optical isolation does not occur on the side of the part, but, for example, occurs on a surface parallel to the substrate, because the crystal plane parallel to the growth surface has better electrical properties. This enables a better electrical response, that is, a higher current can be obtained for the same operating voltage, and therefore, in the case of a light-emitting diode, a larger amount of light can be emitted for the same injected electrical power. On the other hand, making electrical contact on a surface parallel to the substrate involves not etching the semiconductor to the substrate so as to retain a portion at the bottom of the groove, which degrades the optical isolation between pixels, that is, increases the crosstalk between pixels. This is described in the document "Processing and characterization of high resolution GaN / InGaN LED arrays at 10 micron pitch for micro display applications" (L. Dupré et al, Proc. SPIE 10104, Gallium Nitride Materials and Devices XII, 1010422, 2017).

[0006] Therefore, a compromise must be reached between the optical isolation of the pixel and the obtained electrical response.

[0007] In document FR2992465A1, an LED device is made of a stack of semiconductor layers pre-structured in the form of independent elements, each element being used to make an LED of the device. Making the anode of each LED consists in etching an opening in a dielectric layer previously deposited on a p-type semiconductor. In order to ensure good geometric definition of the electrode, it is necessary to make the opening by plasma-assisted dry etching. However, the InGaN used to make the device is a wide-bandgap semiconductor that is damaged by this type of etching, which leads to a poor electrical interface and therefore to an irreversible degradation of the electrical characteristics of the LED. In addition, the method described in this document involves the implementation of a lithography step that requires precise alignment, which is limited compared to the automatic alignment method, which has no alignment restrictions and therefore no restrictions on the minimum size of the structure made. Summary of the invention

[0008] An object of the invention is to propose a diode whose structure is able to reconcile good optical isolation between pixels and good pixel electrical response, which can be achieved in a self-aligned manner and without degrading its electrical characteristics.

[0009] To this end, the present invention provides a method for manufacturing at least one light emitting diode or a light receiving diode, the method comprising at least:

[0010] - making at least one stack on a first substrate, the stack comprising a first semiconductor layer and a second semiconductor layer doped according to opposite conductivity types and at least one third intrinsic semiconductor layer or a non-intentionally doped semiconductor arranged between the first semiconductor layer and the second semiconductor layer, the first layer being arranged between the first substrate and the third layer;

[0011] - etching a trench that passes through the second and third layers and the first portion of the first layer, surrounds remaining portions of the second and third layers and remaining portions of the first portion of the first layer, and has a bottom wall or bottom of the trench formed by the second portion of the first layer disposed between the first portion of the first layer and the first substrate;

[0012] - making at least one dielectric spacer in the trench covering the sidewalls of said remaining portion;

[0013] - performing etching so that the trench extends through the portion of the second portion of the first layer not covered by the dielectric spacer, to the first substrate;

[0014] - laterally etching a portion of the dielectric spacer, exposing a (eg horizontal) contact surface of the second portion of the first layer;

[0015] - making at least one first electrode in the trench, the first electrode being in contact with the contact surface of the second portion of the first layer and with the side, sidewall or side edge of the second portion of the first layer.

[0016] Since the first layer extends to the first substrate, the optical isolation of the diode is very effective. When the diode forms a pixel comprising adjacent pixels, good optical isolation between pixels is obtained, which makes it possible to avoid optical interactions between adjacent diodes.

[0017] Furthermore, since the first electrode is electrically connected to the semiconductor of the remaining part of the first layer by means of the sidewalls of the second part of the first layer and by means of contact surfaces formed by lateral etching of the dielectric spacer, a good electrical response of the diode is also obtained.

[0018] The diode uses a dielectric spacer (i.e., an electrically insulating element) that covers the sides of some of the elements that form the pn junction of the diode and is able to electrically insulate and passivate these sides (particularly with respect to the first electrode), and is also able to electrically insulate the doped semiconductor portions of the pn junction relative to each other. The dielectric spacer also makes it possible to provide electrical insulation between the first electrode and the second electrode while occupying a minimum amount of space in the diode. This position of the dielectric spacer on the side of the pn junction of the diode makes it possible to increase the ratio between the active surface of the diode (the surface occupied by the pn junction) and the total surface occupied by the diode, and thus reduce its overall size.

[0019] Furthermore, this high level of integration of the dielectric spacer also has the advantage of minimizing the current density obtained in the electrodes of the diode and thus reducing the Joule effect heat generated in the diode through an overall reduction in the thermal resistance of the diode.

[0020] The structure of this diode makes it possible to reduce its manufacturing costs and its energy consumption. In the field of lighting, this diode improves the resulting electrical injection and therefore increases its energy efficiency. In the field of imaging devices, this diode makes it possible to make high-resolution devices by reducing the size of the pixel, which becomes limited only by the formation means used.

[0021] The term "layer" is used here and in the rest of this document to denote a single layer or a stack of multiple layers.

[0022] The produced pn junction and the dielectric spacer form a mesa structure. The expression "mesa structure" refers to the fact that the diode is produced in the form of a stack of doped semiconductor parts and a junction region comprising an intrinsic semiconductor arranged between these doped semiconductor parts, and this stack is etched here in the form of an element called a mesa over its entire height.

[0023] The dielectric spacer is deposited on the side of the structure etched in the stack and can be made by an automatic alignment method, so that, for example, by conformal deposition of the dielectric spacer material and subsequent (for example, anisotropic) etching of the portion of the dielectric material that does not cover the side of the structure, the electrodes of the diode can be isolated without using a mask specifically suitable for making the dielectric spacer.

[0024] The bottom wall of the groove may be horizontal.

[0025] The first semiconductor layer may be n-doped and the second semiconductor layer may be p-doped, and in this case the first electrode may form the cathode of the diode.

[0026] The diodes fabricated may include a substantially flat continuous surface on a side opposite to the side where the first substrate is located. The substantially flat continuous surface enables the diode to be easily intermixed with another component (such as a substrate), for example without the use of inserts (such as connecting beads), enables various connection configurations of the diode to be fabricated, for example by direct metal-to-metal bonding (for electrodes) and dielectric-to-dielectric bonding (particularly for dielectric spacers), and can also include a flat surface on which a material similar to that of the diode is located. The substantially flat continuous surface is also well suited for fabricating interconnect structures directly on the electrodes, thereby avoiding many of the difficulties associated with the residual topology of prior art diode structures.

[0027] The expression "substantially planar" is used here to denote the fact that the surface thus formed may exhibit variations in height or thickness between about 0 and 150 nm. These slight variations in height or thickness may result from the implementation of a chemical mechanical planarization (CMP) in the presence of the material of the electrode and of the dielectric material, these various materials being etched at different rates from one another. These slight variations in height or thickness may have the advantage of ensuring excellent isolation of the electrodes of the diodes from one another and / or relative to the electrodes of adjacent diodes when a recess is formed in the top surface of the electrode.

[0028] The first semiconductor layer may include a stack of at least two semiconductors doped according to different conductivity levels. For example, when the first semiconductor layer is n-doped, it may include a stack of a first n+ doped semiconductor disposed on a first substrate and a second n- doped semiconductor disposed on the first semiconductor.

[0029] The diode may be a photodiode or an LED. When the diode is an LED, it may include a plurality of third intrinsic semiconductor layers forming an emission active region having at least one quantum well, the at least one quantum well being arranged between the first semiconductor layer and the second semiconductor layer.

[0030] As used herein, a lateral etch is an etch that reduces the thickness of at least a portion of a dielectric spacer.

[0031] Before performing the lateral etching, the initial thickness of the dielectric spacer may be greater than or equal to about 1 μm.

[0032] The thickness of the portion of the dielectric spacer removed during the lateral etch may be between about 10 nm and the initial thickness of the spacer minus about 10 nm, such that the remaining spacer thickness is sufficient to ensure good electrical insulation.

[0033] The contact surface of the second portion of the first layer may be substantially perpendicular to the sidewalls of the remaining portion.

[0034] The method may further include, between forming the stack and etching the grooves through the second layer and the third layer and the first portion of the first layer, forming at least one etch mask disposed on the stack and having a pattern corresponding to the pattern of the grooves, and forming a dielectric spacer that also covers the sidewalls of the etch mask.

[0035] In a first embodiment, the lateral etching of a portion of the dielectric spacer is an isotropic etch.

[0036] The etch mask may include at least one material that is at least partially etched during the lateral etching of a portion of the dielectric spacer.

[0037] The dielectric spacer may include SiO2.

[0038] In a second embodiment, fabricating the dielectric spacer may include:

[0039] - depositing at least one layer of a first dielectric material, the first dielectric material covering the sidewalls of the remaining portion;

[0040] - depositing at least one layer of a second dielectric material covering the layer of the first dielectric material, the second dielectric material being selected such that during lateral etching of a portion of the dielectric spacer as an anisotropic etch, the second dielectric material is etched at a rate greater than the first dielectric material;

[0041] And wherein, during the same etching step, etching for extending the trench and lateral etching of a portion of the dielectric spacer can be performed simultaneously.

[0042] The method could be something like this:

[0043] - the layer stack further comprises at least one conductive layer, such that the second layer is arranged between the third layer and the conductive layer (when an etch mask is used, the conductive layer may be arranged between the second layer and the etch mask);

[0044] - a trench etched through the conductive layer and surrounding at least a remaining portion of the conductive layer forming the first portion of the second electrode;

[0045] - a dielectric spacer covers side walls of the first portion of the second electrode;

[0046] And the method may further include the step of forming a second portion of the second electrode after laterally etching a portion of the dielectric spacer.

[0047] In this case, making the second part of the first electrode and the second electrode may at least include:

[0048] - making at least one opening through the stack and exposed on the first portion of the second electrode;

[0049] - depositing at least one conductive material in the openings and the trenches;

[0050] - Planarization of conductive materials.

[0051] In this case, the production of the electrode corresponds to the implementation of a "damascene" type method, in which one or more conductive materials are formed by at least one full-wafer deposition, that is, a conductive material is deposited over the entire structure produced, and the electrode is subsequently obtained by planarization of this or these conductive materials. The production of the first electrode therefore does not require specific alignment steps or specific masking steps. The position of the first electrode can correspond to the space formed by the trench between adjacent diodes.

[0052] The method may further include, after forming the second parts of the first electrode and the second electrode, transferring the light emitting diode or the light receiving diode to an interconnect substrate so that the first electrode and the second electrode of the light emitting diode or the light receiving diode are electrically connected to the interconnect substrate, and then removing the first substrate.

[0053] The conductive layer may be optically reflective, i.e. may have an amplitude reflectance (ratio of the amplitude of the reflected light to the amplitude of the incident light) of at least 80%. In this case, the second electrode may be optically reflective, the second electrode being arranged on the side opposite to the side through which light is to enter or leave the diode. Thus, light may enter or leave the diode without having to pass through a transparent electrode (e.g. comprising a conductive transparent oxide such as ITO) which causes light loss of the emitted or received light.

[0054] The present invention also relates to a method for manufacturing an electronic device, comprising implementing the above method, wherein the steps implemented form a plurality of light emitting diodes and / or a plurality of light receiving diodes, wherein the first electrodes of the diodes are electrically connected together.

[0055] Depending on the particular configuration, the first electrodes of the diodes of the device may form a common cathode for these diodes.

[0056] The diodes may form part of a diode matrix having a similar structure forming a pixel matrix of an electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The invention will be better understood by reading the description of example embodiments given purely indicatively and not limitingly, with reference to the accompanying drawings, in which:

[0058] Figures 1A to 1J The steps of a method for producing an electronic device which is an object of the present invention (including a method for producing a light emitting diode or a light receiving diode which is also an object of the present invention according to the first embodiment) are shown;

[0059] Figure 2A and Figure 2B A photograph showing a structure obtained during isotropic lateral etching using a mask similar to the etching mask used during the method for producing a light-emitting diode or a light-receiving diode as the object of the present invention according to the first embodiment;

[0060] Figure 3A and Figure 3B Some steps of a method for producing an electronic device which is an object of the present invention (including a method for producing a light-emitting diode or a light-receiving diode which is also an object of the present invention according to a second embodiment) are shown.

[0061] The same, similar or equivalent parts of the various figures described below have the same reference numerals to facilitate passing from one figure to another.

[0062] In order to make the drawings more clearly legible, the various components shown in the drawings are not necessarily shown to the same scale.

[0063] It must be understood that the various possibilities (variants and embodiments) are not exclusive of one another but can be combined with one another. DETAILED DESCRIPTION

[0064] Figures 1A to 1J The steps of a method for producing an electronic device 100 according to a first embodiment are shown. In the first embodiment described herein, the device 100 comprises a plurality of diodes 102, here corresponding to light emitting diodes or light emitting diodes.

[0065] like Figure 1AAs shown, device 100 is fabricated from a first substrate 104 comprising, for example, sapphire, silicon, a semiconductor similar to the semiconductor used to form the active portion of diode 102, or any other material that enables first substrate 104 to form a growth substrate for deposition of the semiconductor stack that will form diode 102. First substrate 104 serves as a support for the deposition or growth of layers intended to be used to form diode 102 of device 100.

[0066] A first semiconductor layer 106 doped with a first conductivity type (eg, n-type) is formed on the first substrate 104 .

[0067] According to a specific example embodiment, the first layer 106 corresponds to a plurality of different semiconductor layers (eg, with a donor concentration of, for example, between about 5.10 17 and 5.10 20 Donor / cm 3 n+ doped semiconductor layer 108 is provided with a donor concentration of, for example, about 10 17 and 5.10 19 Donor / cm 3 10 and 110). For example, layer 108 may include GaN and layer 110 may include InGaN. The thickness of layer 108 is, for example, greater than about 100 nm, for example equal to about 3 μm, and the thickness of layer 110 is, for example, between about 5 nm and 500 nm. The total thickness of first layer 106 (i.e., the sum of the thicknesses of layer 108 and layer 110 in this particular example embodiment) is, for example, between about 20 nm and 10 μm, and preferably between about 2 μm and 4 μm. Layer 108 is formed here as a buffer layer arranged between layer 110 and first substrate 104, and is particularly used to filter growth defects so that these defects are not located in layer 110 used to form the pn junction of diode 102.

[0068] In a variation, layer 108 and layer 110 may be doped to the same doping level.

[0069] According to another variant, the layer 106 may correspond to a single semiconductor layer. This single semiconductor layer is, for example, n-doped and may have, for example, a value between about 10 17 and 5.10 20 Donor / cm 3 By way of example, this layer may comprise GaN and have a thickness, for example, between about 20 nm and 10 μm, and advantageously between about 2 μm and 4 μm.

[0070] According to another variation, layer 106 may correspond to a plurality of different semiconductor layers (e.g., an unintentionally doped semiconductor layer 108 formed as a buffer layer disposed between layer 110 and first substrate 104, on which a donor concentration, for example, between about 10 17 and 5.10 20 Donor / cm 3 The thickness of layer 108 is, for example, greater than about 100 nm, for example, equal to about 3 μm, and the thickness of layer 110 is, for example, between about 100 nm and 3 μm.

[0071] On the first layer 106 (at Figure 1A In the example shown, one or more third intrinsic semiconductor layers 112 are formed on the layer 110, that is, they are not intentionally doped (residual donor concentration n nid For example, it is equal to about 10 17 Donor / cm 3 , or between 10 15 and 10 18 Donor / cm 3 In the first embodiment described herein, the third layer 112 is an active region including one or more (e.g., five) emission layers, each of which is used to form a quantum well in the diode 102. These emission layers include, for example, InGaN. Each emission layer is disposed between two barrier layers (including, for example, GaN). The thickness of the emission layer or each of the emission layers is, for example, equal to about 3 nm, more generally between about 0.5 nm and 10 nm, and the thickness of each of the barrier layers is, for example, between about 1 nm and 25 nm.

[0072] A second semiconductor layer 114 doped with a second conductivity type is formed on the third layer 112. The second semiconductor layer 114 has a doping type opposite to that of the first layer 106, and is therefore p-type. The acceptor concentration is, for example, between about 10 17 and 5.10 19 Acceptor / cm 3 The layers 106, 112 and 114 (more particularly the layers 110, 112 and 114 in the example described herein) are intended to form a pin junction of the diode 102. The semiconductor of the second layer 114 is, for example, GaN, and its thickness is, for example, between about 20 nm and 10 μm.

[0073] In a variant embodiment, the electron blocking layer (not in Figures 1A to 1J ) can be disposed between the second layer 114 and the third layer or layers 112, the electron blocking layer comprising, for example, AlGaN with 12% aluminum, and can have an acceptor concentration, for example, equal to about 1.10 17 Acceptor / cm 3p-doped.

[0074] Materials other than those described above may be used to make layers 106, 112, and 114. For example, the material of the emission layer formed by third layer 112 is selected based on the desired emission spectrum of diode 102.

[0075] On the second layer 114 there is arranged a conductive layer 115 intended to form in each diode 102 a first portion of a second electrode to be in contact with the semiconductor of the second layer 114. The conductive material used is advantageously optically reflective and is for example aluminium or silver.

[0076] A layer 116 for forming an etching mask is formed on the layer 115. The material of the layer 116 is, for example, SiO2.

[0077] Layers 106 , 112 , 114 , and 115 together form a stack 117 from which diode 102 will be fabricated.

[0078] like Figure 1B As shown, a pattern is made in layer 116 by photolithography and etching (using, for example, a fluorinated plasma such as CHF3 or SF6) so that the remaining portion of layer 116 forms an etch mask 118. The photoresist used to make etch mask 118 is then removed. The openings formed in etch mask 118 correspond to the pattern of trenches to be etched in the layers of stack 117 in order to define the mesa structure of diode 102.

[0079] According to the pattern of the etch mask 118, the etching of the trench 120 is performed, the trench 120 passing through the conductive layer 115, the second layer 114, the third layer or layers 112 and the first portion 122 of the first layer 106. The etching stops at a depth level located in the first layer 106, so that the second portion 123 of the first layer 106 remains at the bottom of each of the etched trenches 120. Figure 1B , the first portion 122 of the first layer 106 is symbolically delimited by a dashed line from the second portion 123 of the first layer 106. In the example described herein, the etching stops at a level located in the layer 110, so that the layer 108 and a portion of the thickness of the layer 110 are not etched. The thickness of the first layer 106 that is etched (i.e., the thickness of the first portion 122 of the first layer 106) is, for example, between about 100 nm and 5 μm.

[0080] At the end of this etch, trench 120 surrounds:

[0081] - Etching mask 118;

[0082] - a remaining portion 124 of the conductive layer 115 forming the first portion of the second electrode of the diode 102;

[0083] - a remaining portion 126 of the second layer 114 for forming a part of the pn junction of the diode 102;

[0084] - the remaining portion 128 of the third layer 112 forming the active area of ​​each diode 102, and

[0085] A remaining portion 130 of the first portion 122 of the first layer 106 for forming a pn junction of the diode 102 together with a remaining portion 126 of the second layer 114 .

[0086] The layers 115 , 112 , 114 , and 106 are etched by a dry process, such as by reactive ion etching performed using a plasma torch system, or ICP-RIE (Inductively Coupled Plasma–Reactive Ion Etching).

[0087] Next, a dielectric spacer 132 is formed in the trench 120 (see Figure 1C ). For this purpose, a dielectric layer is conformally deposited on the etch mask 118 and against the side walls and bottom wall of the trench 120, for example by PECVD (plasma enhanced chemical vapor deposition) type deposition. The portions of the dielectric layer that do not cover the side walls of the trench 120 (i.e. the portions located on the etch mask 118 and the portions located at the bottom of the trench 120) are removed by anisotropic etching, for example corresponding to dry etching (e.g. RIE etching or reactive ion etching). The remaining portion of the dielectric layer forms a dielectric spacer 132 that covers the side walls of the remaining portions 124, 126, 128 and 130 and the side walls of the etch mask 118.

[0088] The dielectric spacer 132 has an initial thickness equal to the thickness of the deposited dielectric layer. The thickness is large, for example, greater than or equal to about 1 μm. Figure 1C In FIG. 1 , this initial thickness is referenced as “ e1 .” The thickness of the dielectric spacer 132 corresponds to a dimension perpendicular to the surface on which the material of the dielectric spacer 132 is deposited.

[0089] like Figure 1D As shown, a second etch of layer 106 is then performed, extending trench 120 through the portion of second portion 123 of first layer 106 not covered by dielectric spacer 132 to first substrate 104. At the end of this second etch, trench 120 also surrounds remaining portion 134 of second portion 123 of first layer 106.

[0090] The etching mask 118, the remaining parts 124, 126, 128, 130, 134 and the dielectric spacer 132 form a mesa structure (i.e., an island-shaped stack) disposed on the first substrate 104. Each mesa structure of each diode 102 has, for example, a rectangular cross-section in a plane parallel to the surface of the first substrate 104 on which these structures are supported. Thus, each of the mesa structures can form a parallelepiped-shaped element. It is possible to have mesa structures of different shapes, for example cylindrical.

[0091] Next, a lateral etching of a portion of the dielectric spacer 132 is performed to expose the contact surface 136 of the second portion 123 of the first layer 106 (see Figure 1E ). The contact surface 136 of the exposed second portion 123 of the first layer 106 is preferably substantially horizontal in the orientation of the drawing. Therefore, the lateral etching exposes crystal planes parallel to the growth surface, which have better electrical properties than crystal planes perpendicular to the growth surface. The thickness of the portion of the dielectric spacer 132 removed during the lateral etching process (in Figure 1E The thickness of the dielectric spacer 132 is, for example, between about 10 nm and the initial thickness of the spacer (e1) minus about 10 nm, so that the remaining spacer thickness (denoted by "e3") is sufficient to ensure good electrical insulation. When the initial thickness e1 of the dielectric spacer 132 is equal to about 1 μm, the thickness e2 is, for example, equal to about 600 nm. Therefore, the thickness of the remaining portion of the dielectric spacer 132 is e3=e1-e2, and is, for example, equal to 400 nm for the above example.

[0092] In this first embodiment, the lateral etching performed on the dielectric spacer 132 is an isotropic etching (e.g., wet chemical etching or isotropic plasma etching). During such an isotropic etching, if the material of the etch mask 118 is sensitive to the etchant used, the etch mask 118 is also at least partially etched as a result (this is the case in the example embodiment described herein, in which the etch mask 118 and the dielectric spacer 132 include SiO2).

[0093] Next, an opening 138 is formed through the etch mask 118 to form a location for forming a second portion of the second electrode of the diode 102 ( Figure 1F ). These openings 138 pass through the entire thickness of the etch mask 118, so that the bottom wall of the openings 138 is formed by the portion 124. The etching is, for example, of the ICP-RIE type.

[0094] Next, a first conductive material 140 is deposited in the trench 120, on the top surface of the etch mask 118 and in the opening 138 ( Figure 1G). The first conductive material 140 is conformally deposited (i.e., forms a layer of substantially constant thickness on the etch mask 118 and along the walls of the trench 120 and the walls of the opening 138). In the example embodiment described herein, the first conductive material 140 is formed by depositing a first titanium layer having a thickness, for example, between about 5 nm and 300 nm, followed by depositing a second aluminum layer having a thickness, for example, between about 50 nm and 1 μm. In a variant embodiment, the first conductive material 140 is formed by a single aluminum layer having a thickness, for example, between about 50 nm and 1 μm.

[0095] The deposited first conductive material 140 is in electrical contact with the sides of the portion 134, but also with a contact surface 136 which, in addition to being in contact with the sides of the portion 134, actively participates in the electrical contact with the semiconductor of the first layer 106. The conductive material 140 is also in contact with the portion 124 at the bottom wall of the opening 138. These electrical contacts are intended to form electrical contacts between the pn junction and the anode and cathode of the diode 102.

[0096] like Figure 1H As shown, the second conductive material 142 is deposited by filling the remaining volume of the trench 120 and the remaining volume of the opening 138. Figure 1H , the thickness of the second conductive material 142 is such that it also covers the portion of the first conductive material 140 disposed on the etch mask 118. The second conductive material 142 is, for example, copper, which can be formed by performing full-wafer electrochemical deposition (ECD), i.e., formed on the entire structure previously fabricated.

[0097] Finally, the diode 102 of the device 100 is completed by performing a chemical mechanical planarization (CMP) which removes the portions of the first conductive material 140 and the second conductive material 142 that protrude beyond the trench 120 and the opening 138 and that are disposed over the etch mask 118. This planarization electrically isolates the portions of the conductive material disposed in the trench 120 from the portions of the conductive material disposed in the opening 138. Fig. 1I ). The portions of the conductive materials 140 and 142 disposed in the trench 120 form a first electrode 144 (corresponding to a cathode in the example embodiments described herein), which extends over the entire height of the mesa structure of the diode 102 and is electrically connected to the semiconductor portion 134. The portions of the conductive materials 140 and 142 disposed in the opening 138 form second portions of a second electrode 146 (corresponding to an anode in the examples described herein), which is electrically connected to the portions 124 corresponding to the first portions of the second electrode 146. The second electrode 146 is connected to these portions 126 at their top surfaces.

[0098] This planarization also forms a face 148 of the device 100 that is substantially planar and is formed by the top surfaces of the electrodes 144, 146, the top surface of the dielectric spacer 132, and the top surface of the etch mask 118. This face 148 forms the back side of the diode 102 where electrical connections to the electrodes 144, 146 will be made.

[0099] By means of the dielectric spacer 132 , the first electrode 144 is well electrically insulated from the semiconductor portion 124 , from the second electrode 146 and from the portion 128 forming the active area of ​​the diode 102 .

[0100] In order to ensure electrical insulation between the electrodes 144, 146 of the diode 102 and to avoid the presence of portions of the conductive material 140 and the conductive material 142 that electrically connect the one or more first electrodes 144 to the one or more second electrodes 146, a planarization step can be advantageously performed until the portions of the conductive material 140 and the conductive material 142 disposed in the trenches 120 and the openings 138 are overetched relative to the dielectric material of the dielectric spacer 132 and the dielectric material of the etch mask 118, thereby forming recesses in the electrodes 144, 146 at their top surfaces. The depth of these recesses can be between about 5 nm and 150 nm relative to the plane of the top surface 148. This overetching can be obtained by acting on the etching selectivity that exists between the dielectric material of the spacer 132 and the etch mask 118 and the conductive materials 140 and 142. The chemical mechanical planarization that is implemented has different grinding speeds depending on the material, and in the method described herein, the grinding of the conductive material 140 and the conductive material 142 is faster than the grinding of the dielectric material of the spacer 132 and the dielectric material of the etch mask 118. This results in the removal of the materials 140, 142 relative to the dielectric spacer 132 and the etch mask 118 at the top surface 148 of the device 100. Therefore, the electrodes 144, 146 of the diode 102 remain completely isolated from each other due to the inherent characteristics of the planarization used. This overetching can also be achieved by RIE etching.

[0101] The substantially flat surface obtained at the top surface 148 of the device 100 makes it possible to easily mix the matrix of diodes 102 produced with any type of connecting element (e.g., electronic circuit), and in particular makes it possible to perform such mixing by direct bonding (also referred to as molecular bonding) of the matrix of diodes 102 with the electronic circuit, without the need to use inserts (e.g., microbeads) between the matrix of diodes 102 and the electronic circuit. The direct bonding of the metal-metal type and the direct bonding of the dielectric-dielectric type formed in this case have the advantage of being impermeable. The fact that these depressions are present on the top surfaces of the electrodes 144, 146 does not cause any problems for the implementation of such direct bonding, since during such direct bonding, the material of these parts expands, so that very good contact can be obtained between these electrodes and the conductive elements of the electronic circuit. The details of the implementation of such direct bonding are described, for example, in the document "Mechanisms of copper direct bonding observed by in-situ and quantitative transmission electronmicroscopy" (M.Martinez et al., Thin Solid Films 530 (2013) 96-99).

[0102] like Figure 1J As shown, the matrix of diodes 102 is transferred on its top surface 148, for example by direct bonding as described above, to an interconnect substrate 150 including electrical contacts 152 and 154, to which electrodes 144, 146 may be electrically connected. The interconnect substrate 150 may be an electronic circuit onto which the matrix of diodes 102 is transferred.

[0103] The methods described herein and the substantially flat surface obtained at the top surface 148 of the device 100 are also compatible with conventional hybridization methods using, for example, inserts (eg, microbeads or microtubes) for hybridizing the matrix of diodes 102 .

[0104] After this transfer, the first substrate 104 can be removed, leaving clearly visible the front side 156 of the diode 102 through which light is intended to enter or leave (leave in the examples described herein, where the diode 102 is an LED). The type of removal performed depends in particular on the nature of the first substrate 104. For example, in the case of a first sapphire substrate 104, this can be removed by stripping. The first substrate 104 can also be removed by grinding or selective etching.

[0105] To illustrate the lateral etching performed in the above method, Figure 2A and Figure 2BImages obtained by electron microscopy during this lateral etching process are shown.

[0106] Figure 2A Semiconductor mesa structure 10 is shown having a geometry similar to that formed by portions 124 , 126 , 128 , 130 , and 134 and etch mask 118 after etching trench 120 . Figure 2B The contact surface 136 obtained by partial lateral removal of the etch mask 118 after carrying out an isotropic lateral etching (here chemically) is shown.

[0107] The steps of a method for producing an electronic device 100 according to a second embodiment are described below. In the second embodiment described herein, the device 100 comprises a plurality of diodes 102, which in this second embodiment are light emitting diodes.

[0108] First, implement the aforementioned Figure 1A and Figure 1B each step.

[0109] Next, a dielectric spacer 132 is formed in the trench 120. Unlike the first embodiment in which the dielectric spacer 132 is formed by depositing a single thick dielectric material layer, here, the dielectric spacer 132 is formed by conformally depositing a first dielectric material layer 133, which layer 133 covers the sidewalls of the portions 124, 126, 128 and 130 and the sidewalls of the etch mask 118 in the trench 120. Next, a second dielectric material layer 135 is deposited through the capping layer 133. The first dielectric material and the second dielectric material are selected so that the second dielectric material has a greater etching rate than the first dielectric material during the lateral etching of a portion of the dielectric spacer that is subsequently performed (i.e., the anisotropic etching of the spacer and the etching of the semiconductor layer). For example, the first dielectric material of the layer 133 can be SiO2, and the second dielectric material of the layer 135 can be SiN.

[0110] Portions of the layers 133 and 135 that do not cover the sidewalls of the trench 120 (i.e., portions located on the etch mask 118 and portions located at the bottom of the trench 120) are removed by anisotropic etching (e.g., dry etching (e.g., RIE etching)). The remaining portions of these dielectric layers 133 and 135 form dielectric spacers 132 that cover the sidewalls of the remaining portions 124, 126, 128, and 130 and the sidewalls of the etch mask 118 (see FIG. 1 ). Figure 3A During this anisotropic etching, the difference in etching rate between the first dielectric material and the second dielectric material results in a height difference between layer 135 and layer 133 after fabrication of the dielectric spacer: the remaining portion of layer 135 is smaller than the remaining portion of layer 133.

[0111] Next, a selective etching step may be performed to remove part of the remaining portion of layer 135. In this case, the structure obtained is as follows Figure 3B shown.

[0112] Next, another etch is performed so that the trench 120 extends through the portion of the second portion 123 of the first layer 106 that is not covered by the dielectric spacer 132 (i.e., the portion that is not covered by the portions of the layer 133 and the layer 135) to the first substrate 104. At the end of this second etch, the trench 120 also surrounds the remaining portion 134 of the second portion 123 of the first layer 106.

[0113] Carrying out this etching also removes the remaining portion of layer 135. At the end of this etching, dielectric spacer 132 is formed only by the remaining portion of layer 133. The clear surface left by removing part of layer 135 forms a contact surface 136 for making electrical contact with the semiconductor of portion 134. The resulting structure is thus similar to Figure 1E The structure shown.

[0114] Before performing the etching to extend the groove, the height of the retained portion of layer 135 is adjusted according to the thickness of the etching mask 118, the thickness of each etched semiconductor layer or the etching selectivity of various materials. This is to properly protect the contact surface 136 through the portion of layer 135 during the entire etching process to extend the groove, and to properly remove the portion of layer 135 at the end of the etching.

[0115] In a variant embodiment, after the etching that extends the trench, a portion of the remainder of layer 135 may remain, which portion it will then be necessary to remove by anisotropic etching selective to the material of layer 133 .

[0116] Next, as in the first embodiment, the aforementioned Figure 1F to Figure 1J The diode 102 and the device 100 are completed through the steps described above.

[0117] In the first and second specific embodiments described above, semiconductor portions 130, 134 are n-type and second semiconductor portion 126 is p-type. In a variation, semiconductor portions 130, 134 may be p-type and second semiconductor portion 126 may be n-type, in which case the portion of the conductive material disposed in trench 120 forms an anode of diode 102 and the portion of the conductive material disposed in opening 138 forms a cathode of diode 102 together with portion 124.

[0118] Furthermore, in the first and second embodiments described herein, the previous steps were performed such that the contact surface 136 was substantially perpendicular to the side walls of the remaining portions 124, 126, 128, 130, and 134. In a variant, depending on the desired geometry of the diode 102 and the etching used accordingly, the contact surface 136 may be made non-perpendicular to these side walls.

[0119] In addition, in the first and second embodiments described above, the device 100 includes a matrix of diodes 102 as light emitting diodes, and the microelectronic device 100 can form part of a display device (screen, projector, image wall, etc.) with LEDs. This matrix of diodes 102 includes a first electrode 144, which forms one and the same electrode common to all diodes 102, and each diode 102 includes a second electrode 146, so that each of the diodes 102 can be addressed individually.

[0120] In one variation, the microelectronic device 100 may include a matrix of diodes 102, which are light receiving diodes or photodiodes. In this variation, the electrodes 144, 146 are not used to provide current to the diodes 102, but are used to recover the current generated by the diodes 102 by light.

[0121] In one variation, the device 100 may include, on the top surface 148, a connection structure different from the interconnect substrate 150, forming an electrical connection of the diode 102 and including a first conductive element electrically connected to the first electrode 144 of the diode 102 and a second conductive element electrically connected to the second electrode 146 of the diode 102. These conductive elements of this connection structure are electrically insulated from each other by a dielectric element having a size at least equal to the size of the dielectric spacer 132 and the size of the etch mask 118 in the plane of the surface 148, so that the conductive elements do not form a short circuit between the electrodes of the diode 102.

[0122] In the above embodiment, the diodes 102 are fabricated to form a diode matrix, which is used as a pixel matrix of the device 100. In a variation, the diodes 102 may be fabricated side by side without forming a diode matrix and / or without regular spacing between them.

Claims

1. A method for manufacturing at least one light emitting diode or light receiving diode (102), the method comprising at least: At least one stack (117) is fabricated on a first substrate (104), the stack comprising a first semiconductor layer (106) and a second semiconductor layer (114) doped according to opposite conductivity types and a third layer (112) of at least one intrinsic semiconductor disposed between the first layer (106) and the second layer (114), the first layer (106) being disposed between the first substrate (104) and the third layer (112); Etching a groove (120) passing through the second layer (114) and the third layer (112) and the first portion (122) of the first layer (106), surrounding the remaining portions (126, 128) of the second layer (114) and the third layer (112) and the remaining portion (130) of the first portion (122) of the first layer (106), and making the bottom wall of the groove be formed by the second portion (123) of the first layer (106) disposed between the first portion (122) of the first layer (106) and the first substrate (104); Making at least one dielectric spacer (132) in the trench (120) covering the sidewalls of the remaining portion (126, 128, 130); Etching to extend the trench (120) through the portion of the second portion (123) of the first layer (106) not covered by the dielectric spacer (132) to the first substrate (104); Laterally etching a portion of the dielectric spacer (132) to expose a contact surface (136) of the second portion (123) of the first layer (106); At least one first electrode (144) is made in the groove (120), and the first electrode (144) contacts the contact surface (136) of the second part (123) of the first layer (106) and the side surface of the second part (123) of the first layer (106).

2. The method according to claim 1, wherein: Before performing the lateral etching, the initial thickness of the dielectric spacer (132) is greater than or equal to 1 μm.

3. The method according to claim 1, wherein: The portion of the dielectric spacer (132) removed during the lateral etching process has a thickness (e2) between 10 nm and the initial thickness (e1) of the spacer minus 10 nm.

4. The method according to claim 1, wherein: The contact surface (136) of the second portion (123) of the first layer (106) is perpendicular to the side walls of the remaining portion (126, 128, 130).

5. The method according to claim 1, wherein: The method further comprises: between making the stack (117) and etching the groove (120) through the second layer (114) and the third layer (112) and the first portion (122) of the first layer (106), making at least one etch mask (118), which is arranged on the stack (117) and has a pattern corresponding to the pattern of the groove (120), and wherein the dielectric spacer (132) is also made by covering the sidewalls of the etch mask (118).

6. The method according to claim 1, wherein: The lateral etching of a portion of the dielectric spacer (132) is an isotropic etch.

7. The method according to claim 5, wherein: The lateral etching of a portion of the dielectric spacer (132) is an isotropic etch, and the etch mask (118) includes at least one material that is at least partially etched during the lateral etching of a portion of the dielectric spacer (132).

8. The method according to claim 6, wherein: The dielectric spacer (132) includes SiO2.

9. The method according to claim 1, wherein: Making the dielectric spacer (132) includes: Depositing at least one layer of a first dielectric material (133), the first dielectric material (133) covering the sidewalls of the remaining portions (126, 128, 130); Depositing at least one layer of a second dielectric material (135) covering the first dielectric material layer (133), the second dielectric material being selected such that during lateral etching of a portion of the dielectric spacer (132) corresponding to anisotropic etching, an etching rate of the second dielectric material is greater than an etching rate of the first dielectric material; And wherein the etching to extend the trench (120) and the lateral etching of a portion of the dielectric spacer (132) are performed simultaneously during the same etching step.

10. The method according to claim 1, wherein: The stack (117) further comprises at least one conductive layer (115), such that the second layer (114) is disposed between the third layer (112) and the conductive layer (115); The trench (120) is etched through the conductive layer (115) and surrounds at least one remaining portion (124) of the conductive layer (115) forming a first portion of the second electrode (146); The dielectric spacer (132) covers the sidewalls of the first portion of the second electrode (146), And the method further comprises the step of forming a second portion of the second electrode (146) after the lateral etching of a portion of the dielectric spacer (132).

11. The method according to claim 10, wherein: The steps of manufacturing the first electrode (144) and the second portion of the second electrode (146) include at least: making at least one opening (138) passing through the stack (117) and exposed on the first portion of the second electrode (146); depositing at least one conductive material (140, 142) in the opening (138) and the trench (120); The conductive material (140, 142) is planarized.

12. The method according to claim 10, wherein: The method further comprises: after manufacturing the first electrode (144) and manufacturing the second portion of the second electrode (146), transferring the light emitting diode or the light receiving diode (102) onto an interconnection substrate (150), so that the first electrode (144) and the second electrode (146) of the light emitting diode or the light receiving diode (102) are electrically connected to the interconnection substrate (150), and then removing the first substrate (104).

13. The method according to claim 10, wherein: The conductive layer (115) is optically reflective.

14. A method for manufacturing an electronic device (100), comprising implementing the method according to claim 1, wherein: The performed steps form a plurality of light emitting diodes (102) and / or a plurality of light receiving diodes (102), wherein the first electrodes (144) of the diodes (102) are electrically connected to each other.

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