Interface circuit of digital isolator, digital isolator and digital isolation circuit

Abstract

The present invention discloses an interface circuit of a digital isolator, a digital isolator, and a digital isolation circuit. The interface circuit includes a transmitting end interface circuit and a receiving end interface circuit; the transmitting end interface circuit includes a transmitting control end and a transmitting end; the receiving end interface circuit includes a receiving control end and a receiving end; the transmitting end interface circuit is used to send data to the other end of the isolation device through the transmitting end when the selection signal is in a first level state; the receiving end interface circuit is used to receive data from the other end of the isolation device through the receiving end when the selection signal is in a second level state. The interface circuit of the digital isolator in the present invention is located on one side of the isolation device, and based on the switching of the high and low levels of the selection signal level, the free selection of the receiving and transmitting functions of the interface circuit can be realized, so that the flexible switching of two-way communication can be realized based on a single-channel digital isolator, and it is conducive to reducing the circuit size, and is economical and efficient.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to an interface circuit of a digital isolator, a digital isolator, and a digital isolation circuit. Background Art

[0002] Digital isolators can prevent data from being damaged when circuits communicate with each other. Digital isolation circuits can transmit data between electrically isolated circuits through digital isolators. Specifically, data is first input into the modulation circuit at the transmitting end, and then the data is output from the demodulation circuit at the receiving end, wherein the modulation circuit and the demodulation circuit are electrically isolated. In order to meet the requirements of bidirectional communication, most current digital isolation circuits are implemented through digital isolators that include both forward and reverse channels. For example, electrical isolation from end A to end B is achieved through the forward channel, and electrical isolation from end B to end A is achieved through the reverse channel. Although this multi-channel digital isolator can meet the requirements of bidirectional communication, it is difficult to achieve flexible switching of bidirectional communication, and is not conducive to reducing the size of the circuit, and is not economical and efficient. Summary of the invention

[0003] The technical problem to be solved by the present invention is to overcome the defect that the digital isolator realizing bidirectional communication in the prior art is not economical and efficient enough, and to provide an interface circuit of a digital isolator, a digital isolator and a digital isolation circuit.

[0004] The present invention solves the above technical problems through the following technical solutions:

[0005] An interface circuit of a digital isolator comprises: a transmitting end interface circuit and a receiving end interface circuit; wherein:

[0006] The transmitting end interface circuit includes a transmitting control end and a transmitting end;

[0007] The receiving end interface circuit includes a receiving control end and a receiving end;

[0008] The sending control end and the receiving control end are both used to receive a selection signal, and the sending end and the receiving end are both electrically connected to the same end of the isolation device of the digital isolator;

[0009] The transmitting end interface circuit is used for sending data to the other end of the isolation device through the transmitting end when the selection signal is in the first level state;

[0010] The receiving end interface circuit is used for receiving data from the other end of the isolation device through the receiving end when the selection signal is in the second level state;

[0011] The first level state is opposite to the second level state.

[0012] Preferably, the sending control end includes a first control end and a second control end, the first control end is used to receive the selection signal, and the second control end is used to receive an inverse signal of the selection signal;

[0013] The transmitting end interface circuit further comprises a first driving circuit and a first switching circuit electrically connected, and further comprises a second driving circuit and a second switching circuit electrically connected, wherein the output ends of the first switching circuit and the second switching circuit are both electrically connected to the transmitting end;

[0014] The first driving circuit is used to generate a first driving signal when the selection signal is in the first level state, and the first switch circuit is used to be turned on according to the first driving signal;

[0015] The second driving circuit is used to generate a second driving signal when the selection signal is in the first level state, and the second switch circuit is used to be turned on according to the second driving signal.

[0016] Preferably, the first switch circuit includes a first PMOS transistor, and the second switch circuit includes a first NMOS transistor; wherein:

[0017] The gate of the first PMOS tube is electrically connected to the first driving circuit, the source is electrically connected to the power supply voltage, and the drain is electrically connected to the transmitting end;

[0018] The gate of the first NMOS tube is electrically connected to the second driving circuit, the source is grounded, and the drain is electrically connected to the transmitting end.

[0019] Preferably, the transmitting end interface circuit further includes a first resistor, a third switch circuit and a fourth switch circuit; wherein:

[0020] The input end of the third switch circuit is electrically connected to the output end of the first switch, the output end of the third switch circuit is electrically connected to the transmitting end, and the third switch circuit is used to be turned on when the first switch circuit is turned on;

[0021] The input end of the fourth switch circuit is electrically connected to the output end of the second switch, the output end of the fourth switch circuit is electrically connected to one end of the first resistor, the other end of the first resistor is electrically connected to the transmitting end, and the fourth switch circuit is used to be turned on when the second switch circuit is turned on.

[0022] Preferably, the third switch circuit includes a second PMOS transistor, and the fourth switch circuit includes a second NMOS transistor; wherein:

[0023] The gate of the second PMOS tube is used to receive the inverse signal of the selection signal, the source is electrically connected to the output end of the first switch, and the drain is electrically connected to the sending end;

[0024] The gate of the second NMOS tube is used to receive the selection signal, the source is electrically connected to the output end of the second switch unit, and the drain is electrically connected to one end of the first resistor.

[0025] Preferably, the receiving end interface circuit further includes a second resistor and a fifth switch circuit; wherein:

[0026] One end of the second resistor is electrically connected to the receiving end, and the other end is electrically connected to the fifth switch circuit;

[0027] The fifth switch circuit is configured to be turned on when the selection signal is in the second level state.

[0028] Preferably, the fifth switch circuit comprises a transmission gate;

[0029] The input end of the transmission gate is electrically connected to the other end of the second resistor, the output end is grounded, the third control end is used to receive the selection signal, and the fourth control end is used to receive the inverted signal of the selection signal.

[0030] A digital isolator comprises an isolation device and an interface circuit of any one of the above digital isolators.

[0031] Preferably, the isolation device comprises two capacitors connected in series; wherein one capacitor is electrically connected to the interface circuit.

[0032] A digital isolation circuit comprises any one of the above digital isolators.

[0033] The positive and progressive effect of the present invention is that the interface circuit of the digital isolator in the present invention is located on one side of the isolation device, and based on the switching of the high and low signal levels, the selection of the transmitting interface circuit and the receiving interface circuit in the interface circuit can be realized, that is, the free selection of the transceiver function of the interface circuit can be realized, so that the flexible switching of two-way communication can be realized based on the single-channel digital isolator, and it is conducive to the reduction of circuit size, which is economical and efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 FIG. 1 is a structural block diagram of an interface circuit of a digital isolator according to Embodiment 1 of the present invention.

[0035] Figure 2 Schematic diagram of the circuit structure of a transmitting end interface circuit in the interface circuit of a digital isolator according to Embodiment 1 of the present invention.

[0036] Figure 3 Schematic diagram of the circuit structure of a receiving-end interface circuit in the interface circuit of a digital isolator according to Embodiment 1 of the present invention. DETAILED DESCRIPTION

[0037] The present invention is further described below by way of examples, but the present invention is not limited to the scope of the examples.

[0038] Example 1

[0039] This embodiment provides an interface circuit of a digital isolator. Figure 1 The interface circuit of this embodiment includes a transmitting end interface circuit 1 and a receiving end interface circuit 2. The transmitting end interface circuit 1 includes a transmitting control end and a transmitting end, and the receiving end interface circuit 2 includes a receiving control end and a receiving end. Both the transmitting control end and the receiving control end are used to receive a selection signal TRSEL, and both the transmitting end and the receiving end are electrically connected to the TR end of the isolation device of the digital isolator.

[0040] In this embodiment, the switching of the high and low levels of the selection signal is used to realize the selection of the transmitting end interface circuit 1 and the receiving end interface circuit 2. Specifically, the transmitting end interface circuit 1 is used to send data to the TR end of the isolation device through the transmitting end when the selection signal TRSEL is in the first level state, so as to transmit the data from the TR end of the isolation device to the other end of the isolation device (not shown in the figure); the receiving end interface circuit is used to receive data from the TR end of the isolation device through the receiving end when the selection signal TRSEL is in the second level state, so as to transmit the data from the other end of the isolation device to the TR end of the isolation device, wherein the first level state is opposite to the second level state.

[0041] Specifically, in this embodiment, the sending control end includes a first control end and a second control end, the first control end is used to receive the selection signal TRSEL, and the second control end is used to receive the inverse signal _TRSEL of the selection signal. Figure 1 The transmitting end interface circuit 1 in this embodiment further includes a first driving circuit 11 and a first switch circuit 12 electrically connected, and a second driving circuit 13 and a second switch circuit 14 electrically connected, wherein the output ends of the first switch circuit 12 and the second switch circuit 14 are both electrically connected to the transmitting end. In this embodiment, the first driving circuit 11 is used to generate a first driving signal when the selection signal TRSEL is in a first level state, the first switch circuit 12 is used to be turned on according to the first driving signal, the second driving circuit 13 is used to generate a second driving signal when the selection signal TRSEL is in a first level state, and the second switch circuit 14 is used to be turned on according to the second driving signal.

[0042] Reference Figure 1The transmitting end interface circuit in this embodiment further includes a first resistor R1, a third switch circuit 15 and a fourth switch circuit 16. The input end of the third switch circuit is electrically connected to the output end of the first switch, the output end of the third switch circuit is electrically connected to the transmitting end, and the third switch circuit is used to be turned on when the first switch circuit is turned on; the input end of the fourth switch circuit is electrically connected to the output end of the second switch, the output end of the fourth switch circuit is electrically connected to one end of the first resistor, the other end of the first resistor is electrically connected to the transmitting end, and the fourth switch circuit is used to be turned on when the second switch circuit is turned on.

[0043] Reference Figure 1 The receiving end interface circuit 2 in this embodiment further includes a second resistor R2 and a fifth switch circuit 21. One end of the second resistor is electrically connected to the receiving end, and the other end is electrically connected to the fifth switch circuit; the fifth switch circuit is used to be turned on when the selection signal TRSEL is in the second level state.

[0044] Figure 2 FIG. 1 is a schematic diagram showing the circuit structure of a transmitting end interface circuit in the interface circuit of a digital isolator according to Embodiment 1 of the present invention. Figure 2 , the first switch circuit 12 includes a first PMOS transistor PM1, and the second switch circuit 14 includes a first NMOS transistor NM1. The gate of the first PMOS transistor PM1 is electrically connected to the first drive circuit, the source and the substrate are electrically connected to the power supply voltage VDD, and the drain is electrically connected to the transmitting end; the gate of the first NMOS transistor NM1 is electrically connected to the second drive circuit, the source and the substrate are grounded GND_TX, and the drain is electrically connected to the transmitting end. Figure 2 , the third switch circuit 15 includes a second PMOS transistor PM2, and the fourth switch circuit 16 includes a second NMOS transistor NM2. The gate of the second PMOS transistor PM2 is used to receive the inverse signal _TRSEL of the selection signal, the source is electrically connected to the output end of the first switch, the drain is electrically connected to the transmitting end, and the substrate is electrically connected to the power supply voltage VDD; the gate of the second NMOS transistor NM2 is used to receive the selection signal TRSEL, the source and the substrate are both electrically connected to the output end of the second switch unit, and the drain is electrically connected to one end of the first resistor.

[0045] Figure 3 FIG. 1 is a schematic diagram showing the circuit structure of a receiving end interface circuit in the interface circuit of a digital isolator according to Embodiment 1 of the present invention. Figure 3 The fifth switch circuit 21 includes a transmission gate TG, an input end of the transmission gate TG is electrically connected to the other end of the second resistor, an output end is grounded, a third control end is used to receive a selection signal TRSEL, and a fourth control end is used to receive an inverted signal _TRSEL of the selection signal.

[0046] Specifically, refer to Figure 2 and Figure 3 When the selection signal TRSEL is at a high level, the transmission gate TG in the receiving interface circuit 2 is in a high impedance state, so that no data is received from the TR end of the isolation device, and the transmitting interface circuit 1 sends data to the TR end of the isolation device through the transmitting end.

[0047] For example, for the data signal DATA, the first driving circuit 11 outputs a low-level first driving signal according to the selection signal TRSEL at a high level, the first PMOS tube PM1 is turned on, and the second PMOS tube PM2 is turned on to send the high-level data signal DATA from the transmitting end to the isolation device; the second driving circuit 13 outputs a high-level second driving signal according to the inverse signal _TRSEL of the selection signal at a low level, the first NMOS tube NM1 is turned on, and the second NMOS tube NM2 is turned on to send the low-level data signal DATA from the transmitting end to the isolation device.

[0048] Reference Figure 2 and Figure 3 When the selection signal TRSEL is at a low level, the second NMOS transistor NM2 and the second PMOS transistor PM2 in the transmitting interface circuit 1 are in a high impedance state, so that no data is sent to the TR end of the isolation device. The transmission gate TG in the receiving interface circuit 2 is turned on, so that data is received from the TR end of the isolation device through the receiving end. The received data is restored after being demodulated by a demodulation circuit (not shown in the figure) in the receiving interface circuit 2.

[0049] Furthermore, this embodiment can ensure the common-mode transient immunity CMTI while realizing the free selection of the transceiver function. Specifically, when the falling edge of CMTI comes, the parasitic diode of the first NMOS tube NM1, the parasitic diode of the second NMOS tube NM2 and the first resistor R1 clamp the negative jump of the TR end of the isolation device to a position that will not annihilate the transmitted data signal, so as to ensure the normal transmission of data. At the same time, the release of the AC withstand voltage at both ends of the digital isolator is also guaranteed. When the rising edge of CMTI comes, the instantaneous positive jump amplitude of the TR end of the isolation device does not exceed the voltage of the power supply voltage VDD, and the normal transmission of data can also be guaranteed. Therefore, this embodiment can still maintain normal data transmission under the impact of common-mode transients.

[0050] Therefore, the interface circuit of the digital isolator in this embodiment is located on one side of the isolation device. Based on the switching of the high and low signal levels, the selection of the transmitting interface circuit and the receiving interface circuit in the interface circuit can be realized, that is, the free selection of the transceiver function of the interface circuit can be realized, so that the flexible switching of the two-way communication can be realized based on the single-channel digital isolator, which is conducive to the reduction of the circuit size and is economical and efficient. In addition, the interface circuit of this embodiment can also resist common-mode transient interference, thereby improving the reliability of the interface circuit.

[0051] Example 2

[0052] This embodiment provides a digital isolator, which specifically includes an isolation device and an interface circuit of the digital isolator provided in Embodiment 1. In this embodiment, the isolation device preferably includes two capacitors connected in series, wherein one capacitor is electrically connected to the interface circuit provided in Embodiment 1, and the other capacitor is electrically connected to another interface circuit. This embodiment is not intended to limit the structure of the other interface circuit.

[0053] The digital isolator in this embodiment can realize the selection of the transmitting interface circuit and the receiving interface circuit in the interface circuit based on the switching of the high and low signal levels, that is, the free selection of the transceiver function of the interface circuit can be realized, so that the flexible switching of the two-way communication can be realized based on the single-channel digital isolator, which is conducive to the reduction of the circuit size and is economical and efficient. In addition, the digital isolator in this embodiment can also resist common-mode transient interference, thereby improving the reliability of the digital isolator.

[0054] Example 3

[0055] This embodiment provides a digital isolation circuit, specifically including the digital isolator provided in Embodiment 2. Therefore, the digital isolation circuit of this embodiment can realize flexible switching of bidirectional communication based on a single-channel digital isolator, and can also resist common-mode transient interference, thereby improving the reliability of the digital isolation circuit.

[0056] Although the specific embodiments of the present invention are described above, it should be understood by those skilled in the art that this is only for illustration and the protection scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.

Claims

1. An interface circuit of a digital isolator, characterized in that: include: The transmitting end interface circuit and the receiving end interface circuit; wherein: The transmitting end interface circuit includes a transmitting control end and a transmitting end; The receiving end interface circuit includes a receiving control end and a receiving end; The sending control end and the receiving control end are both used to receive a selection signal, and the sending end and the receiving end are both electrically connected to the same end of the isolation device of the digital isolator; The transmitting end interface circuit is used for sending data to the other end of the isolation device through the transmitting end when the selection signal is in the first level state; The receiving end interface circuit is used for receiving data from the other end of the isolation device through the receiving end when the selection signal is in the second level state; Wherein, the first level state is opposite to the second level state; The sending control end includes a first control end and a second control end, the first control end is used to receive the selection signal, and the second control end is used to receive an inverse signal of the selection signal; The transmitting end interface circuit further comprises a first driving circuit and a first switching circuit electrically connected, and further comprises a second driving circuit and a second switching circuit electrically connected, wherein the output ends of the first switching circuit and the second switching circuit are both electrically connected to the transmitting end; The first driving circuit is used to generate a first driving signal when the selection signal is in the first level state, and the first switch circuit is used to be turned on according to the first driving signal; The second driving circuit is used to generate a second driving signal when the selection signal is in the first level state, and the second switch circuit is used to be turned on according to the second driving signal.

2. The interface circuit of the digital isolator according to claim 1, characterized in that: The first switch circuit includes a first PMOS transistor, and the second switch circuit includes a first NMOS transistor; wherein: The gate of the first PMOS tube is electrically connected to the first driving circuit, the source is electrically connected to the power supply voltage, and the drain is electrically connected to the transmitting end; The gate of the first NMOS tube is electrically connected to the second driving circuit, the source is grounded, and the drain is electrically connected to the transmitting end.

3. The interface circuit of the digital isolator according to claim 1, characterized in that: The transmitting end interface circuit also includes a first resistor, a third switch circuit and a fourth switch circuit; wherein: The input end of the third switch circuit is electrically connected to the output end of the first switch, the output end of the third switch circuit is electrically connected to the transmitting end, and the third switch circuit is used to be turned on when the first switch circuit is turned on; The input end of the fourth switch circuit is electrically connected to the output end of the second switch, the output end of the fourth switch circuit is electrically connected to one end of the first resistor, the other end of the first resistor is electrically connected to the transmitting end, and the fourth switch circuit is used to be turned on when the second switch circuit is turned on.

4. The interface circuit of the digital isolator as claimed in claim 3, characterized in that: The third switch circuit includes a second PMOS transistor, and the fourth switch circuit includes a second NMOS transistor; wherein: The gate of the second PMOS tube is used to receive the inverse signal of the selection signal, the source is electrically connected to the output end of the first switch, and the drain is electrically connected to the sending end; The gate of the second NMOS transistor is used to receive the selection signal, the source is electrically connected to the output end of the second switch circuit, and the drain is electrically connected to one end of the first resistor.

5. The interface circuit of the digital isolator according to claim 1, characterized in that: The receiving end interface circuit also includes a second resistor and a fifth switch circuit; wherein: One end of the second resistor is electrically connected to the receiving end, and the other end is electrically connected to the fifth switch circuit; The fifth switch circuit is configured to be turned on when the selection signal is in the second level state.

6. The interface circuit of the digital isolator as claimed in claim 5, characterized in that: The fifth switch circuit includes a transmission gate; The input end of the transmission gate is electrically connected to the other end of the second resistor, the output end is grounded, the third control end is used to receive the selection signal, and the fourth control end is used to receive the inverted signal of the selection signal.

7. A digital isolator, characterized in that: An interface circuit comprising an isolation device and the digital isolator according to any one of claims 1 to 6.

8. The digital isolator according to claim 7, characterized in that The isolation device includes two capacitors connected in series, wherein one capacitor is electrically connected to the interface circuit.

9. A digital isolation circuit, characterized in that: Comprising a digital isolator as claimed in claim 7 or 8.

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