A vehicle event data recording (EDR) system test device and test method

Abstract

The present invention discloses a vehicle event data recording EDR system test device and test method, the device comprises a vibration table and an MCU and an FPGA connected to the MCU, a host computer and a test unit fixed on the vibration table, the MCU and the host computer are respectively connected to the central processor built into the vehicle event data recording EDR system to be tested, the MCU is also connected to the vibration table to control the vibration table action, the method comprises: 1) substantial test of the EDR built-in acceleration sensor; 2) EDR functional test. The device is low in cost and can realize large-scale EDR functional test, the method is practical, simple to operate, and has high accuracy in testing the performance effect of EDR.

Description

Technical Field

[0001] The present invention relates to automobile data recording technology, in particular to an automobile event data recording system EDR (Event Data Recorder, EDR for short) testing device and testing method. Background Art

[0002] When a vehicle collision occurs, in order to scientifically analyze and collect evidence of the cause of the collision, a complete and effective vehicle collision event data recording system is needed to record the relevant data of the vehicle when the collision occurs. On the one hand, it can objectively determine the cause of the collision, ensure judicial fairness, and protect the public interest; on the other hand, it can provide a basis for improving the vehicle safety system, avoid similar collisions, and improve vehicle safety. This is the significance of the vehicle event data recording system EDR. Summary of the invention

[0003] The purpose of the present invention is to provide a vehicle event data recording (EDR) system test device and test method in view of the shortcomings of the prior art. The device has low cost and can realize large-scale EDR functional testing. The method has good practicality, simple operation, and high accuracy in testing the performance of EDR.

[0004] The technical solution for achieving the purpose of the present invention is:

[0005] A vehicle event data recording (EDR) system test device comprises a vibration table, an MCU and an FPGA connected to the MCU, a host computer and a test unit fixed on the vibration table, wherein a group of brackets are arranged on the test unit, each bracket is arranged with a group of probes, the number of probes in each group is adjustable, the number of probes in each group matches the number of contacts of the EDR interface to be tested, each group of probes has a number of replaceable probes, the specific number matches the number of contacts of the EDR interface to be tested, 4 of which are used to connect SPI contacts, 2 are used to connect CAN bus differential line signal contacts, 2 are used to connect TXD and RXD signal line contacts of UART, 1 is used to share the GND contact of EDR, 1 is used to power the VCC contact of EDR, and the rest are used to simulate peripheral loads and connect other contacts reserved for EDR, and the probes in two of the brackets in this group of brackets are respectively connected to the standard through high-precision acceleration sensors. The standard first automobile event data recording EDR system and the second automobile event data recording EDR system are used for comparison standards, the remaining brackets in this group of brackets are used to place the automobile event data recording EDR system to be tested, the probe in the bracket for placing the automobile event data recording EDR system to be tested is connected to the acceleration sensor built into the automobile event data recording EDR system to be tested, the test unit is also provided with 6 buffers, of which 3 buffers are used to connect the standard first automobile event data recording EDR system and the second automobile event data recording EDR system with FPGA, and the other 3 buffers are used to connect the automobile event data recording EDR system to be tested with FPGA, the MCU and the host computer are respectively connected to the central processing unit built into the automobile event data recording EDR system to be tested, and the MCU is also connected to the vibration table to control the movement of the vibration table.

[0006] The test unit connected to the vibration table provides the EDR built-in acceleration sensor to be tested with real acceleration information and the peripheral signals, load simulation and power-off test of the EDR controller in the national standard 5.3.2 and the national standard 5.3.5 of the vehicle event data recording system bench test requirements, and provides the necessary MCU-controlled peripheral circuits; the FPGA is responsible for signal acquisition, integration, acceleration sensor simulation and real-time signal processing; the MCU is responsible for burning the EDR program, CAN bus information reception and transmission, forwarding local transmission to the upper computer, information obtained in the EDR and processed by the FPGA, and coordinating and controlling the system platforms; the upper computer is responsible for test waveform editing, independent reception and transmission data verification, and analysis of the effectiveness of the EDR built-in acceleration sensor to be tested, that is, curve fitting. When the EDR to be tested is placed in the bracket, the probe on the bracket directly contacts the contacts of the built-in acceleration sensor in the EDR. There are four circuits on the vibration table: 1. The power supply circuit, data selection circuit, SPI interface selection circuit and the function of the EDR to be tested are 1. Cut off the EDR power supply circuit during the power-off test, select the EDR to be tested of the SPI interface of the FPGA simulation acceleration sensor through the data selector during polling, and block the SPI interface signal of the EDR during the substantial test of the EDR built-in acceleration sensor, so that the acceleration sensor can transmit data to the FPGA instead of the EDR through the contacts; 2. Peripheral load simulation circuit, used to simulate the load conditions such as the real car ignition signal in the actual work of the EDR; 3. Multi-channel SPI bus and CAN bus, used to exchange information with multiple parallel sampling EDR built-in acceleration sensors and provide peripheral signal simulation for multiple EDR central processors; 4. MCU, FPGA power supply circuit, crystal oscillator circuit, used to ensure the normal operation of MCU and FPGA. To ensure that data is not accumulated, the throughput of the rear-stage bus must be higher than that of the front-stage. Therefore, the acquisition bus adopts a multi-channel parallel low-speed SPI bus, the FPGA and MCU adopt the FSMC parallel medium-speed bus, and the MCU and the host computer are connected by the CAN bus.

[0007] The vibration table is a Sushi Test DL-3000-40 large displacement electric vibration test system, which has large displacement, high acceleration, i.e. >50 times the acceleration of gravity, and moderate oscillation period (50-200Hz).

[0008] The model of the MCU is STM32F407ZET7.

[0009] The model of the FPGA is Xilinx Spartan-6 XC6SLX75.

[0010] The test method of the EDR system test device using the above-mentioned automobile event data recording comprises the following steps:

[0011] 1) Substantive testing of EDR built-in acceleration sensor, including:

[0012] 1-1) Signal link selection: including:

[0013] 1-1-1) Place the probe on the SPI interface of the accelerometer;

[0014] 1-1-2) MCU controls the signal selection circuit to release the EDR central processor from the control of the built-in acceleration sensor SPI serial bus;

[0015] 1-1-3) MCU configures the function selection module in FPGA, i.e., the value in the register, through the FSMC interface. That is, MCU addresses the function selection module through the address extension line, and modifies the value of the corresponding address through the reusable data extension line to enable the FSMC interface - waveform storage - bit splicing - CRC check code generation - data framing - parallel-serial conversion - SPI interface link;

[0016] MCU enables CAN control and connects the FSMC interface-data framing-CAN interface data link through the data selection code block;

[0017] 1-2) Data communication: including:

[0018] 1-2-1) FPGA configures 2 high-precision acceleration sensors and several EDR built-in acceleration sensors in parallel through multi-channel SPI interfaces;

[0019] 1-2-2) FPGA receives multiple SPI data in parallel and caches one frame of data from all acceleration sensors;

[0020] 1-2-3) According to the accuracy and sampling rate of the EDR built-in acceleration sensor, extract the data of the high-precision acceleration sensor, and intercept it to the same accuracy as the EDR built-in acceleration sensor, and cache it in DRAM;

[0021] 1-2-4) Extract the useful 14-bit acceleration data from the 32-bit data and perform CRC check. If there is no error, it will be recorded as 1, and if there is an error, it will be recorded as 0. At the same time, perform even check. Concatenate the check result and data into a 16-bit number and store it in the register corresponding to the continuous address of FSMC. After storage, pull up the MCU interrupt line;

[0022] 1-2-5) After the MCU interrupt is set, the interrupt service program is executed, and the block read instruction is used to transmit the data corresponding to several consecutive addresses after the first address of the register used to store acceleration data in the FSMC at one time, and the CAN bus data identifier, i.e., the address, is set, so that the CAN bus data identifier is transmitted to the host computer;

[0023] 1-2-6) The host computer receives the data pushed by the CAN bus in the carrier sense multiple access mode;

[0024] 1-3) Data analysis: including:

[0025] 1-3-1) Reference signal mutual calibration:

[0026] 1-3-1-1) The formula Q=∑(y(i)-y*(i))^2 and ∑y(i)^2 are used to calculate the residual sum of squares and variance. y(i) represents the i-th element of the sampling sequence, and y*(i) represents the i-th element of the standard sequence. In the mutual calibration stage, the two high-precision accelerometers are each other's sampling sequence and standard sequence.

[0027] 1-3-1-2) Calculate the goodness of fit index RNew=1-(Q / ∑y^2)^(1 / 2) based on the residual sum of squares Q and variance;

[0028] 1-3-1-3) If the two sets of fit indicators calculated by the two high-precision acceleration sensors are similar and have a high fit, it is considered that the reference signal mutual calibration is successful and the reference signal is credible, otherwise an alarm is triggered;

[0029] 1-3-2) Determine the y* sequence according to the reference signal, calculate the residual sum of squares between all EDR built-in acceleration sensor sampling sequences and the standard sequence y*, and calculate the variance of all EDR built-in acceleration sensor sampling sequences;

[0030] 1-3-3) Calculate the fit index between the sampling sequence of all EDR built-in acceleration sensors and the standard sequence;

[0031] 1-3-4) Display the fit index of all EDR built-in acceleration sensor sampling sequences on the human-machine interface. When the fit index is too low, it indicates that the EDR built-in acceleration sensor whose fit index is below the threshold is abnormal.

[0032] 2) EDR functional test: EDR functional test includes EDR system trigger test, storage event number test, storage overwrite mechanism test and power-off storage test, specifically:

[0033] 2-1) Test data setting: The host computer inputs data through the user, including test data and acceleration waveform data of peripheral signals received by the EDR controller under the simulated real vehicle state, and caches 5 groups of different test data by calling the database or internal storage. After the cache is completed, the host computer detects the event type corresponding to the data. Among the first 3 groups, group 1 must be a non-locking event, group 2 must be a locking event, and groups 4 and 5 must be locking events;

[0034] 2-2) Signal link selection: including:

[0035] 2-2-1) MCU controls the signal selection circuit to release the EDR central processor from the control of the built-in acceleration sensor SPI serial bus;

[0036] 2-2-2) MCU configures the function selection module in FPGA, i.e., the value in the register, through the FSMC interface. That is, MCU addresses the function selection module through the address extension line, and modifies the value of the corresponding address through the reusable data extension line to enable the SPI-DRAM-CRC check-bit splicing-distributed register-FSMC interface link;

[0037] 2-2-3) MCU enables CAN control and connects the data link between CAN interface and FSMC interface through the data selection code block;

[0038] 2-3) MCU controls the peripheral circuits of the test area, simulates peripheral loads such as ignition signals, polls in sequence according to the position of the EDR to be tested on the test bench, sets the CAN bus identifier and controls the data selector to connect the SPI bus polling to the EDR to be tested corresponding to the identifier;

[0039] 2-4) Import waveform data from the host computer to the RAM storage area in the FPGA. The waveform data should meet the requirements of the national standard for the acceleration of the trigger shock waveform;

[0040] 2-5) Import the peripheral signals received by the EDR controller in the simulation of the real vehicle state from the host computer and cache them in the test array of the MCU. The MCU chooses to use the A-level array elements or the B-level array elements according to the host computer instructions;

[0041] 2-6) The test array in the MCU transmits the data in the array to the EDR under test through the CAN bus, simulating the peripheral signals received by the EDR controller under the actual vehicle state;

[0042] 2-7) After the data in step 2-3-2) is stable after a short delay, the FPGA simulates the acceleration sensor and transmits the acceleration information with the same waveform as that stored in step 2-3-1) to the EDR to be tested, triggering the EDR to record the event;

[0043] 2-8) After the FPGA simulation waveform transmission is completed, the interrupt signal line is pulled high, the MCU enters the interrupt service program, and informs the host computer of the number of experiments currently being performed through the CAN bus. The host computer automatically transmits the next set of test data to the MCU;

[0044] 2-9) Repeat steps 2-4) to 2-8) three times. After receiving the third interrupt signal, the MCU informs the host computer that the test is over. The host computer connects to the EDR to be tested via the CAN bus and reads the data recorded in the three tests.

[0045] 2-10) Through the host computer comparison, if the three experimental data recorded by the EDR are consistent with the data preset by the host computer, it means that the EDR to be tested meets the requirements of the EDR system trigger test and storage event number test specified in the national standard;

[0046] 2-11) Power failure test, simulating the situation where the vehicle power supply system fails at the moment of collision, causing the whole vehicle to lose power, including:

[0047] 2-11-1) Repeat steps 2-4) - 2-7);

[0048] 2-11-2) After receiving the interrupt, the MCU controls the test unit to power off, and after a short delay, it powers on again, and reads the data stored in the EDR through the host computer again, and compares it with the preset data stored in the host computer. If the EDR can still record the preset data completely and correctly, it is considered that the charge stored in the onboard large capacitor can support the EDR to maintain a specific working time, and the power-off test passes;

[0049] 2-12) The host computer repeats steps 2-4) to 2-8) through the CAN bus, and the data transmitted are all data corresponding to event 4, until the EDR controller to be tested does not have enough storage space to record an event;

[0050] 2-13) The host computer repeats steps 2-4) to 2-8) through the CAN bus to continue transmitting a set of data corresponding to event 4;

[0051] 2-14) After receiving the interrupt signal of this transmission, the MCU informs the host computer that the test is over. The host computer connects to the EDR to be tested via the CAN bus and reads all the test record data;

[0052] 2-15) The host computer compares the first three sets of data one by one. If the data corresponding to the unlocked event is overwritten and the overwritten data is consistent with the data of event 4 cached locally on the host computer, the EDR to be tested is considered to meet the requirements of the unlocked event coverage test;

[0053] 2-16) The host computer repeats steps 2-4) to 2-8) through the CAN bus to transmit a set of data corresponding to event 5;

[0054] 2-17) After receiving the interrupt signal of this transmission, the MCU informs the host computer that the test is over. The host computer connects to the EDR to be tested via the CAN bus and reads all the test record data;

[0055] 2-18) All data are compared one by one by the host computer. If no data block consistent with event 5 appears, it is considered that the EDR to be tested meets the requirements of the lock event coverage test;

[0056] 2.19) Power-off test: MCU controls the test bench to power off. After a short delay, it powers on again and reads the data stored in the EDR through the host computer again. All data are compared one by one through the host computer. If they are consistent with the data obtained by the host computer in 2-17), it is considered that the EDR meets the requirements of the power-off test.

[0057] 2.20) Repeat steps 2-3) to 2-19) until all EDRs to be tested are polled.

[0058] This technical solution uses electrical signals to replace traditional mechanical simulation, which greatly reduces the equipment cost. At the same time, compared with the mechanical simulation solution, the use of electrical signals to simulate acceleration information can ensure higher consistency; FPGA is used to collect the sampling data of all built-in acceleration sensors in parallel to ensure that the sampling time of each sensor is consistent with the high-precision acceleration sensor that is calibrated with each other, so as to ensure that the acceleration provided by the vibration table to each sensor is the same, which can realize the substantial test of large-scale built-in acceleration sensors, and the serial port IAP with buffer is used to realize the EDR central processor (ARM The large-scale programming and debugging of the Coterx-M3 architecture microcontroller is realized by using FPGA to simulate the SPI interface timing of the acceleration sensor, and cooperating with the CAN bus communication test to quickly poll the peripheral EDR to be tested, so as to realize the functional test of the EDR on a large scale. The technical scheme adopts the electrical signal to simulate the collision acceleration instead of the built-in acceleration sensor to transmit the acceleration information to the EDR central processor, and completes the functional test of the EDR together with the CAN bus communication test. The built-in acceleration sensor of the EDR is shaken by the vibration table, and the sampling data is obtained by the probe, and its sampling curve is fitted with the sampling curves of two high-precision acceleration sensors that are calibrated with each other. The validity of the built-in acceleration sensor is judged according to the fitting degree, and the substantial test of its built-in acceleration sensor is completed.

[0059] This device is low-cost and can realize large-scale EDR functional testing. This method is practical, simple to operate, and has a high accuracy rate in testing the performance of EDR. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 It is a structural schematic diagram of an embodiment. DETAILED DESCRIPTION

[0061] The content of the present invention is further described below in conjunction with the drawings and embodiments, but the present invention is not limited thereto.

[0062] Example:

[0063] Reference Figure 1, a vehicle event data recording EDR system test device, including a vibration table, and also including an MCU and an FPGA connected to the MCU, a host computer and a test unit fixed on the vibration table, wherein a group of brackets are provided on the test unit, each bracket is provided with a group of probes, the number of probes in each group is adjustable, and the number of probes in each group matches the number of contacts of the EDR interface to be tested. In this example, each group of probes has 4 probes, 4 of which are used to connect SPI contacts, 2 are used to connect CAN bus differential line signal contacts, 2 are used to connect UART TXD and RXD signal line contacts, 1 is used for the GND contact common ground of EDR, 1 is used to power the VCC contact of EDR, and the rest are used for peripheral load simulation and connection of other contacts reserved for EDR. The probes in two of the brackets in this group of brackets are respectively connected to the standard first vehicle event data through high-precision acceleration sensors. The recording EDR system and the second automobile event data recording EDR system are used as standards for comparison. The remaining brackets in this group of brackets are used to place the automobile event data recording EDR system to be tested. The probe in the bracket for placing the automobile event data recording EDR system to be tested is connected to the acceleration sensor built into the automobile event data recording EDR system to be tested. The test unit is also provided with 6 buffers, of which 3 buffers are used to connect the standard first automobile event data recording EDR system and the second automobile event data recording EDR system with FPGA, and the other 3 buffers are used to connect the automobile event data recording EDR system to be tested with FPGA. The MCU and the host computer are respectively connected to the central processing unit built into the automobile event data recording EDR system to be tested, and the MCU is also connected to the vibration table to control the movement of the vibration table.

[0064] The test unit connected to the vibration table provides the EDR built-in acceleration sensor to be tested with real acceleration information and the peripheral signals, load simulation and power-off test of the EDR controller in the national standard 5.3.2 and the national standard 5.3.5 of the vehicle event data recording system bench test requirements, and provides the necessary MCU-controlled peripheral circuits; the FPGA is responsible for signal acquisition, integration, acceleration sensor simulation and real-time signal processing; the MCU is responsible for burning the EDR program, CAN bus information reception and transmission, forwarding local transmission to the upper computer, information obtained in the EDR and processed by the FPGA, and coordinating and controlling the system platforms; the upper computer is responsible for test waveform editing, independent reception and transmission data verification, and analysis of the effectiveness of the EDR built-in acceleration sensor to be tested, that is, curve fitting. When the EDR to be tested is placed in the bracket, the probe on the bracket directly contacts the contacts of the built-in acceleration sensor in the EDR. There are four circuits on the vibration table: 1. The power supply circuit, data selection circuit, SPI interface selection circuit and the function of the EDR to be tested are 1. Cut off the EDR power supply circuit during the power-off test, select the EDR to be tested of the SPI interface of the FPGA simulation acceleration sensor through the data selector during polling, and block the SPI interface signal of the EDR during the substantial test of the EDR built-in acceleration sensor, so that the acceleration sensor can transmit data to the FPGA instead of the EDR through the contacts; 2. Peripheral load simulation circuit, used to simulate the load conditions such as the real car ignition signal in the actual work of the EDR; 3. Multi-channel SPI bus and CAN bus, used to exchange information with multiple parallel sampling EDR built-in acceleration sensors and provide peripheral signal simulation for multiple EDR central processors; 4. MCU, FPGA power supply circuit, crystal oscillator circuit, used to ensure the normal operation of MCU and FPGA. To ensure that data is not accumulated, the throughput of the rear-stage bus must be higher than that of the front-stage. Therefore, the acquisition bus adopts a multi-channel parallel low-speed SPI bus, the FPGA and MCU adopt the FSMC parallel medium-speed bus, and the MCU and the host computer are connected by the CAN bus.

[0065] The vibration table in this example is the Sushi Test DL-3000-40 large displacement electric vibration test system, which has large displacement, high acceleration, i.e. >50 times the acceleration of gravity, and moderate oscillation period (50-200Hz).

[0066] The MCU model in this example is STM32F407ZET7. The program burned into STM32F407ZET7 includes Figure 1 The typical program blocks shown in the figure are all commonly used driver codes, and the program blocks can be connected through Figure 1 The block diagram shown is for data interaction and signal connectivity.

[0067] The FPGA model in this example is Xilinx Spartan-6 XC6SLX75. The digital circuit generated by Xilinx Spartan-6 XC6SLX75 based on the high-level hardware language Verilog includes Figure 1 The typical digital circuit modules shown in the figure are commonly used modules in the fields of communication and signal processing, and the program blocks can be connected through Figure 1 The block diagram shown is for data interaction and signal connectivity.

[0068] The test method of the EDR system test device using the above-mentioned automobile event data recording comprises the following steps:

[0069] 1) Substantive testing of EDR built-in acceleration sensor, including:

[0070] 1-1) Signal link selection: including:

[0071] 1-1-1) Place the probe on the SPI interface of the accelerometer;

[0072] 1-1-2) MCU controls the signal selection circuit to release the EDR central processor from the control of the built-in acceleration sensor SPI serial bus;

[0073] 1-1-3) MCU configures the function selection module in FPGA, i.e., the value in the register, through the FSMC interface. That is, MCU addresses the function selection module through the address extension line, and modifies the value of the corresponding address through the reusable data extension line to enable the FSMC interface - waveform storage - bit splicing - CRC check code generation - data framing - parallel-serial conversion - SPI interface link;

[0074] MCU enables CAN control and connects the FSMC interface-data framing-CAN interface data link through the data selection code block;

[0075] 1-2) Data communication: including:

[0076] 1-2-1) FPGA configures 2 high-precision acceleration sensors and several EDR built-in acceleration sensors in parallel through multi-channel SPI interfaces;

[0077] 1-2-2) FPGA receives multiple SPI data in parallel and caches one frame of data from all acceleration sensors;

[0078] 1-2-3) According to the accuracy and sampling rate of the EDR built-in acceleration sensor, extract the data of the high-precision acceleration sensor, and intercept it to the same accuracy as the EDR built-in acceleration sensor, and cache it in DRAM;

[0079] 1-2-4) Extract the useful 14-bit acceleration data from the 32-bit data and perform CRC check. If there is no error, it will be recorded as 1, and if there is an error, it will be recorded as 0. At the same time, perform even check. Concatenate the check result and data into a 16-bit number and store it in the register corresponding to the continuous address of FSMC. After storage, pull up the MCU interrupt line;

[0080] 1-2-5) After the MCU interrupt is set, the interrupt service program is executed, and the block read instruction is used to transmit the data corresponding to several consecutive addresses after the first address of the register used to store acceleration data in the FSMC at one time, and the CAN bus data identifier, i.e., the address, is set, so that the CAN bus data identifier is transmitted to the host computer;

[0081] 1-2-6) The host computer receives the data pushed by the CAN bus in the carrier sense multiple access mode;

[0082] 1-3) Data analysis: including:

[0083] 1-3-1) Reference signal mutual calibration:

[0084] 1-3-1-1) The formula Q=∑(y(i)-y*(i))^2 and ∑y(i)^2 are used to calculate the residual sum of squares and variance. y(i) represents the i-th element of the sampling sequence, and y*(i) represents the i-th element of the standard sequence. In the mutual calibration stage, the two high-precision accelerometers are each other's sampling sequence and standard sequence.

[0085] 1-3-1-2) Calculate the goodness of fit index RNew=1-(Q / ∑y^2)^(1 / 2) based on the residual sum of squares Q and variance;

[0086] 1-3-1-3) If the two sets of fit indicators calculated by the two high-precision acceleration sensors are similar and have a high fit, it is considered that the reference signal mutual calibration is successful and the reference signal is credible, otherwise an alarm is triggered;

[0087] 1-3-2) Determine the y* sequence according to the reference signal, calculate the residual sum of squares between all EDR built-in acceleration sensor sampling sequences and the standard sequence y*, and calculate the variance of all EDR built-in acceleration sensor sampling sequences;

[0088] 1-3-3) Calculate the fit index between the sampling sequence of all EDR built-in acceleration sensors and the standard sequence;

[0089] 1-3-4) Display the fit index of all EDR built-in acceleration sensor sampling sequences on the human-machine interface. When the fit index is too low, it indicates that the EDR built-in acceleration sensor whose fit index is below the threshold is abnormal.

[0090] 2) EDR functional test: EDR functional test includes EDR system trigger test, storage event number test, storage overwrite mechanism test and power-off storage test, specifically:

[0091] 2-1) Test data setting: The host computer inputs data through the user, including test data and acceleration waveform data of peripheral signals received by the EDR controller under the simulated real vehicle state, and caches 5 groups of different test data by calling the database or internal storage. After the cache is completed, the host computer detects the event type corresponding to the data. Among the first 3 groups, group 1 must be a non-locking event, group 2 must be a locking event, and groups 4 and 5 must be locking events;

[0092] 2-2) Signal link selection: including:

[0093] 2-2-1) MCU controls the signal selection circuit to release the EDR central processor from the control of the built-in acceleration sensor SPI serial bus;

[0094] 2-2-2) MCU configures the function selection module in FPGA, i.e., the value in the register, through the FSMC interface. That is, MCU addresses the function selection module through the address extension line, and modifies the value of the corresponding address through the reusable data extension line to enable the SPI-DRAM-CRC check-bit splicing-distributed register-FSMC interface link;

[0095] 2-2-3) MCU enables CAN control and connects the data link between CAN interface and FSMC interface through the data selection code block;

[0096] 2-3) MCU controls the peripheral circuits of the test area, simulates peripheral loads such as ignition signals, polls in sequence according to the position of the EDR to be tested on the test bench, sets the CAN bus identifier and controls the data selector to connect the SPI bus polling to the EDR to be tested corresponding to the identifier;

[0097] 2-4) Import waveform data from the host computer to the RAM storage area in the FPGA. The waveform data should meet the requirements of the national standard for the acceleration of the trigger shock waveform;

[0098] 2-5) Import the peripheral signals received by the EDR controller in the simulation of the real vehicle state from the host computer and cache them in the test array of the MCU. The MCU chooses to use the A-level array elements or the B-level array elements according to the host computer instructions;

[0099] 2-6) The test array in the MCU transmits the data in the array to the EDR under test through the CAN bus, simulating the peripheral signals received by the EDR controller under the actual vehicle state;

[0100] 2-7) After the data in step 2-3-2) is stable after a short delay, the FPGA simulates the acceleration sensor and transmits the acceleration information with the same waveform as that stored in step 2-3-1) to the EDR to be tested, triggering the EDR to record the event;

[0101] 2-8) After the FPGA simulation waveform transmission is completed, the interrupt signal line is pulled high, the MCU enters the interrupt service program, and informs the host computer of the number of experiments currently being performed through the CAN bus. The host computer automatically transmits the next set of test data to the MCU;

[0102] 2-9) Repeat steps 2-4) to 2-8) three times. After receiving the third interrupt signal, the MCU informs the host computer that the test is over. The host computer connects to the EDR to be tested via the CAN bus and reads the data recorded in the three tests.

[0103] 2-10) Through the host computer comparison, if the three experimental data recorded by the EDR are consistent with the data preset by the host computer, it means that the EDR to be tested meets the requirements of the EDR system trigger test and storage event number test specified in the national standard;

[0104] 2-11-1) Repeat steps 2-4) - 2-7);

[0105] 2-11-2) After receiving the interrupt, the MCU controls the test unit to power off, and after a short delay, it powers on again, and reads the data stored in the EDR through the host computer again, and compares it with the preset data stored in the host computer. If the EDR can still record the preset data completely and correctly, it is considered that the charge stored in the onboard large capacitor can support the EDR to maintain a specific working time, and the power-off test passes;

[0106] 2-12) The host computer repeats steps 2-4) to 2-8) through the CAN bus, and the data transmitted are all data corresponding to event 4, until the EDR controller to be tested does not have enough storage space to record an event;

[0107] 2-13) The host computer repeats steps 2-4) to 2-8) through the CAN bus to continue transmitting a set of data corresponding to event 4;

[0108] 2-14) After receiving the interrupt signal of this transmission, the MCU informs the host computer that the test is over. The host computer connects to the EDR to be tested via the CAN bus and reads all the test record data;

[0109] 2-15) The host computer compares the first three sets of data one by one. If the data corresponding to the unlocked event is overwritten and the overwritten data is consistent with the data of event 4 cached locally on the host computer, the EDR to be tested is considered to meet the requirements of the unlocked event coverage test;

[0110] 2-16) The host computer repeats steps 2-4) to 2-8) through the CAN bus to transmit a set of data corresponding to event 5;

[0111] 2-17) After receiving the interrupt signal of this transmission, the MCU informs the host computer that the test is over. The host computer connects to the EDR to be tested via the CAN bus and reads all the test record data;

[0112] 2-18) All data are compared one by one by the host computer. If no data block consistent with event 5 appears, it is considered that the EDR to be tested meets the requirements of the lock event coverage test;

[0113] 2.19) Power-off test: MCU controls the test bench to power off. After a short delay, it powers on again and reads the data stored in the EDR through the host computer again. All data are compared one by one through the host computer. If they are consistent with the data obtained by the host computer in 2-17), it is considered that the EDR meets the requirements of the power-off test.

[0114] 2.20) Repeat steps 2-3) to 2-19) until all EDRs to be tested are polled.

Claims

1. A test method for an EDR test device of an automobile event data recording system, the test device comprising a vibration table, an MCU and an FPGA connected to the MCU, a host computer and a test unit fixed on the vibration table, the test unit being provided with a group of brackets, each bracket being provided with a group of probes, the number of probes in each group being adjustable, the number of probes in each group matching the number of contacts of an EDR interface to be tested, the probes in two brackets in the group of brackets being connected to a standard first automobile event data recording EDR system and a second automobile event data recording EDR system respectively through high-precision acceleration sensors, the remaining brackets in the group of brackets being used to place automobile events to be tested A data recording EDR system, a probe placed in a bracket of the automobile event data recording EDR system to be tested is connected to an acceleration sensor built into the automobile event data recording EDR system to be tested, the test unit is also provided with 6 buffers, 3 of which are used for connecting the standard first automobile event data recording EDR system and the second automobile event data recording EDR system to be tested with the FPGA, and the other 3 buffers are used for connecting the automobile event data recording EDR system to be tested with the FPGA, the MCU and the host computer are respectively connected to the central processing unit built into the automobile event data recording EDR system to be tested, and the MCU is also connected to a vibration table to control the movement of the vibration table; The vibration table is a Sushi Test DL-3000-40 large displacement electric vibration test system; The model of the MCU is STM32F407ZET7; The model of the FPGA is Xilinx Spartan-6XC6SLX75. It is characterized in that The method comprises the following steps: 1) Substantive testing of EDR built-in acceleration sensor, including: 1-1) Signal link gating, including: 1-1-1) Place the probe on the SPI interface of the accelerometer; 1-1-2) MCU control signal selection circuit releases the EDR central processor from the control of the built-in acceleration sensor SPI serial bus; 1-1-3) MCU configures the function selection module in FPGA, i.e., the value in the register, through the FSMC interface. That is, MCU addresses the function selection module through the address extension line, and modifies the value of the corresponding address through the reusable data extension line to enable the FSMC interface - waveform storage - bit splicing - CRC check code generation - data framing - parallel-to-serial conversion - SPI interface link; MCU enables CAN control and connects the FSMC interface-data framing-CAN interface data link through the data selection code block; 1-2) Data communication, including: 1-2-1) FPGA configures 2 high-precision acceleration sensors and several EDR built-in acceleration sensors in parallel through a multi-channel SPI interface; 1-2-2) FPGA receives multiple SPI data in parallel and caches one frame of data from all acceleration sensors; 1-2-3) extracting the data of the high-precision acceleration sensor according to the accuracy and sampling rate of the EDR built-in acceleration sensor, and intercepting it to the same accuracy as the EDR built-in acceleration sensor, and caching it in DRAM; 1-2-4) Extract the useful 14-bit acceleration data from the 32-bit data and perform CRC check. If there is no error, it will be recorded as 1, and if there is an error, it will be recorded as 0. At the same time, perform even check. Concatenate the check result and data into a 16-bit number and store it in the register corresponding to the continuous address of FSMC. After storage is completed, output an interrupt trigger signal; 1-2-5) After the MCU interrupt is set, the interrupt service program is executed, and the block read instruction is used to transmit the data corresponding to several consecutive addresses after the first address of the register used to store acceleration data in the FSMC at one time, and the CAN bus data identifier, i.e., the address, is set, so that the CAN bus data identifier is transmitted to the host computer; 1-2-6) The host computer receives the data pushed by the CAN bus in the carrier sense multiple access mode; 1-3) Data analysis: including: 1-3-1) Reference signal mutual calibration: 1-3-1-1) The residual sum of squares and variance are calculated using the formula Q = ∑(y(i)-y*(i))^2 and ∑y(i)^2, where y(i) represents the i-th element of the sampling sequence and y*(i) represents the i-th element of the standard sequence. In the mutual calibration stage, the two high-precision accelerometers are each other's sampling sequence and standard sequence; 1-3-1-2) Calculate the goodness of fit index RNew = 1-(Q / ∑y^2)^(1 / 2) based on the residual sum of squares Q and variance; 1-3-1-3) If the two sets of fit indicators calculated by the two high-precision acceleration sensors are similar and have a high fit, it is considered that the reference signal mutual calibration is successful and the reference signal is credible, otherwise an alarm is triggered; 1-3-2) Determine the y* sequence according to the reference signal, calculate the residual sum of squares between all EDR built-in acceleration sensor sampling sequences and the standard sequence y*, and calculate the variance of all EDR built-in acceleration sensor sampling sequences; 1-3-3) Calculate the fit index between the sampling sequence of all EDR built-in acceleration sensors and the standard sequence; 1-3-4) Display the fit index of all EDR built-in acceleration sensor sampling sequences on the human-machine interface. When the fit index is too low, it is prompted that the EDR built-in acceleration sensor whose fit index is below the threshold is abnormal; 2) EDR functional test: EDR functional test includes EDR system trigger test, storage event number test, storage overwrite mechanism test and power-off storage test, specifically: 2-1) Test data setting: The host computer inputs data through the user, including test data and acceleration waveform data of peripheral signals received by the EDR controller under the simulated real vehicle state, and caches 5 groups of different test data by calling the database or internal storage. After the cache is completed, the host computer detects the event type corresponding to the data. Among the first 3 groups, group 1 must be a non-locking event, group 2 must be a locking event, and groups 4 and 5 must be locking events; 2-2) Signal link gating, including: 2-2-1) MCU control signal selection circuit releases the EDR central processor from the control of the built-in acceleration sensor SPI serial bus; 2-2-2) MCU configures the function selection module in FPGA, i.e., the value in the register, through the FSMC interface. That is, MCU addresses the function selection module through the address extension line, and modifies the value of the corresponding address through the reusable data extension line to enable the SPI-DRAM-CRC check-bit splicing-distributed register-FSMC interface link; 2-2-3) MCU enables CAN control and connects the data link between CAN interface and FSMC interface through the data selection code block; 2-3) MCU controls the peripheral circuit of the test area, simulates the peripheral loads such as the ignition signal, polls in sequence according to the position of the EDR to be tested on the test bench, sets the CAN bus identifier and controls the data selector to connect the SPI bus polling with the EDR to be tested corresponding to the identifier; 2-4) Import waveform data from the host computer to the RAM storage area in the FPGA. The waveform data should meet the requirements of the national standard for the acceleration of the trigger shock waveform; 2-5) Import the peripheral signals received by the EDR controller in the simulation of the real vehicle state from the host computer and cache them in the test array of the MCU. The MCU chooses to use the A-level array element or the B-level array element according to the host computer instruction; 2-6) The test array in the MCU transmits the data in the array to the EDR under test through the CAN bus, simulating the peripheral signals received by the EDR controller under the actual vehicle state; 2-7) After the data in step 2-3-2) is stable after a short delay, the FPGA simulates the acceleration sensor and transmits the acceleration information with the same waveform as that stored in step 2-3-1) to the EDR to be tested, triggering the EDR to record the event; 2-8) After the FPGA simulation waveform transmission is completed, the interrupt signal line is pulled high, the MCU enters the interrupt service program, and informs the host computer of the number of experiments currently being performed through the CAN bus. The host computer automatically transmits the next set of test data to the MCU; 2-9) Repeat steps 2-4) to 2-8) three times. After receiving the third interrupt signal, the MCU informs the host computer that the test is over. The host computer connects to the EDR to be tested via the CAN bus and reads the data recorded in the three tests. 2-10) Through the host computer comparison, if the three experimental data recorded by the EDR are consistent with the data preset by the host computer, it means that the EDR to be tested meets the requirements of the EDR system trigger test and storage event number test specified in the national standard; 2-11) Power failure test, simulating the situation where the vehicle power supply system fails at the moment of collision, resulting in power failure of the entire vehicle, including: 2-11-1) Repeat steps 2-4) to 2-7); 2-11-2) After receiving the interrupt, the MCU controls the test unit to power off, and after a short delay, it powers on again, and reads the data stored in the EDR through the host computer again, and compares it with the preset data stored in the host computer. If the EDR can still record the preset data completely and correctly, it is considered that the charge stored in the onboard large capacitor can support the EDR to maintain a specific working time, and the power-off test passes; 2-12) The host computer repeats steps 2-4) to 2-8) through the CAN bus, and the transmitted data are all data corresponding to event 4, until the EDR controller to be tested does not have enough storage space to record an event; 2-13) The host computer repeats steps 2-4) to 2-8) through the CAN bus to continue transmitting a set of data corresponding to event 4; 2-14) After receiving the interrupt signal of this transmission, the MCU informs the host computer that the test is over. The host computer connects to the EDR to be tested via the CAN bus and reads all the test record data; 2-15) The host computer compares the first three sets of data one by one. If the data corresponding to the unlocked event is overwritten and the overwritten data is consistent with the data of event 4 cached locally on the host computer, the EDR to be tested is considered to meet the requirements of the unlocked event coverage test; 2-16) The host computer repeats steps 2-4) to 2-8) through the CAN bus to transmit a set of data corresponding to event 5; 2-17) After receiving the interrupt signal of this transmission, the MCU informs the host computer that the test is over. The host computer connects to the EDR to be tested via the CAN bus and reads all the test record data; 2-18) All data are compared one by one by the host computer. If no data block consistent with event 5 appears, it is considered that the EDR to be tested meets the requirements of the lock event coverage test; 2.19) Power-off test: MCU controls the test bench to power off. After a short delay, it powers on again and reads the data stored in the EDR through the host computer again. All data are compared one by one through the host computer. If they are consistent with the data obtained by the host computer in 2-17), it is considered that the EDR meets the requirements of the power-off test. 2.20) Repeat steps 2-3) to 2-19) until all EDRs to be tested are polled.

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