Semiconductor device and method

Abstract

The present disclosure relates to semiconductor devices and methods. A method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material on the first fin and the second fin; etching the dummy gate material using a first etching process to form a groove between the first fin and the second fin, wherein during the first etching process, a sacrificial material is formed on the sidewalls of the groove; filling the groove with an insulating material; removing the dummy gate material and the sacrificial material using a second etching process; and forming a first replacement gate on the first fin and a second replacement gate on the second fin, wherein the first replacement gate is separated from the second replacement gate by the insulating material.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and methods. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be solved. Summary of the invention

[0004] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a first fin and a second fin protruding from a semiconductor substrate; forming a dummy gate extending above the first fin and the second fin; forming a patterned mask above the dummy gate, the patterned mask comprising an opening located between the first fin and the second fin; etching the dummy gate through the opening in the patterned mask to form a groove in the dummy gate, the etching comprising a plasma etching process, the plasma etching process using a process gas comprising one or more etching gases and one or more polymer forming gases, wherein, during the etching, the process gas reacts with a material of the dummy gate to form a reaction product deposited on a sidewall of the groove; depositing an insulating material to fill the groove, the insulating material covering the reaction product; removing the dummy gate and the reaction product; and forming a first gate structure extending above the first fin and a second gate structure extending above the second fin, wherein the insulating material extends from the first gate structure to the second gate structure.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, including: forming a first fin and a second fin on a substrate; forming a dummy gate material above the first fin and the second fin; etching the dummy gate material using a first etching process to form a groove between the first fin and the second fin, wherein during the first etching process, a sacrificial material is formed on the sidewalls of the groove; filling the groove with an insulating material; removing the dummy gate material and the sacrificial material using a second etching process; and forming a first replacement gate above the first fin and a second replacement gate above the second fin, wherein the first replacement gate is separated from the second replacement gate by the insulating material.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a plurality of first fins protruding from a substrate; a plurality of second fins protruding from the substrate; a first gate stack extending over the plurality of first fins; a second gate stack extending over the plurality of second fins, wherein the first gate stack is longitudinally aligned with the second gate stack; and an isolation region extending between the first gate stack and the second gate stack, the isolation region electrically isolating the first gate stack from the second gate stack, wherein a first distance between the first gate stack and the second gate stack near a top surface of the isolation region is smaller than a second distance between the first gate stack and the second gate stack near a bottom surface of the isolation region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When with Figure 1 When read together, various aspects of the present disclosure will be best understood from the following detailed description. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1-4 , 5A, 5B, 6, 7A, 7B, 7C, 8A, 8B, 8C, 9, 10A, 10B, and 10C illustrate perspective and cross-sectional views of intermediate stages in forming a fin field effect transistor (FinFET) device according to some embodiments.

[0009] Fig.11A , 11B 11C illustrate cross-sectional views of intermediate stages in forming openings for gate isolation regions of FinFET devices, according to some embodiments.

[0010] Fig.12 and Fig.13 A cross-sectional view is shown of an intermediate stage in forming an opening for a gate isolation region of a FinFET device according to other embodiments.

[0011] Fig.14A , 14B , 14C, 15A, 15B, 15C, 16A, and 16B illustrate cross-sectional views of intermediate stages in forming a gate isolation region of a FinFET device according to some embodiments.

[0012] Fig.17A , 17B , 18A, 18B, 18C, 19A, 19B, 19C, 20A, 20B, and 20C illustrate cross-sectional views of intermediate stages in forming a FinFET device with a gate isolation region according to some embodiments.

[0013] Fig.21 and Fig. 22 A cross-sectional view of an intermediate stage in forming a gate isolation region of a FinFET device according to other embodiments is shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted and formed, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0016] According to various embodiments, a semiconductor device and a method for forming the same are provided. Specifically, an isolation region is formed between adjacent gates of a FinFET device. A FinFET device is formed in a gate-last process, wherein a dummy gate is formed from polysilicon in an intermediate step of manufacturing. An etching process is used to form a groove in the dummy gate between adjacent fins, and a sacrificial material is formed on the sidewalls of the groove during the etching process. The etching process is controlled so that the sacrificial material causes the groove to have a top width that is smaller than the bottom width. An isolation material is deposited into the groove to form a gate isolation region having a top width that is smaller than the bottom width. By forming a gate isolation region having such a tapered profile, materials or residues can be more completely removed in subsequent process steps. In addition, a replacement gate material with higher filling efficiency and uniformity can be deposited near the gate isolation region.

[0017] In the various views and illustrative embodiments, similar reference numerals are used to designate similar elements. In some of the illustrated embodiments, the formation of a fin field effect transistor (FinFET) is used as an example to explain the concepts of the present disclosure. Other types of transistors such as planar transistors, gate-around (GAA) transistors, etc. may also employ embodiments of the present disclosure. The embodiments discussed herein provide examples to enable the subject matter of the present disclosure to be made or used, and those of ordinary skill in the art will readily understand the modifications that may be made while remaining within the intended scope of the different embodiments. Similar reference numerals and letters in the following figures refer to similar components. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order. Some of the embodiments discussed herein are discussed in the context of FinFETs formed using a post-gate process. In other embodiments, a gate-first process may be used. In addition, some embodiments consider aspects used in planar devices such as planar FETs.

[0018] Figure 1A perspective view of an initial structure according to some embodiments is shown. The initial structure includes a wafer 10, which further includes a substrate 20. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., using a p-type or n-type dopant) or undoped. The substrate 20 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide layer (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates may also be used. In some embodiments, the semiconductor material of the substrate 20 may include: silicon; germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor comprising silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide and / or gallium indium arsenide phosphide; or a combination thereof.

[0019] exist Figure 1 In the figure, the fin 24 is shown as being formed in the substrate 20. The fin 24 is a semiconductor strip and may be referred to as a "semiconductor strip 24" or a "strip" 24. According to some embodiments of the present disclosure, the fin 24 is part of the original substrate 20, so the material of the fin 24 is the same as the material of the substrate 20. In some embodiments, the fin 24 is formed by etching a portion of the substrate 20 to form a groove. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. The fin 24 may be patterned by any suitable method. For example, one or more photolithography processes (including double patterning or multi-patterning processes) may be used to pattern the fin 24. Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes so that the pattern is created to have, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. A spacer is formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 24. In some embodiments, a mask (or other layer) may remain on the fins 24.

[0020] In some embodiments, fin 24 may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of substrate 20, and a trench may be etched through the dielectric layer to expose substrate 20 below. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form a fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for fin 24. For example, Figure 1The fin 24 in the substrate 20 may be recessed, and a material different from the fin 24 may be epitaxially grown on the recessed fin 24. In such an embodiment, the fin 24 includes a recessed material and an epitaxially grown material disposed on the recessed material. Therefore, the fin 24 may be formed of a semiconductor material different from the semiconductor material of the substrate 20. According to some embodiments, the fin 24 is formed of the following materials: silicon, germanium, a compound semiconductor (including silicon phosphide, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide); an alloy semiconductor (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination thereof.

[0021] In further embodiments, a dielectric layer may be formed over the top surface of substrate 20, and trenches may be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the trench using a material different from substrate 20, and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form fins 24. In some embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, the epitaxially grown material may be doped in situ during growth, which may avoid prior and subsequent implants, but in situ doping and implant doping may be used together.

[0022] like Figure 1 As shown, shallow trench isolation (STI) regions 22 can be formed between fins 24. STI regions 22 may include materials such as oxides (e.g., silicon oxide), nitrides, etc., or combinations thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system, and post-curing to convert it into another material (e.g., oxide), etc., or combinations thereof. Other materials formed by any acceptable process may be used. Once the material is formed, an annealing process may be performed. Although STI regions 22 are shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of substrate 20 and fins 24. Thereafter, a filling material as described above may be formed over the liner.

[0023] After forming the material of the STI region 22, a planarization process may be performed to remove the material of the STI region 22 and expose the fin 24. The planarization process may be, for example, chemical mechanical polishing (CMP), a deep etching process, a combination thereof, etc. The planarization process may expose the fin 24 so that after the planarization process is completed, the top surfaces of the fin 24 and the STI region 22 are flush. In an embodiment where a mask remains on the fin 24, the planarization process may expose the mask or remove the mask so that after the planarization process is completed, the top surface of the mask or the fin 24, respectively, is flush with the top surface of the STI region 22.

[0024] Figure 2 The formation of a dielectric dummy fin 25 according to some embodiments is shown, which can be formed by etching one of the fins 24 to form a groove and then filling the groove with a dielectric material. In other embodiments, the dielectric dummy fin 25 can be formed by etching a groove in the STI region 22 and filling the groove with a dielectric material. In these embodiments, the bottom of the etched groove can be higher than the top surface of the substrate 20, flush with the top surface of the substrate 20, or lower than the top surface of the substrate 20. The dielectric material may include a high-k dielectric material, silicon oxide, silicon nitride, etc. or a combination thereof. In some embodiments, the material of the dielectric dummy fin 25 is selected to have a low etching selectivity relative to the material of the STI region 22. The bottom surface of the dielectric dummy fin 25 can be higher than the bottom surface of the STI region 22, flush with the bottom surface of the STI region 22, or lower than the bottom surface of the STI region 22. The top surface of the dielectric dummy fin 25 can be flush with the surface of the fin 24 or the STI region 22.

[0025] refer to Figure 3 , the STI region 22 is recessed. The STI region 22 may be recessed so that the top portions of the fin 24 and the dielectric dummy fin 25 protrude above the top surface 22A of the remaining portion of the STI region 22 to form protruding fins 24' and 25', respectively. The top surface of the STI region 22 may have a flat surface, a convex surface, a concave surface (e.g., a dish shape), or a combination thereof as shown. The STI region 22 may be recessed using an acceptable etching process, such as an etching process that is selective to the material of the STI region 22 (e.g., etching the material of the STI region 22 at a faster rate than the material of the fin 24 or the dielectric dummy fin 25). For example, etching may be performed using a dry etching process, such as a process in which HF3 and NH3 are used as etching gases. According to an alternative embodiment of the present disclosure, a wet etching process is used to perform the recessing of the STI region 22. For example, dilute hydrofluoric acid (dHF) may be used to remove oxides.

[0026] Further references Figure 3 , dummy gate stacks 30 are formed on the top surfaces and sidewalls of the protruding fins 24' and 25'. Each dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 formed on the dummy gate dielectric 32. Each dummy gate stack 30 may also include a mask layer 36 on the dummy gate electrode 34. The mask layer 36 may include one or more layers.

[0027] The dummy gate dielectric 32 may include, for example, silicon oxide, silicon nitride, combinations thereof, and the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate electrode 34 may be deposited on the dummy gate dielectric 32, and then the dummy gate electrode 34 may be flattened, for example, by CMP. A mask layer 36 may be deposited on the dummy gate electrode 34. The dummy gate electrode 34 may be a conductive material or a non-conductive material, and may be selected from a group including: amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polycrystalline SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate electrode 34 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used to deposit the selected material. The dummy gate electrode 34 may be made of other materials having high etching selectivity relative to the etching of the isolation region. The mask layer 36 may include, for example, silicon nitride, silicon oxide, and the like. Note that dummy gate dielectric 32 is shown covering fins 24 and STI regions 22 , but in other embodiments, dummy gate dielectric 32 may be deposited such that dummy gate dielectric 32 does not extend onto the surface of STI regions 22 .

[0028] Mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride or multiple layers thereof. Dummy gate stack 30 may span single or multiple protruding fins 24' and 25' and / or STI regions 22. The longitudinal direction of dummy gate stack 30 is also perpendicular to the longitudinal direction of protruding fin 24'.

[0029] Next, a gate spacer 38 is formed on the sidewalls of the dummy gate stack 30. In some embodiments, thermal oxidation or deposition followed by anisotropic etching may form the gate spacer 38. According to some embodiments of the present disclosure, the gate spacer 38 is formed of a dielectric material such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon carbon nitride oxide, etc., and may be a single-layer structure or a multi-layer structure including a plurality of dielectric layers. After forming the gate spacer 38, an implantation for a lightly doped source / drain (LDD) region (not explicitly shown) may be performed. In some embodiments, one or more layers of the gate spacer 38 are formed after implanting the LDD region.

[0030] In the embodiments shown above, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more lithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines lithography and self-alignment processes so that the pattern is created to have, for example, a smaller spacing than that obtainable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. A spacer is formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0031] exist Figure 4 In accordance with some embodiments of the present disclosure, an etching step (hereinafter referred to as source / drain recess) may be performed to etch the portion of the protruding fin 24' that is not covered by the dummy gate stack 30 and the gate spacer 38. The recess may be an anisotropic etching process that does not etch the portion of the protruding fin 24' that is directly below the dummy gate stack 30 and the gate spacer 38. The top surface of the recessed fin 24 may be lower than the top surface 22A of the STI region 22. The space left by the etched portion of the protruding fin 24' is referred to as a groove 40. In the etching process, the dielectric dummy fin 25' is not etched. For example, the protruding fin 24' may be etched using a selective etch such as NF3 and NH3, HF and NH3, etc.

[0032] Go to Figure 5A-Figure 5B According to some embodiments, epitaxial source / drain regions 42 are formed. For example, epitaxial source / drain regions 42 may be formed by selectively growing (one or more) semiconductor materials from recesses 40, thereby producing Figure 5A The structure shown. According to some embodiments, the epitaxial source / drain region 42 includes silicon germanium, silicon, silicon carbon, germanium, etc. or a combination thereof. Depending on whether the FinFET produced is a p-type FinFET or an n-type FinFET, p-type or n-type impurities may be in-situ doped during the epitaxial growth process. For example, when the FinFET produced is a p-type FinFET, silicon germanium, germanium, germanium tin, boron-doped silicon germanium (SiGeB), boron-doped germanium, etc. or a combination thereof may be grown. When the FinFET produced is an n-type FinFET, silicon phosphide (SiP), silicon carbide (SiC), phosphorus-doped silicon carbide (SiCP), etc. may be grown. According to an alternative embodiment of the present disclosure, the epitaxial source / drain region 42 is formed of a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination thereof or a multilayer thereof. The epitaxial source / drain region 42 may also have a surface protruding from the corresponding surface of the fin 24 and may have a small facet.

[0033] Figure 5B The formation of epitaxial source / drain regions 42 is shown in accordance with an alternative embodiment of the present disclosure, wherein Figure 4 The protruding fin 24 ′ is shown not being recessed, and the epitaxial source / drain regions 42 are grown on the protruding fin 24 ′. Figure 5B The material of the epitaxial source / drain regions 42 may be similar to Figure 5A The epitaxial source / drain regions 42 shown may be made of materials, depending on whether the resulting FinFET is a p-type or n-type FinFET. In some cases, the epitaxial source / drain regions 42 may be considered to also include the protruding fins 24'. Implantation may (or may not) be performed to implant the epitaxial source / drain regions 42 with n-type impurities or p-type impurities. Subsequent figures illustrate the epitaxial source / drain regions 42 formed by the fins 24'. Figure 5B The structure shown in the figure is formed by the structure, but the embodiments and techniques described herein can be used with Figure 5A The structures shown may be used together with other structures, embodiments or devices.

[0034] exist Figure 6 In the embodiment, a first interlayer dielectric (ILD) 48 is deposited on Figure 5B . The first ILD 48 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or flowable CVD (FCVD). The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), and the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 46 is disposed between the first ILD 48 and the epitaxial source / drain regions 42, the mask layer 36, and the gate spacer 38. The CESL 46 may include a dielectric material having a different etch rate than the material of the overlying first ILD 48, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, and the like. A planarization process (e.g., a CMP process or a mechanical grinding process) may be performed to make the top surfaces of the ILD 48, the dummy gate stack 30, and the gate spacer 38 flush with each other, such as Figure 6 shown.

[0035] Figures 7A to 20C The gate isolation process ( Figures 11A-16B ), followed by a process for forming contacts ( Figures 20A-20C ). The reference numerals of subsequent processes may include the letters "A", "B" or "C". Unless otherwise specified, the drawings with reference numerals with the letter "A" are from the same process as the process including Figure 6 The drawings with reference numerals having the letter "B" are taken from the same vertical plane as the vertical plane of the line AA in FIG. Figure 6 The drawings having reference numerals with the letter "C" are taken from the same vertical plane as the vertical plane of the line BB in FIG. Figure 6 The vertical plane of line CC is obtained in the same vertical plane. Fig.18C , 19C and 20C is from and contains Figure 6 The same vertical plane as the vertical plane of line DD is obtained.

[0036] For example, Fig. 7A , 7B 7C shows a schematic diagram of a method according to some embodiments of the present invention. Figure 6 A cross-sectional view of the structure shown. Fig. 7A Shown along section AA, Figure 7B is shown along section BB, and Figure 7C Shown along section CC.

[0037] exist Fig. 8A , 8B and 8C, according to some embodiments, in Figure 6 , 7A , 7B and 7C, and a mask layer 50 (e.g., a hard mask) is deposited on the structure shown in FIG. 7B and 7C, and a photoresist structure 52 is formed on the mask layer 50. The mask layer 50 may include silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon nitride oxide, silicon oxide, etc., or a combination thereof. The mask layer 50 may be formed by CVD, PVD, ALD, a spin-on dielectric process, etc., or a combination thereof. In some embodiments, the mask layer 50 is formed to have a thickness between about 20 nm and about 120 nm. In some embodiments, the photoresist structure 52 is formed using a spin-on technique, etc., and may be formed to have a thickness between about 5 nm and about 20 nm. These are examples, and other thicknesses or techniques are also possible.

[0038] In some embodiments, the photoresist structure 52 is a three-layer photoresist structure. In these embodiments, the three-layer photoresist structure 52 includes a top photoresist layer, a middle layer, and a bottom layer ( Fig. 8A , 8Band 8C are not separately labeled). As advanced semiconductor manufacturing processes have reached the limits of photolithography processes, thinner top photoresist layers are needed to achieve smaller process windows. However, a thin top photoresist layer may not be sufficient to support etching of a target layer (e.g., mask layer 50). The three-layer photoresist structure 52 can provide a relatively thin top photoresist layer. The middle layer can include an anti-reflective material (e.g., a back anti-reflective coating (BARC) layer) to assist in the exposure and focusing of the processing of the top photoresist layer. By having an middle layer, the thin top photoresist layer is only used to pattern the middle layer. The bottom layer can include a hard mask material, such as a carbon-containing material that is easily removed by O2, N2 / H2 plasma, etc. The middle layer is used to pattern the bottom layer. In some embodiments, the middle layer has a high etching selectivity to the bottom layer, and in some embodiments, the bottom layer is more than 10 times thicker than the middle layer. Thus, the three-layer photoresist structure 52 allows for robust patterning of underlying layers (eg, mask layer 50 ) while still providing a relatively thin top photoresist layer.

[0039] exist Fig. 9 , 10A 10B and 10C, the photoresist structure 52 is patterned to form one or more gate isolation openings 56 that expose the mask layer 50 , according to some embodiments. Fig. 9 shows a perspective view of a structure having a gate isolation opening 56, and Figures 10A-10C The gate isolation opening 56 is used to subsequently form the gate isolation region 60 (see Figures 15A-15C ). Therefore, the gate isolation opening 56 may be located at one or more dummy gate stacks 30 (see Fig. 10A ) and / or one or more dielectric dummy fins 25 (see Fig. 10B and 10C ) above.

[0040] The photoresist structure 52 may be patterned using acceptable photolithography techniques to form the gate isolation openings 56. After the photoresist structure 52 is patterned, a trimming process may be performed on the patterned photoresist structure 52. In an embodiment, the trimming process is an anisotropic plasma etching process, and its process gas includes O2, CO2, N2 / H2, H2, etc., combinations thereof, or any other suitable gas for trimming photoresist.

[0041] In the embodiment where the photoresist structure 52 is a three-layer photoresist structure, the top photoresist layer of the three-layer photoresist 52 can be patterned using any suitable photolithography technique. For example, a photomask (not shown) can be disposed above the top photoresist layer, which can then be exposed to radiation, such as from a laser beam. The exposure of the top photoresist layer can be performed using an immersion lithography system to improve resolution and reduce the minimum accessible spacing. A baking or curing operation can be performed to harden the top photoresist layer, and a developer can be used to remove the exposed or unexposed portion of the top photoresist layer, depending on whether a positive resist or a negative resist is used. After the top photoresist layer of the three-layer photoresist structure 52 is patterned, a trimming process can be performed on the top photoresist layer of the three-layer photoresist structure 52. After the trimming process, the middle and bottom layers may be patterned, leaving a patterned three-layer photoresist structure 52 with gate isolation openings 56, as shown in FIG. Fig. 9 and Figures 10A-10C shown.

[0042] Fig.11A , 11B 11C illustrate the use of patterned photoresist structure 52 as an etch mask to extend gate isolation opening 56 through mask layer 50 and into dummy gate stack 30 in accordance with some embodiments. Fig. 11B and 11C As shown, the gate isolation opening 56 can extend through the dummy gate electrode 34 to the dielectric dummy fin 25. The dielectric dummy fin 25 can be exposed by the gate isolation opening 56, or the dielectric dummy fin 25 can remain covered by the dummy gate dielectric 32. In this way, the gate isolation opening 56 will Fig. 9 and Figure 10A-10C The dummy gate stack 30 of the structure shown is separated into two separate and electrically isolated dummy gate stacks 30. Therefore, forming the gate isolation openings 56 to form separate dummy gate stacks 30 can be considered a "gate cutting" process. It should be understood that a single dummy gate stack 30 can be separated into two or more dummy gate stacks 30 by forming additional gate isolation openings 56 that can be formed simultaneously. In some embodiments, the gate isolation openings 56 can extend from the top surface of the dummy gate electrode 34 to a depth D1 between about 15nm and about 300nm. These are examples, and other dimensions (e.g., depths) or techniques are also possible.

[0043] The gate isolation opening 56 may extend through the mask layer 50 and into the dummy gate stack 30 using one or more suitable etching processes, such as an isotropic dry etching process described in more detail below. In some embodiments, the etching process may also form a sacrificial material 54 on the sidewalls of the gate isolation opening 56, as will be described in more detail below.

[0044] In some embodiments, the gate isolation opening 56 has substantially vertical sidewalls, or has a substantially uniform width. For example, the gate isolation opening 56 has an upper width W1 at or near the top of the gate isolation opening 56, and the upper width W1 can be substantially the same as the lower width W2 at or near the bottom of the gate isolation opening 56. In some embodiments, the gate isolation opening 56 has inclined sidewalls, or has a tapered width, such as Fig. 11B and 11C For example, the upper width W1 of the gate isolation opening 56 may be greater than the lower width W2 thereof. In some embodiments, the lower width W2 of the gate isolation opening 56 may be less than, approximately equal to, or greater than the width of the corresponding dielectric dummy fin 25 .

[0045] In some embodiments, the etching process used to extend the gate isolation opening 56 into the dummy gate electrode 34 also forms a sacrificial material 54 on the sidewalls of the gate isolation opening 56. The sacrificial material 54 can be formed by reaction products deposited on the sidewalls during the etching process. In some embodiments, these reaction products can be formed by chemical reactions between the etching material and various process gases used during the etching process. For example, the sacrificial material 54 can include, for example, oxides, nitrides, polymers, etc. and combinations thereof. In some embodiments, the sacrificial material 54 is formed as a product from a reaction between process gases used during the etching process and / or a reaction between the process gases and the material of the dummy gate electrode 34. For example, the sacrificial layer 54 can include a material such as SiO x 、SiN x 、SiBr x O y 、SiO x Cl y etc., or a combination thereof. Reaction products such as these examples may be formed by reactions involving etchant gases such as Cl2, HBr, N2, etc., and / or polymer gases such as O2, CO2, SO2, HBr, N2, etc., and / or materials such as the previously described dummy gate electrode 34. Other gases, reactions, or reaction products other than these examples may be used to form the sacrificial material 54. Some other examples of process gases that may be used for the etching process are described below.

[0046] During the etching process, sacrificial material 54 may form on exposed surfaces, including on existing sacrificial material 54. Therefore, areas of gate isolation openings 56 formed relatively early during the etching process may have a thicker buildup of sacrificial material 54 than areas formed relatively late during the etching process. This may result in the thickest portion of sacrificial material 54 being near the top of gate isolation openings 56, and the thickness of sacrificial material 54 decreasing with the depth of gate isolation openings 56. Fig. 11B and 11C This was explained, Fig. 11B and 11C The upper region of the gate isolation opening 56 is shown to have a thicker sacrificial material 54 than the lower region of the gate isolation opening 56. In some embodiments, the upper region of the gate isolation opening 56 may have a thickness T1 of the sacrificial material 54 between about 1 nm and about 10 nm. These are examples, and other thicknesses or techniques are possible.

[0047] In some embodiments, the sacrificial material 54 can be formed such that the presence of the sacrificial material 54 reduces the upper width W1 of the gate isolation opening 56 to a width W3 that is less than the upper width W1. In some cases, the width W3 of the gate isolation opening 56 can be approximately the same as or less than the lower width W2. For example, the total thickness of the sacrificial material 54 added to the sidewalls of the gate isolation opening 56 (e.g., 2×T1) can be greater than the difference (W1-W2) between the upper width W1 and the lower width W2 of the gate isolation opening 56. In this manner, the presence of the sacrificial material 54 can form a gate isolation opening 56 that is narrower near the upper region than near the lower region. In some cases, the presence of the sacrificial material 54 can also reduce the lower width W2. By controlling the thickness or distribution of the sacrificial material 54 on the sidewalls of the gate isolation opening 56, the subsequently formed gate isolation region 60 (see Figure 15A-Figure 15C ) shape.

[0048] In some embodiments, the etching process for extending the gate isolation opening 56 and forming the sacrificial material 54 includes a plasma etching process. In some embodiments, the plasma etching process includes one or more process gases, which may include one or more etching gases and / or one or more polymer forming gases. For example, in some embodiments, the etching gas may include Cl2, BCl3, Ar, CH4, C2H2, CF4, C2F2, C4F6, C6F8, CHF3, CH3F, HBr, SiCl4, SF6, NF3, N2, CO2, O2, etc. or a combination thereof. In some embodiments, the polymer forming gas may include gases such as SiCl4, C4F6, C4F8, CHF3, C2H2, CH3F, CH4, HBr, O2, SO2, CO2, N2, etc. or a combination thereof. The pressure of the process gas may be between about 3mTorr and about 300mTorr, or may be another pressure. The process temperature may be between about 0°C and about 120°C, or may be another temperature. In some embodiments, the plasma etching process may include a plasma generated at a power between about 0 watts and about 2500 watts. However, any other suitable process gases, etching techniques or process parameters may be used in other embodiments. In some embodiments, some or all of the photoresist structure 52 may be consumed during the plasma etching process. The plasma etching process may include multiple cycles using various etchants effective for etching of the gate isolation opening 56 and the formation of the sacrificial material 56. Other process gases or process conditions may be used and are considered within the scope of the present disclosure.

[0049] In some embodiments, the type, ratio, or flow rate of the process gas may be controlled to control the formation of the sacrificial material 54 on the sidewalls of the gate isolation opening 56. For example, during the plasma etching process, a larger ratio or a larger flow rate of the polymer forming gas may form a sacrificial material 54 having a larger thickness (e.g., T1), which may reduce the width W3. In some embodiments, the type, ratio, or flow rate of the process gas may be controlled or varied during the etching process to control the formation of the sacrificial material 54. The thickness variation of the sacrificial material 54 within the gate isolation opening 56 may be controlled in this manner, so that the angle of the surface of the sacrificial material 54 relative to the vertical direction may be controlled, or the thickness profile of the sacrificial material 54 within the gate isolation opening 56 may be controlled.

[0050] Fig.12 and Fig.13 A gate isolation opening 56 is shown according to an alternative embodiment. Fig.12 and Fig.13 The gate isolation opening 56 shown in FIG. Fig. 11B A similar cross-sectional view is shown. Fig.12An embodiment is shown in which the bottom of the gate isolation opening 56 extends below the top of the dielectric dummy fin 25. Fig.12 As shown, the etching process can remove portions of the dummy gate dielectric 32. In some embodiments, the gate isolation opening 56 can extend a distance D2 below the top surface of the dielectric dummy fin 25, and the distance D2 is between about 0 nm and about 100 nm. In some embodiments, the gate isolation opening 56 can extend to or into the STI region 22. The gate isolation opening 56 can also have a bottom width W4 that is greater than the width of the dielectric dummy fin 25. In some embodiments, the gate isolation opening 56 can have a bottom width W4 between about 10 nm and about 70 nm. These are examples, and other sizes, shapes, or dimensions are also possible.

[0051] Fig.13 An embodiment is shown where gate isolation opening 56 extends into STI region 22 . Fig.13 An embodiment is also shown in which there is no dielectric dummy gate 25, but in this embodiment and other embodiments described herein, there may be a dielectric dummy gate 25 or fin 24 below the gate isolation opening 56. In some embodiments, the gate isolation opening 56 may extend a distance D3 below the top surface of the dummy gate electrode 34, the distance D3 being between about 20 nm and about 400 nm. In some embodiments, the gate isolation opening 56 may extend completely through the STI region 22 and into the substrate 20. These are examples, and other sizes, shapes, or dimensions are possible.

[0052] exist Fig.14A , 14B In 14C, according to some embodiments, a dielectric material 60' is formed within the gate isolation opening 56 and over the structure. The dielectric material 60' can be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride or silicon oxynitride), etc., or a combination thereof. The dielectric material 60' can be formed by a suitable process such as CVD, HDP-CVD, FCVD, etc., or a combination thereof. These or other dielectric materials can be formed by any acceptable process. The dielectric material 60' can be a material different from the sacrificial material 54, so that the sacrificial material 54 can be selectively etched from the dielectric material 60'.

[0053] exist Fig.15A , 15BIn 15C, according to some embodiments, a planarization process is performed to form a gate isolation region 60. The planarization process removes excess dielectric material 60' from the surface of the structure, and the remaining portion of the dielectric material 60' within the gate isolation opening 56 forms the gate isolation region 60. In some embodiments, the planarization process includes an etching process, such as a wet etching process or a dry etching process, a CMP process, a mechanical grinding process, etc. or a combination thereof. The surface of the gate isolation region 60 and the sacrificial material 54 can be exposed after the planarization process and can be flush with the dummy gate electrode 34 or the first ILD 48. The gate isolation region 60 is between the dummy gate stack 30 and the replacement gate (see Figures 18A-18C ) to provide isolation.

[0054] exist Fig.16A and 16B In the embodiment, the dummy gate dielectric 32 , the dummy gate electrode 34 , and the sacrificial material 54 are removed according to some embodiments. Fig.16A Shows Fig.15A The structure (such as Fig.15A The enlarged part shown in Fig.17A , 18A , 19A and 20A also show this enlarged portion. In some embodiments, the dummy gate dielectric 32, the dummy gate electrode 34 and the sacrificial material 54 are removed using an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate dielectric 32, the dummy gate electrode 34 and the sacrificial material 54 without etching the gate isolation region 60, the first ILD 48 or the gate spacer 38. In some embodiments, a wet etching process or an oxide removal process may be used. In some embodiments, the dummy gate dielectric 32 is removed from the groove 90 in the first region of the die (e.g., the core logic region) and remains in the groove 90 in the second region of the die (e.g., the input / output region). Removal of the dummy gate dielectric 32 and the dummy gate electrode 34 forms a groove 90 that exposes the channel region of the corresponding fin 24. During removal, the dummy gate dielectric 32 may serve as an etch stop layer when etching the dummy gate electrode 34. Then, the dummy gate dielectric 32 may optionally be removed after removing the dummy gate electrode 34 .

[0055] like Fig. 16B As shown, after removing the dummy gate dielectric 32, the dummy gate electrode 34, and the sacrificial material 54, the gate isolation region 60 remains. The remaining gate isolation region 60 can have a size and contour similar to the portion of the corresponding gate isolation opening 56 that includes the sacrificial material 54. The same is true for gate isolation openings 56 having different shapes or sizes, such as Fig.12 and Fig.13 As shown. By controlling the etching of the gate isolation opening 56 and the formation of the sacrificial material 54, the shape and size of the gate isolation region 60 can be controlled. Due to the presence of the sacrificial material 54, the gate isolation region 60 can be formed to have a top width W5 approximately equal to or less than the bottom width W6. Therefore, the gate isolation region 60 can be formed to have a vertical sidewall, or can be formed to have an inclined sidewall or a tapered width. In some embodiments, the top width W5 can be between about 1nm and about 70nm, and the bottom width W6 can be between about 10nm and about 70nm. In some cases, the bottom width W6 can be approximately the same as the lower width W2 of the corresponding gate isolation opening 56. The bottom width W6 of the gate isolation region 60 can be less than, approximately equal to, or greater than the width of the corresponding dielectric dummy fin 25. These are examples, and other sizes, shapes or dimensions are also possible.

[0056] In some cases, forming a gate isolation region having a top width greater than a bottom width may result in a "shadow" effect during anisotropic etching or a subsequent deposition step due to the larger top width. During an etching step or a cleaning step, this shadowing effect may result in residues on the gate isolation region or the surface of the dielectric dummy fin not being completely removed. For example, the residues may include oxides, polymers, materials from the photoresist structure 52 or the mask layer 50, residues from subsequently deposited materials (e.g., subsequently deposited anti-reflective coatings or other materials), etc., or a combination thereof. The presence of such residues may result in undesirable voltage threshold shifts in the FinFET device, incomplete or inefficient metal filling in a subsequent deposition step, and reduced device performance. By forming a gate isolation region 60 having a top width W5 less than a bottom width W6, as Fig. 16B As shown, shadowing effects can be reduced or eliminated, allowing for greater or complete removal of residues and improved metal fill. Thus, the formation of gate isolation regions 60 as described herein can improve device performance, uniformity, and reliability.

[0057] exist Fig.17A and 17B, a gate dielectric layer 92 and a gate electrode 94 for replacing the gate are formed. The gate dielectric layer 92 is conformally deposited in the recess 90, for example, on the top surface and sidewalls of the fin 24, and on the sidewalls of the gate spacer 38. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 48. According to some embodiments, the gate dielectric layer 92 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 92 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 92 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of the dummy gate dielectric 32 remains in the recess 90, the gate dielectric layer 92 includes the material of the dummy gate dielectric 32 (e.g., SiO2).

[0058] The gate electrodes 94 are deposited on the gate dielectric layer 92 and fill the remaining portion of the recess 90. The gate electrodes 94 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, and combinations thereof or multilayers thereof. For example, although the single-layer gate electrode 94 is Fig. 17B , but the gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and filler materials 94C, such as Fig.17A As shown. After filling the recess 90, a planarization process (e.g., CMP) may be performed to remove excess portions of the material of the gate dielectric layer 92 and the gate electrode 94, which are located above the top surface of the ILD 48. Thus, the material of the gate electrode 94 and the remaining portion of the gate dielectric layer 92 form a replacement gate of the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 may be collectively referred to as a "replacement gate stack" or "gate stack". The replacement gate stack may extend along the sidewalls of the channel region of the fin 24. The gate isolation region 60 separates and electrically isolates the replacement gate stack.

[0059] The formation of the gate dielectric layer 92 in different regions of the wafer 10 may occur simultaneously, such that the gate dielectric layer 92 in each region is formed of the same material, and the formation of the gate electrode 94 may occur simultaneously, such that the gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region may be formed by a different process, such that the gate dielectric layer 92 may be a different material, and / or the gate electrode 94 in each region may be formed by a different process, such that the gate electrode 94 may be a different material. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0060] exist Fig.18A , 18B In 18C, a hard mask 62 is formed over the gate stack according to some embodiments. Fig.18C (and the subsequent Fig.19C and 20C ) Figure 6 The cross section DD shown is shown. In some embodiments, the hard mask 62 is formed of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, etc. or a combination thereof. The formation of the hard mask 62 may include using one or more etching processes to recess the gate stack (including the gate dielectric layer 92 and the corresponding overlying gate electrode 94) to form a groove, thereby forming a groove directly above the gate stack and between the opposite portions of the gate spacer 38. Then, a dielectric material is filled into the groove, and a planarization process is performed to remove excess portions of the dielectric material. The remaining portion of the dielectric material is the hard mask 62. The gate contact 110 ( Figures 20A-20C ) passes through the hard mask 62 to contact the top surface of the recessed gate electrode 94.

[0061] Go to Fig.21 and Fig. 22 , a gate isolation region 60 is shown according to an alternative embodiment. Fig.21 and Fig. 22 The gate isolation region 60 is shown in FIG. Fig.18B Similar cross-sectional views are shown. Fig.21 An embodiment is shown in which gate isolation region 60 extends into STI region 22, for example, Fig.13 The gate isolation opening 56 of the illustrated embodiment is formed. Fig.21 Also shown is an embodiment in which no dielectric dummy gate 25 is present, which is consistent with Fig.13 In some embodiments, gate isolation region 60 may extend completely through STI region 22 and into substrate 20 .

[0062] Fig. 22 An embodiment is shown in which a dummy fin 24D is formed instead of a dielectric dummy fin 25. The dummy fin 24D may be formed in a manner similar to the other fins 24. Fig. 22 As shown, gate isolation region 60 extends over dummy fin 24D and into STI region 22. In some embodiments, the bottom of gate isolation opening 56 may be formed to extend below the top of dummy fin 24D, and then filled with dielectric material 60' to form gate isolation region 60. During etching of gate isolation opening 56, the upper portion of dummy fin 24D may be removed. In some embodiments, gate isolation opening 56 may extend to or into STI region 22, or may extend through STI region 22 and into substrate 20.

[0063] Back to Fig.19A , 19B 19C, the second ILD 108 is deposited on the first ILD 48. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD.

[0064] exist Fig. 20A , 20B In 20C, according to some embodiments, a gate contact 110 and a source / drain contact 112 are formed through the second ILD 108 and the first ILD 48. An opening for forming the source / drain contact 112 is formed through the first ILD 48 and the second ILD 108, and an opening for forming the gate contact 110 is formed through the second ILD 108 and the hard mask 62. The opening can be formed using acceptable photolithography and etching techniques. A liner and a conductive material such as a diffusion barrier layer, an adhesion layer, etc. are formed in the opening. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second ILD 108. The remaining liner and conductive material form the source / drain contact 112 and the gate contact 110 in the opening. An annealing process may be performed to form silicide at the interface between the epitaxial source / drain regions 42 and the source / drain contacts 112. The source / drain contacts 112 are physically and electrically coupled to the epitaxial source / drain regions 42, and the gate contact 110 is physically and electrically coupled to the gate electrode 94. The source / drain contacts 112 and the gate contact 110 may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross section, it should be understood that each of the source / drain contacts 112 and the gate contact 110 may be formed in different cross sections, which may avoid contact shorting.

[0065] Although not explicitly shown, it will be readily understood by those skilled in the art that Fig. 20A , 20B Further processing steps are performed on the structure in 20C. For example, various intermetal dielectrics (IMDs) and their corresponding metallizations may be formed over the second ILD 108 .

[0066] Embodiments can achieve advantages. By controlling the formation of sacrificial material during etching of the gate isolation opening, the shape or profile of the gate isolation opening can be controlled. For example, a gate isolation opening having a top width less than a bottom width can be formed. Filling these gate isolation openings with insulating material can form a gate isolation region having a top width less than a bottom width. By forming a gate isolation region with a narrower upper portion, material can be more completely removed from the gate isolation region or the underlying structure (e.g., a dummy fin) during an etching or cleaning step. This can improve process reliability and device reliability and reduce adverse effects such as voltage threshold shifts. In addition, the gate isolation region formed as described herein can allow the gate stack material to be deposited with a higher filling efficiency. Therefore, the technology described herein can allow improved device performance and improved process reliability.

[0067] In some embodiments, a method includes: forming a first fin and a second fin protruding from a semiconductor substrate; forming a dummy gate extending over the first fin and the second fin; forming a patterned mask over the dummy gate, the patterned mask including an opening located between the first fin and the second fin; etching the dummy gate through the opening in the patterned mask to form a recess in the dummy gate, the etching including a plasma etching process, the plasma etching process using a process gas including one or more etching gases and one or more polymer forming gases, wherein during the etching, the process gas reacts with a material of the dummy gate to form a reaction product deposited on a sidewall of the recess; depositing an insulating material to fill the recess, the insulating material covering the reaction product; removing the dummy gate and the reaction product; and forming a first gate structure extending over the first fin and a second gate structure extending over the second fin, wherein the insulating material extends from the first gate structure to the second gate structure. In an embodiment, the reaction product is formed to have a first thickness on the sidewall near the top of the recess that is greater than a second thickness of the reaction product on the sidewall near the bottom of the recess. In an embodiment, the first thickness is in a range between 1 nm and 10 nm. In an embodiment, the reaction product is a polymer comprising silicon. In an embodiment, the reaction product comprises SiO x 、SiN x 、SiBr x O y or SiO x Cl yIn an embodiment, the polymer forming gas comprises at least one of O2, CO2, SO2, N2 or HBr. In an embodiment, the insulating material comprises silicon nitride. In an embodiment, the method comprises forming a hard mask layer on the dummy gate, wherein the groove extends through the hard mask layer. In an embodiment, the dummy gate and the reaction product are removed in the same step.

[0068] In some embodiments, a method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; etching the dummy gate material using a first etching process to form a groove between the first fin and the second fin, wherein during the first etching process, a sacrificial material is formed on the sidewalls of the groove; filling the groove with an insulating material; removing the dummy gate material and the sacrificial material using a second etching process; and forming a first replacement gate over the first fin and a second replacement gate over the second fin, wherein the first replacement gate is separated from the second replacement gate by the insulating material. In an embodiment, the first etching process includes a plasma etching process using an etching gas and a polymer forming gas. In an embodiment, the sacrificial material is formed to have a thickness on an upper portion of the sidewalls of the groove that is greater than a thickness on a lower portion of the sidewalls of the groove. In an embodiment, a top surface of the insulating material has a smaller width than a bottom surface of the insulating material. In an embodiment, the sacrificial material is silicon oxide. In an embodiment, the method includes forming a dummy fin between the first fin and the second fin, wherein the recess exposes the dummy fin, and wherein the insulating material remains on the dummy fin after the second etching process.

[0069] In some embodiments, a device includes: a plurality of first fins protruding from a substrate; a plurality of second fins protruding from the substrate; a first gate stack extending over the plurality of first fins; a second gate stack extending over the plurality of second fins, wherein the first gate stack is longitudinally aligned with the second gate stack; and an isolation region extending between the first gate stack and the second gate stack, the isolation region electrically isolating the first gate stack from the second gate stack, wherein a first distance between the first gate stack and the second gate stack near a top surface of the isolation region is less than a second distance between the first gate stack and the second gate stack near a bottom surface of the isolation region. In an embodiment, the device further includes a dielectric fin extending from a bottom surface of the isolation region toward the substrate, wherein a bottom surface of the dielectric fin is lower than a bottom surface of the first gate stack. In an embodiment, the isolation region extends into the substrate. In an embodiment, the first gate stack extends below a bottom surface of the isolation region. In an embodiment, the first distance is between 1 nm and 70 nm.

[0070] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications in the present disclosure without departing from the spirit and scope of the present disclosure.

[0071] Example 1. A method for manufacturing a semiconductor device, comprising: forming a first fin and a second fin protruding from a semiconductor substrate; forming a dummy gate extending above the first fin and the second fin; forming a patterned mask above the dummy gate, the patterned mask including an opening located between the first fin and the second fin; etching the dummy gate through the opening in the patterned mask to form a groove in the dummy gate, the etching comprising a plasma etching process, the plasma etching process using a process gas including one or more etching gases and one or more polymer forming gases, wherein, during the etching, the process gas reacts with a material of the dummy gate to form a reaction product deposited on a sidewall of the groove; depositing an insulating material to fill the groove, the insulating material covering the reaction product; removing the dummy gate and the reaction product; and forming a first gate structure extending above the first fin and a second gate structure extending above the second fin, wherein the insulating material extends from the first gate structure to the second gate structure.

[0072] Example 2. The method of Example 1, wherein the reaction product is formed to have a first thickness on a sidewall near a top of the groove that is greater than a second thickness of the reaction product on a sidewall near a bottom of the groove.

[0073] Example 3. A method according to Example 2, wherein the first thickness is in a range between 1 nm and 10 nm.

[0074] Example 4. The method of Example 1, wherein the reaction product is a polymer comprising silicon.

[0075] Example 5. The method according to Example 4, wherein the reaction product comprises SiO x 、SiN x 、SiBr x O y or SiO x Cl y At least one of .

[0076] Example 6. The method of Example 1, wherein the polymer-forming gas comprises at least one of O2, CO2, SO2, N2, or HBr.

[0077] Example 7. The method of Example 1, wherein the insulating material comprises silicon nitride.

[0078] Example 8. The method of Example 1, further comprising forming a hard mask layer on the dummy gate, wherein the groove extends through the hard mask layer.

[0079] Example 9. The method of Example 1, wherein the dummy gate and the reaction product are removed in the same step.

[0080] Example 10. A method for manufacturing a semiconductor device, comprising: forming a first fin and a second fin on a substrate; forming a dummy gate material above the first fin and the second fin; etching the dummy gate material using a first etching process to form a groove between the first fin and the second fin, wherein during the first etching process, a sacrificial material is formed on the sidewalls of the groove; filling the groove with an insulating material; removing the dummy gate material and the sacrificial material using a second etching process; and forming a first replacement gate above the first fin and a second replacement gate above the second fin, wherein the first replacement gate is separated from the second replacement gate by the insulating material.

[0081] Example 11. The method of Example 10, wherein the first etching process comprises a plasma etching process using an etching gas and a polymer forming gas.

[0082] Example 12. The method of Example 10, wherein the sacrificial material is formed to have a greater thickness on an upper portion of a sidewall of the recess than on a lower portion of the sidewall of the recess.

[0083] Example 13. The method of Example 10, wherein a top surface of the insulating material has a smaller width than a bottom surface of the insulating material.

[0084] Example 14. The method of Example 10, wherein the sacrificial material is silicon oxide.

[0085] Example 15. The method of Example 10, further comprising forming a dummy fin between the first fin and the second fin, wherein the groove exposes the dummy fin, and wherein the insulating material remains on the dummy fin after the second etching process.

[0086] Example 16. A semiconductor device comprising: a plurality of first fins protruding from a substrate; a plurality of second fins protruding from the substrate; a first gate stack extending over the plurality of first fins; a second gate stack extending over the plurality of second fins, wherein the first gate stack is longitudinally aligned with the second gate stack; and an isolation region extending between the first gate stack and the second gate stack, the isolation region electrically isolating the first gate stack from the second gate stack, wherein a first distance between the first gate stack and the second gate stack near a top surface of the isolation region is less than a second distance between the first gate stack and the second gate stack near a bottom surface of the isolation region.

[0087] Example 17. The semiconductor device of Example 16 further includes a dielectric fin extending from a bottom surface of the isolation region toward the substrate, wherein a bottom surface of the dielectric fin is lower than a bottom surface of the first gate stack.

[0088] Example 18. The semiconductor device of Example 16, wherein the isolation region extends into the substrate.

[0089] Example 19. The semiconductor device of Example 16, wherein the first gate stack extends below a bottom surface of the isolation region.

[0090] Example 20. The semiconductor device of Example 16, wherein the first distance is between 1 nm and 70 nm.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first fin and a second fin protruding from a semiconductor substrate; forming a dummy gate extending over the first fin and the second fin; forming a patterned mask over the dummy gate, the patterned mask comprising an opening between the first fin and the second fin; etching the dummy gate through the opening in the patterned mask to form a recess in the dummy gate, the etching comprising a plasma etching process using a process gas comprising one or more etching gases and one or more polymer forming gases, wherein during the etching, the process gas reacts with a material of the dummy gate to form a reaction product deposited on a sidewall of the recess; depositing an insulating material to fill the groove, wherein the insulating material covers the reaction product; removing the dummy gate and the reaction product; and A first gate structure extending over the first fin and a second gate structure extending over the second fin are formed, wherein the insulating material extends from the first gate structure to the second gate structure.

2. The method according to claim 1, wherein: The reaction product is formed to have a first thickness on a sidewall near a top of the groove that is greater than a second thickness of the reaction product on a sidewall near a bottom of the groove.

3. The method according to claim 2, wherein: The first thickness is in the range of 1 nm to 10 nm.

4. The method according to claim 1, wherein: The reaction product is a polymer that includes silicon.

5. The method according to claim 4, wherein: The reaction product includes SiO x 、SiN x 、SiBr x O y or SiO x Cl y At least one of .

6. The method according to claim 1, wherein: The polymer-forming gas includes at least one of O2, CO2, SO2, N2 or HBr.

7. The method according to claim 1, wherein: The insulating material includes silicon nitride.

8. The method according to claim 1, further comprising forming a hard mask layer on the dummy gate, wherein The recess extends through the hard mask layer.

9. The method according to claim 1, wherein: The dummy gate and the reaction product are removed in the same step.

10. A method for manufacturing a semiconductor device, comprising: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; etching the dummy gate material using a first etching process to form a recess between the first fin and the second fin, wherein during the first etching process, a sacrificial material is formed on a sidewall of the recess; filling the groove with an insulating material; removing the dummy gate material and the sacrificial material using a second etching process; and A first replacement gate is formed over the first fin and a second replacement gate is formed over the second fin, wherein the first replacement gate is separated from the second replacement gate by the insulating material.

11. The method according to claim 10, wherein: The first etching process includes a plasma etching process using an etching gas and a polymer forming gas.

12. The method according to claim 10, wherein: The sacrificial material is formed to have a thickness greater on an upper portion of a sidewall of the groove than on a lower portion of the sidewall of the groove.

13. The method according to claim 10, wherein: A top surface of the insulating material has a smaller width than a bottom surface of the insulating material.

14. The method according to claim 10, wherein: The sacrificial material is silicon oxide.

15. The method according to claim 10, further comprising forming a dummy fin between the first fin and the second fin, wherein The recess exposes the dummy fin, and wherein the insulating material remains on the dummy fin after the second etching process.

16. A semiconductor device comprising: a plurality of first fins protruding from the substrate; a plurality of second fins protruding from the substrate; a first gate stack extending over the plurality of first fins; a second gate stack extending over the plurality of second fins, wherein the first gate stack is longitudinally aligned with the second gate stack; and An isolation region extends between the first gate stack and the second gate stack, the isolation region electrically isolating the first gate stack from the second gate stack, wherein a first distance between the first gate stack and the second gate stack near a top surface of the isolation region is less than a second distance between the first gate stack and the second gate stack near a bottom surface of the isolation region, and wherein a top width of the isolation region is less than a bottom width of the isolation region.

17. The semiconductor device according to claim 16, further comprising a dielectric fin extending from a bottom surface of the isolation region toward the substrate, wherein A bottom surface of the dielectric fin is lower than a bottom surface of the first gate stack.

18. The semiconductor device according to claim 16, wherein: The isolation region extends into the substrate.

19. The semiconductor device according to claim 16, wherein: The first gate stack extends below a bottom surface of the isolation region.

20. The semiconductor device according to claim 16, wherein The first distance is between 1 nm and 70 nm.

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