Semiconductor device manufacturing method

Abstract

Embodiments of the present disclosure provide a semiconductor device and a method of manufacturing the same, which utilizes a passivation dopant to passivate a gate dielectric layer. The passivation dopant is introduced into the gate dielectric layer by a process such as a dip method, through a work function layer. The passivation dopant is an atom that can help passivate electrical trapping defects, such as fluorine.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a fin field-effect transistor. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly shrinking the minimum feature size, which allows more components to be integrated within a given area. However, as the minimum feature size shrinks, additional problems also arise that need to be addressed. Summary of the Invention

[0004] This disclosure provides a method for manufacturing a semiconductor device, comprising: forming a gate dielectric layer on a semiconductor fin; then forming a first work function layer on the gate dielectric layer, the first work function layer having a first thickness after formation; immersing the first work function layer in a first precursor, the first precursor including a passivation dopant; wherein the immersion step of the first work function layer introduces the passivation dopant into the gate dielectric layer; and wherein the first work function layer has a first thickness after immersion. Next, a filler material is formed over the first work function layer.

[0005] This disclosure provides a method for manufacturing a semiconductor device, comprising: depositing a first work function metal to a first thickness on a high-dielectric-constant dielectric on a semiconductor fin; then conformally diffusing fluorine through the high-dielectric-constant dielectric and through the first work function metal into an interface oxide by immersing the first work function metal in nitrogen trifluoride, wherein the first work function metal has a first thickness after conformally depositing the fluorine; and then depositing a filler material after conformally diffusing the fluorine.

[0006] This disclosure provides a semiconductor device, including: a semiconductor fin; an interface layer on the semiconductor fin; a gate dielectric layer on the interface layer; a first work function metal layer on the gate dielectric layer, wherein the first work function metal layer has a first decreasing concentration of fluorine and also has a first increasing concentration of fluorine; and a filling material on the first work function metal layer. Attached Figure Description

[0007] Reading the following detailed description in conjunction with the accompanying drawings is the best way to understand all aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity, the dimensions of the components may be arbitrarily enlarged or reduced.

[0008] Figure 1 According to some embodiments of this disclosure, a perspective view of forming a semiconductor fin is shown.

[0009] Figures 2A to 2B According to some embodiments of this disclosure, steps for forming source / drain regions and removing dummy gate electrodes are shown.

[0010] Figure 3 According to some embodiments of this disclosure, steps for forming a first dielectric layer and a work function layer are shown.

[0011] Figure 4 The soaking process is illustrated according to some embodiments of this disclosure.

[0012] Figure 5 The following are some embodiments of the present disclosure illustrating the steps for forming a filler material.

[0013] Figure 6 The steps for forming the top cover are shown according to some embodiments of the present disclosure.

[0014] Figure 7 This is a first scan of fluorine concentration according to some embodiments of the present disclosure.

[0015] Figure 8 This is a second scan of fluorine concentration according to some embodiments of the present disclosure.

[0016] Explanation of reference numerals in the attached figures:

[0017] 100: Semiconductor devices

[0018] 101: Substrate

[0019] 103: First trench

[0020] 105: First Quarantine Zone

[0021] 107: Fins

[0022] 109: Dummy gate dielectric

[0023] 111: Dummy gate electrode

[0024] 113: First spacer

[0025] 115: Stacking

[0026] 201: Source / Drain Region

[0027] 203: Interlayer dielectric layer

[0028] 301: First dielectric layer

[0029] 303: First (p-type) metallic work function layer

[0030] 305: Interface Layer

[0031] 401: Passivation dopant

[0032] 403: Precursor

[0033] 501: Filler material

[0034] 503: First gate stack

[0035] 601: Cap layer

[0036] 701, 703, 705, 707, 709, 711, 713, 801, 803, 807, 809, 813: Lines

[0037] 715, 815: Background Charts Detailed Implementation

[0038] The following disclosed embodiments provide many different embodiments or examples for implementing various features of this disclosure. Specific examples of the components and their configurations are described below to simplify the description of the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, if the description refers to a first component forming on or on a second component, it may include embodiments where the formed first and second components are in direct contact, or it may include embodiments where an additional component is formed between the first and second components such that they are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in different examples of the embodiments of this disclosure. Such repetition is for brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0039] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," and "higher," may be used to facilitate the description of the relationship between one or more components or features in the accompanying drawings and another component or feature(s). Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0040] The embodiments will be described below with reference to specific examples, including fin field-effect transistor manufacturing processes that prevent blistering and semiconductor devices that reduce the number of blister formations. However, the embodiments are not limited to the examples provided herein, and the concepts of this disclosure can be implemented in a wide variety of embodiments.

[0041] Now refer to Figure 1 This diagram shows a perspective view of a semiconductor device 100, such as a fin field-effect transistor device. In one embodiment, the semiconductor device 100 includes a substrate 101 and a first trench 103. The substrate 101 may be a silicon substrate, although other substrates may also be used, such as semiconductor-on-insulator (SOI), strained SOI, and silicon-germanium on insulator. The substrate 101 may be a p-type semiconductor, although in other embodiments, the substrate 101 may be an n-type semiconductor.

[0042] The first trench 103 can be formed as an initial step in the final formation of the first isolation region 105. A masking layer can be used (in... Figure 1 (Not shown separately) The first trench 103 is formed using a suitable etching process. For example, the mask layer can be a hard mask containing silicon nitride, formed by, for example, a chemical vapor deposition (CVD) process, although other materials can be used, such as oxides, oxide nitrides, silicon carbide, combinations thereof, or similar, and other processes can be used, such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or even nitridation can be performed after the formation of silicon oxide. Once the material of the mask layer is formed, the mask layer can be patterned using a suitable photolithography process to expose the portion of the substrate 101 that will be removed to form the first trench 103.

[0043] Once the mask layer is formed and patterned, a first trench 103 is formed within the substrate 101. To form the first trench 103 within the substrate 101, the exposed substrate 101 can be removed by a suitable process (e.g., reactive ion etching (RIE)), although any suitable process can be used. In one embodiment, the first trench 103 can be formed having a first depth, which is less than approximately [missing information - likely a measurement] from the surface of the substrate 101. For example, about 2500 angstroms.

[0044] However, those skilled in the art to which this disclosure pertains will understand that the aforementioned process for forming the first trench 103 is merely one possible process and is not intended to be the only embodiment. Rather, the first trench 103 can be formed by any suitable process, and any suitable process including any number of masking and removal steps can be used.

[0045] In addition to forming the first trench 103, the masking and etching processes additionally form fins 107 in the portion of the substrate 101 that is retained but not removed. For convenience, the fins 107 are separated from the substrate 101 by dashed lines in the figures, although physical markings of this separation may or may not be present. These fins 107 can be used to form channel regions for multiple-gate FinFETs, as discussed below. Although Figure 1 Only two fins 107 formed from the substrate 101 are shown, but any number of fins 107 can be used.

[0046] Fins 107 can be formed such that the fins 107 have a width between about 5 nanometers and about 80 nanometers on the surface of the substrate 101, for example, about 30 nanometers. Furthermore, the fins 107 are spaced apart from each other at a distance between about 10 nanometers and about 100 nanometers, for example, about 50 nanometers. By separating the fins 107 in this manner, each fin 107 can form a separate channel region, while the fins 107 are still close enough to share a common gate (discussed further below).

[0047] Once the first trench 103 and fin 107 are formed, the first trench 103 is filled with a dielectric material, and the dielectric material can be etched into the first trench 103 to form a first isolation region 105. The dielectric material can be an oxide material, a high-density plasma (HDP) oxide, or the like. After an optional cleaning step and lining formation of the first trench 103, the dielectric material can be formed using a chemical vapor deposition (CVD) method (e.g., a high-aspect-ratio process (HARP)), a high-density plasma chemical vapor deposition method, or one of other suitable formation methods known in the art to which this disclosure pertains.

[0048] The first trench 103 can be filled by overfilling the first trench 103 and the substrate 101 with a dielectric material, followed by removing excess material from the first trench 103 and the exterior of the fin 107 using a suitable process (e.g., chemical mechanical polishing (CMP), etching, a combination of the above, or the like). In one embodiment, the removal process also removes any dielectric material located above the fin 107, thus exposing the surface of the fin 107 for further processing steps.

[0049] Once the first trench 103 is filled with dielectric material, the dielectric material can then be etched away from the surface of the fin 107. The etching step can be performed to expose at least a portion of the sidewalls of the fin 107 adjacent to the top surface of the fin 107. The dielectric material can be etched using wet etching by immersing the top surface of the fin 107 in an etchant such as HF, although other etchants, such as H2, can also be used, as well as other methods such as reactive ion etching, dry etching using NH3 / NF3 as an etchant, chemical oxide removal, or dry chemical cleaning. The dielectric material can be etched down to approximately [distance from the surface of the fin 107]. to approximately The distance between them, for example, approximately In addition, the etching step can also remove any remaining dielectric material located above the fin 107 to ensure that the fin 107 is exposed for further processing.

[0050] However, those skilled in the art to which this disclosure pertains will understand that the foregoing steps may be only part of the overall manufacturing process for filling and etching the dielectric material. For example, a lining step, a cleaning step, an annealing step, a gap-filling step, combinations thereof, and the like may be used to form the first trench 103 and fill it with the dielectric material. The scope of embodiments of this disclosure is fully intended to encompass all possible process steps.

[0051] After forming the first isolation region 105, a dummy gate dielectric 109, a dummy gate electrode 111 on the dummy gate dielectric 109, and a first spacer 113 may be formed on each fin 107. In one embodiment, the dummy gate dielectric 109 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known and used in the art to which this disclosure pertains for forming the gate dielectric. The thickness of the dummy gate dielectric 109 above the top of the fin 107 may differ from the thickness of the dummy gate dielectric 109 on the sidewalls of the fin 107, depending on the technique used to form the gate dielectric.

[0052] The dummy gate dielectric 109 may comprise a material such as silicon dioxide or silicon oxynitride, with a thickness ranging from about 3 angstroms to about 100 angstroms, for example, about 10 angstroms. The dummy gate dielectric 109 may be formed of a high-k material (e.g., having a relative permittivity greater than about 5), such as lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), or zirconium oxide (ZrO₂), or combinations thereof, and have an equivalent oxide thickness of about 0.5 angstroms to about 100 angstroms, for example, about 10 angstroms or less. Furthermore, any combination of silicon dioxide, silicon oxynitride, and / or high-k materials may be used for the dummy gate dielectric 109.

[0053] The dummy gate electrode 111 may comprise a conductive or non-conductive material and may be selected from the group consisting of: polysilicon, W, Al, Cu, AlCu, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof, or similar materials. The dummy gate electrode 111 may be formed by chemical vapor deposition, sputtering deposition, or other techniques known and used in the art to which this disclosure pertains for depositing conductive materials. The thickness of the dummy gate electrode 111 may range from about 5 angstroms to about 200 angstroms. The top surface of the dummy gate electrode 111 may have a non-planar top surface and may be planarized before patterning the dummy gate electrode 111 or etching the gate. At this stage, ions may or may not be introduced into the dummy gate electrode 111. Ions may be introduced, for example, by ion implantation techniques.

[0054] Once the dummy gate dielectric 109 and dummy gate electrode 111 are formed, they can be patterned to form a series of stacks 115 on the fin 107. The stacks 115 define a multi-channel region located on each side of the fin 107 below the dummy gate dielectric 109. A gate mask (in the image) is deposited and patterned on the dummy gate electrode 111 using deposition and photolithography techniques known in the art to which this disclosure pertains. Figure 1 (Not shown separately) A stack 115 can be formed. The gate mask may comprise commonly used masking and sacrificial materials, such as (but not limited to) silicon oxide, silicon oxynitride, SiCON, SiC, SiOC, and / or silicon nitride, and may be deposited to a thickness between about 5 angstroms and about 200 angstroms. A dry etching process can be used to etch the dummy gate electrode 111 and the dummy gate dielectric 109 to form a patterned stack 115.

[0055] Once the stack 115 is patterned, a first spacer 113 can be formed. The first spacer 113 can be formed on opposite sides of the stack 115. Typically, this is achieved by blanketing the spacer layer onto the previously formed structure. Figure 1 The first spacer 113 is formed by means of (not shown separately in the diagram). The spacer layer may comprise SiN, oxide nitride, SiC, SiON, SiOCN, SiOC, oxides, and similar materials, and may be formed by methods for forming such a spacer layer, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition, sputtering, and other methods known in the art to which this disclosure pertains. The spacer layer may comprise different materials with different etch properties, or the same material as the dielectric material in the first isolation region 105. The first spacer 113 may then be patterned by, for example, one or more etching processes to remove the spacer layer from the horizontal surface of the structure to form the first spacer 113.

[0056] In one embodiment, a first spacer 113 may be formed to have a thickness between about 5 angstroms and about 500 angstroms. Furthermore, once the first spacer 113 has been formed, a distance between about 5 nanometers and about 200 nanometers, for example about 20 nanometers, can be used to separate the first spacer 113 adjacent to one stack 115 from the first spacer 113 adjacent to another stack 115. However, any suitable thickness and distance may be used.

[0057] Figures 2A to 2B This illustrates the removal of fins 107 and the regrowth of source / drain regions 201 in areas never protected by the stack 115 and the first spacer 113. Figure 2B This shows that after removing the dummy gate dielectric 109 and the dummy gate electrode 111, along... Figure 2A The single fin 107 of line 2-2'. The step of removing the fin 107 from the area not protected by the stack 115 and the first spacer 113 can be performed using the stack 115 and the first spacer 113 as a hard mask by reactive ion etching (RIE) or by any other suitable removal process. This removal can continue until the fin 107 is coplanar with the surface of the first isolation region 105 (as shown) at or below the surface of the first isolation region 105.

[0058] Once these portions of fin 107 are removed, a hard mask (not shown separately) is placed and patterned to cover the dummy gate electrode 111 to prevent growth, and the source / drain regions 102 can contact each fin 107 for regrowth. In one embodiment, the source / drain regions 201 can regrow, while in some embodiments, the source / drain regions 201 can regrow to form a stressor that applies stress to the channel regions of the fins 107 located beneath the stack 115. In an embodiment where the fins 107 comprise silicon and the fin field-effect transistors are p-type devices, the source / drain regions 201 can be regrowed via a selective epitaxial process using, for example, silicon or other materials having a different lattice constant than the channel regions, such as silicon-germanium. The epitaxial growth process can use precursors such as silanes, dichlorosilanes, germananes, and the like, and can last between about 5 minutes and about 120 minutes, for example, about 30 minutes.

[0059] In one embodiment, the source / drain region 201 may be formed with a thickness between about 5 angstroms and about 1000 angstroms, and a height above the first isolation region 105 between about 10 angstroms and about 500 angstroms, for example, about 200 angstroms. In this embodiment, the source / drain region 201 may be formed with a height between about 5 nanometers and about 250 nanometers, for example, about 100 nanometers, on the upper surface of the first isolation region 105. However, any suitable height may be used.

[0060] Once the source / drain region 201 is formed, suitable dopants can be implanted into the source / drain region 201 to supplement the dopants in the fin 107. For example, p-type dopants such as boron, gallium, indium, or the like can be implanted to form a PMOS device. Alternatively, n-type dopants such as phosphorus, arsenic, antimony, or the like can be implanted to form an NMOS device. These dopants can be implanted using the stack 115 and the first spacer 113 as a mask. It should be noted that those skilled in the art to which this disclosure pertains will appreciate that many other processes, steps, or the like can be used to implant dopants. For example, those skilled in the art to which this disclosure pertains will appreciate that various combinations of spacers and substrates can be used to perform multi-pass implantation processes to form source / drain regions with a specific shape or characteristics suitable for a particular purpose. Any of these processes can be used to implant dopants, and the above description is not intended to limit the embodiments of this disclosure to the steps described above.

[0061] Additionally, the hard mask covering the dummy gate electrode 111 during the formation of the source / drain region 201 is removed at this time. In one embodiment, the hard mask can be removed using, for example, a wet or dry etching process selective for the material of the hard mask. However, any suitable removal process can be used.

[0062] Figure 2A It is also shown that an interlayer dielectric (ILD) layer 203 is formed on the stack 115 and the source / drain regions 201 (in Figure 2A (Seen in dashed lines for clarity of the structure below). The interlayer dielectric layer 203 may comprise a material such as boron phosphorous silicate glass (BPSG), although any suitable dielectric may be used. The interlayer dielectric layer 203 may be formed using a process such as PECVD, although other processes such as LPCVD may be used alternatively. The interlayer dielectric layer 203 may be formed to a thickness between about 100 angstroms and about 3000 angstroms. Once formed, the ILD layer 203 may be planarized using a planarization process such as chemical mechanical polishing to make it flush with the first spacer 113, although any suitable process may be used.

[0063] Figures 2A to 2B Further details illustrate the process for removing and replacing the dummy gate electrode 111 and the dummy gate dielectric 109. In one embodiment, the dummy gate electrode 111 and the dummy gate dielectric 109 can be removed, for example, by one or more wet or dry etching processes using an etchant selective to the materials of the dummy gate electrode 111 and the dummy gate dielectric 109. However, any suitable removal process can be used.

[0064] Figure 3 This illustrates that once the dummy gate electrode 111 and the dummy gate dielectric 109 are removed, the first gate stack 503 can be formed by depositing a series of layers (in...). Figure 3 Not shown in, but shown in Figure 5 The process (in the middle). In one embodiment, the series of layers may include an optional interface layer 305 (in the middle). Figure 3 (represented by dashed lines), first dielectric layer 301 and first p-type metal work function layer 303.

[0065] An optional interface layer 305 may be formed prior to the formation of the first dielectric layer 301. In one embodiment, the interface layer 305 may be a material such as silicon dioxide, formed by a process such as in-situ steam generation (ISSG). In another embodiment, the interface layer 305 may be a high dielectric constant material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, combinations thereof, or similar, with a thickness ranging from about 5 angstroms to about 20 angstroms, for example, about 10 angstroms. However, any suitable material or process may be used to form it.

[0066] Once the interface layer 305 is formed, a first dielectric layer 301 can be formed on the interface layer 305. In one embodiment, the first dielectric layer 301 is a high dielectric constant material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, combinations thereof, or similar materials, deposited by processes such as atomic layer deposition, chemical vapor deposition, or similar methods. The first dielectric layer 301 can be deposited to a thickness between about 5 angstroms and about 200 angstroms, for example, about 12 angstroms, although any suitable material and thickness can be used.

[0067] A first metal work function layer 303 may be formed on a first dielectric layer 301. In one embodiment, the first metal work function layer may be formed of a metallic material, such as TiN, Al, LaO, Ti, TiAlN, TaC, TaCN, TaSiN, TaSi2, NiSi2, Mn, Zr, ZrSi2, TaN, Ru, Mo, MoSi2, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations thereof, or similar. Furthermore, the first p-type metal work function layer 303 may be deposited by, for example, atomic layer deposition, chemical vapor deposition, sputtering, or similar deposition processes, and may be deposited to a thickness between about 5 angstroms and about 50 angstroms, for example, about 12 angstroms, although any suitable deposition process or thickness may be used.

[0068] Furthermore, in other specific embodiments, the first metal work function layer 303 may comprise multiple layers of material, rather than a single layer of a single material. For example, in some embodiments, the first metal work function layer 303 may comprise a first layer of material such as aluminum, and also a second layer of material such as titanium nitride. However, any suitable number of layers and any suitable combination of materials may be used, and the scope of this disclosure is fully intended to encompass all such combinations.

[0069] Figure 4 As shown, once the first metal work function layer 303 is deposited, the passivation dopants (in...) can be... Figure 4 (Indicated by dot 401) It is introduced through the first metal work function layer 303 into the first dielectric layer 301, and optionally into the interface layer 305. The step of introducing the passivation dopant 401 helps to passivate the electrical trapping defects in the first dielectric layer 301 and / or the interface layer 305.

[0070] In one embodiment, the passivating dopant 401 may be an atom or a molecule that diffuses through the first metal work function layer 303 and enters and / or passes through the first dielectric layer 301 and the interface layer 305, and may also passivate defects in the material of the first dielectric layer 301 and the material of the interface layer 305. In a particular embodiment, the passivating dopant 401 may be an atom, such as fluorine, nitrogen, hydrogen, chlorine, a combination thereof, or the like. However, any suitable atom or molecule may be used.

[0071] To introduce the passivation dopant 401 into the first dielectric layer 301 and / or interface layer 305, a precursor (in) can be used. Figure 4 The process is an immersion process (represented by an "X" labeled 403). In such an immersion process, a precursor 403 of the passivation dopant 401 is introduced into a reaction chamber containing a structured reaction chamber comprising a first metal work function layer 303. The passivation dopant 401 is then moved into and through the first metal work function layer 303, into the first dielectric layer 301, and in some embodiments, into the interface layer 305 through flow rate, diffusion, and chemical reaction. However, the precursor 403 can be introduced in any suitable manner.

[0072] In some embodiments, the precursor 403 is one or more molecules containing the desired passivation dopant 401 (e.g., fluorine) and does not react significantly with the material of the first metal work function layer 303. Therefore, while the specific precursor 403 selected depends at least in part on the specific material selected for the passivation dopant 401 and the specific material selected for the first metal work function layer 303, in embodiments where the passivation dopant 401 is fluorine and the material of the first metal work function layer 303 is titanium nitride, the precursor 403 may be a fluorine-containing precursor, such as nitrogen trifluoride (NF3), fluorine (F2), combinations thereof, or the like. However, any other suitable precursor suitable for the selected dopant may also be used, such as nitrogen (N2), ammonia (NH3), hydrogen (H2), chlorine (Cl2), combinations thereof, or the like.

[0073] In one embodiment, the precursor 403 may be introduced into the first metal work function layer 303 at a flow rate such that the fresh quantity of precursor 403 compensates for any concentration decrease that occurs in the reaction chamber due to the diffusion of previously introduced precursor 403 into the first metal work function layer 303 and / or reaction. For example, the precursor 403 may be introduced at a flow rate between about 0.2 L / min and about 1.8 L / min, such as 1 L / min. However, any suitable flow rate may be used.

[0074] Furthermore, in some embodiments, precursor 403 may be introduced together with a diluent or carrier gas to facilitate the transport and control of precursor 403. In one embodiment using nitrogen trifluoride as precursor 403, a diluent such as nitrogen, hydrogen, or argon may also be introduced into the reaction chamber. In one embodiment, the diluent may be introduced at a flow rate between about 1 L / min and about 6 L / min. However, any suitable flow rate may be used.

[0075] The introduction of precursor 403 can be performed under process conditions that ensure no other unwanted reactions or processes occur, and that the desired diffusion and reaction (described further below) take place. For example, in some embodiments, to accelerate the diffusion process while avoiding unwanted reactions between the precursor and diluent (e.g., unwanted reactions between nitrogen trifluoride and nitrogen), the introduction step can be performed at temperatures below 600°C, such as between about 250°C and 350°C. Similarly, the process can be performed at pressures below about 1 torr, such as between about 0.4 torr and about 0.5 torr. However, any suitable process conditions may be used.

[0076] During the immersion process, the precursor 403 diffuses into the first metal work function layer 303, through the first metal work function layer 303, and at least into the first dielectric layer 301, and in some embodiments, into the interface layer 305. Once in the first dielectric layer 301 or the interface layer 305, the precursor 403 reacts with open sites and / or dangling bonds in the first dielectric layer 301, thereby bonding the passivating dopant 401 (e.g., fluorine) to the material of the first dielectric layer 301 and passivating defects in the materials of the first dielectric layer 301 and the interface layer 305.

[0077] Furthermore, once the passivation dopant 401 reacts to passivate the defects in the first dielectric layer 301 and the interface layer 305, the remaining portion of the precursor 403 (e.g., nitrogen in an embodiment where the precursor is nitrogen trifluoride) will leave the structure. For example, once the passivation dopant 401 is relieved, the remaining portion of the precursor 403 will diffuse from the first dielectric layer 301 and the interface layer 305 to the outside, from the first metal work function layer 303 to the outside, and diffuse into the surrounding atmosphere. In this way, only the passivation dopant 401 remains in the structure, and the remaining portion of the precursor 403 is degassed from the structure.

[0078] The immersion process can be sustained for a period of time sufficient for the passivation dopant 401 to diffuse through the first metal work function layer 303 into the first dielectric layer 301, and in some embodiments, into the interface layer 305 and continue for a period of time sufficient for the reaction of the precursor 403 and subsequent degassing to occur. In one embodiment, the process can be sustained for a period of time between about 10 minutes and about 2 hours, for example, about 1 hour. However, any suitable time may be used.

[0079] By using the thermal soaking process described herein, the passivation dopant 401 can be implanted more conformally than other methods. For example, by immersing the first metal work function layer 303 in an environment where the concentration of the precursor 403 is nearly constant (due to, for example, the constant flow of the precursor 403 and its associated mixing), the precursor 403 will diffuse into the first metal work function layer 303 from all directions. Compared to other more directional implantation methods (e.g., ion implantation processes), this diffusion from all directions results in a more conformally dispersed distribution of the passivation dopant 401 in the first dielectric layer 301. This greater degree of control allows for greater process margin, thus improving the overall process.

[0080] Furthermore, by using the precursor 403 described herein, less damage caused by undesirable chemical reactions can occur during implantation. For example, in other processes using highly reactive species (e.g., diatomic fluorine (F2)), longer processing times are required to ensure adequate incorporation of the passivation dopant 401, and during these longer processing times, fluorine can react undesirably with the material of the first work function layer 303, potentially leading to undesirable etching of the first work function layer 303. By using the less reactive precursor 403, which does not significantly react with the material of the first p-type work function layer 303, the material of the first work function layer 303 will remain intact, and the first work function layer 303 will maintain the same thickness before and after the introduction of the precursor 403.

[0081] Figure 5 The diagram illustrates that once the passivation dopant 401 is introduced, a glue layer (not shown separately) and a filler material 501 can be formed. In one embodiment, the glue layer can be formed to help bond the upper filler material 501 to the lower material and to provide a nucleation layer for forming the filler material 501. In one embodiment, the glue layer can be a material such as titanium nitride and can be formed to a thickness between about 10 angstroms and about 100 angstroms, for example, about 50 angstroms, using a similar process (e.g., ALD). However, any suitable material and process can be used.

[0082] Once the adhesive layer is formed, a filler material 501 is deposited to fill the remaining portion of the opening. In one embodiment, the filler material 501 may be, for example, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof, or similar materials, and may be formed using deposition processes such as electroplating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, or similar materials. Furthermore, the filler material 501 may be deposited to a thickness between about 100 angstroms and about 2000 angstroms, for example, about 1500 angstroms. However, any suitable material may be used.

[0083] Figure 5 It is also shown that after the deposited filler material 501 fills and overfills the opening, the filler material 501 can be planarized to form the first gate stack 503. In one embodiment, this material can be planarized using, for example, a chemical mechanical polishing process, to make it separate from the first spacer 113 (see...). Figure 1 It can be flush, although any suitable process, such as grinding or etching, can be used.

[0084] After the material of the first gate stack 503 is formed and planarized, the material of the first gate stack 503 may be etched and capped using a capping layer 601. In one embodiment, the material of the first gate stack 503 may be etched using, for example, a wet or dry etching process that uses an etchant selective to the material of the first gate stack 503. In one embodiment, the material of the first gate stack 503 may be etched at a distance between about 5 nanometers and about 150 nanometers, for example, about 120 nanometers. However, any suitable process and distance may be used.

[0085] Once the material of the first gate stack 503 is etched, a capping layer 601 can be deposited and planarized to be flush with the first spacer 113. In one embodiment, the material of the capping layer 601 is, for example, SiN, SiON, SiCON, SiC, SiOC, combinations thereof, or the like, and is deposited using deposition processes such as atomic layer deposition, chemical vapor deposition, sputtering, or the like. The capping layer 601 can be deposited to a thickness between about 5 angstroms and about 200 angstroms, and then planarized using a planarization process such as chemical mechanical polishing to make the capping layer 601 flush with the first spacer 113.

[0086] Figure 7The diagram shows energy dispersive spectroscopy (EDS) graphs of various atoms in substrate 101, first dielectric layer 301, first metal work function layer 303, and filler material 501 in a specific embodiment. To prepare for the scan in this embodiment, a hot immersion was performed for 1 hour at a flow rate of 1 L / min, a temperature of 300°C, and a pressure of 100 Pa. Furthermore, in this embodiment, the first metal work function layer 303 comprises multiple layers of various materials, such as a first layer of aluminum followed by a second layer of titanium nitride. In this scan, line 701 represents the concentration of silicon, line 703 represents the concentration of hafnium, line 705 represents the concentration of tungsten, line 707 represents the concentration of titanium, line 709 represents the concentration of aluminum, line 711 represents the concentration of nitrogen, and line 713 represents the concentration of oxygen. Additionally, background graph 715 represents the concentration of fluorine.

[0087] As can be seen, the concentration of fluorine in the passivation dopant 401 reaches a maximum in the first dielectric layer 301, and the concentration decreases from this maximum in both directions. Furthermore, in this embodiment where multiple layers of different materials exist, the concentration of fluorine in the first metal work function layer 303 will also decrease and then increase.

[0088] Figure 8 The diagram shows, in another embodiment, the energy dispersive spectra of various atoms in the substrate 101, the first dielectric layer 301, the first metal work function layer 303, and the filling material 501. (For preparation...) Figure 8 The scan was performed by hot immersion for 1 hour at a flow rate of 1.5 L / min, a temperature of 350 °C, and a pressure of 100 Pa. Furthermore, in this embodiment, the first metal work function layer 303 comprises a monolayer material, such as TiN. In this scan, line 801 represents the concentration of silicon, line 803 represents the concentration of hafnium, line 807 represents the concentration of titanium, line 809 represents the concentration of aluminum, and line 813 represents the concentration of oxygen. Additionally, background graph 815 represents the concentration of fluorine.

[0089] As can be seen, the concentration of fluorine in the passivation dopant 401 reaches a maximum in the first dielectric layer 301, and the concentration decreases from this maximum in both directions. Furthermore, the concentration of fluorine continues to decrease as it passes through the first metal work function layer 303 and enters the filler material 501.

[0090] By utilizing the thermal soaking method described herein, the passivation dopant 401 can be more conformally introduced into the first dielectric layer 301. Furthermore, by using a precursor that does not significantly react with the material of the first metal work function layer 303, conformal introduction can be performed without causing unnecessary etching and degradation of the first metal work function layer 303. This allows for greater process control and a higher process margin.

[0091] In one embodiment, a method of manufacturing a semiconductor device includes: forming a gate dielectric layer on a semiconductor fin; forming a first work function layer on the gate dielectric layer, the first work function layer having a first thickness after formation; immersing the first work function layer in a first precursor, the first precursor including a passivation dopant, wherein the immersion step of the first work function layer introduces the passivation dopant into the gate dielectric layer, and wherein the first work function layer has a first thickness after immersion; and forming a filler material over the first work function layer. In one embodiment, the passivation dopant is fluorine. In one embodiment, the precursor containing the passivation dopant is nitrogen trifluoride. In one embodiment, the immersion step of the gate dielectric is performed at a temperature below 600°C. In one embodiment, the immersion step of the gate dielectric is performed at a temperature between about 250°C and about 350°C. In one embodiment, nitrogen trifluoride is introduced at a flow rate between about 1 liter per minute and about 1.8 liters per minute. In one embodiment, the first work function layer includes titanium nitride.

[0092] In another embodiment, a method of manufacturing a semiconductor device includes: depositing a first work function metal to a first thickness on a high-dielectric-constant dielectric on a semiconductor fin; conformally diffusing fluorine through the high-dielectric-constant dielectric and through the first work function metal into an interface oxide by immersing the first work function metal in nitrogen trifluoride, wherein the first work function metal has a first thickness after conformally depositing the fluorine; and depositing a filler material after conformally diffusing the fluorine. In one embodiment, the step of immersing the first work function metal includes flowing nitrogen trifluoride at a flow rate between about 1 liter per minute and about 1.8 liters per minute. In one embodiment, the step of immersing the first work function metal includes flowing nitrogen gas at a flow rate between about 1 liter per minute and about 6 liters per minute. In one embodiment, the step of immersing the first work function metal is performed at a temperature between about 250°C and about 350°C. In one embodiment, the step of immersing the first work function metal is performed at a pressure less than about 1 torr. In one embodiment, the step of immersing the first work function metal is performed at a pressure between about 0.4 torr and about 0.5 torr. In another embodiment, the step of immersing the first work function metal is performed for a time between about 10 minutes and about 1 hour.

[0093] In another embodiment, a semiconductor device includes: a semiconductor fin; an interface layer on the semiconductor fin; a gate dielectric layer on the interface layer; a first work function metal layer on the gate dielectric layer, wherein the first work function metal layer has a first decreasing concentration of fluorine and also has a first increasing concentration of fluorine; and a filler material on the first work function metal layer. In one embodiment, the first work function metal layer includes a first layer of a first material and a second layer of a second material different from the first material. In one embodiment, the first material is titanium nitride, and the second material is aluminum. In one embodiment, the gate dielectric layer includes hafnium oxide. In one embodiment, the first work function metal layer includes titanium nitride. In one embodiment, the interface layer includes silicon oxide and has a decreasing concentration of fluorine.

[0094] The foregoing outlines components of several embodiments to facilitate a better understanding of the views expressed in the embodiments of this disclosure by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of this disclosure to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the concept and scope of this disclosure, and that various changes, substitutions, and replacements can be made without departing from the concept and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A gate dielectric layer is formed on a semiconductor fin; A first work function layer is formed on the gate dielectric layer. The first work function layer has a first thickness after its formation, and the first work function layer has a first exposed surface after its formation. A first precursor is introduced onto the semiconductor fin, wherein at the beginning of the introduction step, the first exposed surface remains exposed, and wherein the introduction step immerses the first exposed surface of the first work function layer in the first precursor, the first precursor comprising a passivation dopant, wherein the step of immersing the first work function layer introduces the passivation dopant into the gate dielectric layer, and wherein the first work function layer has the first thickness after immersion, wherein the passivation dopant is fluorine, and wherein fluorine has a concentration distribution that increases from a minimum concentration toward an upper surface and a lower surface of the first work function layer; and A filling material is formed above the first work function layer.

2. The semiconductor device manufacturing method of claim 1, wherein the precursor of the passivation dopant is nitrogen trifluoride.

3. The semiconductor device manufacturing method of claim 2, wherein the step of immersing the gate dielectric is performed at a time less than... Performed at a temperature of C.

4. The semiconductor device manufacturing method of claim 3, wherein the step of immersing the gate dielectric is performed between... C and Performed at temperatures between C.

5. The semiconductor device manufacturing method of claim 4, wherein nitrogen trifluoride is introduced at a flow rate between 1 liter per minute and 1.8 liters per minute.

6. The semiconductor device manufacturing method of claim 5, wherein the first work function layer comprises titanium nitride.

7. A method for manufacturing a semiconductor device, the method comprising: A first work function metal is deposited to a first thickness on a high dielectric constant dielectric material on a semiconductor fin, the first work function metal having a first exposed surface; By immersing the first work function metal in nitrogen trifluoride, fluorine is conformally diffused through the high dielectric constant dielectric and through the first work function metal into an interface oxide, wherein the first work function metal has the first thickness after conformally depositing fluorine, the first exposed surface is exposed at the start of immersion of the first work function metal, and wherein fluorine has a concentration distribution that increases from a minimum concentration toward an upper surface and a lower surface of the first work function metal; and A filler material is deposited after conformal diffusion of fluorine.

8. The semiconductor device manufacturing method of claim 7, wherein the step of immersing the first work function metal includes flowing nitrogen trifluoride at a flow rate between 1 liter per minute and 1.8 liters per minute.

9. The semiconductor device manufacturing method of claim 8, wherein the step of immersing the first work function metal includes flowing nitrogen gas at a flow rate between 1 liter per minute and 6 liters per minute.

10. The semiconductor device manufacturing method of claim 7 or 8, wherein the step of immersing the first work function metal is performed between C and Performed at temperatures between C.

11. The semiconductor device manufacturing method of claim 7 or 8, wherein the step of immersing the first work function metal is performed at a pressure of less than 1 torr.

12. The semiconductor device manufacturing method of claim 11, wherein the step of immersing the first work function metal is performed at a pressure between 0.4 torr and 0.5 torr.

13. The semiconductor device manufacturing method of claim 7 or 8, wherein the step of immersing the first work function metal is performed for a time between 10 minutes and 1 hour, and wherein after conformal diffusion of fluorine, the first work function metal has a first decreasing concentration of fluorine and also has a first increasing concentration of fluorine.

14. A method for manufacturing a semiconductor device, the method comprising: An interface layer is formed on a semiconductor fin; A gate dielectric layer is formed on the interface layer; A first work function metal layer is formed on the interface layer, wherein the first work function metal layer has a first decreasing concentration of fluorine and also a first increasing concentration of fluorine, wherein fluorine has a concentration distribution that increases from a minimum concentration toward an upper surface and a lower surface of the first work function metal layer; and A filling material is formed on the first work function metal layer.

15. The semiconductor device manufacturing method of claim 14, wherein the step of forming the first work function metal layer includes forming a first layer of a first material and forming a second layer of a second material different from the first material.

16. The semiconductor device manufacturing method of claim 15, wherein the first material is titanium nitride and the second material is aluminum.

17. The semiconductor device manufacturing method of claim 14 or 15, wherein the step of forming the gate dielectric layer includes forming hafnium oxide.

18. The semiconductor device manufacturing method of claim 14 or 15, wherein the step of forming the first work function metal layer includes forming titanium nitride.

19. The semiconductor device manufacturing method of claim 14 or 15, wherein the step of forming the interface layer includes forming silicon oxide having a decreasing concentration of fluorine.

20. A semiconductor device, the device comprising: A gate dielectric layer is located on a semiconductor fin; A first work function layer is located on the gate dielectric layer, wherein the first work function layer has a first fluorine concentration gradient and a second fluorine concentration gradient opposite to the first fluorine concentration gradient, wherein fluorine has a concentration distribution that increases from a minimum concentration toward an upper surface and a lower surface of the first work function layer; and A filling material is located on the first work function layer.

21. The semiconductor device of claim 20, wherein the first work function layer comprises titanium nitride.

22. The semiconductor device of claim 20 or 21, further comprising an interface layer located between the semiconductor fin and the gate dielectric layer.

23. The semiconductor device of claim 22, wherein the gate dielectric layer has a third fluorine concentration gradient.

24. The semiconductor device of claim 23, wherein the interface layer has a fourth fluorine concentration gradient.

25. The semiconductor device of claim 20 or 21, wherein the first work function layer comprises titanium nitride and aluminum.

26. The semiconductor device of claim 20 or 21, wherein the first work function layer comprises tungsten nitride.

27. A semiconductor device, the device comprising: A semiconductor fin is located on a semiconductor substrate; A gate dielectric is located above the semiconductor fin; A first work function layer is located above the gate dielectric; Fluorine is located in the first work function layer, wherein the concentration of fluorine varies throughout the first work function layer, and the maximum concentration of fluorine is located at a position far from any surface of the first work function layer, wherein the concentration of fluorine has a distribution that increases from the minimum concentration toward an upper surface and a lower surface of the first work function layer; and A filling material is located on the first work function layer.

28. The semiconductor device of claim 27, wherein the first work function layer comprises titanium nitride.

29. The semiconductor device of claim 28, wherein the first work function layer comprises aluminum.

30. The semiconductor device of claim 27 or 28, further comprising an interface layer located between the semiconductor fin and the gate dielectric layer.

31. The semiconductor device of claim 30, wherein fluorine extends into both the gate dielectric and the interface layer.

32. The semiconductor device of claim 31, wherein fluorine has a varying concentration throughout the gate dielectric, and the maximum concentration of fluorine is located at a position away from any surface of the gate dielectric.

33. The semiconductor device of claim 32, wherein the fluorine in the interface layer has the highest concentration near the gate dielectric.

34. A semiconductor device, the device comprising: A semiconductor fin; An interface layer is applied to the semiconductor fin; A gate dielectric layer is located on the interface layer; A first work function metal layer is located on the gate dielectric layer, wherein the first work function metal layer has a first decreasing concentration of fluorine and also a first increasing concentration of fluorine, wherein fluorine has a concentration distribution that increases from a minimum concentration toward an upper surface and a lower surface of the first work function metal layer; and A filler material is located on the first work function metal layer.

35. The semiconductor device of claim 34, wherein the first work function metal layer comprises a first layer of a first material and a second layer of a second material different from the first material.

36. The semiconductor device of claim 35, wherein the first material is titanium nitride and the second material is aluminum.

37. The semiconductor device of claim 34 or 35, wherein the gate dielectric layer comprises hafnium oxide.

38. The semiconductor device of claim 34 or 35, wherein the first work function metal layer comprises titanium nitride.

39. The semiconductor device of claim 34 or 35, wherein the interface layer comprises silicon oxide and has a decreasing concentration of fluorine.

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