Semiconductor device and manufacturing method

Abstract

The present disclosure relates to semiconductor devices and methods of manufacture. Semiconductor devices and methods utilizing a treatment process for a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process, in which materials are added to fill holes and pores within the material of the bottom anti-reflective layer, or the treatment process may be a chemical treatment process, in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer, diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects caused by such diffusion.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices and methods of manufacturing. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a first layer over a raised semiconductor region; applying a bottom anti-reflective layer over the first layer, the bottom anti-reflective layer having a first diffusivity relative to a first chemical substance; patterning the bottom anti-reflective layer; reducing the first diffusivity to a second diffusivity relative to the first chemical substance; and removing a portion of the first layer using the first chemical substance when the bottom anti-reflective layer is present.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: depositing a hard mask layer over a work function layer over a semiconductor fin; depositing a bottom anti-reflective layer over the hard mask layer; patterning the bottom anti-reflective layer; processing the bottom anti-reflective layer, wherein processing the bottom anti-reflective layer reduces the diffusivity of a first etchant through the bottom anti-reflective layer; and removing a portion of the hard mask layer using the first etchant when the bottom anti-reflective layer is present.

[0006] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: depositing a lanthanum oxide layer over a semiconductor fin; depositing an aluminum oxide layer over the lanthanum oxide layer; placing a bottom anti-reflection layer over the aluminum oxide layer; patterning the bottom anti-reflection layer; adding a material to the bottom anti-reflection layer after patterning the bottom anti-reflection layer; etching a portion of the aluminum oxide layer when the bottom anti-reflection layer is present; and etching a portion of the lanthanum oxide layer when the bottom anti-reflection layer is present. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A perspective view illustrating the formation of semiconductor fins in accordance with some embodiments.

[0009] Figure 2 The formation of source / drain regions is shown in accordance with some embodiments.

[0010] Figure 3 The formation of a bottom anti-reflective layer and a photoresist according to some embodiments is shown.

[0011] Figure 4 Removal of photoresist is shown in accordance with some embodiments.

[0012] Figure 5 Processing of a bottom anti-reflective layer according to some embodiments is shown.

[0013] Figure 6 A first removal process is shown in accordance with some embodiments.

[0014] Figure 7 A second removal process is shown in accordance with some embodiments.

[0015] Figure 8 Removal of a bottom anti-reflective layer is shown in accordance with some embodiments.

[0016] Fig. 9 The formation of a fill material according to some embodiments is shown.

[0017] Fig.10 The formation of a cap is shown according to some embodiments.

[0018] Fig.11 The formation of a protective layer according to some embodiments is shown.

[0019] Fig.12 A first removal process with a protective layer is shown in accordance with some embodiments.

[0020] Fig.13 A second removal process with a protective layer is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0023] Embodiments will now be described with respect to specific examples including a finFET manufacturing process with blister prevention and a semiconductor device with a reduced number of bubble formations. However, the embodiments are not limited to the examples provided herein and the concepts may be implemented in a wide variety of embodiments.

[0024] Reference now Figure 1 , a perspective view of a semiconductor device 100 such as a finFET device is shown. In one embodiment, the semiconductor device 100 includes a substrate 101 and a first trench 103. The substrate 101 may be a silicon substrate, but other substrates such as semiconductor on insulator (SOI), strained SOI, and silicon germanium on insulator may also be used. The substrate 101 may be a p-type semiconductor, but in other embodiments, it may be an n-type semiconductor.

[0025] The first trench 103 may be formed as an initial step in the final formation of the first isolation region 105. A masking layer ( Figure 1The first trench 103 is formed by a masking layer 101 formed by a process such as chemical vapor deposition (CVD), which is not shown separately) and an appropriate etching process. For example, the masking layer can be a hard mask including silicon nitride formed by a process such as chemical vapor deposition (CVD), but other materials (e.g., oxides, oxynitrides, silicon carbide, combinations of these, etc.) and other processes (e.g., plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or silicon oxide formation followed by nitridation) can be used. Once formed, the masking layer can be patterned by an appropriate photolithography process to expose those portions of the substrate 101 that will be removed to form the first trench 103.

[0026] Once the masking layer has been formed and patterned, a first trench 103 is formed in the substrate 101. The exposed substrate 101 may be removed by a suitable process such as reactive ion etching (RIE) to form the first trench 103 in the substrate 101, but any suitable process may be used. In one embodiment, the first trench 103 may be formed to a first depth of less than about 1000 mm from the surface of the substrate 101. For example, about

[0027] However, as will be appreciated by those skilled in the art, the above process for forming the first trench 103 is only one possible process and is not meant to be the only embodiment. Instead, any suitable process by which the first trench 103 can be formed can be utilized, and any suitable process including any number of masking and removal steps can be used.

[0028] In addition to forming the first trench 103, the masking and etching process also forms fins 107 from the portion of the substrate 101 that remains unremoved. For convenience, the fins 107 are shown in the figure as being separated from the substrate 101 by a dotted line, but there may or may not be a physical indication of the separation. As described below, these fins 107 can be used to form the channel region of a multi-gate FinFET. Although Figure 1 Only two fins 107 formed from substrate 101 are shown, but any number of fins 107 may be used.

[0029] The fins 107 may be formed such that they have a width between about 5 nm and about 80 nm, for example, about 30 nm, at the surface of the substrate 101. In addition, the fins 107 may be spaced apart from each other by a distance between about 10 nm and about 100 nm, for example, about 50 nm. By spacing the fins 107 apart in this manner, the fins 107 may each form a separate channel region while still being close enough to share a common gate (discussed further below).

[0030] Once the first trench 103 and the fin 107 have been formed, the first trench 103 may be filled with a dielectric material, and the dielectric material may be recessed within the first trench 103 to form a first isolation region 105. The dielectric material may be an oxide material, a high density plasma (HDP) oxide, etc. The dielectric material may be formed after optional cleaning and lining of the first trench 103 using a chemical vapor deposition (CVD) method (e.g., a HARP process), a high density plasma CVD method, or other suitable formation methods as known in the art.

[0031] The first trench 103 may be filled by overfilling the first trench 103 and the substrate 101 with a dielectric material, and then removing the excess material outside the first trench 103 and the fin 107 by a suitable process such as chemical mechanical polishing (CMP), etching, combinations of these, etc. In one embodiment, the removal process also removes any dielectric material located above the fin 107, such that removing the dielectric material will expose the surface of the fin 107 to further process steps.

[0032] Once the first trench 103 has been filled with the dielectric material, the dielectric material may then be recessed away from the surface of the fin 107. The recessing may be performed to expose at least a portion of the sidewalls of the fin 107 adjacent to the top surface of the fin 107. The dielectric material may be recessed using a wet etch by immersing the top surface of the fin 107 in an etchant such as HF, although other etchants (e.g., H2) and other methods (e.g., reactive ion etching, dry etching using an etchant such as NH3 / NF3, chemical oxide removal, or dry chemical cleaning) may be used. The dielectric material may be recessed to about 1000 mm from the surface of the fin 107. About The distance between, for example, about Furthermore, the recess may also remove any remaining dielectric material located above the fin 107 to ensure that the fin 107 is exposed to further processing.

[0033] However, as one of ordinary skill in the art will appreciate, the above steps may be only a portion of the entire process flow for filling and recessing the dielectric material. For example, a lining step, a cleaning step, an annealing step, a gap filling step, a combination of these, etc. may also be used to form the first trench 103 and fill the first trench 103 with a dielectric material. All potential process steps are fully intended to be included within the scope of the present embodiment.

[0034] After the first isolation region 105 has been formed, a dummy gate dielectric 109, a dummy gate electrode 111 on the dummy gate dielectric 109, and a first spacer 113 may be formed over each fin 107. In one embodiment, the dummy gate dielectric 109 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known in the art and used to form a gate dielectric. Depending on the technique of gate dielectric formation, the thickness of the dummy gate dielectric 109 on the top of the fin 107 may be different from the thickness of the gate dielectric on the sidewalls of the fin 107.

[0035] The dummy gate dielectric 109 may include a material such as silicon dioxide or silicon oxynitride, with a thickness in a range of about 3 angstroms to about 100 angstroms, for example, about 10 angstroms. The dummy gate dielectric 109 may be formed of a high dielectric constant (high-k) material (e.g., having a relative dielectric constant greater than about 5), such as lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), or zirconium oxide (ZrO2), or a combination thereof, with an equivalent oxide thickness of about 0.5 angstroms to about 100 angstroms, for example, about 10 angstroms or less. In addition, any combination of silicon dioxide, silicon oxynitride, and / or high-k materials may also be used for the dummy gate dielectric 109.

[0036] The dummy gate electrode 111 may include a conductive material or a non-conductive material and may be selected from the group consisting of polysilicon, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof, etc. The dummy gate electrode 111 may be deposited by chemical vapor deposition (CVD), sputtering deposition, or other techniques known in the art and used to deposit conductive materials. The thickness of the dummy gate electrode 111 may be about 1000 Å. to about The top surface of the dummy gate electrode 111 may have a non-flat top surface and may be flattened before patterning or gate etching of the dummy gate electrode 111. At this time, ions may or may not be introduced into the dummy gate electrode 111. The ions may be introduced, for example, by an ion implantation technique.

[0037] Once formed, the dummy gate dielectric 109 and the dummy gate electrode 111 can be patterned to form a series of stacks 115 above the fin 107. The stacks 115 define a plurality of channel regions on each side of the fin 107 below the dummy gate dielectric 109. The gate mask ( Figure 1The gate mask may be combined with commonly used masking and sacrificial materials such as, but not limited to, silicon oxide, silicon oxynitride, SiCON, SiC, SiOC, and / or silicon nitride, and may be deposited to about Peace A dry etching process may be used to etch the dummy gate electrode 111 and the dummy gate dielectric 109 to form a patterned stack 115 .

[0038] Once the stack 115 has been patterned, a first spacer 113 may be formed. The first spacer 113 may be formed on the opposite side of the stack 115. The spacer layer is typically formed by blanket depositing a spacer layer ( Figure 1 The first spacer 113 is formed by depositing a plurality of dielectric layers (not separately shown in the figure). The spacer layer may include SiN, oxynitride, SiC, SiON, SiOCN, SiOC, oxide, etc., and may be formed by methods for forming such layers, such as chemical vapor deposition (CVD), plasma enhanced CVD, sputtering, and other methods known in the art. The spacer layer may include a different material having different etching characteristics than the dielectric material in the first isolation region 105, or a material that is the same as the dielectric material in the first isolation region 105. The first spacer 113 may then be patterned, for example, by one or more etches to remove the spacer layer from the horizontal surface of the structure to form the first spacer 113.

[0039] In one embodiment, the first spacer 113 may be formed to have a size of approximately Peace In addition, once the first spacers 113 have been formed, the first spacers 113 adjacent to one stack 115 can be separated from the first spacers 113 adjacent to another stack 115 by a distance between about 5 nm and about 200 nm, for example, about 20 nm. However, any suitable thickness and distance may be used.

[0040] Figure 2 The removal of the fin 107 and the regrowth of the source / drain region 201 from those areas not protected by the stack 115 and the first spacer 113 is shown. The removal of the fin 107 from those areas not protected by the stack 115 and the first spacer 113 can be performed by reactive ion etching (RIE) using the stack 115 and the first spacer 113 as a hard mask, or by any other suitable removal process. The removal can continue until the fin 107 is coplanar with the surface of the first isolation region 105 (as shown) or below the surface of the first isolation region 105.

[0041] Once these portions of the fins 107 are removed, a hard mask (not separately shown) is placed and patterned to cover the dummy gate electrodes 111 to prevent growth, and the source / drain regions 201 can be regrown in contact with each fin 107. In one embodiment, the source / drain regions 201 can be regrown, and in some embodiments, the source / drain regions 201 can be regrown to form a stressor that will apply stress to the channel region of the fins 107 located below the stack 115. In embodiments where the fins 115 include silicon and the FinFET is a p-type device, the source / drain regions 201 can be regrown using a material such as silicon or another material such as silicon germanium having a different lattice constant than the channel region through a selective epitaxial process. The epitaxial growth process can use precursors such as silane, dichlorosilane, germane, etc., and can last between about 5 minutes and about 120 minutes, for example, about 30 minutes.

[0042] In one embodiment, the source / drain region 201 may be formed to have a thickness of approximately Peace and about Peace The height between, for example, about In this embodiment, the source / drain regions 201 may be formed to have a height between about 5 nm and about 250 nm, for example, about 100 nm, above the upper surface of the first isolation region 105. However, any suitable height may be utilized.

[0043] Once the source / drain region 201 is formed, dopants can be injected into the source / drain region 201 by injecting appropriate dopants to supplement the dopants in the fin 107. For example, p-type dopants (e.g., boron, gallium, indium, etc.) can be injected to form a PMOS device. Alternatively, n-type dopants (e.g., phosphorus, arsenic, antimony, etc.) can be injected to form an NMOS device. The stack 115 and the first spacer 113 can be used as a mask to inject these dopants. It should be noted that a person of ordinary skill in the art will recognize that many other processes, steps, etc. can be used to inject dopants. For example, a person of ordinary skill in the art will recognize that various combinations of spacers and liners can be used to perform multiple injections to form source / drain regions with specific shapes or characteristics suitable for specific purposes. Any of these processes can be used to inject dopants, and the above description is not meant to limit the present embodiment to the above steps.

[0044] Also at this point, the hard mask covering the dummy gate electrode 111 is removed during the formation of the source / drain regions 201. In one embodiment, the hard mask may be removed using, for example, a wet or dry etching process that is selective to the material of the hard mask. However, any suitable removal process may be used.

[0045] Figure 2 Also shown is an interlayer dielectric (ILD) layer 203 formed over the stack 115 and the source / drain regions 201 (in Figure 2 The ILD layer 203 may include a material such as borophosphosilicate glass (BPSG), but any suitable dielectric may be used. The ILD layer 203 may be formed using a process such as PECVD, but other processes such as LPCVD may be used instead. The ILD layer 203 may be formed to a thickness of about Peace Once formed, the ILD layer 203 and the first spacers 113 may be planarized using, for example, a planarization process such as a chemical mechanical polishing process, although any suitable process may be used.

[0046] Figure 3 Shown along line 3-3' Figure 2 sectional view to better illustrate the use of the first gate stack 1002 (in Figure 3 Not shown but discussed below Fig.10 The multiple layers shown and described above are removed and replaced with materials of the dummy gate electrode 111 and the dummy gate dielectric 109. Figure 3 In FIG. 1 , although the first gate stack 1002 is shown as being within the first region 302 of the substrate 101, a second region 304 of the substrate 101 (for the second gate stack 1004) is also shown, wherein the second region 304 may be immediately adjacent to the first region 302, or may be spaced apart from the first region 302 by a certain distance (in Figure 3 In one embodiment, the first gate stack 1002 may be a gate stack for a first transistor (e.g., a first NMOS finFET), and the second gate stack 1004 may be a gate stack for a second transistor (e.g., a first PMOS finFET). However, any suitable device may be used.

[0047] In one embodiment, the dummy gate electrode 111 and the dummy gate dielectric 109 may be removed using, for example, one or more wet or dry etching processes utilizing an etchant that is selective to the material of the dummy gate electrode 111 and the gate dielectric 109. However, any suitable removal process may be employed.

[0048] Once the dummy gate electrode 111 and the dummy gate dielectric 109 are removed, the process of forming the first gate stack 1002 and the second gate stack 1004 may begin by depositing a series of layers. In one embodiment, the series of layers may include an optional interface layer (not separately shown), a first dielectric material 301, an optional first n-metal work function layer 303, and a first p-metal work function layer 305.

[0049] An optional interfacial layer may be formed prior to forming the first dielectric material 301. In one embodiment, the interfacial layer may be a material such as silicon dioxide formed by a process such as in-situ steam generation (ISSG). In another embodiment, the interfacial layer may be a high-k material such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, combinations thereof, etc., having a thickness of about 100 Å. Peace Between, for example, about However, any suitable material or formation process may be used.

[0050] Once the interface layer is formed, a first dielectric material 301 may be formed on the interface layer. In one embodiment, the first dielectric material 301 is a high-k material deposited by a process such as atomic layer deposition, chemical vapor deposition, etc., for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, combinations thereof, etc. The first dielectric material 301 may be deposited to Peace The thickness between, for example, about However, any suitable material and thickness may be used.

[0051] The first n-metal work function layer 303 may be formed on the first dielectric material 301. In one embodiment, the first n-metal work function layer 303 may be a material such as W, Cu, AlCu, TiAlC, TiAlN, Ti, TiN, Ta, TaN, Co, Ni, Ag, Al, TaAl, TaAlC, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. For example, the first n-metal work function layer 303 may be deposited to about 100 Å using an atomic layer deposition (ALD) process, a CVD process, or the like. Peace The thickness between, for example, about However, any suitable material and process may be used to form the first n-metal work function layer 303 .

[0052] The first p-metal work function layer 305 may be formed on the first n-metal work function layer 303 (if present) or on the first dielectric material 301 (if the first n-metal work function layer 303 is not present). In one embodiment, the first p-metal work function layer 305 may be formed of a metal-containing material, for example, LaO, TiN, Ti, TiAlN, TaC, TaCN, TaSiN, TaSi2, NiSi2, Mn, Zr, ZrSi2, TaN, Ru, Al, Mo, MoSi2, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, and the like. In addition, the first p-metal work function layer 305 may be deposited to about 1000 Å using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, and the like. Peace The thickness between, for example, about However, any suitable deposition process or thickness may be used.

[0053] Figure 3 Also shown is the formation of a hard mask layer 307 over the first region 302 and the placement and patterning of a bottom anti-reflective layer 309. In one embodiment, the hard mask layer 307 can be a masking material such as aluminum oxide, but any suitable masking material can also be used, such as titanium nitride (TiN), tungsten carbide (WC), and silicon (Si), combinations thereof, etc. The hard mask layer 307 can be formed to about 1000 Å using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, etc. to about The thickness between, for example, about However, any suitable materials, formation processes, and thicknesses may be used.

[0054] In an embodiment, the bottom anti-reflective layer 309 has different optical properties than the subsequently placed photoresist 313, which is used to prevent energy (e.g., light) from being uncontrollably and undesirably reflected back into the photoresist 313 above during exposure of the photoresist 313, thereby preventing the reflected light from causing reactions in undesired areas of the photoresist 313. For example, the bottom anti-reflective layer 309 can have a different refractive index (n), a different extinction coefficient (k), or a different thickness (T) value than the photoresist 313. In addition, the bottom anti-reflective layer 309 can be used to provide a flat surface, thereby helping to reduce the negative effects of energy impinging at a certain angle.

[0055] In an embodiment, the material for forming the bottom anti-reflection layer 309 includes a polymer resin, a catalyst and a cross-linking agent, which are all placed in a BARC solvent for dispersion. The polymer resin may include a polymer having various monomers, which are combined with a chromophore by a cross-linking agent. In a specific embodiment, the cross-linking monomer may include a hydrocarbon chain, which also includes, for example, a hydroxyl group, a carboxylic acid group, a carboxylate group, an epoxy group, a carbamate group, an amide group, a combination thereof, etc. In addition, the cross-linking agent may be a melamine-based reagent, a urea-based reagent, an ethylene urea-based reagent, an propylene urea-based reagent, a glycoluril-based reagent, an aliphatic cyclic hydrocarbon (having a hydroxyl group, a hydroxyalkyl group, or a combination thereof), an oxygen-containing derivative of an aliphatic cyclic hydrocarbon, a glycoluril compound, an etherified amino resin, a polyether polyol, a polyglycidyl ether, a vinyl ether, a triazine, a combination thereof, etc. However, any suitable monomer, polymer and cross-linking agent may be used.

[0056] The material for the bottom anti-reflective layer 309 may be applied so that the material for the bottom anti-reflective layer 309 coats the upper exposed surface, and may be applied using a process such as a spin coating process, a dip coating method, an air knife coating method, a curtain coating method, a wire rod coating method, a gravure coating method, a lamination method, an extrusion coating method, a combination of these, and the like. In one embodiment, the material for the bottom anti-reflective layer 309 may be initially applied so that it has a thickness between about 10 nm and about 1000 nm, for example, about 100 nm. Once in place, the material for the bottom anti-reflective layer 309 may be baked to drive off the BARC solvent and react the cross-linking agent to cross-link the polymers to each other to form the bottom anti-reflective layer 309.

[0057] After the bottom anti-reflective layer 309 is placed, the material of the bottom anti-reflective layer 309 may have physical properties that allow certain defects to occur in further processing. For example, in some embodiments, the deposited bottom anti-reflective layer 309 may have diffusivity (e.g., the rate at which a chemical can diffuse through the material of the anti-reflective layer 309) that allows the material of a subsequently applied chemical (e.g., the first wet etchant 601 (described below with respect to the present invention) to diffuse through the material of the anti-reflective layer 309) after a certain period of exposure. Figure 6 Further described)) diffuses through the bottom anti-reflective layer 309 and reacts with the underlying layers.

[0058] Figure 3Also shown is patterning of the bottom anti-reflective layer 309 using an intermediate layer 311 and a photoresist 313. In one embodiment, the intermediate layer 311 can be an organic layer or an inorganic layer having a different etch resistance than the photoresist 313. In a specific embodiment, the intermediate layer 311 is a hard mask material, such as a low temperature oxide, aluminum oxide, silicon, silicon nitride, other oxides, oxynitrides, silicon carbide, combinations of these, and the like. The hard mask material for the intermediate layer 311 can be formed by a process such as chemical vapor deposition (CVD), but other processes may alternatively be used, such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), spin coating, or silicon oxide formation followed by nitridation. Any suitable method or combination of methods for forming or otherwise placing the material of the intermediate layer 311 may be utilized, and all such methods or combinations are fully intended to be included within the scope of the embodiments. The intermediate layer 311 may be formed to be approximately To date The thickness between, for example, about

[0059] The photoresist 313 is placed on the intermediate layer 311 to provide a patterned mask so that the intermediate layer 311 can be patterned into a desired pattern. In one embodiment, the photoresist 313 is a photosensitive material that is dispersed on the intermediate layer 311 and then exposed to a patterned energy source (e.g., light) to cause a chemical reaction in the exposed portion of the photosensitive material. The chemical reaction causes a change in physical properties that can be used in a development process to separate the exposed portion of the photosensitive material from the unexposed portion of the photosensitive material to form a patterned photoresist.

[0060] Once the photoresist 313 has been patterned into a desired pattern, the photoresist 313 may be used as a mask to pattern the material of the intermediate layer 311. For example, an anisotropic etching process such as reactive ion etching (RIE) may be used to transfer the pattern of the photoresist 313 to the intermediate layer 311, whereby ions of a suitable etchant such as CF4-O2 may be utilized in a dry etch to remove portions of the intermediate layer 311 exposed by the patterned photoresist 313. However, any other suitable etchant, such as CHF3 / O2, CH2F2, CH3F, etc., and any other suitable removal method, such as wet stripping, may be used instead.

[0061] Once the pattern of the photoresist 313 has been transferred to the intermediate layer 311, the pattern of the photoresist 313 can be transferred to the bottom anti-reflective layer 309 using the intermediate layer 311 to expose the hard mask layer 307 in the second region 304. In one embodiment, the bottom anti-reflective layer 309 can be etched using an etching process that uses the photoresist 313 and the intermediate layer 311 (now patterned) as a masking layer. The etching process can be a dry etching process using an etchant such as: oxygen, nitrogen, hydrogen, ammonia, sulfur hexafluoride, difluoromethane, nitrogen trifluoride, chlorine trifluoride, chlorine, carbon monoxide, carbon dioxide, helium, boron dichloride, argon, fluorine, trifluoromethane, tetrafluoromethane, perfluorocyclobutane, perfluoropropane, combinations thereof, etc. However, any other suitable etching process (e.g., wet etching, or wet etching performed simultaneously with the intermediate layer 311) and any other suitable etchant can be used.

[0062] Figure 4 It is shown that once the bottom anti-reflective layer 309 has been patterned, the photoresist 313 and the intermediate layer 311 can be removed. In one embodiment, the photoresist 313 can be removed using, for example, an ashing process, whereby the temperature of the photoresist 313 is raised to a point where the photoresist 313 undergoes thermal decomposition, after which the decomposed photoresist 313 can be easily removed.

[0063] Once the photoresist 313 has been removed, the intermediate layer 311 may be removed. In one embodiment, the intermediate layer 311 may be removed using one or more etching processes (eg, a wet etching or a dry etching process). However, any suitable removal process may be used.

[0064] Figure 5 The processing technology (in Figure 5 309), the treatment process can be used to treat and protect the bottom anti-reflective layer 309, reduce the diffusion of etchants through the bottom anti-reflective layer 309, and help prevent subsequent chemicals from undesirably and unnecessarily penetrating the bottom anti-reflective layer 309. Figure 5 In the illustrated embodiment, the treatment is a non-reactive physical treatment that does not chemically modify the structure of the bottom anti-reflective layer 309 (see below). Figure 11-13 Other embodiments are discussed further below.) In certain embodiments, the treatment process 501 can be a filling treatment that fills the pores (e.g., by capillary forces) and other openings of the bottom anti-reflective layer 309, thereby preventing subsequently applied chemicals from entering those pores and other openings when they attempt to pass through the bottom anti-reflective layer 309.

[0065] In such an embodiment, the first treatment chemistry may be applied (at Figure 5 In one embodiment, the first treatment chemical 503 may be a chemical having physical properties that allow it to enter the pores of the bottom anti-reflective layer 309. For example, in some embodiments, the first treatment chemical 503 may have a viscosity of less than about 5 cp, such as between about 1 cp and about 3 cp, and may also have a surface tension of less than about 40 mN / m, such as between about 10 mN / m and about 30 mN / m. In addition, the specific gravity of the first treatment chemical 503 may be between about 0.7 and about 2, such as about 0.79. Finally, the water solubility of the first treatment chemical 503 may be about 10 - 1 g / mL and about 10 -4 g / mL and will not chemically react with subsequently applied chemicals.

[0066] In certain embodiments, the first processing chemistry 503 may be, for example, a hydrocarbon, isopropyl alcohol (IPA), hexane, acetone, benzene, combinations of these, etc. However, any other suitable chemistry may also be used, such as other normal alkanes, other alkanes, etc. Any suitable chemistry capable of inhibiting the migration of subsequently applied chemicals through the bottom anti-reflective layer 309 may be used, and all such chemistries are fully intended to be included within the scope of the embodiments.

[0067] The treatment process 501 may begin by physically contacting the first treatment chemistry 503 with the bottom anti-reflective layer 309. In one embodiment, the first treatment chemistry 503 may be applied using a spin coating process, dip coating, air knife coating, curtain coating, wire bar coating, gravure coating, lamination, extrusion coating, combinations of these, etc. However, any suitable method of applying the first treatment chemistry 503 may be utilized.

[0068] The first treatment chemistry 503 can be applied at a temperature between about 5° C. and about 80° C., for example, about 25° C. In addition, the treatment process 501 can be continued for a time sufficient to fill the holes and openings of the bottom anti-reflective layer 309, for example, a time period between about 30 seconds and about 240 seconds, for example, about 120 seconds. However, any suitable time and temperature can be utilized.

[0069] During the treatment process 501, the first treatment chemistry 503 will enter the holes and other openings located in the bottom anti-reflective layer 309 and penetrate (soak) the bottom anti-reflective layer 309 by using capillary forces. By filling these holes and other openings and remaining in these holes and other openings, the first treatment chemistry 503 will slow down or even completely prevent the movement of subsequently applied chemicals through the bottom anti-reflective layer 309 (discussed further below). By slowing the movement of subsequent chemicals, the subsequently applied chemicals will not be able to reach the underlying hard mask layer 307. In addition, by preventing the subsequently applied chemicals from reaching the underlying hard mask layer 307, the subsequently applied chemicals will not be able to react with the underlying hard mask layer 307 and prevent the occurrence of defects such as blistering. For smaller process nodes (e.g., N5, N3, etc.) and smaller fin-to-fin spacing, this prevention allows for an increase in the available cleaning time and an expansion of the wet cleaning window.

[0070] Figure 6 The hard mask layer 307 is shown removed from the second region 304. In an embodiment, a wet etchant (in Figure 6 The hard mask layer 307 is removed by a wet etching process (represented by an X labeled 601 in the figure) that selectively removes a material (e.g., aluminum oxide) selected for the hard mask layer 307. Thus, in embodiments where the hard mask layer 307 is aluminum oxide, the removal of the hard mask layer 307 may be performed with a first wet etchant 601 (e.g., ammonium hydroxide (NH4OH), phosphoric acid (H3PO4), hydrogen peroxide, combinations of these, etc.).

[0071] In a particular embodiment, a dilute ammonium hydroxide solution may be used to remove the hard mask layer 307. For example, the wet etching solution may include ammonium hydroxide and water in a ratio of 1:20. In another embodiment, a mixture of ammonium hydroxide and hydrogen peroxide in a solvent such as water may be used to remove the hard mask layer 307. For example, the wet etching solution may include 29% ammonium hydroxide and 31% hydrogen peroxide, with the remainder of the solution including water. However, any suitable etchant and etching solution may be used.

[0072] In an embodiment, the wet etching process may be performed at a temperature sufficient to react the first wet etchant 601 with the material of the hard mask layer 307, for example, a temperature between about 5° C. and about 70° C., for example, about 25° C. In addition, the wet etching process may be performed for a time period between about 20 seconds and about 300 seconds, for example, about 144 seconds. However, any suitable time and temperature may be utilized.

[0073] However, in the case where the first processing chemistry 503 is still present in the pores and openings of the bottom anti-reflective layer 309, the diffusivity of the first wet etchant 601 (e.g., the speed of diffusion through the bottom anti-reflective layer 30) can be reduced, and thus any diffusion of the first wet etchant 601 into and / or through the bottom anti-reflective layer 309 is reduced or even eliminated. In this way, as long as the wet etching process is performed for a period of time less than that allowing the first wet etchant 601 to penetrate the bottom anti-reflective layer 309, the first wet etchant 601 will not penetrate the bottom anti-reflective layer 309, thereby preventing any reaction between the hard mask layer 307 and the first wet etchant 601. In this way, defects caused by such reactions (e.g., bubble defects or blistering defects, which are difficult to remove by an ashing process and may cause wafer acceptance test failure for threshold voltage breakdown voltage, work function deviation from target failure, etc.) can be avoided.

[0074] Figure 7 The first p-metal work function layer 305 is shown removed from the second region 304. In one embodiment, the first p-metal work function layer 305 may be removed by one or more etching processes, such as a wet etching process or a dry etching process that is selective to the material (e.g., lanthanum oxide) of the first p-metal work function layer 305. However, any suitable removal process may be used.

[0075] In one embodiment, a second wet etchant (in Figure 7 The first p-metal work function layer 305 is removed by a wet etching process (indicated by an X marked as 701 in the figure), and the second wet etchant selectively removes the material (e.g., lanthanum oxide) selected for the first p-metal work function layer 305. Thus, in an embodiment in which the first p-metal work function layer 305 is lanthanum oxide, the removal of the first p-metal work function layer 305 can be performed with the second wet etchant 701 (e.g., hydrochloric acid, phosphoric acid, hydrogen peroxide, a combination of these, etc.).

[0076] In a particular embodiment, a mixture of hydrochloric acid and water may be used to remove the first p-metal work function layer 305. For example, in this embodiment, the mixture may include hydrochloric acid and water in a ratio of 1:25. In another embodiment, a mixture of hydrochloric acid and hydrogen peroxide in a solvent such as water may be used to remove the first p-metal work function layer 305. In this embodiment, the second wet etchant 701 may include 37% hydrochloric acid and 31% hydrogen peroxide, with the remainder of the solution including water. However, any suitable etchant may be used.

[0077] In one embodiment, the wet etching process for removing the first p-metal work function layer 305 can be performed at a temperature sufficient to react the second wet etchant 701 with the material of the first p-metal work function layer 305, for example, a temperature between about 5° C. and about 70° C., for example, about 50° C. In addition, the wet etching process can be performed for a time period between about 20 seconds and about 280 seconds, for example, about 154 seconds. However, any suitable time and temperature can be utilized.

[0078] However, with the first processing chemistry 503 still present in the pores of the bottom anti-reflective layer 309, any diffusion of the second wet etchant 701 into and / or through the bottom anti-reflective layer 309 is reduced or eliminated. Thus, as long as the wet etching process is performed for a period of time less than that allowing the second wet etchant 701 to penetrate the bottom anti-reflective layer 309, the second wet etchant 701 does not penetrate the bottom anti-reflective layer 309, thereby preventing any reaction between the hard mask layer 307 and the second wet etchant 701. Thus, defects (e.g., bubble defects or blistering defects) due to such a reaction can be avoided.

[0079] For example, the second wet etchant 701 (having, for example, hydrochloric acid therein) may reach the surface of the hard mask layer 307 (e.g., aluminum oxide) without the first processing chemistry 503 being present in the pores of the bottom anti-reflective layer 309. If the second wet etchant 701 does reach the surface, the reactions represented by Equations 1 and 2 may occur.

[0080] Al2O3+3H2O→2Al(OH)3 Equation 1

[0081] Al(OH)3+3HCl→AlCl3+3H2O Equation 2 Furthermore, since AlCl 3 is water soluble, it will lift the overlying bottom anti-reflective layer 309 and cause blistering. However, in the presence of the first process chemistry 503 , these reactions can be prevented by preventing the second wet etchant 701 from reaching the hard mask layer 307 .

[0082] For example, in an embodiment where the second wet etchant 701 is applied for 210 seconds and the treatment process 501 is applied for 60 seconds, the number of defects can be reduced from 182 bubble defects (for a device that does not use the treatment process 501) to 154 defects. In addition, in an embodiment where the second wet etchant 701 is applied for 154 seconds and the treatment process 501 is applied for 30 seconds or 60 seconds, the number of defects can be reduced from 216 bubble defects (for a device that does not use the treatment process 501) to 2 defects (at 30 seconds of the treatment process 501) and even no defects (at 60 seconds of the treatment process 501).

[0083] Once the first p-metal work function layer 305 is removed, the structure can be cleaned and then the bottom anti-reflective layer 309 can be removed. In one embodiment, the structure can be cleaned by applying a first wet etchant 601 for a short period of time between about 5 seconds and about 120 seconds (e.g., about 10 seconds), and then rinsing the structure with a rinse solution such as deionized water for a period of time between about 10 seconds and about 120 seconds (e.g., about 30 seconds). However, any suitable cleaning process can also be used at this stage.

[0084] Additionally, although the above description presents a process in which treatment process 501 is performed prior to removing hard mask layer 307, this is intended to be exemplary and is not intended to limit the embodiments. Rather, bottom anti-reflective layer 309 may be treated at any point in the process, which helps prevent unwanted diffusion of a large number of chemicals through bottom anti-reflective layer 309. For example, in some embodiments, intermediate layer 311 and hard mask layer 307 may include the same material (e.g., aluminum oxide), and it would be beneficial to pattern hard mask layer 307 in the same process step as removing intermediate layer 311. In such embodiments, because intermediate layer 311 is still present at the beginning to protect the bottom anti-reflective coating, treatment process 501 may not occur until after patterning of hard mask layer 307 and before patterning of first p-metal work function layer 305. Any suitable placement of treatment process 501 in the process may be utilized, and all such placements are fully intended to be included within the scope of the embodiments.

[0085] In addition, although certain chemical etchants have been described herein to discuss the removal and / or patterning of the hard mask layer 307 and the first p-metal work function layer 305, the process of treating the bottom anti-reflective layer 309 to avoid the formation of bubbles is not intended to be limited to the above-mentioned bulk chemicals. However, the treatment process can be used to protect the underlying layers from various bulk chemicals, which can be used to remove and / or pattern various materials during the manufacture of semiconductor devices. For example, various etchants and etching solutions are formed using bulk chemicals such as sulfuric acid (H2SO4), phosphoric acid (H3PO4), hydrochloric acid, hydrogen fluoride (HF), ammonium hydroxide, hydrogen peroxide (H2O2), ammonium fluoride, ozone, combinations thereof, etc. Processes utilizing these bulk chemicals can benefit from utilizing the ideas expressed herein, and all of these uses are fully intended to be included within the scope of the embodiments.

[0086] Figure 8It is shown that once the structure has been cleaned, the bottom anti-reflective layer 309 can be removed. In one embodiment, an etching process or an ashing process can be used to remove the bottom anti-reflective layer 309. In embodiments where the bottom anti-reflective layer 309 is removed in an ashing process, the temperature of the bottom anti-reflective layer 309 is increased until the bottom anti-reflective layer 309 undergoes thermal decomposition and can then be removed. However, any other suitable process can be used to remove the bottom anti-reflective layer 309.

[0087] Fig. 9 It is shown that once the bottom anti-reflective layer 309 has been removed, a glue layer (not shown separately) and a fill material 901 may be formed. In one embodiment, the glue layer may be formed to facilitate adhesion of the fill material 901 above to the underlying material, as well as to provide a nucleation layer for forming the fill material 901. In one embodiment, the glue layer may be a material such as titanium nitride and may be formed to a thickness of about 100 Å using a similar process (e.g., ALD). Peace Between, for example, about However, any suitable materials and processes may be used.

[0088] Once the glue layer is formed, a fill material 901 is deposited to fill the remainder of the opening with the glue layer. In one embodiment, the fill material 901 may be a material such as Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of these, and the like, and may be formed using a deposition process such as plating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, and the like. Additionally, the fill material 901 may be deposited to a thickness of about Peace Between, for example, about However, any suitable material may be used.

[0089] Fig.10 It is shown that after the fill material 901 has been deposited to fill and overfill the openings, the material within each opening of the first region 302 and the second region 304 can be planarized to form the first gate stack 1002 and the second gate stack 1004. In one embodiment, the material can be planarized with the first spacer 113 (see FIG. 1 ) using, for example, a chemical mechanical polishing process. Figure 1 ) planarization, but any suitable process may be used, such as grinding or etching.

[0090] After the material of the first gate stack 1002 and the second gate stack 1004 has been formed and planarized, the material of the first gate stack 1002 and the second gate stack 1004 can be recessed and capped by the capping layer 1001. In one embodiment, the material of the first gate stack 1002 and the second gate stack 1004 can be recessed using, for example, a wet etching process or a dry etching process that utilizes an etchant that is selective to the material of the first gate stack 1002 and the second gate stack 1004. In one embodiment, the material of the first gate stack 1002 and the second gate stack 1004 can be recessed a distance between about 5 nm and about 150 nm, for example, about 120 nm. However, any suitable process and distance can be utilized.

[0091] Once the materials of the first gate stack 1002 and the second gate stack 1004 have been recessed, a capping layer 1001 may be deposited and planarized with the first spacer 113. In one embodiment, the capping layer 1001 is a material such as SiN, SiON, SiCON, SiC, SiOC, combinations of these, etc., deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, etc. The capping layer 1001 may be deposited to approximately Peace The cap layer 1001 and the first spacer 113 are then planarized using a planarization process such as chemical mechanical polishing so that the cap layer 1001 and the first spacer 113 are planar.

[0092] Fig.11 Another embodiment is shown, in which the treatment process 501 is performed by exposing a portion of the bottom anti-reflective layer 309 to a first reactant (in Fig.11 In one embodiment, the protective layer 1101 can be formed by introducing the first reactant 1103 into the bottom anti-reflective layer 309 to form the protective layer 1101.

[0093] In an embodiment, the first reactant 1103 may be an organic reactant suitable for reacting with the material of the bottom anti-reflective layer 309 and forming the protective layer 1101. Thus, while the precise reactant used to form the protective layer 1101 depends at least in part on the material selected for the bottom anti-reflective layer 309, in some embodiments, the first reactant 1103 may be a material such as hexamethyldisilazane (HMDS), citric acid, acetic acid, combinations of these, etc. However, any suitable material may be used.

[0094] In another specific embodiment, the first reactant 1103 can be an organic reactant suitable for forming a self-aligned monolayer (SAM) along the top surface of the bottom anti-reflection layer 309. In such an embodiment, the first reactant 1103 will react with the exposed terminal groups of the bottom anti-reflection layer 309 and form a monolayer of the self-aligned monolayer with the outermost terminal groups of the bottom anti-reflection layer 309. In this embodiment, the first reactant 1103 can be an organic molecule with an OH or carboxylic acid group, for example, R-OH, R-COOH, a combination of these, etc., wherein R represents a carbon chain with any suitable number of carbon atoms. However, any suitable reactant can be used.

[0095] In an embodiment, the first reactant 1103 may be introduced into the bottom anti-reflective layer 309 by a wet process or a dry process, depending on the desired reactant. For example, in an embodiment where the first reactant 1103 is HMDS, the first reactant 1103 may be introduced in liquid form by a process such as a spin coating process, a dip coating method, an air knife coating method, a curtain coating method, a wire bar coating method, a gravure coating method, a lamination method, an extrusion coating method, a combination of these, etc. However, any suitable process may be utilized.

[0096] Additionally, in embodiments where the first reactant 1103 is in liquid form in contact with the bottom anti-reflective layer 309, the process may be performed at a temperature between about 5° C. and about 80° C., for example, about 25° C. Additionally, the process may be performed for a time between about 5 seconds and about 240 seconds, for example, about 60 seconds. However, any suitable process conditions may be utilized.

[0097] Once the first reactant 1103 has contacted the bottom anti-reflective layer 309, the first reactant 1103 will both diffuse into the bottom anti-reflective layer 309 and react with the material of the bottom anti-reflective layer 309 to form the protective layer 1101. In a specific embodiment where the first reactant 1103 is HMDS, the protective layer 1101 can be a reaction product between the first reactant 1103 and the material of the bottom anti-reflective layer 309. However, any suitable material can be formed for the protective layer 1101.

[0098] Additionally, the protective layer 1101 can be formed to a depth and thickness sufficient to help reduce or even eliminate diffusion of subsequently applied chemicals. Thus, while the depth can depend at least in part on the materials selected for the bottom anti-reflective layer 309 and the chemicals, in some embodiments, the protective layer 1101 can be formed to a depth and thickness sufficient to help reduce or even eliminate diffusion of subsequently applied chemicals. Peace The thickness between, for example, about However, any suitable depth and any suitable thickness may be formed.

[0099] Fig.12 The hard mask layer 307 is shown removed from the second region 304 with an appropriate protective layer 1101. In one embodiment, the hard mask layer 307 may be removed as described above with respect to Figure 6 The hard mask layer 307 is removed (eg, using a wet etching process with a first wet etchant 601 such as ammonium hydroxide). However, any suitable removal process may be utilized to remove the hard mask layer 307 from the second region 304 .

[0100] Additionally, in the presence of the protective layer 1101 during the removal of the hard mask layer 307, the protective layer 1101 helps reduce or prevent any diffusion of the first wet etchant 601 into or through the bottom anti-reflective layer 309. In this way, the likelihood that the first wet etchant 601 will penetrate the bottom anti-reflective layer and physically contact the underlying layers is reduced, and the likelihood that these chemicals will react with the underlying layers and cause defects is reduced.

[0101] Fig.13 The first p-metal work function layer 305 is shown removed from the second region 304 with an appropriate protective layer 1101. In one embodiment, the first p-metal work function layer 305 may be removed as described above with respect to Figure 7 The first p-metal work function layer 305 is removed (eg, using a wet etching process with a second wet etchant 701 such as hydrochloric acid). However, any suitable removal process may be used to remove the first p-metal work function layer 305 from the second region 304 .

[0102] Additionally, in the presence of the protective layer 1101 during the removal of the first p-metal work function layer 305, the protective layer 1101 helps to reduce or prevent any diffusion of the second wet etchant 701 into or through the bottom anti-reflective layer 309. In this way, the likelihood that the second wet etchant 701 will penetrate the bottom anti-reflective layer and physically contact the underlying layers is reduced, and the likelihood that these chemicals will react with the underlying layers and cause defects is reduced.

[0103] Once the first p-metal work function layer 305 has been removed from the second region 304, the Figure 8-10 Further processes are performed. For example, etching and / or ashing processes may be used to remove the bottom anti-reflection layer 309 (and the protection layer 1101), deposit the filling material 901, and form the capping layer 1001. However, any suitable process may be used subsequently.

[0104] By utilizing the processes described herein, undesirable defects can be avoided during the patterning process of the hard mask layer 307 and / or the patterning process of the first p-metal work function layer. Specifically, by inhibiting or eliminating the movement of etching chemicals through the bottom anti-reflective layer 309, these chemicals will not be able to react with the underlying layers and cause blistering. In this way, in the absence of blistering, overall damage can be reduced, especially as device dimensions are reduced to smaller and smaller process nodes.

[0105] In an embodiment, a method of manufacturing a semiconductor device, the method comprising: forming a first layer over a raised semiconductor region; applying a bottom anti-reflective layer over the first layer, the bottom anti-reflective layer having a first diffusivity relative to a first chemical; patterning the bottom anti-reflective layer; reducing the first diffusivity to a second diffusivity relative to the first chemical; and removing a portion of the first layer using the first chemical when the bottom anti-reflective layer is present. In an embodiment, reducing the first diffusivity is at least partially accomplished by a physical process. In an embodiment, the physical process fills the holes of the bottom anti-reflective layer with a second chemical. In an embodiment, the second chemical comprises isopropyl alcohol. In an embodiment, reducing the first diffusivity is at least partially accomplished by a chemical process. In an embodiment, the chemical process reacts a portion of the bottom anti-reflective layer with a first reactant. In an embodiment, the first reactant is hexamethyldisilazane.

[0106] In another embodiment, a method of manufacturing a semiconductor device, the method comprising: depositing a hard mask layer over a work function layer over a semiconductor fin; depositing a bottom anti-reflective layer over the hard mask layer; patterning the bottom anti-reflective layer; treating the bottom anti-reflective layer, wherein treating the bottom anti-reflective layer reduces diffusivity of a first etchant through the bottom anti-reflective layer; and removing a portion of the hard mask layer using the first etchant when the bottom anti-reflective layer is present. In an embodiment, the hard mask layer comprises aluminum oxide. In an embodiment, the work function layer comprises lanthanum oxide. In an embodiment, treating the bottom anti-reflective layer is a physical treatment. In an embodiment, the physical treatment applies isopropyl alcohol to the bottom anti-reflective layer. In an embodiment, treating the bottom anti-reflective layer is a chemical treatment. In an embodiment, the chemical treatment forms a protective layer at least partially within the bottom anti-reflective layer.

[0107] In yet another embodiment, a method of manufacturing a semiconductor device includes: depositing a lanthanum oxide layer over a semiconductor fin; depositing an aluminum oxide layer over the lanthanum oxide layer; placing a bottom anti-reflective layer over the aluminum oxide layer; patterning the bottom anti-reflective layer; adding a material to the bottom anti-reflective layer after patterning the bottom anti-reflective layer; etching a portion of the aluminum oxide layer when the bottom anti-reflective layer is present; and etching a portion of the lanthanum oxide layer when the bottom anti-reflective layer is present. In an embodiment, etching the portion of the aluminum oxide layer is performed at least in part with ammonium hydroxide. In an embodiment, etching the portion of the lanthanum oxide layer is performed at least in part with hydrochloric acid. In an embodiment, the adding material adds isopropyl alcohol. In an embodiment, the adding material reacts the bottom anti-reflective layer with a first reactant. In an embodiment, the first reactant is hexamethyldisilazane.

[0108] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0109] Example 1 is a method for manufacturing a semiconductor device, the method comprising: forming a first layer over a raised semiconductor region; applying a bottom anti-reflective layer over the first layer, the bottom anti-reflective layer having a first diffusivity relative to a first chemical; patterning the bottom anti-reflective layer; reducing the first diffusivity to a second diffusivity relative to the first chemical; and removing a portion of the first layer using the first chemical while the bottom anti-reflective layer is present.

[0110] Example 2 is the method of Example 1, wherein reducing the first diffusivity is accomplished at least in part by a physical process.

[0111] Example 3 is the method of Example 2, wherein the physical process fills the holes of the bottom anti-reflective layer with a second chemical.

[0112] Example 4 is the method of Example 3, wherein the second chemical comprises isopropyl alcohol.

[0113] Example 5 is the method of Example 1, wherein reducing the first diffusivity is accomplished at least in part by a chemical process.

[0114] Example 6 is the method of Example 5, wherein the chemical process reacts a portion of the bottom anti-reflective layer with a first reactant.

[0115] Example 7 is the method described in Example 6, wherein the first reactant is hexamethyldisilazane.

[0116] Example 8 is a method for manufacturing a semiconductor device, the method comprising: depositing a hard mask layer over a work function layer over a semiconductor fin; depositing a bottom anti-reflective layer over the hard mask layer; patterning the bottom anti-reflective layer; processing the bottom anti-reflective layer, wherein processing the bottom anti-reflective layer reduces the diffusivity of a first etchant through the bottom anti-reflective layer; and removing a portion of the hard mask layer using the first etchant when the bottom anti-reflective layer is present.

[0117] Example 9 is the method of Example 8, wherein the hard mask layer comprises aluminum oxide.

[0118] Example 10 is the method of Example 9, wherein the work function layer includes lanthanum oxide.

[0119] Example 11 is the method of Example 8, wherein processing the bottom anti-reflective layer is a physical process.

[0120] Example 12 is the method of Example 11, wherein the physical treatment applies isopropyl alcohol to the bottom anti-reflective layer.

[0121] Example 13 is the method of Example 8, wherein treating the bottom anti-reflective layer is a chemical treatment.

[0122] Example 14 is the method of Example 13, wherein the chemical treatment at least partially forms a protective layer within the bottom anti-reflective layer.

[0123] Example 15 is a method for manufacturing a semiconductor device, the method comprising: depositing a lanthanum oxide layer over a semiconductor fin; depositing an aluminum oxide layer over the lanthanum oxide layer; placing a bottom anti-reflective layer over the aluminum oxide layer; patterning the bottom anti-reflective layer; adding a material to the bottom anti-reflective layer after patterning the bottom anti-reflective layer; etching a portion of the aluminum oxide layer while the bottom anti-reflective layer is present; and etching a portion of the lanthanum oxide layer while the bottom anti-reflective layer is present.

[0124] Example 16 is the method of Example 15, wherein etching the portion of the aluminum oxide layer is performed at least in part with ammonium hydroxide.

[0125] Example 17 is the method of Example 15, wherein etching the portion of the lanthanum oxide layer is performed at least in part with hydrochloric acid.

[0126] Example 18 is the method of Example 15, wherein isopropyl alcohol is added to the additive material.

[0127] Example 19 is the method of Example 15, wherein a material is added to react the bottom anti-reflective layer with a first reactant.

[0128] Example 20 is the method of Example 19, wherein the first reactant is hexamethyldisilazane.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a first layer over the raised semiconductor region; applying a bottom anti-reflection layer over the first layer, the bottom anti-reflection layer having a first diffusivity with respect to a first chemical substance, wherein the material used to form the bottom anti-reflection layer comprises a polymeric resin, a catalyst, and a cross-linking agent, the polymeric resin comprises a polymer having various monomers bonded together with chromophores by a cross-linking agent, and the first chemical substance is an etchant; patterning the bottom anti-reflective layer; reducing the first diffusivity to a second diffusivity relative to the first chemical, wherein reducing the first diffusivity to the second diffusivity comprises applying isopropyl alcohol or hexamethyldisilazane to the bottom antireflective layer; and The first chemistry is used to remove a portion of the first layer in the presence of the bottom anti-reflective layer.

2. The method according to claim 1, wherein: Reducing the first diffusivity is accomplished at least in part by a physical process.

3. The method according to claim 2, wherein: The physical process fills the holes of the bottom anti-reflective layer with a second chemical substance.

4. The method according to claim 3, wherein: The second chemical substance includes the isopropyl alcohol.

5. The method according to claim 1, wherein: Reducing said first diffusivity is accomplished at least in part by a chemical process.

6. The method according to claim 5, wherein: The chemical process reacts a portion of the bottom anti-reflective layer with a first reactant.

7. The method according to claim 6, wherein: The first reactant is the hexamethyldisilazane.

8. A method for manufacturing a semiconductor device, the method comprising: depositing a hard mask layer over the work function layer over the semiconductor fin; Depositing a bottom anti-reflection layer on the hard mask layer, wherein the material for forming the bottom anti-reflection layer comprises a polymer resin, a catalyst and a cross-linking agent, the polymer resin comprises a polymer having various monomers which are bonded together with chromophores through a cross-linking agent; patterning the bottom anti-reflective layer; treating the bottom anti-reflective layer, wherein treating the bottom anti-reflective layer reduces diffusivity of a first etchant through the bottom anti-reflective layer, wherein treating the bottom anti-reflective layer comprises applying isopropyl alcohol or hexamethyldisilazane to the bottom anti-reflective layer; and A portion of the hard mask layer is removed using the first etchant in the presence of the bottom anti-reflective layer.

9. The method according to claim 8, wherein: The hard mask layer includes aluminum oxide.

10. The method according to claim 9, wherein: The work function layer includes lanthanum oxide.

11. The method according to claim 8, wherein: Treating the bottom anti-reflection layer is a physical treatment.

12. The method according to claim 11, wherein: The physical treatment applies the isopropyl alcohol to the bottom anti-reflective layer.

13. The method according to claim 8, wherein: Treating the bottom anti-reflection layer is a chemical treatment.

14. The method according to claim 13, wherein: The chemical treatment forms a protective layer at least partially within the bottom anti-reflective layer.

15. A method for manufacturing a semiconductor device, the method comprising: depositing a lanthanum oxide layer over the semiconductor fin; depositing an aluminum oxide layer on top of the lanthanum oxide layer; placing a bottom anti-reflection layer on the aluminum oxide layer, wherein the material for forming the bottom anti-reflection layer comprises a polymer resin, a catalyst and a cross-linking agent, the polymer resin comprises a polymer having various monomers which are bonded together with chromophores by a cross-linking agent; patterning the bottom anti-reflective layer; adding a material to the bottom anti-reflective layer after patterning the bottom anti-reflective layer, wherein adding the material to the bottom anti-reflective layer comprises applying isopropyl alcohol or hexamethyldisilazane to the bottom anti-reflective layer, and adding the material to the bottom anti-reflective layer reduces diffusivity of an etchant through the bottom anti-reflective layer; etching a portion of the aluminum oxide layer in the presence of the bottom anti-reflective layer; and A portion of the lanthanum oxide layer is etched in the presence of the bottom anti-reflective layer.

16. The method according to claim 15, wherein: Etching the portion of the aluminum oxide layer is performed at least in part with ammonium hydroxide.

17. The method according to claim 15, wherein: Etching the portion of the lanthanum oxide layer is performed at least in part with hydrochloric acid.

18. The method according to claim 15, wherein: Add Materials Add the isopropyl alcohol.

19. The method according to claim 15, wherein: The additive material allows the bottom anti-reflection layer to react with the first reactant.

20. The method according to claim 19, wherein: The first reactant is the hexamethyldisilazane.

Images