Semiconductor device and inverter

Abstract

Semiconductor devices and inverters are disclosed. In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain, and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.

Description

BACKGROUND

[0001] To date, transistors used in power electronics applications have typically been fabricated using silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS®, Si power MOSFETs, and Si insulated gate bipolar transistors (IGBTs). Group III nitride-based semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates to carry large currents, support high voltages, and provide very low on-resistance and fast switching times.

[0002] In some applications, such as inverters, it would be useful to be able to control the turn-on / off speed (i.e., dv / dt or slew rate) to a target value. For silicon transistors, gate resistors are typically used to control the switching speed. Active gate control has also been used in silicon devices to control and slow down the dv / dt. It would also be desirable to be able to control the slew rate in other types of semiconductor devices, such as group III nitride-based transistor devices. SUMMARY

[0003] According to the present invention, there is provided a semiconductor device comprising: a lateral transistor device having a source, a drain, and a gate; and a monolithically integrated capacitor coupled between the gate and the drain. The semiconductor device comprises a reverse transfer capacitance C rss wherein C rss(Vds=0V) / C rss(Vds=400V) < 50.

[0004] In some embodiments, the lateral transistor device is a III-V semiconductor transistor device, such as a group III nitride-based transistor device, for example a group III nitride-based high electron mobility transistor.

[0005] In some embodiments, the semiconductor device comprises a semiconductor body having a first surface, the lateral transistor device comprises a source finger electrode, a drain finger electrode, and a gate finger electrode arranged on the first surface of the semiconductor body, the gate finger electrode is arranged laterally between the source finger electrode and the drain finger electrode, and a metallization structure is arranged on the first surface, and the capacitor is integrated into the metallization structure and coupled between the gate finger electrode and the drain finger electrode.

[0006] In some embodiments, the capacitor is formed on the first surface and comprises a first plate formed by a first conductive layer of the metallization structure, a second plate formed by a second conductive layer of the metallization structure, the first conductive layer and the second conductive layer are spaced apart from each other by a first insulating layer of the metallization structure.

[0007] In some embodiments, the lateral transistor device includes an active region that contributes to the current switch, and the capacitor is positioned laterally adjacent to the active region.

[0008] In some embodiments, the capacitor is arranged on the first surface laterally adjacent to the source finger electrode, the drain finger electrode, and the gate finger electrode.

[0009] In some embodiments, a first plate of the capacitor extends from a gate flow channel formed from the first conductive layer, the gate flow channel electrically coupled to the gate finger electrode, or the first plate extends from a gate pad formed from the first conductive layer, the gate pad electrically coupled to the gate finger electrode, and a second plate of the capacitor extends from a drain bus formed from the second conductive layer, the drain bus electrically coupled to the drain finger electrode.

[0010] In some embodiments, the lateral transistor device includes an active region that contributes to the current switch, and the capacitor is positioned laterally adjacent to the active region.

[0011] In some embodiments, the capacitor is at least partially arranged over the source finger electrode.

[0012] In some embodiments, the metallization structure further includes a third conductive layer including a source finger arranged on the source finger electrode, a drain finger arranged on the drain finger electrode, and a gate flow channel positioned laterally adjacent to the gate finger electrode, the source finger electrode, and the drain finger electrode. The first conductive layer is arranged over the source finger and insulated from the source finger by the second insulating layer.

[0013] In some embodiments, the second conductive layer includes alternating drain buses and source buses arranged vertically over the source and drain fingers and extending substantially perpendicular to the source and drain fingers. The source fingers are coupled to the source buses by first conductive vias extending through the first insulating layer, and the drain fingers are coupled to the drain buses by second conductive vias extending through the first insulating layer.

[0014] In some embodiments, the semiconductor device further includes a third insulating layer between the source and drain fingers of the third conductive layer, and a fourth insulating layer arranged on the first surface extending between the source and drain finger electrodes and covering the gate finger electrode, wherein the third insulating layer is arranged on the fourth insulating layer.

[0015] In some embodiments, the first conductive layer is coupled to the gate flow channel by a third conductive via extending through the third and fourth insulating layers.

[0016] In an embodiment, an inverter is provided that includes one or more half-bridge circuits, each half-bridge circuit including a first switch coupled in series with a second switch. At least one of the first switch and the second switch includes a semiconductor device that includes a lateral transistor device having a source, a drain, and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.

[0017] In some embodiments, the inverter is a voltage source inverter for a motor drive.

[0018] In some embodiments, the inverter further includes a gate driver circuit for actively controlling a gate current of at least one of the first switch and the second switch.

[0019] In some embodiments, the gate driver circuit is a multi-level current control gate driver circuit, where a first current level is used at startup, and a second current level is used to maintain current.

[0020] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0021] Elements in the figures are not necessarily to scale. Like reference numerals designate corresponding similar parts. Features of the various illustrated embodiments can be combined, unless they are mutually exclusive. Exemplary embodiments are depicted in the drawings and detailed descriptions are set forth in the subsequent description.

[0022] Figure 1 An equivalent circuit diagram of a transistor device including an additional capacitor is illustrated.

[0023] Figure 2 A schematic diagram of a semiconductor device including a transistor device and an integrated capacitor is illustrated.

[0024] Figure 3A A plan view of a semiconductor device according to an embodiment is illustrated, the semiconductor device including a transistor device including a linearized capacitor.

[0025] Figure 3B An enlarged plan view of a connection between the linearized capacitor and the drain metal is illustrated.

[0026] Figure 3C An enlarged plan view of a connection between the linearized capacitor and the gate metal is illustrated.

[0027] FIG. 3D illustrates a cross-sectional view along line A-A of Figure 3A FIG. 3E illustrates a cross-sectional view along line A-A of

[0028] FIG. 3E illustrates a cross-sectional view along line A-A of Figure 3AA cross-sectional view of line BB.

[0029] Figure 3F The diagram follows Figure 3A A cross-sectional view of line CC.

[0030] Figure 4 includes Figure 4A and Figure 4B The illustration shows a plan view and a cross-sectional view of a semiconductor device including a lateral transistor device and a linearized capacitor according to an embodiment.

[0031] Figure 5 includes Figure 5A and Figure 5B The illustration shows a plan view and a cross-sectional view of a semiconductor device including a lateral transistor device and a linearized capacitor according to an embodiment. Detailed Implementation

[0032] In the following detailed description, reference is made to the accompanying drawings, which form a part herein, and which illustrate by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terms such as “top,” “bottom,” “front,” “rear,” “forward,” “end,” etc., are used to indicate orientation with reference to the described figures(s). Because components of the embodiments may be positioned in many different orientations, these directional terms are used for illustrative purposes and are by no means limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. The following detailed description of the invention is not taken in a limiting sense, and the scope of the invention is defined by the appended claims.

[0033] Many exemplary embodiments will now be explained. In this context, the same or similar reference numerals are used in the various figures to identify the same structural features. In the context of this description, “lateral” or “lateral direction” should be understood to mean a direction or extension generally parallel to the lateral extension of the semiconductor material or semiconductor carrier. Thus, the lateral direction generally extends parallel to these surfaces or sides. In contrast, the term “vertical” or “vertical direction” is understood to mean a direction generally perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. Thus, the vertical direction travels in the thickness direction of the semiconductor material or semiconductor carrier.

[0034] As used in this specification, when an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it may be directly on or directly extending to the other element, or there may be intermediate elements. Conversely, when an element is referred to as "directly on" or "directly extending to" another element, there are no intermediate elements.

[0035] As employed in this specification, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0036] Depletion mode devices, such as high voltage depletion mode transistors, have a negative threshold voltage, which means that they can conduct current at zero gate voltage. These devices are normally on. Enhancement mode devices, such as low voltage enhancement mode transistors, have a positive threshold voltage, which means that it cannot conduct current at zero gate voltage and are normally off. Enhancement mode devices are not limited to low voltage and can also be high voltage devices.

[0037] As used herein, a "high voltage device", such as a high voltage depletion mode transistor, is an electronic device optimized for high voltage switching applications. That is, when the transistor is off, it is able to block a high voltage, such as about 300V or more, about 600V or more, or about 1200V or more, and when the transistor is on, it has a low enough on-resistance (RON) for the application in which it is used, i.e., it experiences low enough on-loss when a significant current is passing through the device. A high voltage device can be able to block at least a voltage equal to the high voltage supply or maximum voltage in a circuit for which it is used. A high voltage device can be able to block 300V, 600V, 1200V, or other suitable blocking voltage required by the application.

[0038] As used herein, a "low voltage device", such as a low voltage enhancement mode transistor, is an electronic device able to block a low voltage, such as between 0V and V low , but not a voltage higher than V low . V low may be about 10V, about 20V, about 30V, about 40V, or between about 5V and 50V, such as between about 10V and 30V.

[0039] As used herein, the phrase "Group III Nitride" refers to a compound semiconductor that includes nitrogen (N) and at least one Group III element, for example including aluminum (Al), gallium (Ga), indium (In), and boron (B), and includes, but is not limited to, any one of its alloys, such as aluminum gallium nitride (Al x Ga (1-x) N), indium gallium nitride (In y Ga (1-y) N), aluminum indium gallium nitride (Al x In y Ga (1-x-y) N), gallium arsenide phosphide (GaAs a Pb N (1-a-b) ) and aluminum gallium indium arsenide phosphide (Al x In y Ga (1-x-y) As a P b N (1-a-b) ). Aluminum gallium nitride and AlGaN refer to alloys described by the expression Al x Ga (1-x) N, where 0 < x < 1.

[0040] For applications where it is desirable to control the slew rate or dv / dt of a silicon transistor device, various methods can be used. For example, a gate resistor can be used. The gate resistor acts against the intrinsic gate-drain capacitance C GD or Miller capacitance to provide slew rate control. However, for other types of semiconductor devices, such as III-V semiconductor devices and Group III nitride based transistor devices, a gate resistor results in high losses. This is because C GD is nonlinear for Group III nitride based devices, which results in a nonlinear slew rate. Thus, if the fastest part of the switching speed is limited to a particular value, the overall switching speed becomes slower and the losses higher than desirable. Additionally, the slew rate is dependent on the load current.

[0041] One method for controlling the slew rate in III-V semiconductor devices and Group III nitride based devices, such as Group III nitride based HEMTs, is to control the gate drive current to compensate for the nonlinearity in C GD and achieve a more linear slew rate.

[0042] A further method for controlling the slew rate in III-V semiconductor devices and Group III nitride based devices, such as Group III nitride based HEMTs, is to include an additional capacitance coupled in parallel with the intrinsic gate-drain capacitance C GD . The additional capacitance is linear, so the characteristics of the combined parallel capacitances are dominated by the additional linear capacitor, and thus linearizes the dv / dt. While this method can result in an increase in the total gate charge, the gate charge for Group III nitride based transistor devices is low, so any increase in the gate charge is acceptable because the total gate charge is still low compared to other types of semiconductor devices, such as silicon based transistor devices.

[0043] The additional capacitance can be provided by an external capacitor. The external capacitor can result in an increase in size, and also results in requiring an additional pin in the package of the transistor device for connecting the external capacitor to the transistor device.

[0044] According to embodiments described herein, an additional capacitor coupled between the drain and the gate of a III-V transistor device, such as a Group III nitride-based transistor device, is integrated into the semiconductor device. The additional capacitor can be integrated into and monolithically integrated into a metallization structure disposed on a major surface of the semiconductor device including the transistor device. Thus, a linearization capacitor can be added to the equivalent circuit without requiring additional pins or significantly increasing the size footprint, such that the slew rate is linearized and more precisely controllable.

[0045] The transistor device includes a reverse transfer capacitance C rss that is a dynamic characteristic of the transistor device dependent on a drain source voltage V ds . By including an additional capacitor coupled between the gate and the drain, the value of C ds at particular values of V rss is increased due to a linearization effect of the additional capacitor. In some embodiments, the ratio between C rss at a drain source voltage of 0 V (i.e., C rss(Vds=0V) ) and C rss at a drain source voltage of 400 V (i.e., C rss(Vds=400V) ) is less than 50 or less than 20. In some embodiments, the ratio between C rss at a drain source voltage of 0 V (i.e., C rss(Vds=0V) ) and C rss at a drain source voltage of 200 V (i.e., C rss(Vds=200V) ) is less than 20.

[0046] For a comparative transistor device without an additional capacitor coupled between the gate and the drain, the ratio between C rss at a drain source voltage of 0 V (i.e., C rss(Vds=0V) ) and C rss at a drain source voltage of 400 V (i.e., C rss(Vds=400V) ) is greater than 100. For a comparative gallium nitride-based HEMT without an additional capacitor coupled between the gate and the drain, C rss(Vds=0V) / C rss(Vds=400V) may be greater than 500.

[0047] Figure 1 An equivalent circuit diagram 10 of a transistor device 11 with a controllable slew rate or dv / dt is illustrated. The transistor device 11 can be a lateral transistor device (e.g., a III-V semiconductor device), and in some embodiments, a lateral Group III nitride-based transistor device, such as a Group III nitride-based HEMT (high electron mobility transistor).

[0048] The transistor device 11 has a source connected to a low voltage bus 12 which can be grounded and a drain connected to a high voltage bus 13. The transistor device 11 includes an intrinsic drain-source capacitance C DS , an intrinsic gate-source capacitance C GS , and an intrinsic gate-drain capacitance C GD . An additional capacitor 14 is coupled between the drain and the gate of the transistor device 11 and is also coupled in parallel with the intrinsic gate-drain capacitance C GD of the transistor device 11. The additional capacitor 14 has a capacitance C GD which is greater than the capacitance C M . For example, the capacitance C M of the additional capacitor 14 can be at least 10 times greater than the capacitance C GD .

[0049] In this circuit, the discharge and charge times of the additional capacitor 14 are variable and dv / dt is controllable and can be slowed down to provide a desired value. The capacitance of the additional capacitor 14 can be selected to linearize dv / dt. The additional capacitor 14 is coupled between the drain and the gate and coupled in parallel with the intrinsic gate-drain capacitance C GD . This has the effect of linearizing the slope of dv / dt which enables dv / dt to be more precisely controlled and enables the switching speed of the transistor 11 to be set at a desired value.

[0050] As used herein, a transistor device will be described as having a source, a drain, and a gate. These terms also encompass functionally equivalent terminals of other types of devices such as insulated gate bipolar transistors. For example, as used herein, the term "source" encompasses not only the source of a MOSFET device but also the emitter of an insulated gate bipolar transistor (IGBT) device and the emitter of a BJT device, the term "drain" encompasses not only the drain of a MOSFET device but also the collector of an insulated gate bipolar transistor (IGBT) device and the collector of a BJT device, and the term "gate" encompasses not only the gate of a MOSFET device but also the gate of an insulated gate bipolar transistor (IGBT) device and the base of a BJT device.

[0051] According to embodiments described herein, the additional capacitor 14 is integrated into the semiconductor device including the transistor device 11 as indicated by the dashed line 15 in Figure 1 . The additional capacitor 14 can be monolithically integrated into the semiconductor device including the transistor device 11. In some embodiments, the capacitor 14 is monolithically integrated into the metallization structure of the semiconductor device and / or the transistor device 11. In some embodiments, the transistor device is a lateral transistor device.

[0052] The semiconductor device can be used in applications such as inverters comprising one or more half-bridge circuits, each half-bridge circuit comprising a first switch coupled in series with a second switch. The first switch can be a low-side switch of the half-bridge circuit and the second switch can be a high-side switch of the half-bridge circuit. At least one of the first switch and the second switch can be provided by a transistor device 15 having a capacitor 14 coupled between the drain and the gate, such that the total gate-drain capacitance and thus the slew rate or dv / dt of the transistor device 15 is linearized and the switching speed is more precisely controllable.

[0053] In a half-bridge circuit, the source of the low-side switch or first transistor device is coupled to a low voltage bus (e.g. ground), the drain of the low-side switch is coupled to the source of the high-side switch via an output node, which can be coupled to a load to be driven by the half-bridge circuit, and the drain of the high-side switch is coupled to a high voltage bus.

[0054] The inverter can be, for example, a voltage source inverter for motor drives. In some embodiments, the inverter further comprises a gate driver circuit. In some embodiments, the gate driver circuit is configured to actively control the gate current. In some embodiments, the gate driver circuit is a multi-level current control gate driver circuit, wherein a first current level is used at start-up and a second current level is used to maintain the current.

[0055] Figure 2 A schematic diagram of a semiconductor device 20 is shown. The semiconductor device 20 can provide an equivalent circuit of the device 15 schematically indicated in Figure 1 Fig. 1.

[0056] The semiconductor device 20 comprises a semiconductor body 21 having a first surface 22, a lateral transistor device 23 formed in the semiconductor body 21 and a metallization structure 24 arranged on the first surface 22. A capacitor 25 is integrated into the semiconductor device 20, for example into the metallization structure 24.

[0057] The lateral transistor device 23 comprises a source electrode 26, a drain electrode 27 and a gate electrode 28 arranged on the first surface 22. The gate electrode 28 is arranged laterally between the source electrode 26 and the drain electrode 27. The capacitor 25 is electrically coupled between the drain electrode 27 and the gate electrode 28.

[0058] The lateral transistor device 23 can be a III-V semiconductor device, such that the semiconductor body 21 comprises one or more III-V semiconductor materials. In some embodiments, the lateral transistor device 23 is a III-nitride based semiconductor device, such that the semiconductor body 21 comprises one or more III-nitride materials.

[0059] Typically, the lateral transistor device 23 comprises a plurality of source, drain and gate electrodes 26, 27, 28, and the capacitor 25 is electrically coupled between the drain and gate electrodes 27, 28. In some embodiments, the lateral transistor device 23 comprises source, drain and gate finger electrodes arranged on the first surface 22 of the semiconductor body 21. In these embodiments, the capacitor 25 is integrated into the metallization structure 24 and electrically coupled between the gate and drain finger electrodes.

[0060] An additional linear capacitor 25 is used, which is coupled between the gate and drain electrodes of the transistor device 23 and in parallel with the intrinsic gate-drain capacitance C GD of the transistor device 23 to linearize dv / dt without occupying additional space outside the semiconductor device 20. Since the transistor device 23 is a lateral device, all three electrodes, source, drain and gate, are conveniently positioned on the common first surface 22, thus simplifying the integration of the capacitor 25 into the metallization structure 24 and into the portion of the metallization structure 24 coupled to the drain and gate electrodes.

[0061] The additional linearization capacitor 25 can be integrated into the metallization structure 24 in different ways. Various embodiments will now be described with reference to Figures 3 to 5.

[0062] Figure 3 comprises Figures 3A to 3F a semiconductor device 30 comprising a lateral transistor device 31, in accordance with an embodiment.

[0063] In some embodiments, the semiconductor device 30 is a III-V semiconductor device, and in some embodiments, such as in the embodiment illustrated in Figure 2 the semiconductor device 30 is a III-nitride based semiconductor device. The transistor device 31 can be a III-nitride based HEMT (high electron mobility transistor) device. The transistor device 31 can be a high voltage device with a blocking voltage of 600 V or more, and can be an enhancement mode device or a depletion mode device.

[0064] The semiconductor device 30 has a semiconductor body 45 with a first or top surface 46. In Figure 3AIn a plan view, it can be seen that the transistor device 31 comprises an active region or cell field region 38. A plurality of source fingers 32 arranged in alternation with a plurality of drain fingers 33 are located on a first surface 46 of the semiconductor device 30. Each of the source fingers 32 and the drain fingers 33 are elongate and extend substantially parallel to each other. The source fingers 32 are electrically coupled to a common source pad 34 arranged adjacent to a first lateral side of the cell field region 38 and the drain fingers 33 are electrically coupled to a common drain pad 35 arranged on an opposite side of the cell field region 38 by a drain bus 44. This arrangement of source and drain fingers 32, 33 is also referred to as a cross- comb arrangement.

[0065] In a plan view, it can be seen that the transistor device 31 comprises an active region or cell field region 38. A plurality of source fingers 32 arranged in alternation with a plurality of drain fingers 33 are located on a first surface 46 of the semiconductor device 30. Each of the source fingers 32 and the drain fingers 33 are elongate and extend substantially parallel to each other. The source fingers 32 are electrically coupled to a common source pad 34 arranged adjacent to a first lateral side of the cell field region 38 and the drain fingers 33 are electrically coupled to a common drain pad 35 arranged on an opposite side of the cell field region 38 by a drain bus 44. This arrangement of source and drain fingers 32, 33 is also referred to as a cross- comb arrangement. Figure 3A In a plan view, it can be seen that the transistor device 31 comprises an active region or cell field region 38. A plurality of source fingers 32 arranged in alternation with a plurality of drain fingers 33 are located on a first surface 46 of the semiconductor device 30. Each of the source fingers 32 and the drain fingers 33 are elongate and extend substantially parallel to each other. The source fingers 32 are electrically coupled to a common source pad 34 arranged adjacent to a first lateral side of the cell field region 38 and the drain fingers 33 are electrically coupled to a common drain pad 35 arranged on an opposite side of the cell field region 38 by a drain bus 44. This arrangement of source and drain fingers 32, 33 is also referred to as a cross- comb arrangement.

[0066] In the embodiment illustrated in Figure 3, the semiconductor device 30 also comprises a diode 37 for ESD protection, which is positioned adjacent to one lateral side of the cell field region 38 and the transistor device 31.

[0067] An additional linearization capacitor 40 is arranged on the first surface 46 electrically coupled between the drain fingers 32 and the gate flow 39. In this embodiment, the additional linearization capacitor 40 is positioned laterally adjacent to the cell field region 38 and laterally adjacent to the outermost fingers, in this case the source fingers of the cell field region 38. In this embodiment, the additional linearization capacitor 40 is positioned laterally between the cell field region 38 and the diode 37 and on the first surface 46. In this embodiment, the capacitor 40 has an elongate shape in a plan view. However, the shape of the capacitor 40 and its position on the first surface of the semiconductor device 30 can vary depending on the space available on the top surface 46 of the semiconductor device 30.

[0068] As in Figure 3B and Figure 3CAs can be seen more clearly in the enlarged plan view of Figure 2, the capacitor 40 includes a first or bottom plate 41, a second or top plate 42 arranged vertically above the first plate 41, and a dielectric 43 arranged between the first plate 41 and the second plate 42. The first plate 41 includes a conductive material connected to the gate pad 36 of the transistor device 31. In some embodiments, the first plate 41 can be formed from an extension 45 of the gate flow 39. In the design of Figure 2, the extension 45 can be substantially perpendicular to the gate flow 39. The gate pad 36 is located on the top of the gate flow 39.

[0069] As can be seen in the enlarged plan view of Figure 2, the second plate 42 of the capacitor 40 is formed from a portion of the conductive layer that forms the drain bus 44. The drain bus 44 extends substantially perpendicular to the drain fingers 33 that are laterally adjacent to the cell field region 38 and electrically couples the drain fingers 33 to one another. In this embodiment, the second plate 42 of the capacitor 40 is formed from an extension of the drain bus 44 on the first surface 46 that extends substantially perpendicular to the drain bus 44 and substantially parallel to the drain fingers 33. In some embodiments, the drain bus 44 and the second plate 42 are formed from a layer of titanium nitride. The drain pad 35 is formed on the drain bus 44 and can include a metal such as copper. Figure 3C As can be seen in the enlarged plan view of Figure 2, the second plate 42 of the capacitor 40 is formed from a portion of the conductive layer that forms the drain bus 44. The drain bus 44 extends substantially perpendicular to the drain fingers 33 that are laterally adjacent to the cell field region 38 and electrically couples the drain fingers 33 to one another. In this embodiment, the second plate 42 of the capacitor 40 is formed from an extension of the drain bus 44 on the first surface 46 that extends substantially perpendicular to the drain bus 44 and substantially parallel to the drain fingers 33. In some embodiments, the drain bus 44 and the second plate 42 are formed from a layer of titanium nitride. The drain pad 35 is formed on the drain bus 44 and can include a metal such as copper.

[0070] As can be seen in the enlarged plan view of Figure 2, the second plate 42 of the capacitor 40 is formed from a portion of the conductive layer that forms the drain bus 44. The drain bus 44 extends substantially perpendicular to the drain fingers 33 that are laterally adjacent to the cell field region 38 and electrically couples the drain fingers 33 to one another. In this embodiment, the second plate 42 of the capacitor 40 is formed from an extension of the drain bus 44 on the first surface 46 that extends substantially perpendicular to the drain bus 44 and substantially parallel to the drain fingers 33. In some embodiments, the drain bus 44 and the second plate 42 are formed from a layer of titanium nitride. The drain pad 35 is formed on the drain bus 44 and can include a metal such as copper.

[0071] Thus, by appropriately configuring a mask used to prepare the metallization structure, an additional capacitor 40 is monolithically integrated into the metallization structure arranged on the first surface 46 of the semiconductor device 30. In this embodiment, the capacitor 40 is monolithically integrated into the metallization structure without including any additional layers exclusively for the capacitor 40.

[0072]

[0073] ​Fig. 3D illustrates a cross-sectional view along the line A-A of Figure 3A Fig. 3D, and illustrates a cross-sectional view of a central region of the capacitor 40. In Fig. 3D, it can be seen that the semiconductor device 30 comprises a semiconductor body 45 comprising a first or top surface 46. The semiconductor device 30 is a group III nitride based device and comprises a multi-layer group III nitride structure, wherein a transition layer 47 is arranged on a not illustrated substrate, a channel layer 48 is located on the transition layer 47, and a barrier layer 49 is located on the channel layer 48 to form a heterojunction 50. The channel layer 48 can comprise gallium nitride and the barrier layer 49 can comprise aluminum gallium nitride, thereby forming the heterojunction 50 between the channel layer 48 and the barrier layer 49 capable of supporting a two-dimensional carrier gas.

[0074] The dielectric layer 43 of the capacitor 40 is located on the first plate 41, and the second plate 42, which is connected to the drain bus 44 and the drain pad 35, is located on the dielectric layer 43. The conductive layer, which provides the first plate 41 of the capacitor 40 and the gate runner 39, is electrically insulated from the barrier layer 49 of the semiconductor body 45 by an insulating layer 51, which can be formed by silicon nitride, for example. The first conductive layer, and thus the first plate 41 and the gate runner 39, can comprise a metal, such as copper. The dielectric layer 43 can comprise or can be formed by silicon nitride and / or silicon dioxide. The second plate 42 and the drain bus 44 can comprise titanium nitride or a metal.

[0075] A passivation layer 52 is also illustrated in Fig. 3D, which is located on the second plate 42. The passivation layer 52 can comprise two or more sub-layers. In the example illustrated in Fig. 3D, the passivation layer 52 comprises a silicon nitride sub-layer 53, which is located on the second plate 42, and a silicon dioxide sub-layer 54, which is located on the silicon nitride sub-layer 53.

[0076] Fig. 3E illustrates a cross-sectional view along the line B-B of Figure 3A Fig. 3E, and a cross-sectional view along a length of a portion of the capacitor 40 and a connection between the second plate 42 of the capacitor 40 and the drain pad 35.

[0077] Figure 3E illustrates that the bottom first plate 41 of the capacitor 40 coupled to the gate pad 36 has a distal end 55 laterally spaced from the drain pad 35. The conductive layer forming the second plate 42 has a connection region 56 that extends laterally beyond the distal end 55 of the first plate 41 and under the drain pad 35. The connection region 56 is in direct contact with the drain pad 35 to electrically connect the second plate 42 to the drain pad 35. Below the drain pad 35 and the connection region 56 of the second plate 42 in the vertical direction, the semiconductor body 45 only includes insulating material in the space between the connection region 56 and the top surface 46 of the semiconductor body. The area of the capacitor 40 and thus the provided capacitance at this end of the capacitor 40 is limited by the lateral extension of the first plate 41.

[0078] Figure 3F illustrates a cross-sectional view along the line C-C of Figure 3A and illustrates a cross-sectional view at the opposite end of the capacitor 40. Figure 3F illustrates that the second plate 42 has a distal end 56 spaced from the gate pad 36. The conductive layer providing the first plate 41 includes a connection region 58 that extends under the gate pad 36 and is spaced from the gate pad 36 by a dielectric layer 43. A conductive via 57 is provided that extends vertically between the connection region 58 of the first plate 41 and the gate pad 36 and electrically couples the first plate 41 to the gate pad 36 and to the gate finger of the transistor device. The area of the capacitor 40 at this end of the capacitor 40 is thus limited by the lateral extension of the second plate 42.

[0079] Figure 4 includes Figure 4A and Figure 4B illustrating a plan view and a cross-sectional view of a semiconductor device 60 including a lateral transistor device 61 according to an embodiment. The transistor device 61 includes a capacitor 62 integrated into a metallization structure 64 on a first surface 65 of a semiconductor body 66 of the semiconductor device 60. In this embodiment, the capacitor 62 is located on an active region 63 of the transistor device 61 and above a cell field region.

[0080] Referring to the cross-sectional view of Figure 4B , the semiconductor body 66 is a group III nitride based semiconductor body including a transition structure 67 arranged on a non-illustrated substrate, a channel layer 68 arranged on the transition layer 67, and a barrier layer 69 arranged on the channel layer 68, such that a heterojunction 70 is formed at the interface between the channel layer 68 and the barrier layer 69. The channel layer 68 can include gallium nitride and the barrier layer 69 can include aluminum gallium nitride, and the heterojunction 70 formed between the channel layer 68 and the barrier layer 69 is capable of supporting a two-dimensional charge gas, such as a two-dimensional electron gas (2DEG).

[0081] The transistor device 61 comprises a source finger electrode 71, a drain finger electrode 72 and a gate finger electrode 73 arranged on a first surface 65 of a semiconductor body 66. Thus, the transistor device 61 is a lateral transistor device having an electrically conductive channel extending substantially parallel to the first surface 65.

[0082] Each of the source finger electrode 71, the drain finger electrode 72 and the gate finger electrode 73 has an elongated shape in a cross-sectional view extending into the plane of the drawing into which the source finger electrode 71, the drain finger electrode 72 and the gate finger electrode 73 are arranged. Figure 4B Each of the source finger electrode 71, the drain finger electrode 72 and the gate finger electrode 73 has an elongated shape in a cross-sectional view extending into the plane of the drawing into which the source finger electrode 71, the drain finger electrode 72 and the gate finger electrode 73 are arranged. Figure 4A Using a Cartesian coordinate system having the plane of the drawing in the x-y plane, each of the source finger electrode 71, the drain finger electrode 72 and the gate finger electrode 73 has a length extending in the y-direction, a width extending in the x-direction and a thickness extending in the z-direction. Figure 4A

[0083] In the views illustrated in Figure 4A and Figure 4B , a single source electrode 71 is illustrated, wherein a gate finger electrode 65 is positioned adjacent to two opposite sides of the source finger electrode 71 and a drain electrode 72 is positioned adjacent to each gate finger electrode 73, such that the gate finger electrode 73 is positioned laterally between the source finger electrode 71 and one drain finger electrode 72.

[0084] In the plan view of Figure 4A , the source finger electrode 71, the drain finger electrode 72 and the gate finger electrode 73 are not illustrated, Figure 4A The plan view of illustrates a structure of a metallization layer 64 arranged on the first surface 65 of the semiconductor body 66 and arranged on the source finger electrode 71, the drain finger electrode 72 and the gate finger electrode 73.

[0085] The capacitor 62 is located above the source finger electrode 71 and comprises a first plate 74 formed by a first conductive layer 75 of the metallization structure 64 and a second plate 76 formed by a second conductive layer 77 of the metallization structure 64. The first conductive layer 75 and the second conductive layer 77 are spaced apart from each other by a first insulating layer 78 of the metallization structure 64 also forming a dielectric of the capacitor 62.

[0086] Figure 4A The metallization structure 64 further comprises a third conductive layer 79 located between the first conductive layer 75 and the first surface 65 of the semiconductor body 66. The third conductive layer 79 comprises a source finger 80 arranged on the source finger electrode 71 and a drain finger 81 located on the drain finger electrode 72. The third conductive layer 79 also comprises a gate finger 82 located on the gate finger electrode 73.The gate flow channels 82, as seen in the plan view, are positioned laterally adjacent to the gate finger electrodes 73, the source finger electrodes 71 and the drain finger electrodes 72. In particular, the gate flow channels 82 extend substantially perpendicular to the lengthwise extent of the source finger electrodes 71, the drain finger electrodes 72 and the gate finger electrodes 73 and in the x-direction and are spaced apart from the distal ends of the source finger electrodes 71 and the drain finger electrodes 72. The gate finger electrodes 73 extend into the gate flow channels 82 and are connected with the gate flow channels 82, so that the gate flow channels 82 electrically couple the respective gate finger electrodes 73 with each other.

[0087] The first conductive layer 75 and in particular the first plate 74 of the capacitor 62 is located above the third conductive layer 79 and vertically above the source fingers 80. The first plate 74 is electrically insulated from the underlying source fingers 80 and the source finger electrodes 71 by the second insulating layer 83. In some embodiments, the second insulating layer 83 can comprise silicon nitride and can be much thinner than the first insulating layer 78 located between the conductive plates 74, 76 of the capacitor 62.

[0088] The source fingers 80 have a width which is larger than the width of the source finger electrodes 71 and can have a width such that they are located above the gate finger electrodes 73. The metallization structure 64 further comprises a third insulating layer 84 located between the source fingers 80 and the gate fingers 81 and a fourth insulating layer 85 located on the first surface 65 and extending between the source fingers 80 and the drain fingers 81 and also covering the gate finger electrodes 73 in order to electrically insulate the gate finger electrodes 73 from the source fingers 80 above.

[0089] As can be seen in the plan view of Figure 4A The source fingers 80 also have an elongated shape and are spaced apart from the drain fingers 81 which also have an elongated shape. The source fingers 80 and the drain fingers 81 have a lengthwise direction extending in the y-direction and a width extending in the x-direction.

[0090] The metallization structure 64 comprises a second conductive layer 77 which is used to electrically couple the source fingers 80 with each other and the drain fingers 81 with each other. With reference to Figure 4A The second conductive layer 77 is structured to provide at least one source bus 86 and at least one drain bus 87 which are spaced apart from each other laterally and have a lengthwise direction extending in the x-direction and perpendicular to the lengthwise direction of the source fingers 80 and the drain fingers 81. The source buses 86 and the drain buses 87 are arranged alternatingly in the y-direction.

[0091] The source bus 86 and the drain bus 87 are elongated and extend substantially perpendicular to the source fingers 80 and the drain fingers 81 and have a lateral extension such that they extend over at least two, if not more, source fingers 80 and drain fingers 81. The drain bus 87 extends over the source fingers 80 and is electrically coupled to the drain fingers 81 located on opposite sides of the source fingers 80 by conductive vias 88 extending through the first insulating layer 78. The drain bus 87 is electrically insulated from the source fingers by the first insulating layer 78. Similarly, the source bus 86 extends over the drain fingers 81 and is electrically insulated from the drain fingers 81 by the first insulating layer 78. The source bus 86 is electrically coupled to the source fingers 80 by conductive vias 89 extending from the source bus through the first insulating layer 78 to the source fingers 80. The conductive vias 88, 89 have an offset arrangement. The conductive vias 89 from the source fingers 80 are positioned laterally adjacent to the first plate 74 of the capacitor 62 and spaced apart in the y-direction from the first plate 74 of the capacitor 62 which is also located on the source fingers 80 but is spaced apart and insulated from the source fingers 80 by the second insulating layer 83.

[0092] A plan view of the Cartesian coordinate system, Figure 4A may be considered to be in the x-y plane whereby the source electrode fingers 71, the drain electrode fingers 72, the gate electrode fingers 73, the source fingers 80 and the drain fingers 81 of the third conductive layer 79 extend in the y-direction and the source bus 86, the drain bus 87 of the second conductive layer 77 and the gate bus 82 of the third conductive layer 79 extend in the x-direction. The z-direction extends substantially perpendicular to the first main surface 65 of the semiconductor body 66 such that the conductive vias 88, 89 and 90 extend in the z-direction.

[0093] The first conductive layer 75 has a lateral extension corresponding to the lateral extension of the width of the first plate 74 of the capacitor 62. As can be seen in the plan view of Figure 4A the transistor device 61, the first conductive layer 75 extends beyond the distal end of the source fingers 80 and over the gate runners 82 formed in the underlying third conductive layer 79. The first conductive layer 75 and the first plate 74 of the capacitor 62 are electrically coupled to the gate bus 82 by conductive vias 90 extending through the first insulating layer 78 located between the first conductive layer 75 and the gate runners 82.

[0094] The capacitor 62 is formed within the active area of the transistor device 61 as it is located above the source fingers 80 of the third conductive layer and the drain bus 87 of the second conductive layer 77. Capacitors having a form corresponding to the form of the capacitor 62 can be located above some or all of the source fingers 80 of the transistor device 61.

[0095] In the embodiment illustrated in FIG. 4, the first plate of the capacitor 62 has a width in the x-direction that is slightly less than the width of the underlying source finger 80 in the x-direction, such that the top edge of the source finger 80 is surrounded by the first insulating layer 78, the second insulating layer 83, and the third insulating layer 84.

[0096] The capacitor 62 includes a first plate 74 formed from the first conductive layer 75 and a second plate 76 formed from a portion of the second conductive layer 77 that also forms the drain bus 87. The dielectric of the capacitor 62 is formed from a portion of the first insulating layer 78, which also serves as the interlevel dielectric for the metallization structure 64, which electrically insulates the second conductive layer 77 from the underlying third conductive layer 79, and in particular, electrically insulates the drain bus 87 from the underlying source finger 80 and the source bus 86 from the underlying drain finger 81.

[0097] In this embodiment, the additional conductive layer 75 is included in the metallization structure for the transistor device 61 to form the first plate 74, which does not form any part of the redistribution structure between one of the electrodes of the transistor device 61 and an external contact pad. The first conductive layer 75 forming the first plate can be used exclusively for the purpose of monolithically integrating the capacitor 62 into the metallization structure 64 at a location above the cell field region and the active region 63 of the transistor device 61.

[0098] The first plate 74 is coupled to the gate electrode finger by virtue of the extension of the first plate 74 in the y-direction over the gate runner 82 and the conductive via 90. The second plate 76 is formed from the portion of the drain bus 87 over the first plate 74 and is coupled to the drain finger electrode 72 through the conductive via 89 and the drain finger 81. The capacitor 62 provides a linear capacitance coupled in parallel with the intrinsic gate-drain capacitance of the transistor device 61, such that the combined gate-drain capacitance is linearized and dv / dt is linearized, thus enabling precise control of slew rate.

[0099] The source buses 86 are spaced apart from one another by the intervening drain buses 87. The source buses 86 can be electrically coupled together by further source buses that can extend perpendicular to the source buses 86 and parallel to the source fingers 80, positioned adjacent to the distal ends of the drain buses 87 and spaced apart therefrom. Similarly, the drain buses 87 can be electrically coupled together by further drain buses that extend perpendicular to the drain buses 87 and parallel to the drain fingers 81, and positioned at opposite sides of the active region forming the additional source buses. Source contacts and drain contacts can be located on these additional buses.

[0100] FIG. 5 includes Figure 5A andFigure 5B Fig. 5 illustrates a plan view and a cross-sectional view of a semiconductor device 100 including a lateral transistor device 61 and a linearization capacitor 101 according to an embodiment.

[0101] The lateral transistor device 61 corresponds to the lateral transistor device 61 of the semiconductor device 60 illustrated in Fig. 3. The linearization capacitor 101 includes a first plate 74' formed by the first conductive layer 75, which is located on a second insulating layer 83, which in turn is located on the source finger 80, as in the embodiment illustrated in Fig. 4. The linearization capacitor 101 further includes a second plate 76 formed by the second conductive layer 77 of the metallization structure 64, as in the embodiment illustrated in Fig. 4. The first plate 74' is spaced apart from the second plate 76 by a first insulating layer 78 to form the structure of the linearization capacitor 101. The first insulating layer 78 also forms a first interlayer dielectric of the metallization structure 64.

[0102] The linearization capacitor 101 of the embodiment illustrated in Fig. 5 differs from the linearization capacitor 62 of the embodiment illustrated in Fig. 4 in the value of the provided capacitance and the width of the first plate 74' and also the width of the first plate 74' relative to the width of the underlying source finger 80.

[0103] In the embodiment illustrated in Fig. 5, the first plate 74' has a width in the x-direction that is larger than the width of the source finger 80 in the x-direction, so that the opposing outer peripheral edges 103, 104 of the first plate 74' are positioned vertically above the third insulating layer 84 extending between the source finger 80 and the drain finger 81. The larger overall size of the first plate 74' compared to the first plate 74 in the embodiment illustrated in Fig. 4 results in an increase in capacitance of the capacitor 101 compared to the capacitor 62 illustrated in Fig. 4. The position of the outer peripheral edges 103, 104 above the third insulating layer 84 compared to the embodiment illustrated in Fig. 4 provides an increased gate-source capacitance C GS .

[0104] As in the embodiment illustrated in Fig. 4, the first plate 74' is electrically coupled to the gate bus 82 by a conductive via 90 extending between the first plate 74' and the gate bus 82 at a location laterally adjacent to and spaced apart from the distal ends of the source finger 80 and the drain finger 81. The second plate 76 is formed by a portion of the second conductive layer 77 forming the drain bus 87. As in the embodiment illustrated in Fig. 4, the capacitor 101 can be located over the source fingers 80 of some or all of the transistor devices 61.

[0105] The first plate 74, 74' can comprise titanium nitride and / or tungsten. The material of the second insulating layer 83 and also its thickness, as well as the material and thickness of the third insulating layer 84, between the first plate 74, 74' and the underlying source finger 80 can be chosen so that a desired rated voltage of the transistor device is maintained.

[0106] For the transistor device 61 of the semiconductor device 60 and 100, the metallization structure 64 has a structure formed by the fourth insulating layer 85, the substantially co-planar third conductive layer 79 and the third insulating layer 84, the second insulating layer 83, the first conductive layer 75, the first insulating layer 78 and the second conductive layer 77, starting from the first surface 65 of the semiconductor body 66. In some embodiments, the second conductive layer 77 can comprise two or more sub-layers, for example a titanium nitride layer on the first insulating layer 78 and a metal layer (for example copper or a copper alloy) on the titanium nitride layer. Similarly, the first insulating layer 78 can comprise two or more sub-layers. In some embodiments, the first sub-layer can comprise silicon oxide and a silicon nitride layer can be on the silicon oxide layer.

[0107] The first insulating layer 78 and the third insulating layer 84 can be referred to as inter-layer dielectrics. The third conductive layer 79 is generally referred to as M1 for the first metal layer of the metallization structure 64 and the second conductive layer 77 is generally referred to as M2 for the second metal layer of the metallization structure 64. The third insulating layer 84 is the first inter-layer dielectric ILD1 and the first insulating layer 78 is the second inter-layer dielectric ILD2. In this nomenclature, the first plate 74, 74' can be considered as the third metal layer M3.

[0108] While the first plate of the capacitor, which is coupled to the gate of the transistor device, can be located below the second plate, which is coupled to the drain of the transistor device, in the z-direction, the opposite orientation is also possible, with the plate of the capacitor coupled to the drain being located below the plate of the capacitor coupled to the gate.

[0109] In summary, by monolithically integrating an additional linear capacitor in the metallization structure applied to a semiconductor device comprising a lateral transistor device and electrically coupling the additional linear capacitor between the gate and the drain of the lateral transistor device, the combined gate-drain capacitance of the transistor device is linearized, such that the slew rate of dv / dt is linear, allowing to adjust (e.g. slow down) the switching speed to a desired value. Since the geometry of the capacitor structure can be precisely controlled using the lithographic manufacturing process for preparing the metallization structure (in particular the metal layer providing the capacitor's plate), the capacitance of the capacitor can be well controlled. Since the linearization capacitor is located on the gate and the drain of the transistor structure and is electrically coupled with the gate and the drain of the transistor structure by the metallization structure itself, no additional chip area for the additional capacitor is required and no further pin of the package in which the semiconductor device is encapsulated is required. Thus, external high voltage capacitors can be avoided, which avoids parasitic interconnection impedance, reduces the risk of high frequency oscillations and avoids additional variations of dv / dt due to parasitic capacitances.

[0110] Spatially relative terms such as "under", "below", "lower", "above", "upper" and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to those depicted in the figures. Further, terms such as "first", "second", and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like reference numerals are used to denote like elements throughout the description and drawings.

[0111] As used herein, the terms "have", "comprise", "include", "contain", "together with" and "including" and the like are open ended, that is, meaning "including but not limited to", and allow for elements not expressly listed to be present. The words "a" and "an" and "the" preceding an element or integral are intended to be interpreted to cover both the singular as well as the plural of the element or integral. It is further understood that the various embodiments described herein can be combined with each other, unless specifically stated otherwise.

[0112] While specific embodiments have been illustrated and described herein, it will be appreciated that various alterations, modifications, and / or substitutions can be made by those of ordinary skill in the art without departing from the scope of the application. The application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the application be limited only by the claims and their equivalents.

Claims

1. A semiconductor device (30, 60, 100), comprising: Lateral transistor devices (31, 61) having source, drain and gate; Coupled between the gate and drain and also with the inherent gate-drain capacitance C of the lateral transistor devices (31, 61) GD Parallel-coupled monolithically integrated additional capacitors (40, 62), wherein the monolithically integrated additional capacitors (40, 62) have a value greater than C. GD Capacitor C M , The semiconductor devices (30, 60) include a reverse transfer capacitor C. rss , where C rss(Vds＝0V) / C rss(Vds＝400V) <50.

2. The semiconductor device (30, 60, 100) according to claim 1, in, The semiconductor device (30, 60, 100) includes a semiconductor body (45, 66) having a first surface (46, 65). The lateral transistor device (31, 61) includes a source finger electrode (71), a drain finger electrode (72), and a gate finger electrode (73) disposed on a first surface (46, 65) of a semiconductor body (45, 66), wherein the gate finger electrode (73) is arranged laterally between the source finger electrode (71) and the drain finger electrode (72). Furthermore, the metallized structure (64) is arranged on the first surface (66), The additional capacitors (40, 62) are integrated into the metallization structure (64) and coupled between the gate finger electrode (73) and the drain finger electrode (72).

3. The semiconductor device (30) according to claim 2, in, An additional capacitor (40) is arranged on the first surface (46), which is laterally adjacent to the source finger electrode, the drain finger electrode and the gate finger electrode.

4. The semiconductor device (30) according to claim 2 or 3, wherein, An additional capacitor (40) is formed on a first surface (46) and includes a first electrode (41) formed by a first conductive layer (39) of a metallized structure and a second electrode (42) formed by a second conductive layer (44) of a metallized structure, the first electrode (41) and the second electrode (42) being spaced apart from each other by a first insulating layer (43) of a metallized structure.

5. The semiconductor device (30) according to claim 4, wherein, The first plate (41) of the additional capacitor (40) extends from the gate channel (39) formed by the first conductive layer, the gate channel (39) being electrically coupled to the gate finger electrode, or the first plate extends from the gate pad formed by the first conductive layer, the gate pad being electrically coupled to the gate finger electrode, and The second plate (42) of the additional capacitor extends from the drain bus (44) formed by the second conductive layer, and the drain bus (44) is electrically coupled to the drain finger electrode.

6. The semiconductor device (60, 100) according to claim 2, wherein, The lateral transistor device (61) includes an active region (63) that contributes to the current switching, and an additional capacitor (62) is located above the active region (63).

7. The semiconductor device (60, 100) according to claim 6, wherein, An additional capacitor (62) is arranged at least partially above the source finger electrode (71).

8. The semiconductor device (60, 100) according to claim 7, wherein The metallization structure (64) further includes a third conductive layer (79), which includes source fingers (80) disposed on the source finger electrode (71), drain fingers (81) disposed on the drain finger electrode (72), and a gate channel (82) positioned laterally adjacent to the gate finger electrode (73), the source finger electrode (71), and the drain finger electrode (72). in, The first conductive layer (75) is disposed above the source finger (80) and is insulated from the source finger (80) by the second insulating layer (83).

9. The semiconductor device (60, 100) according to claim 7 or 8, wherein, The second conductive layer (77) includes alternating drain bus (86) and source bus (87), which are arranged to extend vertically above and substantially perpendicular to the source fingers (80) and drain fingers (81). The source finger (80) is coupled to the source bus (86) through a first conductive via (89) extending through the first insulating layer (78), and the drain finger (81) is coupled to the drain bus (87) through a second conductive via (88) extending through the first insulating layer (78).

10. The semiconductor device (60, 100) according to claim 9, further comprising: A third insulating layer (84) is located between the source finger (80) and the drain finger (81) of the third conductive layer (79); A fourth insulating layer (85) is disposed on the first surface (65), extending between the source finger electrode (71) and the drain finger electrode (72) and covering the gate finger electrode (73), wherein a third insulating layer (84) is disposed on the fourth insulating layer (85).

11. The semiconductor device (60, 100) according to claim 10, wherein, The first conductive layer (75) is coupled to the gate channel (82) through a third conductive via (90) extending through the third insulating layer (84) and the fourth insulating layer (85).

12. The semiconductor device (30, 60, 100) according to any one of claims 1 to 3, wherein, The lateral transistor devices (31, 61) are III-V group semiconductor transistor devices.

13. The semiconductor device (30, 60, 100) according to claim 12, wherein, Lateral transistor devices (31, 61) are transistor devices based on group III nitrides.

14. An inverter, comprising: One or more half-bridge circuits, each half-bridge circuit including a first switch coupled in series with a second switch. Wherein, at least one of the first switch and the second switch includes a semiconductor device (30, 60, 100) according to any one of claims 1 to 13.

15. The inverter of claim 14, further comprising a gate driver circuit for actively controlling the gate current of at least one of the first switch and the second switch.

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