Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device with different gate structure structures and a manufacturing method thereof. The semiconductor device includes a first pair of source / drain regions and a second extended source / drain region arranged on a substrate, a first nanostructure channel region and a second nanostructure channel region, and a first gate structure and a second gate structure having different effective work function values. The first gate structure and the second gate structure include a first high-K gate dielectric layer and a second high-K gate dielectric layer, a first barrier metal layer and a second barrier metal layer having different thicknesses, a first work function metal (WFM) oxide layer and a second work function metal oxide layer having substantially equal thicknesses respectively arranged on the first barrier metal layer and the second barrier metal layer, a first dipole layer arranged between the first work function metal oxide layer and the first barrier metal layer, and a second dipole layer arranged between the second work function metal oxide layer and the second barrier metal layer.

Description

[0001] Priority and cross references

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 928,557, filed on October 31, 2019, entitled “Gate Structure for Threshold Voltage Adjustment of FinFETs and Full-Ring FETs,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art

[0004] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to grow. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). This scaling down has increased the complexity of semiconductor manufacturing processes. Summary of the invention

[0005] According to one aspect of the present invention, a semiconductor device is provided, comprising: a substrate; a first epitaxial source / drain (S / D) region and a second epitaxial source / drain region, arranged on the substrate; a first nanostructured channel region and a second nanostructured channel region, respectively arranged between the epitaxial source / drain region of the first epitaxial source / drain region and between the epitaxial source / drain region of the second epitaxial source / drain region; and a first gate structure and a second gate structure, having different effective work function values ​​from each other; wherein the first gate structure and the second gate structure comprise: a first high-K gate dielectric layer and a second high-K gate dielectric layer. layers, surrounding the first nanostructure channel region and the second nanostructure channel region, respectively; a first barrier metal layer and a second barrier metal layer, having thicknesses different from each other, respectively disposed on the first high-K gate dielectric layer and the second high-K gate dielectric layer; a first work function metal (WFM) oxide layer and a second work function metal oxide layer, having thicknesses substantially equal to each other, respectively disposed on the first barrier metal layer and the second barrier metal layer; a first dipole layer, disposed between the first work function metal oxide layer and the first barrier metal layer; and a second dipole layer, disposed between the second work function metal oxide layer and the second barrier metal layer.

[0006] According to another aspect of the present invention, a semiconductor device is provided, comprising: a substrate; a first pair of epitaxial source / drain (S / D) regions and a second pair of epitaxial source / drain regions, arranged on the substrate; a first fin region and a second fin region, respectively arranged between the epitaxial source / drain regions of the first pair of epitaxial source / drain regions and between the epitaxial source / drain regions of the second pair of epitaxial source / drain regions; and a first gate structure and a second gate structure, comprising: a first high-K gate dielectric layer and a second high-K gate dielectric layer, respectively arranged on the first fin region and the second fin region; a first barrier metal layer and a second barrier metal layer, having different thicknesses from each other, respectively arranged on the first high-K gate dielectric layer and the second high-K gate dielectric layer; a first barrier metal oxide layer and a second barrier metal oxide layer, respectively arranged on the first barrier metal layer and the second barrier metal layer; an aluminum (Al)-free rare earth metal-based (REM-based) work function metal (WFM) oxide layer, arranged on the first barrier metal oxide layer; and an aluminum-based work function metal oxide layer, arranged on the second barrier metal oxide layer.

[0007] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming a first nanostructure channel region and a second nanostructure channel region in a fin structure on a substrate; forming a first high-K gate dielectric layer and a second high-K gate dielectric layer surrounding the first nanostructure channel region and the second nanostructure channel region, respectively; forming a first barrier metal layer and a second barrier metal layer of different thicknesses on the first high-K gate dielectric layer and the second high-K gate dielectric layer; forming a first work function metal (WFM) oxide layer and a second work function metal oxide layer of substantially equal thicknesses on the first barrier metal layer and the second barrier metal layer, respectively; performing a push-in annealing process on the first work function metal oxide layer and the second work function metal oxide layer; forming a third barrier metal layer and a fourth barrier metal layer of substantially equal thicknesses on the first work function metal oxide layer and the second work function metal oxide layer; and forming a first gate metal filling layer and a second gate metal filling layer on the third barrier metal layer and the fourth barrier metal layer, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0009] Figure 1A , Figure 1B-Figure 1E ,and Figure 1F-1O shows an axonometric view, a cross-sectional view, and device characteristics of semiconductor devices having different gate structures according to some embodiments;

[0010] Figure 2is a flow chart of a method for manufacturing a semiconductor device with different gate structures according to some embodiments;

[0011] Figures 3A-14B shows cross-sectional views of semiconductor devices having different gate structures at various stages of their fabrication process according to some embodiments;

[0012] Illustrative embodiments will now be described with reference to the drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0014] For ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "exemplary," etc., indicate that the described embodiment may include specific features, structures, or characteristics, but not every embodiment necessarily includes the specific features, structures, or characteristics. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0016] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, and thus the phraseology or terminology of this specification will be interpreted by those skilled in the relevant (some) fields based on the teachings herein.

[0017] As used herein, the term "etch selectivity" refers to the ratio of etching rates of two different materials under the same etching conditions.

[0018] As used herein, the term "high-k" refers to a high dielectric constant. In the field of semiconductor device structure and manufacturing process, high-k refers to a dielectric constant greater than the dielectric constant of SiO2 (eg, greater than 3.9).

[0019] As used herein, the term "p-type" is defined as structures, layers, and / or regions that are doped with a p-type dopant, such as boron.

[0020] As used herein, the term "n-type" is defined as structures, layers, and / or regions that are doped with an n-type dopant, such as phosphorus.

[0021] As used herein, the term "nanostructured" is defined as structures, layers, and / or regions having horizontal dimensions (eg, along the X and / or Y axes) and / or vertical dimensions (eg, along the Z axis) less than, for example, 100 nm.

[0022] As used herein, the term "n-type work function metal (nWFM)" is defined as a metal or metal-containing material having a work function value closer to the conduction band energy than the valence band energy of the material of the FET channel region. In some embodiments, the term "n-type work function metal (nWFM)" is defined as a metal or metal-containing material having a work function value less than 4.5 eV.

[0023] As used herein, the term "p-type work function metal (pWFM)" is defined as a metal or metal-containing material having a work function value closer to the valence band energy than the material conductivity energy of the FET channel region. In some embodiments, the term "p-type work function metal (pWFM)" is defined as a metal or metal-containing material having a work function value equal to or greater than 4.5 eV.

[0024] In some embodiments, the terms "about" and "substantially" may indicate a value of a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of that value).

[0025] The fin structures disclosed herein can be patterned by any suitable method. For example, the fin structures can be patterned using one or more lithography processes including a double patterning process or a multi-patterning process. Typically, the double patterning process or the multi-patterning process combines lithography and self-alignment processes, allowing the creation of patterns with smaller pitches, for example, than can be obtained using a single direct lithography process. For example, in some embodiments, a sacrificial layer is formed above a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structure.

[0026] The gate voltage required to turn on a field effect transistor (FET) - the threshold voltage Vt may depend on the effective work function (EWF) value of the semiconductor material of the FET channel region and / or the gate structure of the FET. For example, for an n-type FET (NFET), reducing the difference between the EWF value of the NFET gate structure and the conduction band energy of the material of the NFET channel region (e.g., 4.1 eV for Si, or 3.8 eV for SiGe) may reduce the NFET threshold voltage. For a p-type FET (PFET), reducing the difference between the EWF value of the PFET gate structure and the valence band energy of the material of the PFET channel region (e.g., 5.2 eV for Si, or 4.8 eV for SiGe) may reduce the PFET threshold voltage. The EWF value of the FET gate structure may depend on the thickness and / or material composition of each layer of the FET gate structure. In this way, the FET may be manufactured to have different threshold voltages by adjusting the thickness and / or material composition of the FET gate structure.

[0027] As the demand for multifunctional portable devices increases, the demand for FETs with different threshold voltages on the same substrate also increases. One way to achieve such a FET may be to use different work function metal (WFM) layer thicknesses in the FET gate structure. However, different WFM layer thicknesses may be limited by the geometry of the FET gate structure. For example, in a gate-all-around (GAA) FET, the WFM layer thickness may be limited by the spacing between the nanostructure channel regions of the GAA FET. Moreover, as FETs (e.g., GAAFETs and / or finFETs) continue to shrink, depositing different WFM layer thicknesses may become increasingly challenging.

[0028] The present invention provides exemplary FET gate structures having different EWF values ​​to form FETs (e.g., GAAFETs and / or finFETs) with different threshold voltages, and provides exemplary methods for forming such FETs on the same substrate. The exemplary methods form NFETs and PFETs with similar WFM layer thicknesses but with different threshold voltages on the same substrate. Compared to other methods of forming FETs with similar channel dimensions and threshold voltages on the same substrate, these exemplary methods can be simpler and more cost-effective in the manufacture of reliable gate structures with lower gate resistance in FETs with nanostructured channel regions and different threshold voltages. In addition, compared to other methods of forming FETs with similar threshold voltages, these exemplary methods can form FET gate structures with smaller sizes (e.g., thinner gate stacks).

[0029] In some embodiments, NFETs and PFETs having different gate structure configurations but similar WFM layer thicknesses may be selectively formed on the same substrate to achieve different threshold voltages from each other. Different gate structure configurations may have barrier metal layers of different thicknesses disposed between the WFM layer and the high-K gate dielectric layer. In addition, the WFM layer may include a WFM oxide layer that induces a dipole layer at the interface between the WFM layer and the barrier metal layer. Different barrier metal layer thicknesses provide different spacings between the WFM layer and the high-K gate dielectric layer, and provide different spacings between the induced dipole layer and the high-K gate dielectric layer. These different spacings enable the FET gate structures to have different EWF values ​​from each other, and therefore have different threshold voltages from each other. Therefore, adjusting the barrier metal layer thickness may adjust the EWF values ​​of the NFET and PFET gate structures, and therefore may adjust the threshold voltages of the NFET and PFET without changing their WFM layer thicknesses.

[0030] According to some embodiments, reference Figure 1A-Figure 1O A semiconductor device 100 is depicted having NFETs 102N1 - 102N3 and PFETs 102P1 - 102P3 . Figure 1A An isometric view of a semiconductor device 100 is shown in accordance with some embodiments. Figure 1B-Figure 1C and Figure 1D-1E According to some embodiments, Figure 1A A cross-sectional view of the semiconductor device 100 taken along lines AA and BB. Figure 1F-1O 1 shows device characteristics of the semiconductor device 100 according to some embodiments. Figure 1A-Figure 1OSix FETs are discussed, but the semiconductor device 100 may have any number of FETs. Unless otherwise noted, discussions of elements of NFETs 102N1-102N3 and PFETs 102P1-102P3 with the same label apply to each other. Axonometric and cross-sectional views of the semiconductor device 100 are shown for illustration purposes and may not be drawn to scale.

[0031] refer to Figure 1A-Figure 1C , NFETs 102N1-102N3 and PFETs 102P1-102P3 may be formed on a substrate 106. The substrate 106 may be a semiconductor material, such as but not limited to silicon. In some embodiments, the substrate 106 may include a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 106 may include (i) a basic semiconductor (e.g., germanium (Ge)); (ii) a compound semiconductor including a III-V semiconductor material; (iii) an alloy semiconductor (e.g., silicon germanium (SiGe)); (iv) a silicon-on-insulator (SOI) structure; (v) a silicon-germanium (SiGe) on insulator structure (SiGeOI); (vi) a germanium-on-insulator (GeOI) structure; or (vii) a combination thereof. In addition, the substrate 106 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0032] The NFETs 102N1 - 102N3 and PFETs 102P1 - 102P3 may include fin structures 1081 - 1082 extending along the X-axis, epitaxial fin regions 110A- 110B, gate structures 112N1 - 112N3 , and 112P1 - 112P3 inner spacers 142 , and gate spacers 114 .

[0033] refer to Figure 1B-Figure 1C , the fin structure 1081 may include a fin base portion 108A and a nanostructure channel region 120N disposed on the fin base portion 108A, and the fin structure 1082 may include a fin base portion 108B and a nanostructure channel region 120P disposed on the fin base portion 108B. In some embodiments, the fin base portions 108A-108B may include a material similar to the substrate 106. The gate structures 112N1-112N3 may surround the nanostructure channel region 120N, and the gate structures 112P1-112P3 may surround the nanostructure channel region 120P. The nanostructure channel regions 120N-120P may include a semiconductor material similar to or different from the substrate 106, and may include semiconductor materials similar to or different from each other.

[0034] In some embodiments, the nanostructured channel regions 120N for the NFETs 102N1-102N3 may include Si, SiAs, silicon phosphide (SiP), SiC, or silicon carbon phosphide (SiCP), while the nanostructured channel regions 120P for the PFETs 102P1-102P3 may include SiGe, silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), or a III-V semiconductor compound. In some embodiments, the nanostructured channel regions 120N-120P may include Si, SiAs, SiP, SiC, SiCP, SiGe, SiGeB, GeB, SiGeSnB, or a III-V semiconductor compound. Although the nanostructured channel regions 120N-120P are shown as having rectangular cross-sections, the nanostructured channel regions 120N-120P may have cross-sections of other geometric shapes (e.g., circular, elliptical, triangular, or polygonal).

[0035] refer to Figure 1A-Figure 1C , epitaxial fin regions 110A-110B may be grown on fin base portions 108A-108B, respectively, and may be source / drain (S / D) regions of NFETs 102N1-102N3 and PFETs 102P1-102P3. Epitaxial fin regions 110A-110B may include epitaxially grown semiconductor materials that are similar or different from each other. In some embodiments, the epitaxially grown semiconductor material may include a material that is the same as or different from the material of substrate 106. Epitaxial fin regions 110A and 110B may be n-type and p-type, respectively. In some embodiments, n-type epitaxial fin region 110A may include SiAs, SiC, or SiCP. P-type epitaxial fin region 110B may include SiGe, SiGeB, GeB, SiGeSnB, III-V semiconductor compounds, or combinations thereof.

[0036] The gate structures 112N1-112N3 and 112P1-112P3 may be multi-layer structures. The gate structures 112N1-112N3 may surround the nanostructure channel region 120N, and the gate structures 112P1-112P3 may surround the nanostructure channel region 120P. For this structure, the gate structures 112N1-112N3 and 112P1-112P3 may be referred to as "all-around gate (GAA) structures" or "horizontal all-around gate (HGAA) structures". The NFETs 102N1-102N3 and PFETs 102P1-102P3 may be referred to as "GAAFETs 102N1-102N3 and 102P1-102P3" or "GAA NFETs 102N1-102N3 and PFETs 102P1-102P3", respectively.

[0037] In some embodiments, NFETs 102N1-102N3 and PFETs 102P1-102P3 may be finFETs, and as Figure 1D-1E As shown, fin regions 120N*-120P* are provided instead of nanostructured channel regions 120N-120P. Such finFETs 102N1-102N3 and 102P1-102P3 may be as shown. Figure 1D-1E Shown are gate structures 112N1 - 112N3 and 112P1 - 112P3 disposed on fin regions 120N*- 120P*, respectively.

[0038] The gate structures 112N1-112N3 and 112P1-112P3 may include an interfacial oxide layer 127, a high-k (HK) gate dielectric layer 128N1-128N3 and 128P1-128P3, a first barrier metal layer 129N1-129N3 and 129P1-129P3, a barrier metal oxide layer 130N1-130N3 and 130P1-130P3, a dipole layer 131N1-131N3 and 131P1-131P3, a WFM oxide layer 132N1-132N3 and 132P1-132P3, a second barrier metal layer 133, a fluorine-free tungsten (FFW) layer 134, and a gate metal fill layer 135. Although Figure 1B-Figure 1C All layers of the gate structures 112N1-112N3 and 112P1-112P3 are shown to surround the nanostructure channel regions 120N-120P, but the nanostructure channel regions 120N-120P may be surrounded by at least the interface oxide layer 127 and the HK gate dielectric layers 128N1-128N3 and 128P1-128P3 to fill the space between adjacent nanostructure channel regions 120N-120P. In this way, the nanostructure channel regions 120N may be electrically isolated from each other to prevent short circuits between the gate structures 112N1-112N3 and the S / D regions 110A during operation of the NFETs 102N1-102N3. Similarly, the nanostructure channel regions 120P may be electrically isolated from each other to prevent shorts between the gate structures 112P1 - 112P3 and the S / D regions 110B during operation of the PFETs 102P1 - 102P3 .

[0039] The interface oxide layer 127 may be disposed on the nanostructured channel regions 120N-120P and may include silicon oxide and have a thickness ranging from about 0.5 nm to about 1.5 nm. Each of the HK gate dielectric layers 128N1-128N3 and 128P1-128P3 may have a thickness (e.g., about 1 nm to about 3 nm) that is about 2 to 3 times the thickness of the interface oxide layer 127 and may include (i) a high-k dielectric material such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO4). O2); and (ii) high-k dielectric materials having oxides of lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu); or (iii) combinations thereof.

[0040] The first barrier metal layers 129N1-129N3 and 129P1-129P3 may be disposed on and in physical contact with the HK gate dielectric layers 128N1-128N3 and 128P1-128P3, respectively. In some embodiments, the first barrier metal layers 129N1-129N3 and 129P1-129P3 may include metal nitrides (e.g., TiN and / or TaN), or any material that can prevent material from diffusing from the upper layers (e.g., WFM oxide layers 132N1-132N3 and 132P1-132P3) to the HK gate dielectric layers 128N1-128N3 and 128P1-128P3. Each first barrier metal layer 129N1-129N3 and 129P1-129P3 may include a single layer of metal nitride or a stack of metal nitride layers. The stack of metal nitride layers may include two or more metal nitride layers that are similar to or different from each other.

[0041] refer to Figure 1B, the thicknesses T1-T3 of the first barrier metal layers 129N1-129N3 may be different from each other to provide different spacings S1-S3 between the WFM metal oxide layers 132N1-132N3 and the HK gate dielectric layers 128N1-128N3, respectively. The different thicknesses T1-T3 may also provide different spacings S4-S6 between the dipole layers 131N1-131N3 and the HK gate dielectric layers 128N1-128N3. In some embodiments, the thickness T3 is greater than the thickness T2, and the thickness T2 is greater than the thickness T1. As a result, the spacings S3 and S6 may be greater than the spacings S2 and S5, and the spacings S2 and S5 may be greater than the spacings S1 and S4, respectively. The different spacings S1-S3 and / or S4-S6 may cause the gate structures 112N1-112N3 to have different EWF values ​​E1-E3 from each other, and thus have different threshold voltages V1-V3 from each other. The thicknesses T1-T3 and S4-S6 may be proportional to the EWF values ​​E1-E3 and the threshold voltages V1-V3, such as Figure 1F-1I shown.

[0042] Similarly, refer to Figure 1C , the thicknesses T4-T6 of the first barrier metal layers 129P1-129P3 may be different from each other to provide different spacings S7-S9 between the WFM metal oxide layers 132P1-132P3 and the HK gate dielectric layers 128P1-128P3. The different thicknesses T4-T6 may also provide different spacings S10-S12 between the dipole layers 131P1-131P3 and the HK gate dielectric layers 128P1-128P3. The thickness T6 is greater than the thickness T5, and the thickness T5 is greater than the thickness T4. As a result, the spacings S7 and S10 may be greater than the spacings S8 and S11, and the spacings S8 and S11 may be greater than the spacings S9 and S12, respectively. The different spacings S7-S9 and / or S10-S12 may cause the gate structures 112P1-112P3 to have different EWF values ​​E4-E6 from each other, and thus have different threshold voltages V4-V6 from each other. Thicknesses T4-T6 and S10-S12 may be directly proportional to EWF values ​​E4-E6 and to threshold voltages V4-V6, such as Figures 1J-1M shown.

[0043] In some embodiments, thicknesses T1-T3 may be similar to or different from thicknesses T4-T6, respectively. Even if thicknesses T1-T3 are similar to corresponding thicknesses T4-T6, threshold voltages V1-V3 may be different from threshold voltages V4-V6, respectively. In some embodiments, thicknesses T1-T6 may be in a range of about 0.5 nm to about 3 nm.

[0044] The barrier metal oxide layers 130N1-130N3 and 130P1-130P3 may be disposed on the first barrier metal layers 129N1-129N3 and 129P1-129P3, respectively. In some embodiments, the barrier metal oxide layers 130N1-130N3 and 130P1-130P3 may include an oxide of a metal included in the metal nitride of the first barrier metal layers 129N1-129N3 and 129P1-129P3. For example, when the first barrier metal layers 129N1-129N3 and 129P1-129P3 include TiN or TaN, the barrier metal oxide layers 130N1-130N3 and 130P1-130P3 may include Ti (e.g., TiO x ) or Ta (e.g. TaO x ). In some embodiments, the thickness of each barrier metal oxide layer 130N1-130N3 and 130P1-130P3 may be in the range of about 0.1 nm to about 0.2 nm. The barrier metal oxide layers 130P1-130P3 are thicker than the barrier metal oxide layers 130N1-130N3 because during the manufacture of the gate structures 112N1-112N3 and 112P1-112P3, the first barrier metal layers 129P1-129P3 are oxidized more times than the first barrier metal layers 129N1-129N3, as described below with reference to Figures 3A-14B as described.

[0045] The WFM oxide layers 132N1-132N3 and 132P1-132P3 may be disposed on and in physical contact with the barrier metal oxide layers 130N1-130N3 and 130P1-130P3, respectively. For the NFETs 102N1-102N3, the n-type WFM oxide layers 132N1-132N3 (also referred to as "nWFM oxide layers 132N1-132N3") may include an oxide of an Al-free (eg, Al-free) metal. In some embodiments, the WFM oxide layers 132N1-132N3 may include (i) rare earth metal (REM) oxides, such as lanthanum oxide (La2O3), cerium oxide (CeO2), ytterbium oxide (Yb2O3), lutetium oxide (Lu2O3), and erbium oxide (Er2O3); (ii) oxides of metals of Group IIA of the periodic table (e.g., magnesium oxide (MgO) or strontium oxide (SrO)), oxides of metals of Group IIIB (e.g., yttrium oxide (Y2O3)), oxides of metals of Group IVB (e.g., hafnium oxide (HfO2) or zirconium oxide (ZrO2)), or oxides of metals of Group VB (e.g., tantalum oxide (Ta2O5)); (iii) silicon dioxide (SiO2); or (iv) combinations thereof.

[0046] In contrast, for PFETs 102P1-102P3, p-type WFM oxide layers 132P1-132P3-132N3 (also referred to as "pWFM oxide layers 132P1-132P3") may include (i) Al-based metal oxides, such as aluminum oxide (Al2O3) and aluminum titanium oxide (Al2TiO5); (ii) oxides of metals of the VB group of the periodic table (e.g., niobium oxide (NbO)), oxides of metals of the IIIA group (e.g., boron oxide B2O3), oxides of metals of the VA group (e.g., phosphorus oxide (P2O5)); or (iii) combinations thereof. In some embodiments, the thickness of each of the WFM oxide layers 132N1-132N3 and 132P1-132P3 may be in the range of about 0.01 nm to about 2 nm. Thicknesses within this range may allow the WFM oxide layers 132N1 - 132N3 and 132P1 - 132P3 to wrap around the nanostructure channel regions 120N- 120P without being limited by the spacing between adjacent nanostructure channel regions 120N- 120P.

[0047] The thicknesses of WFM oxide layers 132N1-132N3 and 132P1-132P3 may be similar to or different from each other, but the material of WFM oxide layers 132N1-132N3 is different from the material of WFM oxide layers 132P1-132P3. In some embodiments, the material of WFM oxide layers 132N1-132N3 may include a metal oxide whose work function value is closer to the conduction band energy than the valence band energy of the material of nanostructure channel region 120N. Conversely, the material of WFM oxide layers 132P1-132P3 may include a metal oxide whose work function value is closer to the valence band energy than the conduction band energy of the material of nanostructure channel region 120P.

[0048] At the interface between the WFM oxide layers 132N1-132N3 and the barrier metal oxide layers 130N1-130N3, the WFM oxide layers 132N1-132N3 induce dipole layers 131N1-131N3. At the interface between the WFM oxide layers 132P1-132P3 and the barrier metal oxide layers 130P1-130P3, the WFM oxide layers 132P1-132P3 induce dipole layers 131P1-131P3. The dipole layers 131N1-131N3 and 131P1-131P3 may have dipoles of metal ions and oxygen ions. The metal ions (e.g., La ions) of the dipole layers 131N1-131N3 diffuse from the metal oxide (e.g., La2O3) of the WFM oxide layers 132N1-132N3, while the oxygen ions of the dipole layers 131N1-131N3 diffuse from the blocking metal oxide layers 130N1-130N3. Similarly, the metal ions (e.g., Al ions) of the dipole layers 131P1-131P3 diffuse from the metal oxide (e.g., Al2O3) of the WFM oxide layers 132P1-132P3, while the oxygen ions of the dipole layers 131P1-131P3 diffuse from the blocking metal oxide layers 130P1-130P3. The dipoles of the dipole layers 131N1-131N3 may have polarities opposite to those of the dipoles of the dipole layers 131P1-131P3. In some embodiments, the concentrations of dipoles in the dipole layers 131N1 - 131N3 and 131P1 - 131P3 may be similar to each other or different from each other.

[0049] The second barrier metal layer 133 may be disposed on and in physical contact with the WFM oxide layers 132N1-132N3 and 132P1-132P3. In some embodiments, the second barrier metal layer 133 may include a metal nitride (e.g., TiN and / or TaN) and may have a thickness in the range of about 1.5 nm to about 3 nm. In some embodiments, the material composition of the second barrier metal layer 133 may be similar to the material composition of the first barrier metal layers 129N1-129N3 and / or 129P1-129P3.

[0050] The FFW layer 134 may be disposed on and in physical contact with the second barrier metal layer 133. The FFW layer 134 may prevent any substantial fluorine diffusion (e.g., fluorine-free diffusion) of the fluorine-based precursor used during the deposition of the overlying gate metal fill layer 135 to the underlying layers, such as the interface oxide layer 127, the HK gate dielectric layers 128N1-128N3 and 128P1-128P3, the first barrier metal layers 129N1-129N3 and 129P1-129P3, the WFM oxide layers 132N1-132N3 and 132P1-132P3, and the second barrier metal layer 133. The FFW layer 134 may include a substantially fluorine-free tungsten layer. The substantially fluorine-free tungsten layer may include an amount of fluorine contaminants less than about 5 atomic percent in the form of ions, atoms, and / or molecules. In some embodiments, the FFW layers 134 may each have a thickness ranging from about 2 nm to about 4 nm to effectively prevent fluorine from diffusing from the gate metal filling layer 135 .

[0051] The gate metal filling layer 135 may each include a single layer of a metal layer or a stack of metal layers. The stack of metal layers may include metals that are different from each other. In some embodiments, the gate metal filling layer 135 may include a suitable conductive material, such as W, Ti, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0052] Figure 1N It is shown that when the WFM oxide layers 132N1-132N3 include La2O3, along Figure 1B The atomic concentration distribution of oxygen, nitrogen, and lanthanum atoms along line C. Figure 1N As shown, the atomic concentration distribution of La atoms may have peaks at interfaces between the WFM oxide layers 132N1 - 132N3 and the barrier metal oxide layers 130N1 - 130N3 , respectively.

[0053] Fig.1O It is shown that when the WFM oxide layers 132P1-132P3 include Al2O3, along Figure 1C The atomic concentration distribution of oxygen, nitrogen, and lanthanum atoms along line D. Fig.1O As shown, the atomic concentration distribution of Al atoms may have a peak at the interface between the WFM oxide layers 132P1 - 132P3 and the barrier metal oxide layers 130P1 - 130P3 .

[0054] Return to reference Figure 1B-Figure 1E, the gate spacers 114 and the internal spacers 142 may form sidewalls of the gate structures 112N1-112N3 and 112P1-112P3. According to some embodiments, each of the gate spacers 114 and / or the internal spacers 142 may be in physical contact with the interface oxide layer 127 and the HK gate dielectric layers 128N1-128N3 and 128P1-128P3. Each of the gate spacers 114 and the internal spacers 142 may include an insulating material, such as silicon oxide, silicon nitride, a low-k material, and combinations thereof. Each of the gate spacers 114 and the internal spacers 142 may have a low-k material having a dielectric constant less than about 3.9.

[0055] The semiconductor device 100 may further include an etch stop layer (ESL) 116, an interlayer dielectric (ILD) layer 118, and a shallow trench isolation (STI) region 138. The ESL 116 may be disposed on the sidewalls of the gate spacer 114 and on the epitaxial fin regions 110A-110B. The ESL 116 may be configured to protect the gate structures 112N1-112N3 and 112P1-112P3 and / or the S / D regions 110A-110B. In some embodiments, the ESL 116 may include, for example, silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicon carbon boron nitride (SiCBN), or a combination thereof.

[0056] The ILD layer 118 may be disposed on the ESL 116 and may include a dielectric material deposited using a deposition method suitable for a flowable dielectric material (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide). In some embodiments, the dielectric material is silicon oxide. The STI regions 138 may be configured to provide electrical isolation between the NFETs 102N1-102N3 and the PFETs 102P1-102P3 and adjacent FETs (not shown) on the substrate 106 and / or adjacent active and passive elements (not shown) integrated with or deposited on the substrate 106. In some embodiments, the STI regions 138 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable insulating materials.

[0057] The cross-sectional shapes of the semiconductor device 100 and its elements (eg, fin structures 1081 - 1082 , gate structures 112N1 - 112N3 and 112P1 - 112P3 , epitaxial fin regions 110A- 110B, inner spacers 142 , gate spacers 114 , and / or STI regions 138 ) are illustrative and not restrictive.

[0058] Figure 2 1 is a flow chart of an exemplary method 200 for manufacturing a semiconductor device 100 according to some embodiments. For purposes of illustration, reference will be made to a method for manufacturing a semiconductor device 100. Figures 3A-14B The exemplary manufacturing process of the semiconductor device 100 is described as follows. Figure 2 The operation shown. Figures 3A-14B 2 is a cross-sectional view along lines AA and BB of semiconductor device 100 at various stages of fabrication according to some embodiments. The operations may be performed in a different order, or not performed at all, depending on the particular application. It should be noted that method 200 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 200, and only some of the other processes are briefly described here. Figures 3A-14B The elements in Figure 1A-Figure 1O The components in have the same annotations.

[0059] In operation 205, polysilicon structures and epitaxial fin regions are formed on the fin structures of the NFET and PFET. Figure 3A-3B As shown, polysilicon structure 312 may be formed on fin structures 1081-1082, and gate spacers 114 may be formed on sidewalls of polysilicon structure 312. During subsequent processing, polysilicon structure 312 may be replaced in a gate replacement process to form gate structures 112N1-112N3 and 112P1-112P3. After forming gate spacers 114, n-type and p-type epitaxial fin regions 110A-110B may be selectively formed on portions of fin structures 1081-1082 that are not under polysilicon structure 312. After forming epitaxial fin regions 110A-110B, ESL 116 and ILD 118 may be formed to form Figure 3A-3B structure.

[0060] refer to Figure 2 In operation 210, a gate opening is formed on and within one or more fin structures. Figure 4A-4B As shown, gate openings 412N-412P associated with NFETs 102N1-102N3 and PFETs 102P1-102P3, respectively, may be formed on and within fin structures 1081-1082. The formation of gate opening 412N may include the following sequential operations: (i) Figure 3A-3B and (ii) etching the polysilicon structure 312 from Figure 3A-3BIn some embodiments, the etching of nanostructure regions 122N-122P may include using a dry etching process or a wet etching process, which has a higher selectivity for the material of nanostructure regions 122N-122P (e.g., SiGe) than for the material of nanostructure regions 120N-120P (e.g., Si). In some embodiments, the wet etching process may include using a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM) and / or a mixture of ammonium hydroxide (NH4OH) with H2O2 and deionized (DI) water (APM). In some embodiments, the wet etching process may include using a mixture of (NH4OH) and HCl.

[0061] refer to Figure 2 In operations 215-230, a gate-all-around (GAA) structure is formed in the gate opening. For example, based on operations 215-230, gate structures 112N1-112N3 and 112P1-112P3 may surround nanostructure channel regions 120N-120P, as shown in FIG. Figures 5A-14B as described.

[0062] In operation 215, an interfacial oxide layer and a HK gate dielectric layer are deposited and annealed within the gate opening. Figure 5A-Figure 5B As shown, the gate openings 412N-412P (such as Figure 4A-4B An interfacial oxide layer 127 and a gate dielectric layer 128 are deposited and annealed on the nanostructured channel regions 120N-120P in the substrate. During subsequent processing, the HK gate dielectric layer 128 may form HK gate dielectric layers 128N1-128N3 and 128P1-138P3, as shown in FIG. Figure 1A-1E For clarity, Figure 5A-Figure 5B Shows Figure 4A-4B 100A-100B portion of the structure.

[0063] The interface oxide layer 127 may be formed on the exposed surfaces of the nanostructure channel regions 120N-120P within the gate openings 412N-412P, respectively. In some embodiments, the interface oxide layer 127 may be formed by exposing the nanostructure channel regions 120N-120P to an oxidizing environment. For example, the oxidizing environment may include a combination of ozone (O3) and a mixture of ammonium hydroxide, hydrogen peroxide, and water (SC1 solution) and / or a mixture of hydrochloric acid, hydrogen peroxide, and water (SC2 solution). As a result of the oxidation process, an oxide layer ranging from about 0.5 nm to about 1.5 nm may be formed on the exposed surfaces of the nanostructure channel regions 120N-120P.

[0064] The deposition of the HK gate dielectric layer 128 may include blanket depositing the HK gate dielectric layer 128 on a portion of the semiconductor device 100 (not shown) formed after the formation of the interfacial oxide layer 127. The blanket deposited HK gate dielectric layer 128 may be formed as follows: Figure 5A-Figure 5B As shown, the HK gate dielectric layer 128 is substantially conformally deposited on the interface oxide layer 127 and the exposed surface of the portion of the semiconductor device 100 (e.g., the sidewalls of the gate openings 412N-412P and the top surface of the ILD 118). In some embodiments, the HK gate dielectric layer 128 may include a dielectric material having a dielectric constant (k value) greater than about 3.9. In some embodiments, the HK gate dielectric layer 128 may include (i) a high-k dielectric material, such as hafnium oxide (HfO2), TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, and ZrSiO2; (ii) a high-k dielectric material having an oxide of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu; or (iii) a combination thereof. In some embodiments, the HK gate dielectric layer 128 may be formed by ALD using hafnium chloride (HfCl4) as a precursor at a temperature range of about 250° C. to about 350° C. In some embodiments, the gate dielectric layer 128 may have a thickness in a range of about 1 nm to about 3 nm to surround the nanostructure channel regions 120N-120P without being limited by the spacing between adjacent nanostructure channel regions 120N and between adjacent nanostructure channel regions 120P.

[0065] refer to Figure 2 In operation 220, a first barrier metal layer is formed on the HK gate dielectric layer. For example, Figures 6A-10B 1 shows the formation of the first barrier metal layer 129a-129c in one embodiment, Figure 11A-11B The formation of the first barrier metal layers 129a-129c in another embodiment is shown. During subsequent processing, the first barrier metal layers 129a-129c may form first barrier metal layers 129N1-129N3 and 129P1-129P3.

[0066] refer to Figures 6A-10B The formation of the first barrier metal layers 129a-129c may include the following sequential operations: (i) Figure 5A-Figure 5B A metal nitride layer 129a* is deposited on the structure of Figure 6A-6B (ii) patterning the metal nitride layer 129a* to selectively form a first barrier metal layer 129a on the NFET 102N3 and the PFET 102P3, such as Figure 7A-7B as shown; (iii) in Figure 7A-7BA metal nitride layer 129b* is deposited on the structure of Figure 8A-B (iv) patterning the metal nitride layer 129b* to selectively form a first barrier metal layer 129b on the NFETs 102N2-102N3 and the PFETs 102P2-102P3, such as Figure 9A-9B as shown; and (v) Figure 9A-9B The structure shown is covered with a first barrier metal layer 129c ( Figure 10A-10B ) of the metal nitride layer.

[0067] Operations (i)-(v) may be repeated to form additional first barrier metal layers similar to the first barrier metal layers 129a-129c in the NFETs 102N1-102N3 and the PFETs 102P1-102P3. In subsequent processing, (i) the portions of the first barrier metal layer 129c within the gate openings 412N-412P of NFET 102N1 and PFET 102P1 can form first barrier metal layers 129N1 and 129P1, respectively; (ii) the portions of the first barrier metal layer 129b-129c within the gate openings 412N-412P of NFET 102N2 and PFET 102P2 can form first barrier metal layers 129N2 and 129P2, respectively; and (iii) the portions of the first barrier metal layer 129a-129c within the gate openings 412N-412P of NFET 102N2 and PFET 102P2 can form first barrier metal layers 129N2 and 129P2, respectively. Therefore, through multiple deposition and patterning operations, by selectively forming different numbers of stacked layers in the NFETs 102N1-102N3 and the PFETs 102P1-102P3, different thicknesses T1-T6 ( Figure 1B-Figure 1C ).

[0068] The blanket deposition of the metal nitride layer 129a* may include blanket depositing a metal nitride layer of about 0.1 nm to about 0.5 nm thick using an ALD process or a CVD process using titanium tetrachloride (TiCl4) and NH3 as precursors at a temperature ranging from about 400°C to about 450°C and a pressure ranging from about 2 Torr to about 10 Torr. In some embodiments, the metal nitride layer 129a* may be deposited using an ALD process for about 20 cycles to about 30 cycles, wherein one cycle may include the following sequential cycles: (i) a first precursor gas (e.g., TiCl4) gas flow; (ii) a first gas purge process; (iii) a second precursor gas (e.g., NH3) gas flow; and (iv) a second gas purge process. The blanket deposited metal nitride layer 129a* may be substantially conformally deposited (e.g., with a step coverage of about 99%) at Figure 5A-Figure 5B The blanket deposition of metal nitride layers 129b*-129c* may be similar to the blanket deposition of metal nitride layer 129a*. In some embodiments, the material of metal nitride layers 129a*-129c* may include Ti-based or Ta-based nitrides or alloys, and may be similar to or different from each other.

[0069] Patterning the metal nitride layers 129a*-129c* to form the first barrier metal layers 129a-129c may include photolithography and etching processes. The etching process may include a wet etching process using an etchant including a mixture of ammonium hydroxide, hydrogen peroxide, and water (SC1 solution), and / or a mixture of hydrochloric acid, hydrogen peroxide, and water (SC2 solution).

[0070] As an alternative to a different number of stacked layers, the different thicknesses T1-T6 ( Figure 1B-1C ) can be achieved by selectively forming first barrier metal layers 129a-129c of different thicknesses in NFETs 102N1-102N3 and PFETs 102P1-102P3, as shown in FIG. Figure 11A-11B The selective formation of the first barrier metal layer 129a-129c may include the following sequential operations: (i) Figure 5A-Figure 5B (ii) patterning the metal nitride layer with a thickness of T1 to selectively form a first barrier metal layer 129a on the NFET 102N1 and the PFET 102P1, as shown in FIG. Figure 11A-11B(iii) depositing a metal nitride layer (not shown) having a thickness of T2 on the structure formed after forming the first barrier metal layer 129a; (iv) patterning the metal nitride layer having a thickness of T2 to selectively form a first barrier metal layer 129b on the NFET 102N2 and the PFET 102P2, as shown in FIG. Figure 11A-11B (v) depositing a metal nitride layer (not shown) having a thickness of T3 on the structure formed after forming the first barrier metal layer 129b; and (vi) patterning the metal nitride layer having a thickness of T3 to selectively form a first barrier metal layer 129c on the NFET 102N3 and the PFET 102P3, as shown in FIG. Figure 11A-11B Although the first barrier metal layer 129c is described as being formed after the first barrier metal layer 129b, and the first barrier metal layer 129b is described as being formed after the first barrier metal layer 129a, the first barrier metal layers 129a-129c may be formed in any order.

[0071] Figure 11A-11B The blanket deposition and patterning of the metal nitride layer for the first barrier metal layers 129a-129c may be similar to the blanket deposition and patterning process of the metal nitride layer 129a*.

[0072] refer to Figure 2 In operation 225, n-type and p-type WFM oxide layers are selectively formed on the first barrier metal layer of the NFET and the PFET. Figures 12A-13B As shown, the nWFM oxide layer 132N may be selectively formed on Fig. 10A The pWFM oxide layer 132P can be selectively formed on the Fig. 10B Similarly, the nWFM oxide layer 132N may be selectively formed on Fig.11A The pWFM oxide layer 132P can be selectively formed on the Fig. 11B During subsequent processing, the nWFM oxide layer 132N may form nWFM oxide layers 132N1-132N3, and the pWFM oxide layer 132P may form pWFM oxide layers 132P1-132P3.

[0073] refer to Figures 12A-13B The selective formation of the nWFM oxide layer 132N and the pWFM oxide layer 132P may include the following sequential operations: (i) Figure 10A-10B(ii) patterning the metal oxide layer to selectively form the nWFM oxide layer 132N on the NFETs 102N1-102N3, as shown in FIG. Fig. 12A as shown; (iii) in Figure 12A-12B (iv) patterning the metal oxide layer to selectively form the pWFM oxide layer 132P on the PFETs 102P1-102P3, such as Fig. 13B shown.

[0074] In some embodiments, the metal oxide layer for the nWFM oxide layer 132N may include (i) REM oxides, such as La2O3, CeO2, Yb2O3, Lu2O3, and Er2O3; (ii) oxides of metals of Group IIA (e.g., MgO or SrO), Group IIIB (e.g., Y2O3), Group IVB (e.g., HfO2 or ZrO2), or Group VB (e.g., Ta2O5) of the periodic table; (iii) SiO2; or (iv) a combination thereof. In some embodiments, the metal oxide layer for the pWFM oxide layer 132P may include (i) Al-based metal oxides, such as Al2O3 and Al2TiO5; (ii) oxides of metals of Group VB (e.g., NbO), Group IIIA (e.g., B2O3), or Group VA (e.g., P2O5) of the periodic table; or (iii) a combination thereof.

[0075] The blanket deposition of the metal oxide layer for the nWFM oxide layer 132N may include blanket depositing a metal oxide layer of about 0.01 nm to about 2 nm thick using an ALD process or a CVD process using trilanthana (formamido) (La(FAMD)3) or lanthanum tetramethylpimelate (La(thd)3) ​​and O3 as precursors at a temperature in the range of about 250°C to 350°C. In some embodiments, the metal oxide layer for the nWFM oxide layer 132N may be deposited using an ALD process for about 20 cycles to about 30 cycles, wherein one cycle may include the following sequential cycles: (i) a first precursor gas (e.g., La(FAMD)3 or La(thd)3) ​​gas flow; (ii) a first gas purge process; (iii) a second precursor gas (e.g., O3) gas flow; and (iv) a second gas purge process. The blanket deposited metal oxide layer may be substantially conformally deposited (e.g., about 99% step coverage) at a step depth of about 100 nm. Figure 10A-10B in terms of structure.

[0076] Patterning of the blanket deposited metal oxide layer for nWFM oxide layer 132N may include (i) selectively forming a mask layer (e.g., a photoresist layer or a nitride layer; not shown) on portions of the blanket deposited metal oxide on NFETs 102N1-102N3; (ii) selectively removing portions of the blanket deposited metal oxide layer on PFETs 102P1-102P3 to form Figure 12A-12B and (iii) removing the mask layer. The selective removal may include acid-based (eg, HCl-based) wet or dry etching.

[0077] During the blanket deposition of the metal oxide layer for the nWFM oxide layer 132N, the top surface of the first barrier metal layer 129c may be oxidized to form barrier metal oxide layers 130N-130P, such as Figure 12A-12B As shown. The blocking metal oxide layers 130N-130P may have similar thicknesses. The blocking metal oxide layer 130N may form the blocking metal oxide layers 130N1-130N3 in subsequent processing. In some embodiments, the blocking metal oxide layer 130P may be etched during the selective removal of portions of the overlying deposited metal oxide layer on the PFETs 102P1-102P3, and in some embodiments, the blocking metal oxide layer 130P may remain unetched.

[0078] The blanket deposition of the metal oxide layer for the pWFM oxide layer 132P may include blanket depositing a metal oxide layer of about 0.01 nm to about 2 nm thick using an ALD process or a CVD process using trimethylaluminum (TMA) and H2O as precursors at a temperature in the range of about 250°C to about 350°C. In some embodiments, the metal oxide layer for the pWFM oxide layer 132P may be deposited using an ALD process for about 20 cycles to about 30 cycles, wherein one cycle may include the sequential cycles of: (i) a first precursor gas (e.g., TMA) gas flow; (ii) a first gas purge process; (iii) a second precursor gas (e.g., H2O) gas flow; and (iv) a second gas purge process. The blanket deposited metal oxide layer may be substantially conformally deposited (e.g., about 99% step coverage) at Figure 12A-12B in terms of structure.

[0079] Patterning of the blanket deposited metal oxide layer for the pWFM oxide layer 132P may include: (i) selectively forming a mask layer (e.g., a photoresist layer or a nitride layer; not shown) on portions of the blanket deposited metal oxide on the PFETs 102P1-102P3; (ii) selectively removing portions of the blanket deposited metal oxide layer on the NFETs 102N1-102N3 to form Figure 13A-13Band (iii) removing the mask layer. The selective removal may include acid-based (eg, HF-based) wet or dry etching.

[0080] During the blanket deposition of the metal oxide layer for the pWFM oxide layer 132P, the first barrier metal layer 129c on the PFETs 102P1-102P3 may be further oxidized to form a barrier metal oxide layer 130P* ( Fig. 13B ), which is thicker than the blocking metal oxide layer 130P.

[0081] After forming the pWFM oxide layer 132P, Figure 13A-13B The drive-in annealing process is performed on the structure of FIG. The drive-in annealing process increases the concentration of metal ions (e.g., La ions and / or Al ions) at the interface between the nWFM oxide layer 132N and the barrier metal oxide layer 130N and at the interface between the pWFM oxide layer 132P and the barrier metal oxide layer 130P. The increase in the metal ion concentration can increase the dipole layer 131N-131P ( Figure 13A-13B ) The above discussion of dipole layers 131N1-131N3 applies to dipole layer 131N. The above discussion of dipole layers 131P1-131P3 applies to dipole layer 131P.

[0082] The drive-in annealing process may include annealing the nWFM oxide layer 132N and the pWFM oxide layer 132P at a temperature of about 550° C. to about 850° C. and a pressure of about 1 Torr to about 30 Torr for a time period in a range of about 0.1 seconds to about 30 seconds. In some embodiments, the drive-in annealing process may include two annealing processes: (i) a soak annealing process at a temperature of about 550° C. to about 850° C. for a time period in a range of about 2 seconds to about 60 seconds; and (ii) a spike annealing process at a temperature of about 700° C. to about 900° C. for a time period in a range of about 0.1 seconds to about 2 seconds.

[0083] refer to Figure 2 In operation 230, a second barrier metal layer, a FFW layer, and a gate metal filling layer are formed on the n-type and p-type WFM oxide layers. Figure 14A-14B As shown, the second barrier metal layer 133, the FFW layer 134, and the gate metal filling layer 135 may be formed on Figure 13A-13B The material used for the second barrier metal layer 133 may be deposited over the Figure 13A-13BThe material FFW layer 134 may be blanket deposited on the material for the second barrier metal layer 133. The material for the gate metal fill layer 135 may be blanket deposited on the material for the FFW layer 134. After these blanket depositions, the HK gate dielectric layer 128, the first barrier metal layers 129a-129c, the barrier metal oxide layers 130N-130P, the nWFM oxide layer 132N, the pWFM oxide layer 132P, the material for the second barrier metal layer 133, the material for the FFW layer 134, and the material for the gate metal fill layer 135 may be polished by a chemical mechanical polishing process to form Figure 14A-14B Therefore, as described in operations 215-230, gate structures 112N1-112N3 and 112P1-112P3 may be formed on the same substrate 106 with at least three different threshold voltages.

[0084] The present invention provides exemplary FET gate structures with different EWF values ​​to form FETs (e.g., GAA FETs and / or finFETs) with different threshold voltages, and provides exemplary methods for forming such FETs on the same substrate. The exemplary method forms NFETs (e.g., NFETs 102N1-102N3) and PFETs (e.g., PFETs 102P1-102P3) with different gate structure configurations (e.g., gate structures 112N1-112N3 and 112P1-112P3) but with similar WFM layer thicknesses selectively formed on the same substrate (e.g., substrate 106) to achieve different threshold voltages (e.g., threshold voltages V1-V6) from each other. Different gate structure configurations may have barrier metal layers (e.g., barrier metal layers 129N1-129N3 and 129P1-129P3) of different thicknesses disposed between the WFM layer and the high-K gate dielectric layer (e.g., HK gate dielectric layers 128N1-128N3 and 128P1-128P3). In addition, the WFM layer may include a WFM oxide layer (e.g., WFM oxide layers 132N1-132N3 and 132P1-132P3) that induces a dipole layer (e.g., dipole layers 131N1-131N3 and 131P1-131P3) at the interface between the WFM layer and the barrier metal layer. Different barrier metal layer thicknesses (e.g., thicknesses T1-T6) provide different spacings (e.g., spacings S1-S6) between the WFM layer and the high-K gate dielectric layer, and provide different spacings (e.g., spacings S7-S12) between the induced dipole layer and the high-K gate dielectric layer. These different pitches enable the FET gate structures to have different EWF values ​​(e.g., EWF values ​​E1-E6) from each other, and thus have different threshold voltages from each other. Therefore, adjusting the thickness of the barrier metal layer can adjust the EWF value of the NFET and PFET gate structures, and thus adjust the threshold voltage of the NFET and PFET without changing the thickness of their WFM layers.

[0085] In some embodiments, the semiconductor device includes: a substrate; a first epitaxial source / drain (S / D) region and a second epitaxial source / drain region, disposed on the substrate; a first nanostructure channel region and a second nanostructure channel region, respectively disposed between the epitaxial source / drain region of the first epitaxial source / drain region and between the epitaxial source / drain region of the second epitaxial source / drain region; and a first gate structure and a second gate structure, having different effective work function values ​​from each other. The first gate structure and the second gate structure include: a first high-K gate dielectric layer and a second high-K gate dielectric layer, which surround the first nanostructure channel region and the second nanostructure channel region respectively; a first barrier metal layer and a second barrier metal layer, which have different thicknesses from each other and are respectively arranged on the first high-K gate dielectric layer and the second high-K gate dielectric layer; a first work function metal (WFM) oxide layer and a second work function metal oxide layer, which have substantially equal thicknesses from each other and are respectively arranged on the first barrier metal layer and the second barrier metal layer; a first dipole layer, which is arranged between the first work function metal oxide layer and the first barrier metal layer; and a second dipole layer, which is arranged between the second work function metal oxide layer and the second barrier metal layer.

[0086] In the above-mentioned semiconductor device, the first barrier metal layer and the second barrier metal layer respectively have a first stacked layer and a second stacked layer; wherein each layer of the first stacked layer and the second stacked layer has a thickness substantially equal to each other; and wherein the second stacked layer has more layers than the first stacked layer.

[0087] In the above-mentioned semiconductor device, the first gate structure and the second gate structure also include: a first blocking metal oxide layer and a second blocking metal oxide layer, which are respectively arranged on the first blocking metal layer and the second blocking metal layer; and wherein the first blocking metal oxide layer and the second blocking metal oxide layer respectively include oxides of metals in the first blocking metal layer and the second blocking metal layer.

[0088] In the above semiconductor device, the metal concentration distribution at each of the first work function metal oxide layer and the first barrier metal oxide layer has a peak concentration at the interface between the first work function metal oxide layer and the first barrier metal oxide layer.

[0089] In the above semiconductor device, the nitrogen concentration distribution at each of the first barrier metal layer and the first barrier metal oxide layer has a peak concentration at the interface between the first barrier metal layer and the first barrier metal oxide layer.

[0090] In the above semiconductor device, each of the first work function metal oxide layer and the second work function metal oxide layer includes an oxide of a rare earth metal, or an oxide of a Group IIA metal, a Group IIIB metal, or a Group IVB metal of the periodic table.

[0091] In the above semiconductor device, each of the first work function metal oxide layer and the second work function metal oxide layer includes an oxide of an aluminum-based metal, or an oxide of a IIIA group metal, a VA group metal, or a VB group metal of the periodic table.

[0092] In the above semiconductor device, the first dipole layer and the second dipole layer include metal ions of rare earth metals, or metal ions of Group IIA metals, Group IIIB metals, or Group IVB metals of the periodic table.

[0093] In the above semiconductor device, the first dipole layer and the second dipole layer include metal ions of aluminum-based metals, or metal ions of Group IIIA metals, Group VA metals, or Group VB metals of the periodic table.

[0094] In the above-mentioned semiconductor device, the first gate structure and the second gate structure also include: a third barrier metal layer and a fourth barrier metal layer, which are respectively arranged on the first work function metal oxide layer and the second work function metal oxide layer; and wherein the first barrier metal layer, the second barrier metal layer, the third barrier metal layer, and the fourth barrier metal layer have the same metal material.

[0095] In some embodiments, a semiconductor device includes: a substrate; a first pair of epitaxial source / drain (S / D) regions and a second pair of epitaxial source / drain regions, disposed on the substrate; a first fin region and a second fin region, disposed between the epitaxial source / drain regions of the first pair of epitaxial source / drain regions and between the epitaxial source / drain regions of the second pair of epitaxial source / drain regions, respectively. The semiconductor device also includes: a first gate structure and a second gate structure, including: a first high-K gate dielectric layer and a second high-K gate dielectric layer, disposed on the first fin region and the second fin region, respectively; a first barrier metal layer and a second barrier metal layer, having different thicknesses from each other, disposed on the first high-K gate dielectric layer and the second high-K gate dielectric layer, respectively; a first barrier metal oxide layer and a second barrier metal oxide layer, disposed on the first barrier metal layer and the second barrier metal layer, respectively; an aluminum (Al)-free rare earth metal-based (REM-based) work function metal (WFM) oxide layer, disposed on the first barrier metal oxide layer; and an Al-based work function metal oxide layer, disposed on the second barrier metal oxide layer.

[0096] In the above semiconductor device, the lanthanum (La) concentration distribution at each of the aluminum-free rare earth metal-based work function metal oxide layer and the first barrier metal oxide layer has a peak lanthanum concentration at the interface between the aluminum-free rare earth metal-based work function metal oxide layer and the first barrier metal oxide layer.

[0097] In the above semiconductor device, the aluminum concentration distribution at each of the aluminum-based work function metal oxide layer and the second barrier metal oxide layer has a peak aluminum concentration at the interface between the aluminum-based work function metal oxide layer and the second barrier metal oxide layer.

[0098] In the above semiconductor device, the aluminum-free rare earth metal-based work function metal oxide layer includes lanthanum oxide.

[0099] In the above semiconductor device, the aluminum-based work function metal oxide layer includes aluminum oxide.

[0100] In the above-mentioned semiconductor device, the first gate structure and the second gate structure also include: a rare earth metal-based dipole layer, arranged between the aluminum-free rare earth metal-based work function metal oxide layer and the first barrier metal oxide layer; and an aluminum-based dipole layer, arranged between the aluminum-based work function metal oxide layer and the second barrier metal oxide layer.

[0101] In some embodiments, a method includes: forming a first nanostructure channel region and a second nanostructure channel region in a fin structure on a substrate; forming a first high-K gate dielectric layer and a second high-K gate dielectric layer surrounding the first nanostructure channel region and the second nanostructure channel region, respectively; forming a first barrier metal layer and a second barrier metal layer of different thicknesses on the first high-K gate dielectric layer and the second high-K gate dielectric layer; forming a first work function metal (WFM) oxide layer and a second work function metal oxide layer of substantially equal thicknesses on the first barrier metal layer and the second barrier metal layer, respectively; performing a drive-in annealing process on the first work function metal oxide layer and the second work function metal oxide layer; forming a third barrier metal layer and a fourth barrier metal layer of substantially equal thicknesses on the first work function metal oxide layer and the second work function metal oxide layer; and forming a first gate metal filling layer and a second gate metal filling layer on the third barrier metal layer and the fourth barrier metal layer, respectively.

[0102] In the above method, forming the first barrier metal layer and the second barrier metal layer includes: selectively forming a first number of nitride layers on the first high-K gate dielectric layer; and selectively forming a second number of nitride layers on the second high-K gate dielectric layer, wherein the first number is greater than the second number.

[0103] In the above method, forming the first barrier metal layer and the second barrier metal layer includes: depositing a first nitride layer on the first high-K gate dielectric layer and the second high-K gate dielectric layer; etching a first portion of the first nitride layer located on the second high-K gate dielectric layer; and depositing a second nitride layer on the second high-K gate dielectric layer and on a second portion of the first nitride layer located on the first high-K gate dielectric layer.

[0104] In the above method, implementing the push-in annealing process includes: performing soak annealing on the first work function metal oxide layer and the second work function metal oxide layer at a first temperature between about 550°C and about 800°C; and performing spike annealing on the first work function metal oxide layer and the second work function metal oxide layer at a second temperature between about 700°C and about 900°C.

[0105] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: substrate; A first pair of epitaxial source / drain (S / D) regions and a second pair of epitaxial source / drain regions are disposed on the substrate; A first nanostructure channel region and a second nanostructure channel region are respectively arranged between the epitaxial source / drain regions of the first epitaxial source / drain region and between the epitaxial source / drain regions of the second epitaxial source / drain region; as well as The first gate structure and the second gate structure have different effective work function values; wherein the first gate structure and the second gate structure include: A first high-K gate dielectric layer and a second high-K gate dielectric layer surround the first nanostructure channel region and the second nanostructure channel region, respectively; A first barrier metal layer and a second barrier metal layer, having different thicknesses from each other, are disposed on the first high-K gate dielectric layer and the second high-K gate dielectric layer, respectively; A first work function metal (WFM) oxide layer and a second work function metal oxide layer having substantially equal thicknesses to each other, disposed on the first barrier metal layer and the second barrier metal layer, respectively; a first dipole layer disposed between the first work function metal oxide layer and the first barrier metal layer; and a second dipole layer, disposed between the second work function metal oxide layer and the second barrier metal layer; In which, the first gate structure also includes a first blocking metal oxide layer, which is arranged on the first blocking metal layer, and the first blocking metal oxide layer includes an oxide of the metal in the first blocking metal layer, wherein the metal concentration distribution at each of the first work function metal oxide layer and the first blocking metal oxide layer has a peak concentration at the interface between the first work function metal oxide layer and the first blocking metal oxide layer.

2. The semiconductor device according to claim 1, wherein The first barrier metal layer and the second barrier metal layer have a first stacked layer and a second stacked layer, respectively; wherein each layer of the first stacked layer and the second stacked layer has a thickness substantially equal to each other; and Compared with the first stacked layer, the second stacked layer has more layers.

3. The semiconductor device according to claim 1, wherein The second gate structure further includes: a second barrier metal oxide layer disposed on the second barrier metal layer; and wherein The second barrier metal oxide layer includes an oxide of the metal in the second barrier metal layer.

4. The semiconductor device according to claim 3, wherein: The first barrier metal layer includes metal nitride.

5. The semiconductor device according to claim 1, wherein A nitrogen concentration profile at each of the first barrier metal layer and the first barrier metal oxide layer has a peak concentration at an interface between the first barrier metal layer and the first barrier metal oxide layer.

6. The semiconductor device according to claim 1, wherein Each of the first work function metal oxide layer and the second work function metal oxide layer includes an oxide of a Group IIA metal, a Group IIIB metal, or a Group IVB metal of the periodic table.

7. The semiconductor device according to claim 1, wherein Each of the first work function metal oxide layer and the second work function metal oxide layer includes an oxide of a Group IIIA metal, a Group VA metal, or a Group VB metal of the periodic table.

8. The semiconductor device according to claim 1, wherein The first dipole layer and the second dipole layer include metal ions of Group IIA metals, Group IIIB metals, or Group IVB metals of the periodic table.

9. The semiconductor device according to claim 1, wherein: The first dipole layer and the second dipole layer include metal ions of Group IIIA metals, Group VA metals, or Group VB metals of the periodic table.

10. The semiconductor device according to claim 1, wherein Each of the first work function metal oxide layer and the second work function metal oxide layer includes an oxide of a rare earth metal.

11. The semiconductor device according to claim 1, wherein Each of the first work function metal oxide layer and the second work function metal oxide layer includes an oxide of an aluminum-based metal.

12. The semiconductor device according to claim 1, wherein The first dipole layer and the second dipole layer include metal ions of a rare earth metal.

13. The semiconductor device according to claim 1, wherein: The first dipole layer and the second dipole layer include metal ions of an aluminum-based metal.

14. The semiconductor device according to claim 1, wherein The first gate structure and the second gate structure further include: a third barrier metal layer and a fourth barrier metal layer, which are respectively disposed on the first work function metal oxide layer and the second work function metal oxide layer; and The first barrier metal layer, the second barrier metal layer, the third barrier metal layer, and the fourth barrier metal layer have the same metal material.

15. A semiconductor device comprising: substrate; A first pair of epitaxial source / drain (S / D) regions and a second pair of epitaxial source / drain regions are disposed on the substrate; A first fin region and a second fin region, respectively disposed between the epitaxial source / drain regions of the first epitaxial source / drain region and between the epitaxial source / drain regions of the second epitaxial source / drain region; as well as The first gate structure and the second gate structure include: A first high-K gate dielectric layer and a second high-K gate dielectric layer are disposed on the first fin region and the second fin region, respectively; A first barrier metal layer and a second barrier metal layer, having different thicknesses from each other, are disposed on the first high-K gate dielectric layer and the second high-K gate dielectric layer, respectively; A first barrier metal oxide layer and a second barrier metal oxide layer are disposed on the first barrier metal layer and the second barrier metal layer, respectively; an aluminum (Al)-free rare earth metal-based (REM-based) work function metal (WFM) oxide layer disposed on the first barrier metal oxide layer; and an aluminum-based work function metal oxide layer, disposed on the second barrier metal oxide layer; The metal concentration distribution at each of the aluminum-free rare earth metal-based work function metal oxide layer and the first barrier metal oxide layer has a peak concentration at the interface between the aluminum-free rare earth metal-based work function metal oxide layer and the first barrier metal oxide layer.

16. The semiconductor device according to claim 15, wherein: The lanthanum (La) concentration profile at each of the aluminum-free rare earth metal-based work function metal oxide layer and the first barrier metal oxide layer has a peak lanthanum concentration at an interface between the aluminum-free rare earth metal-based work function metal oxide layer and the first barrier metal oxide layer.

17. The semiconductor device according to claim 15, wherein: The aluminum concentration distribution at each of the aluminum-based work function metal oxide layer and the second barrier metal oxide layer has a peak aluminum concentration at an interface between the aluminum-based work function metal oxide layer and the second barrier metal oxide layer.

18. The semiconductor device according to claim 15, wherein: The aluminum-free rare earth metal-based work function metal oxide layer includes lanthanum oxide.

19. The semiconductor device according to claim 15, wherein: The aluminum-based work function metal oxide layer includes aluminum oxide.

20. The semiconductor device according to claim 15, wherein The first gate structure and the second gate structure further include: a rare earth metal-based dipole layer disposed between the aluminum-free rare earth metal-based work function metal oxide layer and the first barrier metal oxide layer; and The aluminum-based dipole layer is disposed between the aluminum-based work function metal oxide layer and the second barrier metal oxide layer.

21. A method for manufacturing a semiconductor device, comprising: forming a first nanostructure channel region and a second nanostructure channel region in the fin structure on the substrate; forming a first high-K gate dielectric layer and a second high-K gate dielectric layer surrounding the first nanostructure channel region and the second nanostructure channel region respectively; forming a first barrier metal layer and a second barrier metal layer having different thicknesses on the first high-K gate dielectric layer and the second high-K gate dielectric layer; forming a first work function metal (WFM) oxide layer and a second work function metal oxide layer having substantially equal thicknesses on the first barrier metal layer and the second barrier metal layer, respectively; performing a drive-in annealing process on the first work function metal oxide layer and the second work function metal oxide layer; forming a third barrier metal layer and a fourth barrier metal layer having substantially equal thicknesses on the first work function metal oxide layer and the second work function metal oxide layer; as well as forming a first gate metal filling layer and a second gate metal filling layer on the third barrier metal layer and the fourth barrier metal layer respectively; A first barrier metal oxide layer is disposed on the first barrier metal layer, and the metal concentration distribution at each of the first work function metal oxide layer and the first barrier metal oxide layer has a peak concentration at the interface between the first work function metal oxide layer and the first barrier metal oxide layer.

22. The method according to claim 21, wherein: Forming the first barrier metal layer and the second barrier metal layer includes: selectively forming a first number of nitride layers on the first high-K gate dielectric layer; and A second number of nitride layers is selectively formed on the second high-K gate dielectric layer, wherein the first number is greater than the second number.

23. The method according to claim 21, wherein: Forming the first barrier metal layer and the second barrier metal layer includes: depositing a first nitride layer on the first high-K gate dielectric layer and the second high-K gate dielectric layer; etching a first portion of the first nitride layer located on the second high-K gate dielectric layer; and A second nitride layer is deposited on the second high-K gate dielectric layer and on a second portion of the first nitride layer that is located on the first high-K gate dielectric layer.

24. The method according to claim 21, wherein: The implementation of the push-on annealing process comprises: performing soaking annealing on the first work function metal oxide layer and the second work function metal oxide layer at a first temperature between 550° C. and 800° C.; and The first work function metal oxide layer and the second work function metal oxide layer are spike annealed at a second temperature between 700° C. and 900° C.

25. The method according to claim 21, wherein: The implementation of the push-on annealing process comprises: Performing soak annealing on the first work function metal oxide layer and the second work function metal oxide layer at a first temperature between 522.5° C. and 840° C.; and The first work function metal oxide layer and the second work function metal oxide layer are spike annealed at a second temperature between 665°C and 945°C.

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