Semiconductor device structure and method for forming the same

Abstract

A semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a plurality of semiconductor nanostructures located above a substrate and two epitaxial structures located above the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack surrounding the semiconductor nanostructures. The semiconductor device structure also includes a dielectric stress structure located between the gate stack and the substrate, and the epitaxial structure extends beyond a top surface of the dielectric stress structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor technology, and more particularly to semiconductor device structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation.

[0003] Throughout the history of integrated circuit development, functional density (i.e., the number of interconnected devices per chip area) has increased while geometry size (i.e., the smallest component or circuit created during the manufacturing process) has decreased. This process of device miniaturization generally has the benefit of increasing production efficiency and reducing associated costs.

[0004] However, these advances have also increased the complexity of processing and manufacturing integrated circuits. As feature sizes continue to shrink, the manufacturing process continues to become more difficult to perform. As a result, it is challenging to form reliable semiconductor devices of increasingly smaller sizes. Summary of the invention

[0005] In some embodiments, a semiconductor device structure is provided, which includes a plurality of semiconductor nanostructures located above a substrate; two epitaxial structures located above the substrate, wherein each of the plurality of semiconductor nanostructures is between the two epitaxial structures, and the two epitaxial structures are p-type doped; a gate stack surrounding the plurality of semiconductor nanostructures; and a dielectric stress structure located between the gate stack and the substrate, wherein the two epitaxial structures extend beyond a top surface of the dielectric stress structure.

[0006] In some other embodiments, a semiconductor device structure is provided, which includes a semiconductor fin located above a substrate; a plurality of channel structures suspended above the semiconductor fin; a gate stack surrounding each of the plurality of channel structures; an epitaxial structure adjacent to the plurality of channel structures; and a dielectric stress structure located between the semiconductor fin and the gate stack, wherein the dielectric stress structure extends beyond both side edges of the gate stack.

[0007] In some other embodiments, a method for forming a semiconductor device structure is provided, which includes forming a sacrificial base layer above a semiconductor base; forming a semiconductor stack above the sacrificial base layer, wherein the semiconductor stack has multiple sacrificial layers and multiple semiconductor layers stacked alternately; patterning the semiconductor stack and the sacrificial base layer to form a fin structure; forming a dummy gate stack to surround a portion of the fin structure; replacing the sacrificial base layer with a dielectric stress structure; removing the dummy gate stack and the multiple sacrificial layers to release multiple semiconductor nanostructures, the multiple semiconductor nanostructures being composed of the remaining portions of the multiple semiconductor layers; and forming a metal gate stack to surround each of the multiple semiconductor nanostructures. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The embodiments of the present invention can be better understood according to the following detailed description and in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features shown in the drawings are not necessarily drawn to scale. In fact, the sizes of various features may be arbitrarily enlarged or reduced to make the description clear.

[0009] Figure 1A-1B 1 is a top view of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0010] Figure 2A-2K Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0011] Figure 3A-Figure 3O Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0012] Figure 4A-4F Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0013] Figure 5A-5C Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0014] Figure 6A-6B Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0015] Figure 7A-7B Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0016] Description of reference numerals:

[0017] 100: Semiconductor substrate

[0018] 101A, 101B: Semiconductor fins

[0019] 102a, 102b, 102c, 102d, 104a, 104b, 104c, 104d: semiconductor layer

[0020] 104b', 104c', 104d': semiconductor nanostructures

[0021] 105a, 105b, 105c, 105d: edge elements

[0022] 105a': Oxidized edge element

[0023] 106A, 106B: Fin structure

[0024] 108: First mask layer

[0025] 110: Second mask layer

[0026] 112, 142: Groove

[0027] 114: Isolation Structure

[0028] 116: Dummy gate dielectric layer

[0029] 118: Dummy gate electrode

[0030] 120A, 120B: dummy gate stack

[0031] 122, 124: Mask layer

[0032] 126, 128, 134: Spacer layer

[0033] 126', 128': Spacer elements

[0034] 136: Internal spacer

[0035] 137: Isolation element

[0036] 138: Epitaxial structure

[0037] 139: Contact Etch Stop Layer

[0038] 140: Dielectric layer

[0039] 144, 130, 132, 302: Notch

[0040] 148: Oxidation element

[0041] 150: Gate dielectric layer

[0042] 152: Work function layer

[0043] 154: Conductive filler

[0044] 156A, 156B: Metal gate stack

[0045] 304: Dielectric stress structure

[0046] 306: Annealed Dielectric Stress Structure

[0047] 702, 702': Seams

[0048] T1, T2: thickness DETAILED DESCRIPTION

[0049] It should be understood that the following disclosure provides many different embodiments or examples to implement different components of the subject provided. The following describes specific examples of each component and its arrangement in order to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the present invention. For example, the following disclosure describes forming a first component on or above a second component, which means that it includes an embodiment in which the formed first component and the second component are in direct contact, and also includes an embodiment in which an additional component can be formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, different examples in the disclosure may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplicity and clarity, and are not used to limit the relationship between the various embodiments and / or the described appearance structures.

[0050] Furthermore, in order to facilitate the description of the relationship between an element or component and another (multiple) element or (multiple) component in the drawings, spatially related terms such as "under...", "below", "lower", "above", "upper" and similar terms may be used. In addition to the orientations shown in the drawings, spatially related terms also cover different orientations of the device in use or operation. For example, if the device in the figure is turned over, elements described as being "under" or "below" other elements or components will be positioned "above" other elements or components. Therefore, the exemplary term "below" can cover both above and below orientations. The device may also be positioned otherwise (e.g., rotated 90 degrees or located in other orientations), and the description of the spatially related terms used may be interpreted accordingly.

[0051] A person of ordinary skill in the art to which the present invention belongs will understand the term "substantially" in the specification, such as "substantially flat" or "substantially coplanar", etc. In some embodiments, the adjective "substantially" may be omitted. Where applicable, the term "substantially" may also include embodiments with "entirely", "completely", "all", etc. Where applicable, the term "substantially" may also mean 90% or higher, such as 95% or higher, in particular 99% or higher, including 100%. Furthermore, terms such as "substantially parallel" or "substantially perpendicular" are interpreted as not excluding minor deviations from a specific configuration, and may include, for example, deviations of up to 10°. The word "substantially" does not exclude "completely", for example, the composition "substantially free of" Y may be completely free of Y.

[0052] Terms such as "about" in combination with specific distances or dimensions are to be interpreted as not excluding minor deviations from the specific distances or dimensions and may include deviations of, for example, up to 10%. The term "about" used for a numerical value x may mean x ± 5% or 10%.

[0053] Embodiments of the present invention may relate to a Fin Field Effect Transistor (FinFET) structure having a fin. The fin may be patterned using any suitable method. For example, the fin may be patterned using one or more photolithography processes (including double patterning or multiple patterning processes). Generally speaking, a double patterning or multiple patterning process combines photolithography and self-alignment processes to create a pattern with a smaller pitch, for example, a pattern with a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. Then, the sacrificial layer is removed, and the remaining spacers may then be used to pattern the fin. However, the fin may be formed using one or more other applicable processes.

[0054] Embodiments of the present invention may relate to gate all around (GAA) transistor structures. The gate all around structures may be patterned using any suitable method. For example, these structures may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes to create patterns with smaller pitches, for example, patterns with smaller pitches than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the gate all around structure may then be patterned using the remaining spacers.

[0055] The specification describes some embodiments of the present invention. Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the stages described may be replaced or eliminated for different embodiments. Additional components may be added to the semiconductor device structure. Some of the components described below may be replaced or eliminated for different embodiments. Although some embodiments are described as operating in a particular order, these operations may also be performed in other logical orders.

[0056] Figure 2A-2K Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments. Figure 2A As shown, a semiconductor substrate 100 is received or provided. In some embodiments, the semiconductor substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. The semiconductor substrate 100 includes silicon or other elemental semiconductor materials, such as germanium. The semiconductor substrate 100 can be undoped or doped (e.g., p-type, n-type, or a combination thereof). In some embodiments, the semiconductor substrate 100 includes an epitaxially grown semiconductor layer on a dielectric layer. The epitaxially grown semiconductor layer can be made of silicon germanium, silicon, germanium, one or more other suitable materials, or a combination thereof.

[0057] In some other embodiments, the semiconductor substrate 100 includes a compound semiconductor. For example, the compound semiconductor includes one or more III-V compound semiconductors having a chemical formula of Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 The composition defined as follows, wherein X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions. Each of X1, X2, X3, Y1, Y2, Y3 and Y4 is greater than or equal to 0, and the sum is equal to 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or a combination of the foregoing. Other suitable substrates including Group II-VI compound semiconductors may also be used.

[0058] In some embodiments, the semiconductor substrate 100 is an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor-on-insulator substrate can be manufactured by using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, other applicable methods, or a combination of the foregoing. In some other embodiments, the semiconductor substrate 100 includes a multilayer structure. For example, the semiconductor substrate 100 includes a silicon germanium layer formed on a bulk silicon layer.

[0059] According to some embodiments, Figure 2A As shown, a semiconductor stack having a plurality of semiconductor layers is formed on a semiconductor substrate 100. In some embodiments, the semiconductor stack includes a plurality of semiconductor layers 102a, 102b, 102c, and 102d, and the semiconductor stack also includes a plurality of semiconductor layers 104a, 104b, 104c, and 104d. In some embodiments, as Figure 2A As shown, the semiconductor layers 102a-102d and the semiconductor layers 104a-104d are arranged alternately.

[0060] In some embodiments, semiconductor layer 102a is used as a sacrificial substrate layer and will be replaced by a dielectric stress material in a subsequent process. In some embodiments, semiconductor layer 104a is used as a protective layer to prevent semiconductor layer 102b thereon from being damaged during a subsequent manufacturing process. In some embodiments, semiconductor layer 104a is thinner than semiconductor layer 104b, 104c, or 104d. In some embodiments, semiconductor layers 102b-102d are used as sacrificial layers that will be removed in a subsequent process to release semiconductor layers 104b-104d. Semiconductor layers 104b-104d can be used as channel structures for one or more transistors.

[0061] like Figure 2A As shown, semiconductor layer 104a has a thickness T1, and semiconductor layer 104b has a thickness T2. In some embodiments, thickness T2 is greater than thickness T1. Thickness T1 may be in a range of about 2 nm to about 6 nm. For example, thickness T1 is about 4 nm. The ratio of thickness T1 to thickness T2 (T1 / T2) may be in a range of about 2 / 5 to about 2 / 3.

[0062] In some embodiments, each semiconductor layer 102a-102d and semiconductor layers 104b-104d have approximately the same thickness. In some embodiments, each semiconductor layer 104b-104d is thicker than each semiconductor layer 102a-102d. In some other embodiments, each semiconductor layer 102a-102d is thicker than each semiconductor layer 104b-104d.

[0063] In some embodiments, the semiconductor layers 102a-102d and the semiconductor layers 104a-104d are made of different materials. In some embodiments, the semiconductor layers 102a-102d are made of or include silicon germanium or germanium, and the semiconductor layers 104a-104d are made of or include silicon.

[0064] In some embodiments, semiconductor layer 102a has a different germanium atomic concentration than semiconductor layer 102b, 102c, or 102d. In some embodiments, semiconductor layer 102a has a lower germanium atomic concentration than semiconductor layer 102b, 102c, or 102d. The germanium atomic concentration of semiconductor layer 102a may be in the range of about 10% to about 20%. The germanium atomic concentration of semiconductor layer 102b, 102c, or 102d may be in the range of about 25% to about 35%. The lower germanium atomic concentration of semiconductor layer 102a enables semiconductor layer 102a to have a different etching selectivity than semiconductor layer 102b, 102c, or 102d.

[0065] In some embodiments, the semiconductor layers 102a-102d and the semiconductor layers 104a-104d are formed by using multiple epitaxial growth operations. Each of the semiconductor layers 102a-102d and the semiconductor layers 104a-104d may be formed by using a selective epitaxial growth (SEG) process, a chemical vapor deposition (CVD) process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process and / or an ultra-high vacuum chemical vapor deposition (UHV-CVD) process), a molecular beam epitaxy process, one or more other applicable processes, or a combination thereof. In some embodiments, the semiconductor layers 102a-102d and the semiconductor layers 104a-104d are grown in-situ in the same process chamber. In some embodiments, the growth of semiconductor layers 102a-102d and the growth of semiconductor layers 104a-104d are performed alternately and sequentially in the same process chamber to complete the formation of the semiconductor stack. In some embodiments, the vacuum of the process chamber is not broken before the epitaxial growth of the semiconductor stack is completed.

[0066] Then, according to some embodiments, such as Figure 2B As shown, a hard mask element is formed over the semiconductor stack to assist in subsequent patterning of the semiconductor stack. One or more etching processes are used to pattern the semiconductor stack into fin structures 106A and 106B. Figure 2BAs shown, the semiconductor stack is partially removed to form the trench 112. Each fin structure 106A and 106B may include a portion of the semiconductor layers 102a-102d and 102a-102d and semiconductor fins 101A and 101B. During the etching process for forming the fin structures 106A and 106B, the semiconductor substrate 100 may also be partially removed. The protruding portions of the remaining semiconductor substrate 100 form the semiconductor fins 101A and 101B.

[0067] Each hard mask element may include a first mask layer 108 and a second mask layer 110. The first mask layer 108 and the second mask layer 110 may be made of different materials. In some embodiments, the first mask layer 108 is made of a material having good adhesion to the semiconductor layer 104d. The first mask layer 108 may be made of silicon oxide, germanium oxide, silicon germanium oxide, one or more other suitable materials, or a combination of the foregoing. In some embodiments, the second mask layer 110 is made of a material having good etching selectivity to the semiconductor layers 102a-102d and 104a-104d. The second mask layer 110 is made of silicon nitride, silicon oxynitride, silicon carbide, one or more other suitable materials, or a combination of the foregoing.

[0068] Figure 1A-1B 1 is a top view of various stages of a process for forming a semiconductor device structure according to some embodiments. Figure 1A As shown, the extension directions of the fin structures 106A and 106B are substantially parallel to each other. In some embodiments, Figure 2B For along Figure 1A A schematic cross-sectional view of the structure taken along line 2B-2B.

[0069] According to some embodiments, Figure 2CAs shown, an isolation structure 114 is formed to surround the fin structures 106A and 106B. In some embodiments, one or more dielectric layers are deposited over the fin structures 106A and 106B and the semiconductor substrate 100 to overfill the trench 112. The dielectric layer may be made of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a low dielectric constant material, a porous dielectric material, one or more other suitable materials, or a combination of the foregoing. The dielectric layer may be deposited by using a flowable chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, one or more other applicable processes, or a combination of the foregoing.

[0070] Afterwards, a planarization process is used to partially remove the dielectric layer. The hard mask element (including the first mask layer 108 and the second mask layer 110) can also serve as a stop layer for the planarization process. The planarization process can include a chemical mechanical polishing (CMP) process, a grinding process, a dry grinding process, an etching process, one or more other applicable processes, or a combination of the foregoing. Afterwards, one or more etch-back processes are used to partially remove the dielectric layer. As a result, the remaining portion of the dielectric layer forms the isolation structure 114. Figure 2C As shown, upper portions of the fin structures 106A and 106B protrude from the top surface of the isolation structure 114 .

[0071] In some embodiments, Figure 2C As shown, the etch-back process used to form the isolation structure 114 is carefully controlled to ensure that the top surface of the isolation structure 114 is lower than the top surface of the semiconductor layer 102a. Therefore, the sidewalls of the semiconductor layer 102a are exposed and not covered by the isolation structure 114, which facilitates the subsequent removal process of the semiconductor layer 102a. Thereafter, the hard mask element (including the first mask layer 108 and the second mask layer 110) is removed. Alternatively, in some other embodiments, the hard mask element is removed or consumed during the planarization process and / or the etch-back process.

[0072] Then, according to some embodiments, such as Figure 1B As shown, dummy gate stacks 120A and 120B are formed to extend across fin structures 106A and 106B. In some embodiments, Figure 2D For along Figure 1B A schematic cross-sectional view of the structure taken along line 2D-2D. Figure 3A-Figure 3N Schematic diagram of a cross section of various stages of a process for forming a semiconductor device structure according to some embodiments. Figure 3A For along Figure 1B A schematic cross-sectional view of the structure taken along line 3A-3A.

[0073] According to some embodiments, Figure 1B , Figure 2D and Figure 3A As shown, dummy gate stacks 120A and 120B are formed to partially cover and extend across fin structures 106A and 106B. In some embodiments, dummy gate stacks 120A and 120B surround fin structures 106A and 106B. Figure 2D As shown, the dummy gate stack 120B extends across and around the fin structures 106A and 106B.

[0074] like Figure 2D and Figure 3A As shown, each dummy gate stack 120A and 120B includes a dummy gate dielectric layer 116 and a dummy gate electrode 118. The dummy gate dielectric layer 116 may be made of silicon oxide or include silicon oxide. The dummy gate electrode 118 may be made of polysilicon or include polysilicon. In some embodiments, the dummy gate dielectric material layer and the dummy gate electrode layer are sequentially deposited on the isolation structure 114 and the fin structures 106A and 106B. The dummy gate dielectric material layer may be deposited using an atomic layer deposition process, a chemical vapor deposition process, one or more other applicable processes, or a combination of the foregoing. The dummy gate electrode layer may be deposited using a chemical vapor deposition process. Thereafter, the dummy gate dielectric material layer and the dummy gate electrode layer are patterned to form dummy gate stacks 120A and 120B.

[0075] In some embodiments, a hard mask element including mask layers 122 and 124 is used to assist in the patterning process for forming the dummy gate stacks 120A and 120B. One or more etching processes are used to partially remove the dummy gate dielectric material layer and the dummy gate electrode layer using the hard mask element as an etching mask. As a result, the remaining portions of the dummy gate dielectric material layer and the dummy gate electrode layer form the dummy gate dielectric layer 116 and the dummy gate electrode 118 of the dummy gate stacks 120A and 120B, respectively.

[0076] Then, according to some embodiments, such as Figure 3B As shown, spacer layers 126 and 128 are deposited on Figure 3A1. The structure shown in FIG. 1 is a top view of a dummy gate stack 120A and 120B. Spacers 126 and 128 extend along the sidewalls of the dummy gate stacks 120A and 120B. Spacers 126 and 128 are made of different materials. Spacer 126 may be made of a dielectric material having a low dielectric constant. Spacer 126 may be made of or include silicon carbide, silicon oxycarbide, silicon oxide, one or more other suitable materials, or a combination of the foregoing. Spacer 128 may be made of a dielectric material that may provide more protection for the gate structure during subsequent processes. Spacer 128 may have a greater dielectric constant than spacer 126. Spacer 128 may be made of silicon nitride, silicon oxynitride, carbon-containing silicon nitride, carbon-containing silicon oxynitride, one or more other suitable materials, or a combination of the foregoing. Spacers 126 and 128 may be sequentially deposited using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition (PVD) process, one or more other applicable processes, or a combination of the foregoing.

[0077] According to some embodiments, Figure 3C As shown, the spacer layers 126 and 128 are partially removed. One or more anisotropic etching processes may be used to partially remove the spacer layers 126 and 128. Thus, the remaining portions of the spacer layers 126 and 128 form spacer elements 126' and 128', respectively. Figure 3C As shown, spacer elements 126 ′ and 128 ′ extend along sidewalls of the dummy gate stacks 120A and 120B.

[0078] Fin structures 106A and 106B are partially removed to form recesses 130 for accommodating epitaxial structures (eg, source / drain structures) to be formed later. Figure 3C As shown, the fin structure 106A is partially removed to form the notch 130. One or more etching processes are used to form the notch 130. In some embodiments, a dry etching process is used to form the notch 130. Alternatively, a wet etching process may be used to form the notch 130. In some embodiments, each notch 130 passes through the fin structure 106A. In some embodiments, as shown in FIG. Figure 3C As shown, the recess 130 extends further into the semiconductor fin 101 A. In some embodiments, the spacer elements 126' and 128' and the recess 130 are formed simultaneously using the same etching process.

[0079] In some embodiments, each notch 130 has a sloped sidewall. The upper portion of the notch 130 is larger (or wider) than the lower portion of the notch 130. In these cases, due to the profile of the notch 130, the upper semiconductor layer (e.g., semiconductor layer 104d) is shorter than the lower semiconductor layer (e.g., semiconductor layer 104b).

[0080] However, there are many variations of the embodiments of the present invention. In some other embodiments, the recess 130 has substantially vertical sidewalls. In these cases, due to the profile of the recess 130, the upper semiconductor layer (e.g., semiconductor layer 104d) is substantially equal in width to the lower semiconductor layer (e.g., semiconductor layer 104b).

[0081] According to some embodiments, Figure 3D As shown, the semiconductor layers 102b-102d are laterally etched. Therefore, the edges of the semiconductor layers 102b-102d are retreated from the edges of the semiconductor layers 104a-104d. Figure 3D As shown, due to the lateral etching of the semiconductor layers 102b-102d, a recess 132 is formed. The recess 132 can be used to accommodate the inner spacer to be formed later. The semiconductor layers 102b-102d can be etched laterally by using a wet etching process, a dry etching process, or a combination thereof.

[0082] As described above, in some embodiments, semiconductor layer 102a has a lower concentration of germanium atoms than semiconductor layers 102b, 102c, or 102d. During the lateral etching of semiconductor layers 102b-102d, semiconductor layer 102a may be slightly (or substantially not) etched. Figure 3D As shown, substantially no notch is formed on the sidewall of the semiconductor layer 102a.

[0083] During the lateral etching of the semiconductor layers 102b-102d, the semiconductor layers 104a-104d may also be slightly etched. Figure 3D As shown, edge portions of semiconductor layers 104a-104d are partially etched and thus shrink to become edge elements 105a-105d. Figure 3D As shown, edge elements 105a-105d of each semiconductor layer 104a-104d are thinner than corresponding inner portions of semiconductor layers 104a-104d. In some embodiments, each edge element 105a is thinner than other upper edge elements (eg, edge elements 105b-105d).

[0084] According to some embodiments, Figure 3E As shown, a spacer layer 134 is deposited over the structure shown in 3D. The spacer layer 134 covers the dummy gate stacks 120A and 120B and overfills the recess 132. The spacer layer 134 may be made of or include carbon-containing silicon nitride (SiCN), carbon-containing silicon oxynitride (SiOCN), carbon-containing silicon oxide (SiOC), one or more other suitable materials, or a combination of the foregoing. The spacer layer 134 may be deposited using a chemical vapor deposition process, an atomic layer deposition process, one or more other applicable processes, or a combination of the foregoing.

[0085] According to some embodiments, Figure 3F As shown, an etching process is used to partially remove the spacer layer 134. Figure 3F As shown, the remaining portion of the spacer layer 134 forms the inner spacer 136. The etching process may include a dry etching process, a wet etching process, or a combination thereof.

[0086] The inner spacers 136 cover the edges of the semiconductor layers 102 b-102 d previously exposed by the recesses 132. The inner spacers 136 can be used to prevent the subsequently formed epitaxial structures (such as source / drain structures) from being damaged during the subsequent removal process of the semiconductor layers 102 b-102 d. The inner spacers 136 can also be used to reduce the parasitic capacitance between the subsequently formed source / drain structures and the gate stack. Therefore, the operating speed of the semiconductor device structure can be improved.

[0087] In some embodiments, Figure 3F As shown, after the etching process for forming the inner spacer 136, the portion of the semiconductor fin 101A that was originally covered by the spacer layer 134 is exposed through the recess 130. Figure 3F As shown, the sidewall of the semiconductor layer 102a previously covered by the spacer layer 134 is also exposed through the notch 130. This prevents the inner spacer 136 from being formed on the sidewall of the semiconductor layer 102a, which facilitates the subsequent removal process of the semiconductor layer 102a.

[0088] According to some embodiments, Figure 2E and Figure 3G As shown, the semiconductor layer 102a is removed to form a recess 302 between the semiconductor layer 104a and the semiconductor fin 101A or 101B. Due to the support of the dummy gate stacks 120A and 120B, even if the semiconductor layer 102a is removed, the fin structures 106A and 106B can be prevented from falling. The semiconductor layer 102a can be removed by using a dry etching process, a wet etching process, or a combination thereof.

[0089] like Figure 3G As shown in FIG. 2E and FIG. 3G , due to the protection of the inner spacer 136 and the semiconductor layer 104a (as a protective layer), the semiconductor layers 102b-102d are prevented from being etched during the removal of the semiconductor layer 102a. In some embodiments, as shown in FIG. 2E and FIG. 3G , since the semiconductor layer 104a and the edge element 105a are also slightly etched during the removal of the semiconductor layer 102a, the semiconductor layer 104a and the edge element 105a become thinner.

[0090] According to some embodiments, as shown in FIGS. 2F and 3H, a dielectric stress structure 304 is formed in the recess 302. As shown in FIGS. 2D-2F and 3F-3H, the semiconductor layer 102a (which serves as a sacrificial base layer) is replaced with the dielectric stress structure 304. In some embodiments, the dielectric stress structure 304 is made of a dielectric material that shrinks or becomes more dense if annealed. The dielectric stress structure 304 may be made of or include silicon nitride (SiN), silicon nitride containing carbon (SiCN), silicon oxynitride containing carbon (SiOCN), silicon oxide containing carbon (SiOC), one or more other suitable materials, or a combination of the foregoing. In some embodiments, the dielectric stress structure 304 is made of a different material than the internal spacer 136. Alternatively, in some other embodiments, the dielectric stress structure 304 and the internal spacer 136 are made of the same material.

[0091] In some embodiments, a dielectric stress layer is deposited over the structure shown in FIG. 3G or FIG. 2E to fill the recess 302. The dielectric stress layer may also extend along the sidewalls of the recess 130 and the tops of the dummy gate stacks 120A and 120B. The dielectric stress layer may be deposited using an atomic layer deposition process, a chemical vapor deposition process, a flowable chemical vapor deposition process, one or more other applicable processes, or a combination of the foregoing. Thereafter, an anisotropic etching process is used to partially remove the dielectric stress layer. Thus, the portion of the dielectric stress layer outside the recess 302 is substantially removed. Figure 2F and Figure 3H As shown, the remaining portion of the dielectric stress layer forms a dielectric stress structure 304 .

[0092] According to some embodiments, Fig. 3I As shown, epitaxial structure 138 is formed next to dummy gate stacks 120A and 120B. Fig. 3I As shown, the epitaxial structure 138 fills the recess 130. In some other embodiments, the epitaxial structure 138 overfills the recess 130. In these cases, the top surface of the epitaxial structure 138 may be higher than the top surface of the dummy gate dielectric layer 116. In some other embodiments, the epitaxial structure 138 partially fills the recess 130.

[0093] In some embodiments, epitaxial structure 138 is connected to semiconductor layers 104a-104d. Each semiconductor layer 104a-104d is between two epitaxial structures 138. In some embodiments, epitaxial structure 138 serves as a source / drain structure. In some embodiments, epitaxial structure 138 is a p-type doped region. Epitaxial structure 138 may include epitaxially grown silicon germanium (SiGe), epitaxially grown silicon, or other suitable epitaxially grown semiconductor materials.

[0094] In some embodiments, the epitaxial structure 138 is formed by using a selective epitaxial growth (SEG) process, a chemical vapor deposition process (e.g., a vapor phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process and / or an ultra-high vacuum chemical vapor deposition (UHV-CVD) process), a molecular beam epitaxy process, one or more other applicable processes, or a combination of the foregoing.

[0095] In some embodiments, epitaxial structure 138 is doped with one or more suitable dopants, such as SiGe source / drain features or Si source / drain features doped with boron (B), gallium (Ga), indium (In), or other suitable dopants.

[0096] In some embodiments, Fig. 3I As shown, before forming the epitaxial structure 138, an isolation element 137 is formed to fill the bottom of the recess 130. The isolation element 137 is used to prevent or reduce leakage current from the epitaxial structure 138. In some embodiments, the isolation element 137 is made of a semiconductor material. The isolation element 137 may be made of silicon germanium, silicon, one or more other suitable materials, or a combination of the foregoing or include the foregoing materials. In some embodiments, the doping concentration of the isolation element 137 is much lower than the doping concentration of the epitaxial structure 138. Therefore, the current from the epitaxial structure 138 is isolated by the isolation element 137 and prevented from entering the semiconductor fin 101A or 101B. In some other embodiments, the isolation element 137 is substantially free of dopants. In these cases, the doping concentration of the isolation element 137 is substantially equal to zero.

[0097] In some embodiments, the isolation elements 137 and the epitaxial structure 138 are formed in-situ in the same process chamber, and the vacuum of the process chamber is not broken after forming the isolation elements 137 and before forming the epitaxial structure 138 .

[0098] In some embodiments, the epitaxial structure 138 is doped in situ during epitaxial growth. The initial reaction gas mixture used to form the epitaxial structure 138 contains dopants. In some other embodiments, the epitaxial structure 138 is not doped during the growth of the epitaxial structure 138. Instead, after the epitaxial structure 138 is formed, the epitaxial structure 138 is doped in a subsequent process. In some embodiments, the doping is achieved by using an ion implantation process, a plasma immersion ion implantation process, a gas phase and / or solid phase source diffusion process, one or more other applicable processes, or a combination of the foregoing. In some embodiments, the epitaxial structure 138 is further exposed to one or more annealing processes to activate the dopants. For example, a rapid thermal annealing process is used.

[0099] According to some embodiments, Figure 3JAs shown, a contact etch stop layer 139 and a dielectric layer 140 are formed to cover the epitaxial structure 138 and surround the dummy gate stacks 120A and 120B. The contact etch stop layer 139 may be made of or include silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, one or more other suitable materials, or a combination of the foregoing. The dielectric layer 140 may be made of or include silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), a low dielectric constant material, a porous dielectric material, one or more other suitable materials, or a combination of the foregoing.

[0100] In some embodiments, the etch stop material layer and the dielectric material layer are sequentially deposited on Fig. 3I The etch stop material layer may be deposited using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, one or more other applicable processes, or a combination of the foregoing. The dielectric material layer may be deposited using a flowable chemical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, one or more other applicable processes, or a combination of the foregoing.

[0101] Afterwards, a planarization process is used to partially remove the etch stop material layer and the dielectric material layer. Thus, the remaining portions of the etch stop material layer and the dielectric material layer form a contact etch stop layer 139 and a dielectric layer 140, respectively. The planarization process may include a chemical mechanical polishing process, a grinding process, an etching process, a dry grinding process, one or more other applicable processes, or a combination of the foregoing. In some embodiments, the mask layers 122 and 124 are removed during the planarization process. In some embodiments, after the planarization process, the top surfaces of the contact etch stop layer 139, the dielectric layer 140, and the dummy gate electrode 118 are substantially coplanar.

[0102] According to some embodiments, Figure 2G and Figure 3K As shown, one or more etching processes are used to remove the dummy gate stacks 120A and 120B to form trenches 142. The trenches 142 expose the dielectric stress structure 304 and the semiconductor layers 102b-102d and 104a-104d previously covered by the dummy gate stacks 120A and 120B and the epitaxial structure 138.

[0103] According to some embodiments, as shown in FIGS. 2H and 3L, the semiconductor layers 102b-102d (which serve as sacrificial layers) are removed to form the recess 144. In some embodiments, an etching process is used to remove the semiconductor layers 102b-102d. Due to the high etching selectivity, the semiconductor layers 104b-104d are slightly (or substantially not) etched. As shown in FIGS. 2H and 3L, the remaining portions of the semiconductor layers 104b-104d form a plurality of semiconductor nanostructures 104b'-104d' of the fin structures 106A and 106B. The semiconductor nanostructures 104b'-104d' are constructed or made of the remaining portions of the semiconductor layers 104b-104d. The semiconductor nanostructures 104b'-104d' suspended above the semiconductor fins 101A or 101B may serve as channel structures of transistors.

[0104] In some embodiments, the etchant used to remove the semiconductor layers 102b-102d also slightly removes the semiconductor layers 104b-104d forming the semiconductor nanostructures 104b'-104d'. Therefore, after removing the semiconductor layers 102b-102d, the resulting semiconductor nanostructures 104b'-104d' become thinner. In some embodiments, since other elements surround the edge elements 105b-105d, the etchant is prevented from reaching and etching the edge elements 105b-105d, so each semiconductor nanostructure 104b'-104d' is thinner than the edge elements 105b-105d.

[0105] In some embodiments, the etchant used to remove semiconductor layers 102b-102d etches through semiconductor layer 104a which is thinner than semiconductor layers 104b, 104c, or 104d. Thus, dielectric stress structure 304 is exposed. Figure 3L As shown, edge element 105a remains but is not completely removed.

[0106] After removing the semiconductor layers 102b-102d (which serve as sacrificial layers), a recess 144 is formed. The recess 144 is connected to the trench 142 and surrounds each semiconductor nanostructure 104b'-104d'. Figure 3L As shown, even though recesses 144 are formed between semiconductor nanostructures 104b'-104d', semiconductor nanostructures 104b'-104d' are maintained by epitaxial structure 138. Therefore, after removing semiconductor layers 102b-102d (which serve as sacrificial layers), released semiconductor nanostructures 104b'-104d' are prevented from falling.

[0107] During the removal of the semiconductor layers 102b-102d (which serve as sacrificial layers), the inner spacers 136 protect the epitaxial structure 138 from being etched or damaged, thereby improving the quality and reliability of the semiconductor device structure.

[0108] As described above, in some embodiments, Figure 2A As shown, the semiconductor layer 104a (later Figure 2E and Figure 3G The ratio (T1 / T2) of the thickness T1 of the semiconductor layer 104a (which serves as a protective layer of the semiconductor layer 102b during the process shown) to the thickness T2 of the semiconductor layer 104b (which becomes the semiconductor nanostructure 104b' later) may be in the range of about 2 / 5 to about 2 / 3. In some cases, the thickness ratio (T1 / T2) is less than about 2 / 5, and the semiconductor layer 104a having the thickness T1 may be too thin. Therefore, during the removal of the semiconductor layer 102a (which serves as a sacrificial base layer) as shown in FIGS. 2E and 3G, the semiconductor layer 104a may be damaged or completely removed, exposing the semiconductor layer 102b above the semiconductor layer 104a to the etchant. The semiconductor layer 102b may be damaged or removed. Therefore, the dielectric stress structure 304 formed later may occupy the space provided to accommodate the semiconductor layer 102b. Subsequent processes may become difficult to perform.

[0109] In some other cases, if the thickness ratio (T1 / T2) is greater than about 2 / 3, the semiconductor layer 104a having a thickness T1 may be too thick. Therefore, an additional or stronger etching process may be required for Figure 3L The process shown is to expose the dielectric stress structure 304. The process time may become longer. The additional or stronger etching process may also damage other elements (such as channel structures) that have been formed. The performance of the semiconductor device structure may be negatively affected.

[0110] According to some embodiments, Fig.2I and Figure 3M As shown, the dielectric stress structure 304 is annealed to form an annealed dielectric stress structure 306. A thermal operation may be used to form the annealed dielectric stress structure 306. The thermal operation may be performed at a temperature in the range of about 500° C. to about 900° C. Alternatively, the thermal operation may be performed at a temperature in the range of about 700° C. to about 800° C. The thermal operation time may be in the range of about 0.5 hours to about 4 hours. The thermal operation may be performed in an oxygen-containing environment. The oxygen-containing environment may include oxygen.

[0111] After the thermal operation, the dielectric stress structures 304 may “shrink” and transform into annealed dielectric stress structures 306. The annealed dielectric stress structures 306 may become denser than the dielectric stress structures 304. In some embodiments, each annealed dielectric stress structure 306 becomes thinner than a dielectric stress structure 304 that has not yet transformed into an annealed dielectric stress structure 306.

[0112] Due to the shrinkage during the transformation of the dielectric stress structure 304 into the annealed dielectric stress structure 306, the annealed dielectric stress structure 306 may apply tensile stress to the epitaxial structure 138, causing the epitaxial structures 138 next to the annealed dielectric stress structure 306 to move slightly closer to each other. In response, the epitaxial structure 138 may apply compressive stress to the semiconductor nanostructures 104b'-104d' as channel structures. Therefore, the hole carrier mobility may be increased. Therefore, the performance of the semiconductor device structure is significantly improved. In some embodiments, the semiconductor nanostructures 104b'-104d' serve as channel structures of p-type metal oxide semiconductor field effect transistors.

[0113] According to some embodiments, as shown in FIGS. 2I and 3M , during the thermal operation for forming the annealed dielectric stress structure 306, surface portions of the semiconductor nanostructures 104b′-104d′ and the exposed semiconductor fins 101A and 101B may also be oxidized to form an oxidized element 148. The oxidized element 148 may be made of a material different from the annealed dielectric stress structure 306. The oxidized element 148 may be made of or include silicon oxide, germanium oxide, one or more other suitable materials, or a combination thereof.

[0114] In some embodiments, Figure 3M As shown, during the thermal operation for forming the annealed dielectric stress structure 306, the edge element 105a is also oxidized to form an oxidized edge element 105a'. The oxidized edge element 105a' is a dielectric element made of or including silicon oxide, germanium oxide, one or more other suitable materials, or a combination of the foregoing. In some embodiments, as Figure 3M As shown, each oxidized edge feature 105 a ′ directly contacts a corresponding inner spacer 136 , a corresponding epitaxial structure 138 and / or a corresponding annealed dielectric stress structure 306 .

[0115] According to some embodiments, Figure 2J and Figure 3N As shown, the oxidized element 148 is removed. After removing the oxidized element 148, the semiconductor nanostructures 104b'-104d' may become thinner or narrower. The oxidized element 148 may be removed by using an etching process. The etching process may also partially remove the annealed dielectric stress structure 306. Figure 3N As shown, the etching process may also partially remove the oxidized edge element 105a'. According to some embodiments, Figure 3N As shown, after the etching process, the oxidized edge features 105 a ′ recede from the inner sidewalls of the inner spacers 136 .

[0116] According to some embodiments, as shown in FIGS. 2K and 3O, metal gate stacks 156A and 156B are formed to fill the trench 142. The metal gate stacks 156A and 156B extend into the recess 144 to surround each semiconductor nanostructure 104b'-104d'. In some embodiments, as shown in FIGS. 2K and 3O, each annealed dielectric stress structure 306 directly contacts the corresponding semiconductor fin 101A or 101B, the corresponding epitaxial structure 138 and / or the corresponding metal gate stack 156A or 156B.

[0117] Each metal gate stack 156A and 156B includes a plurality of metal gate stacks. Each metal gate stack 156A and 156B may include a gate dielectric layer 150, a work function layer 152, and a conductive filler 154. In some embodiments, the formation of the metal gate stacks 156A and 156B includes depositing a plurality of metal gate stack layers over the dielectric layer 140 to fill the trench 142 and the recess 144. The metal gate stack layer extends into the recess 144 to surround each semiconductor nanostructure 104b'-104d'.

[0118] In some embodiments, the gate dielectric layer 150 is made of or includes a dielectric material having a high dielectric constant (high-K). The gate dielectric layer 150 may be made of or include hafnium oxide, zirconium oxide, aluminum oxide, zirconium dioxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high dielectric constant materials, or a combination of the foregoing. The gate dielectric layer 150 may be deposited using an atomic layer deposition process, a chemical vapor deposition process, one or more other applicable processes, or a combination of the foregoing.

[0119] In some embodiments, an interfacial layer is formed on the surface of the semiconductor nanostructures 104b'-104d' before forming the gate dielectric layer 150. The interfacial layer is very thin and is made of, for example, silicon oxide or germanium oxide. In some embodiments, the interfacial layer is formed by applying an oxidant on the surface of the semiconductor nanostructures 104b'-104d'. For example, a liquid containing hydrogen peroxide may be applied or provided on the surface of the semiconductor nanostructures 104b'-104d' to form the interfacial layer.

[0120] The work function layer 152 can be used to provide a desired work function of the transistor to enhance device performance, including improved threshold voltage. In some embodiments, the work function layer 152 is used to form a p-type metal oxide semiconductor device. The work function layer 152 is a p-type work function layer. The p-type work function layer can provide a work function value suitable for the device, for example, equal to or greater than about 4.8 eV.

[0121] The p-type work function layer may include metal, metal carbide, metal nitride, or a combination thereof. For example, the p-type metal includes tantalum nitride, tungsten nitride, titanium, titanium nitride, one or more other suitable materials, or a combination thereof.

[0122] The work function layer 152 may also be made of or include hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminides, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or combinations thereof. The thickness and / or composition of the work function layer 152 may be fine-tuned to adjust the work function level.

[0123] The work function layer 152 may be deposited on the gate dielectric layer 150 by using an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

[0124] In some embodiments, the barrier layer is formed before the work function layer 152 to serve as an interface between the gate dielectric layer 150 and the subsequently formed work function layer 152. The barrier layer may also be used to prevent diffusion between the gate dielectric layer 150 and the subsequently formed work function layer 152. The barrier layer may be made of or include a metal-containing material. The metal-containing material may include titanium nitride, tantalum nitride, one or more other suitable materials, or a combination of the foregoing. The barrier layer may be deposited using an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination of the foregoing.

[0125] In some embodiments, the conductive filler 154 is made of or includes a metal material. The metal material may include tungsten, aluminum, copper, cobalt, one or more other suitable materials, or a combination of the foregoing. The conductive layer used to form the conductive filler 154 may be deposited on the work function layer 152 using a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, a spin coating process, one or more other applicable processes, or a combination of the foregoing.

[0126] In some embodiments, a barrier layer is formed over the work function layer 152 before the conductive layer used to form the conductive filler 154 is formed. The barrier layer can be used to prevent the subsequently formed conductive layer from diffusing or penetrating into the work function layer 152. The barrier layer can be made of or include tantalum nitride, titanium nitride, one or more other applicable materials, or a combination of the foregoing. The barrier layer can be deposited using an atomic layer deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination of the foregoing.

[0127] Thereafter, according to some embodiments, a planarization process is performed to remove the portion of the metal gate stack layer outside the trench 142. Therefore, the remaining portion of the metal gate stack layer forms metal gate stacks 156A and 156B, as shown in FIG. Figure 2K and Fig.3O As shown. In some embodiments, since the recess 144 is small and has been filled with other elements (such as the gate dielectric layer 150 and the work function layer 152), the conductive filler 154 does not extend into the recess 144. However, the embodiments of the present invention are not limited thereto. In some other embodiments, a portion of the conductive filler 154 extends into the recess 144, especially in the lower recess 144 which may have a larger space.

[0128] In some embodiments, the epitaxial structure 138 extends beyond the top surface of the annealed dielectric stress structure 306. In some embodiments, the epitaxial structure 138 extends beyond the interface between the annealed dielectric stress structure 306 and the metal gate stack 156A or 156B. In some embodiments, the epitaxial structure 138 further extends beyond the bottom surface of the annealed dielectric stress structure 306. Therefore, the annealed dielectric stress structure 306 can more easily apply tensile stress to the epitaxial structure 138. Therefore, the epitaxial structure 138 can apply compressive stress to the semiconductor nanostructures 104b'-104d' as channel structures. Therefore, the performance of the semiconductor device structure is significantly improved.

[0129] In some embodiments, Fig.3O As shown, each annealed dielectric stress structure 306 extends beyond the edges of the corresponding metal gate stack 156A or 156B on both sides. The semiconductor nanostructures 104b'-104d' are located directly above the corresponding annealed dielectric stress structure 306. Each annealed dielectric stress structure 306 itself can also help apply compressive stress to the semiconductor nanostructures 104b'-104d'. The performance of the semiconductor device structure is significantly improved.

[0130] In some embodiments, after forming the epitaxial structure 138, the dielectric stress structure 304 is annealed to form the annealed dielectric stress structure 306. However, the embodiments of the present invention are not limited thereto. Many variations and / or modifications may be made to the embodiments of the present invention. In some other embodiments, before forming the epitaxial structure 138, the dielectric stress structure 304 is annealed to form the annealed dielectric stress structure 306.

[0131] Figure 4A-4F Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments. Figure 4A shown, formed or received the same or similar to Figure 3H The structure shown.

[0132] According to some embodiments, Figure 4BAs shown, the dielectric stress structure 304 is annealed to form an annealed dielectric stress structure 306. The thermal operations shown in Figures 2I and 3M can be used to form the annealed dielectric stress structure 306. In some embodiments, since the sidewall surface of the edge element 105a exposed to the recess 130 is very small, the edge element 105a is substantially not oxidized or slightly oxidized.

[0133] Then, according to some embodiments, such as Figure 4C As shown, similar to Fig. 3I In the embodiment shown, the isolation element 137 and the epitaxial structure 138 are formed. Next, according to some embodiments, as Figure 4D As shown, similar to Figure 3J In the illustrated embodiment, a contact etch stop layer 139 and a dielectric layer 140 are formed.

[0134] According to some embodiments, Figure 4E As shown, similar to the embodiment shown in FIGS. 3K-3L, the dummy gate stacks 120A and 120B and the semiconductor layers 102b-102d are removed. Thus, semiconductor nanostructures 104b'-104d' are formed. During the removal of the semiconductor layers 102b-102d, the semiconductor layer 104a is consumed, exposing the annealed dielectric stress structure 306. In some embodiments, as Figure 4E As shown, each edge element 105 a remains between a corresponding inner spacer 136 and a corresponding annealed dielectric stress structure 306 .

[0135] Then, according to some embodiments, such as Figure 4F As shown, similar to Fig.3O In the embodiment shown, metal gate stacks 156A and 156B are formed. In some embodiments, each edge element 105 a directly contacts a corresponding annealed dielectric stress structure 306 and a corresponding inner spacer 136 .

[0136] However, the embodiments of the present invention are not limited thereto. In some other embodiments, Figure 4B The annealing process shown uses a higher temperature or a longer operation time. Even if the exposed surface area of ​​the edge element 105a is small, the edge element 105a is oxidized to form an oxidized edge element. Therefore, after the subsequent process, the same or similar Fig.3O structure.

[0137] In some embodiments, each annealed dielectric stress structure 306 is formed by oxidizing edge elements 105a' (eg, Fig.3O ) or edge element 105a (as shown Figure 4F136 ) are separated from the corresponding internal spacers 136. However, the embodiments of the present invention are not limited thereto. Many variations and / or modifications may be made to the embodiments of the present invention. In some other embodiments, each annealed dielectric stress structure 306 directly contacts one or more internal spacers 136.

[0138] Figure 5A-5C Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments. Figure 5A shown, formed or received the same or similar to Figure 3F The structure shown.

[0139] According to some embodiments, Figure 5B As shown, similar to Figure 3G In the embodiment shown, the semiconductor layer 102a is removed to form the recess 302. Due to the protection of the inner spacer 136 and the semiconductor layer 104a (which acts as a protective layer), the semiconductor layers 102b-102d are prevented from being etched during the removal of the semiconductor layer 102a. Figure 5B As shown, since the semiconductor layer 104a and the edge element 105a are also etched during the removal of the semiconductor layer 102a, the semiconductor layer 104a becomes thinner and the edge element 105a is removed. Figure 5B As shown, bottom surfaces of some of the inner spacers 136 are exposed through the recesses 302 .

[0140] Then, according to some embodiments, a process similar to Figure 3H-Figure 3O or Figure 4A-4F Therefore, the formation Figure 5C The structure shown. Figure 5C As shown, each annealed dielectric stress structure 306 directly contacts some of the inner spacers 136 , some of the epitaxial structures 138 , and / or the semiconductor fins 101A or 101B.

[0141] Many variations and / or modifications may be made to the embodiments of the present invention. Figure 6A-6B Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments. Fig. 6A As shown, the formation is similar to Figure 2C The structure of Fig. 6A As shown, the top surface of the isolation structure 114 is higher than the top surface of the semiconductor layer 102a. Although the semiconductor layer 104a and the isolation structure 114 cover the semiconductor layer 102a, the etchant used to remove the semiconductor layer 102a can still reach the semiconductor layer 102a through the recess 130 (similar to the embodiment shown in Figures 3F-3G).

[0142] Then, according to some embodiments, a process similar to Figure 2D-2K Therefore, the formation Figure 6B According to some embodiments, Figure 6B As shown, the top surface of the annealed dielectric stress structure 306 is lower than the top surface of the isolation structure 114 .

[0143] Many variations and / or modifications may be made to the embodiments of the present invention. Figure 7A-7B Schematic cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0144] like Fig. 7A As shown, the formation is similar to Figure 3H In some embodiments, the dielectric stress structure 304 does not completely fill the recess 302. Therefore, according to some embodiments, Fig. 7A As shown, one or more seams 702 (or voids) are formed in the dielectric stress structure 304 .

[0145] Then, according to some embodiments, a process similar to Figure 3I-Figure 3O Therefore, the formation Figure 7B According to some embodiments, Figure 7B As shown, after annealing the dielectric stress structure 304 to become the annealed dielectric stress structure 306, the seam 702 (or void) becomes smaller and forms a seam 702' (or void).

[0146] Embodiments of the present invention form a semiconductor device structure having a dielectric stress structure under a channel structure. A gate stack surrounds the channel structure. For example, the semiconductor device structure includes a stack of multiple channel structures surrounded by a metal gate stack. The dielectric stress structure is formed under the channel structure. The dielectric stress structure can be annealed using a thermal operation. The dielectric stress structure can cause the epitaxial structure next to the channel structure to apply stress (e.g., compressive stress) to the channel structure. The dielectric stress structure itself can also apply stress (e.g., compressive stress) to the channel structure. Therefore, the carrier mobility in the channel structure can be improved. The performance and reliability of the semiconductor device structure are greatly improved.

[0147] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a plurality of semiconductor nanostructures located above a substrate and two epitaxial structures located above the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack surrounding the semiconductor nanostructures. The semiconductor device structure also includes a dielectric stress structure located between the gate stack and the substrate, and the epitaxial structure extends beyond a top surface of the dielectric stress structure.

[0148] In some other embodiments, the gate stack surrounds each of the plurality of semiconductor nanostructures.

[0149] In some other embodiments, the dielectric stress structure is made of SiN, SiCN, SiOCN, SiOC or a combination thereof.

[0150] In some other embodiments, the two epitaxial structures directly contact the dielectric stress structure.

[0151] In some other embodiments, the semiconductor device structure further includes a plurality of inner spacers, wherein each of the plurality of inner spacers is located between the gate stack and one of the two epitaxial structures.

[0152] In some other embodiments, one of the plurality of inner spacers directly contacts the dielectric stress structure.

[0153] In some other embodiments, the plurality of internal spacers and the dielectric stress structure are made of different materials.

[0154] In some other embodiments, the semiconductor device structure further includes a dielectric element located between the plurality of internal spacers and the dielectric stress structure.

[0155] In some other embodiments, the plurality of semiconductor nanostructures are made of a semiconductor material, and the dielectric element is made of an oxide material of the semiconductor material.

[0156] In some other embodiments, the dielectric stress structure extends beyond both side edges of the gate stack.

[0157] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a semiconductor fin located above a substrate and a plurality of channel structures suspended above the semiconductor fin. The semiconductor device structure also includes a gate stack surrounding each of the channel structures. The semiconductor device structure also includes an epitaxial structure adjacent to the channel structure. In addition, the semiconductor device structure includes a dielectric stress structure located between the semiconductor fin and the gate stack, and the dielectric stress structure extends beyond the two side edges of the gate stack.

[0158] In some other embodiments, the semiconductor device structure further includes an isolation structure surrounding the semiconductor fin, wherein a top surface of the dielectric stress structure is higher than a top surface of the isolation structure.

[0159] In some other embodiments, the dielectric stress structure directly contacts the epitaxial structure.

[0160] In some other embodiments, the semiconductor device structure further includes an inner spacer located between the dielectric stress structure and one of the plurality of channel structures, wherein the inner spacer directly contacts the dielectric stress structure.

[0161] According to some embodiments, a method for forming a semiconductor device structure is provided, the method comprising forming a sacrificial base layer above a semiconductor substrate, and forming a semiconductor stack above the sacrificial base layer. The semiconductor stack has a plurality of sacrificial layers and a plurality of semiconductor layers alternately stacked. The method also comprises patterning the semiconductor stack and the sacrificial base layer to form a fin structure, and forming a dummy gate stack to surround a portion of the fin structure. The method further comprises replacing the sacrificial base layer with a dielectric stress structure. In addition, the method comprises removing the dummy gate stack and the sacrificial layer to release a plurality of semiconductor nanostructures, the semiconductor nanostructures being composed of the remaining portions of the plurality of semiconductor layers. The method also comprises forming a metal gate stack to surround each of the semiconductor nanostructures.

[0162] In some other embodiments, the above method also includes partially removing the fin structure to form a recess, wherein the recess exposes the side surfaces of multiple semiconductor layers and multiple sacrificial layers; forming multiple internal spacers to cover the side surfaces of the multiple sacrificial layers; and after forming the multiple internal spacers, forming a source / drain structure to partially fill the recess.

[0163] In some other embodiments, the method further includes annealing the dielectric stress structure after forming the source / drain structure and before forming the metal gate stack.

[0164] In some other embodiments, the method further comprises annealing the dielectric stress structure before forming the source / drain structure.

[0165] In some other embodiments, the method further includes forming an isolation structure to surround a lower portion of the fin structure, wherein a top surface of the sacrificial base layer is higher than a top surface of the isolation structure.

[0166] In some other embodiments, the sacrificial base layer has a first atomic concentration of germanium, the plurality of sacrificial layers have a second atomic concentration of germanium, and the first atomic concentration of germanium is lower than the second atomic concentration of germanium.

[0167] The foregoing text summarizes the features of many embodiments, so that those skilled in the art can better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the invention of the present invention. Various changes, substitutions or modifications may be made to the embodiments of the present invention without departing from the spirit and scope of the invention of the present invention.

Claims

1. A semiconductor device structure, comprising: A plurality of semiconductor nanostructures are disposed on a substrate; Two epitaxial structures are located above the substrate, wherein each of the plurality of semiconductor nanostructures is between the two epitaxial structures, and the two epitaxial structures are p-type doped; a gate stack surrounding the plurality of semiconductor nanostructures; and A dielectric stress structure is located between the gate stack and the substrate, wherein the two epitaxial structures extend beyond a top surface of the dielectric stress structure. 2 . The semiconductor device structure of claim 1 , wherein the gate stack surrounds each of the plurality of semiconductor nanostructures. 3 . The semiconductor device structure as claimed in claim 1 , wherein the dielectric stress structure is made of SiN, SiCN, SiOCN, SiOC or a combination thereof. The semiconductor device structure as claimed in claim 1 , wherein the two epitaxial structures directly contact the dielectric stress structure. 5 . The semiconductor device structure of claim 1 , further comprising a plurality of inner spacers, wherein each of the plurality of inner spacers is located between the gate stack and one of the two epitaxial structures. 6 . The semiconductor device structure of claim 5 , wherein one of the plurality of inner spacers directly contacts the dielectric stress structure. 7 . The semiconductor device structure as claimed in claim 5 , wherein the plurality of inner spacers and the dielectric stress structure are made of different materials. 8 . The semiconductor device structure as claimed in claim 5 , further comprising a dielectric element disposed between the plurality of inner spacers and the dielectric stress structure. 9 . The semiconductor device structure of claim 8 , wherein the plurality of semiconductor nanostructures are made of a semiconductor material, and the dielectric element is made of an oxide material of the semiconductor material. 10 . The semiconductor device structure as claimed in claim 1 , wherein the dielectric stress structure extends beyond both side edges of the gate stack.

11. A semiconductor device structure, comprising: a semiconductor fin disposed on a substrate; A plurality of channel structures are suspended above the semiconductor fin; a gate stack surrounding each of the plurality of channel structures; an epitaxial structure adjacent to the plurality of channel structures; and A dielectric stress structure is located between the semiconductor fin and the gate stack, wherein the dielectric stress structure extends beyond two side edges of the gate stack. 12 . The semiconductor device structure of claim 11 , further comprising an isolation structure surrounding the semiconductor fin, wherein a top surface of the dielectric stress structure is higher than a top surface of the isolation structure. 13 . The semiconductor device structure of claim 12 , wherein the dielectric stress structure directly contacts the epitaxial structure. 14 . The semiconductor device structure of claim 11 , further comprising an inner spacer between the dielectric stress structure and one of the plurality of channel structures, wherein the inner spacer directly contacts the dielectric stress structure.

15. A method for forming a semiconductor device structure, comprising: forming a sacrificial substrate layer on a semiconductor substrate; forming a semiconductor stack above the sacrificial base layer, wherein the semiconductor stack has a plurality of sacrificial layers and a plurality of semiconductor layers alternately stacked; patterning the semiconductor stack and the sacrificial base layer to form a fin structure; forming a dummy gate stack to surround a portion of the fin structure; replacing the sacrificial base layer with a dielectric stress structure, wherein the entirety of the dielectric stress structure is located below a bottommost surface of the plurality of semiconductor layers; removing the dummy gate stack and the plurality of sacrificial layers to release a plurality of semiconductor nanostructures comprised of remaining portions of the plurality of semiconductor layers; as well as A metal gate stack is formed to surround each of the plurality of semiconductor nanostructures.

16. The method for forming a semiconductor device structure according to claim 15, further comprising: Partially removing the fin structure to form a notch, wherein the notch exposes side surfaces of the plurality of semiconductor layers and the plurality of sacrificial layers; forming a plurality of inner spacers to cover the side surfaces of the plurality of sacrificial layers; as well as After forming the plurality of inner spacers, a source / drain structure is formed to partially fill the recess. 17 . The method for forming a semiconductor device structure as claimed in claim 16 , further comprising annealing the dielectric stress structure after forming the source / drain structure and before forming the metal gate stack. 18 . The method for forming a semiconductor device structure as claimed in claim 16 , further comprising annealing the dielectric stress structure before forming the source / drain structure. 19 . The method for forming a semiconductor device structure according to claim 15 , further comprising forming an isolation structure to surround a lower portion of the fin structure, wherein a top surface of the sacrificial base layer is higher than a top surface of the isolation structure. 20 . The method for forming a semiconductor device structure as claimed in claim 15 , wherein the sacrificial base layer has a first atomic concentration of germanium, the plurality of sacrificial layers have a second atomic concentration of germanium, and the first atomic concentration of germanium is lower than the second atomic concentration of germanium.

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