Bipolar junction transistor (BJT) and method of forming the same

Abstract

Various embodiments of the present invention are directed to a method for forming a bipolar junction transistor (BJT). A dielectric film is deposited over a substrate and includes a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer between the lower dielectric layer and the upper dielectric layer. A first semiconductor layer is deposited over the dielectric film and is subsequently patterned to form an opening exposing the dielectric film. A first etching is performed on the upper dielectric layer through the opening to extend the opening to the intermediate dielectric layer. In addition, the first etching stops on the intermediate dielectric layer and laterally undercuts the first semiconductor layer. Additional etching is performed to extend the opening to the substrate. A lower base structure and an emitter are formed to be stacked in the opening and fill the opening, and the first semiconductor layer is patterned to form an upper base structure. Embodiments of the present application also relate to a bipolar junction transistor (BJT).

Description

Technical Field

[0001] Embodiments of the present invention relate to bipolar junction transistors (BJTs) and methods of forming the same. Background Art

[0002] Bipolar Junction Transistors (BJTs) are commonly used in digital and analog integrated circuit (IC) devices for high frequency applications. BJTs consist of two pn junctions that share a cathode or anode region called the base. The base separates two regions called the emitter and collector, respectively. The emitter and collector have the same doping type and have an opposite doping type to the base. Depending on the doping type of the base, collector, and emitter, the BJT can be either an NPN BJT or a PNP BJT. Summary of the invention

[0003] Some embodiments of the present application provide a bipolar junction transistor (BJT), comprising: a substrate; a dielectric film, located on the substrate and comprising a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer located between the lower dielectric layer and the upper dielectric layer; a lower base structure, located on the intermediate dielectric layer and protruding to the substrate through the intermediate dielectric layer and the lower dielectric layer; an upper base structure, located on the lower base structure, wherein the lower base structure and the upper base structure are different semiconductors and are in contact at a heterojunction; and an emitter, located on the upper base structure and extending through the upper base structure to the lower base structure.

[0004] Other embodiments of the present application provide a bipolar junction transistor (BJT), comprising: a semiconductor substrate; a dielectric film located on the semiconductor substrate; a lower base structure embedded in the dielectric film and contacting the semiconductor substrate; an upper base structure located on the lower base structure and the dielectric film, wherein the upper base structure wraps around the top corner of the dielectric film from the top surface of the dielectric film to the side wall of the dielectric film, wherein the upper base structure extends along the side wall of the dielectric film to the lower base structure, and wherein the lower base structure and the upper base structure are different semiconductors; and an emitter extending through the upper base structure to the lower base structure.

[0005] Some other embodiments of the present application provide a method for forming a bipolar junction transistor (BJT), the method comprising: depositing a film including a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer located between the lower dielectric layer and the upper dielectric layer on a substrate; depositing a first semiconductor layer above the film; patterning the first semiconductor layer to form an opening exposing the film; performing a first etching on the upper dielectric layer through the opening to extend the opening to the intermediate dielectric layer, wherein the first etching stops on the intermediate dielectric layer and laterally undercuts the first semiconductor layer; performing at least one additional etching to extend the opening to the substrate; forming a lower base structure and an emitter stacked in the opening and filling the opening, wherein the lower base structure and the emitter are semiconductors; and patterning the first semiconductor layer to form an upper base structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 Cross-sectional views of some embodiments of bipolar junction transistors (BJTs) including multi-layer base dielectric films are shown.

[0008] Figure 2A and Figure 2B Shows Figure 1 Top view layout diagram of some different embodiments of BJTs.

[0009] FIG. 3A to FIG. 3E Shows Figure 1 Cross-sectional views of some different alternative embodiments of a BJT.

[0010] Figure 4A and Figure 4B Shows Figure 1 Cross-sectional views of some embodiments of a BJT, wherein the BJT is located on a bulk semiconductor substrate.

[0011] Figure 5A and Figure 5B Shows Figure 4A and Figure 4B Cross-sectional views of some optional embodiments of a BJT, wherein the BJT is located on a semiconductor-on-insulator (SOI) substrate.

[0012] Figure 6 A cross-sectional view of some embodiments of an integrated circuit (IC) chip including a plurality of BJTs sharing a multi-layer base dielectric film and covered by an interconnect structure is shown.

[0013] Figures 7 to 18 A series of cross-sectional views of some embodiments of methods for forming a BJT including a multi-layer base dielectric film are shown.

[0014] Fig.19 Shows Figures 7 to 18 A block diagram of some embodiments of the method.

[0015] Figures 20 to 30 A series of cross-sectional views illustrating some embodiments of a method for forming a BJT in which an upper base structure and an emitter are formed in a recess.

[0016] Fig.31 Shows Figures 20 to 30 A block diagram of some embodiments of the method. DETAILED DESCRIPTION

[0017] The present invention provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0019] Some methods of forming a bipolar junction transistor (BJT) include: depositing an oxide layer over a substrate; depositing a base polysilicon layer over the oxide layer; patterning the base polysilicon layer to form an opening over a doped region that exposes the oxide layer and defines a collector in the substrate; forming a sidewall spacer structure on a sidewall of the base polysilicon layer in the opening; etching the oxide layer vertically and laterally through the opening to extend the opening to the collector and extend the opening under the base polysilicon layer; depositing a silicon germanium base at the bottom of the opening; depositing an emitter polysilicon layer over the silicon germanium base that fills the remainder of the opening; and patterning the base polysilicon layer and the base emitter layer to form a polysilicon base and an emitter, respectively. The polysilicon base and the silicon germanium base are in direct contact and together define a base.

[0020] The challenge of this method is that the contact area between the polysilicon base and the silicon germanium base is small, and therefore the contact resistance between the polysilicon base and the silicon germanium base is high. The contact resistance partially defines the total resistance of the base. For example, the resistance of the base (e.g., Rb) can be the sum of the contact resistance, the resistance of the polysilicon base, and the resistance of the silicon germanium base. Therefore, the resistance of the base is also high. High base resistance leads to low current and therefore high conduction time. High conduction time limits the conduction frequency (e.g., Ft) and the maximum oscillation frequency (e.g., Fmax). Therefore, high conduction time limits the performance of the BJT. The maximum oscillation frequency can, for example, be a frequency at which the power gain is one (e.g., unity). The conduction frequency can, for example, be a frequency at which the short-circuit current gain is one (e.g., unity).

[0021] Various embodiments of the present invention are directed to a method for forming a BJT including a multilayer base dielectric film, and a BJT obtained by the method. In some embodiments of the method, the multilayer base dielectric film is deposited over a substrate and includes a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer located between the lower dielectric layer and the upper dielectric layer. A first semiconductor layer is deposited over the multilayer base dielectric film and is subsequently patterned to form an opening exposing the multilayer base dielectric film. A first etching is performed on the upper dielectric layer through the opening to extend the opening to the intermediate dielectric layer. In addition, the first etching stops on the intermediate dielectric layer and laterally undercuts the first semiconductor layer. Additional etching is performed to extend the opening to the substrate. A lower base structure and an emitter are formed to stack in the opening and fill the opening, and the emitter is located above the lower base structure. In addition, the first semiconductor layer is patterned to form an upper base structure that directly contacts the lower base structure. The lower base structure and the upper base structure are semiconductors with different band gaps and are in direct contact at the first semiconductor layer undercut by the first etching.

[0022] Because the intermediate dielectric layer is used as an etch stop layer during the first etch, and because the first etch laterally undercuts the first semiconductor layer, the first etch can extend to a greater extent below the first semiconductor layer, and the contact area between the lower base structure and the upper base structure can be larger. Because the contact area can be larger, the contact resistance between the lower base structure and the upper base structure (e.g., the resistance at the contact area) can be smaller. Therefore, the total resistance of the base defined by the lower base structure and the upper base structure can be smaller. Because the resistance of the base can be smaller, the current through the BJT can be larger, and therefore the conduction time of the BJT can be smaller. Due to the larger current and smaller conduction time, the conduction frequency of the BJT and the maximum oscillation frequency of the BJT can be larger. Because the contact area is increased by a series of depositions (e.g., for a multilayer base dielectric film) and a series of etchings (e.g., a first etching and an additional etching), the contact area can be increased with relatively low complexity and relatively low cost.

[0023] Reference Figure 1 , a cross-sectional view 100 of some embodiments of a BJT 102 including a multilayer base dielectric film 104 is provided. As will be seen below, the multilayer base dielectric film 104 can facilitate the formation of a base 106 having a low resistance. As a result, the conduction frequency (e.g., Ft) of the BJT 102 and the maximum oscillation frequency (e.g., Fmax) of the BJT 102 can be high. The BJT 102 can, for example, be a heterojunction BJT (HBT) or some other suitable type of BJT. Applications of the BJT 102 can, for example, include space-based radar, automated radar, and high-speed short-range wireless communications. However, other suitable applications are also possible.

[0024] The multi-layer base dielectric film 104 accommodates the lower base structure 108 and is located below the upper base structure 110. The lower base structure 108 and the upper base structure 110 together define the base 106. In addition, the multi-layer base dielectric film 104 includes a lower base dielectric layer 112, an upper base dielectric layer 114, and an intermediate base dielectric layer 116. The lower base dielectric layer 112 and the upper base dielectric layer 114 are located below and above the intermediate base dielectric layer 116, respectively, so that the intermediate base dielectric layer 116 is buried in the multi-layer base dielectric film 104. In addition, the lower base dielectric layer 112 and the upper base dielectric layer 114 are different dielectrics from the intermediate base dielectric layer 116, and in some embodiments, are the same dielectric.

[0025] The lower base dielectric layer 112 and the upper base dielectric layer 114 may be, for example, or include silicon oxide, silicon oxynitride, some other suitable dielectric, or any combination thereof. The intermediate base dielectric layer 116 may be, for example, or include silicon nitride, silicon oxynitride, silicon carbide, some other suitable dielectric, or any combination thereof. In some embodiments, the lower base dielectric layer 112 and the upper base dielectric layer 114 are silicon oxide, and the intermediate base dielectric layer 116 is silicon nitride, so that the multi-layer base dielectric film 104 is an ONO dielectric film.

[0026] The lower base structure 108 is embedded in the multi-layer base dielectric film 104 and is located above the intermediate base dielectric layer 116 and the lower base dielectric layer 112 at the periphery of the lower base structure 108. In addition, the lower base structure 108 protrudes through the intermediate base dielectric layer 116 and the lower base dielectric layer 112 at the center of the lower base structure 108 to the collector 118. Therefore, the width W of the lower base structure 108 is b It decreases discretely from top to bottom and may, for example, have a T-shaped profile or some other suitable profile. b The collector 118 is discretely reduced from top to bottom, so during the formation of the opening in which the lower base structure 108 is formed, less of the collector 118 may be exposed to the etchant and / or the surrounding environment. Therefore, damage to the collector 118 may be reduced and leakage current may be reduced. Therefore, the performance of the BJT 102 may be enhanced.

[0027] In some embodiments, the top surface of the lower base structure 108 is flat or substantially flat with the top surface of the multi-layer base dielectric film 104 and / or the bottom surface of the lower base structure 108 is flat or substantially flat with the bottom surface of the multi-layer base dielectric film 104. In addition, in some embodiments, the thickness of the lower base structure 108 is the same as or substantially the same as the thickness of the multi-layer base dielectric film 104.

[0028] The upper base structure 110 is located above the multilayer base dielectric film 104 and the lower base structure 108. In addition, the upper base structure 110 directly contacts the lower base structure 108 at a contact region 120. As shown and described in detail below, due to the multiple layers of the multilayer base dielectric film 104 and the method by which the BJT 102 can be formed, the contact region 120 can be larger. The method can, for example, include: 1) depositing a semiconductor layer over the multilayer base dielectric film 104; 2) patterning the semiconductor layer to form an opening exposing the multilayer base dielectric film 104; 3) performing a first etching of the upper base dielectric layer 114 vertically and laterally while the intermediate base dielectric layer 116 is used as an etch stop layer; 4) performing additional etching to extend the opening to the collector 118; 5) depositing the lower base structure 108 at the bottom of the opening; and 6) patterning the semiconductor layer to form the upper base structure 110. However, other suitable methods of forming the BJT 102 are also possible.

[0029] Because the intermediate base dielectric layer 116 serves as an etch stop during the first etch, and because the first etch extends laterally into the upper base dielectric layer 114, the etch can extend to a greater extent below the semiconductor layer. Because the upper base structure 110 is formed of a semiconductor layer, and because the lower base structure 108 is deposited at the bottom of the opening, the lower base structure 108 can extend to a greater extent below the upper base structure 110. Therefore, the contact region 120 can be larger.

[0030] Because the contact area 120 can be larger, the contact resistance between the lower base structure 108 and the upper base structure 110 (e.g., the resistance at the contact area 120) can be smaller. Therefore, the total resistance of the base 106 can be smaller. Because the resistance of the base 106 can be smaller, the current through the BJT 102 can be larger, and therefore the conduction time of the BJT 102 can be smaller. Due to the larger current and smaller conduction time, the conduction frequency (e.g., Ft) and the maximum oscillation frequency (e.g., Fmax) can be higher. For example, when the BJT 102 is an NPN-type BJT, the conduction frequency can be greater than about 240 gigahertz (GHz) or some other suitable value and / or the maximum oscillation frequency can be greater than about 400 GHz or some other suitable value. As another example, when the BJT 102 is a PNP-type BJT, the conduction frequency can be greater than about 100 GHz or some other suitable value and / or the maximum oscillation frequency can be greater than about 160 GHz or some other suitable value. The maximum oscillation frequency may be, for example, a frequency at which the power gain is one (eg, unity). The conduction frequency may be, for example, a frequency at which the short-circuit current gain is one (eg, unity).

[0031] The lower base structure 108 and the upper base structure 110 are semiconductor materials with different band gaps. For example, the lower base structure 108 can have a lower band gap than the upper base structure 110. Because the lower base structure 108 and the upper base structure 110 are semiconductor materials with different band gaps, the lower base structure 108 and the upper base structure 110 define a heterojunction at the contact area 120. The lower base structure 108 and the upper base structure 110 also share a common doping type (e.g., P-type or N-type). The lower base structure 108 can, for example, be or include doped silicon germanium and / or some other suitable semiconductor material, and / or the upper base structure 110 can, for example, be or include doped polysilicon and / or some other suitable semiconductor material. In some embodiments where the lower base structure 108 is germanium or includes germanium, the upper base structure 110 consists of silicon or consists essentially of silicon.

[0032] The collector 118 is located below the multi-layer base dielectric film 104 and the lower base structure 108. In addition, the collector 118 directly contacts the lower base structure 108, and in some embodiments, contacts the multi-layer base dielectric film 104. The collector 118 is a doped region of the semiconductor substrate 122 surrounded by the trench isolation structure 124. In addition, the collector 118 has an opposite doping type to the base 106. For example, the collector 118 can be P-type and the base 106 can be N-type, or vice versa.

[0033] The trench isolation structure 124 is located below the multilayer base dielectric film 104 and extends into the semiconductor substrate 122 to surround and divide the collector 118. The trench isolation structure 124 may be, for example, or include silicon oxide and / or some other suitable dielectric. In addition, the trench isolation structure 124 may be, for example, a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, or some other suitable type of trench isolation structure.

[0034] The semiconductor substrate 122 has a different band gap than the lower base structure 108 at the interface where the collector 118 and the lower base structure 108 are in direct contact. For example, the semiconductor substrate 122 may have a higher band gap than the lower base structure 108 at the interface. Because the semiconductor substrate 122 and the lower base structure 108 have different band gaps at the interface, the semiconductor substrate 122 and the lower base structure 108 define a heterojunction at the interface. The semiconductor substrate 122 may, for example, be or include single crystal silicon and / or some other suitable semiconductor material, and / or the lower base structure 108 may, for example, be or include silicon germanium and / or some other suitable semiconductor material.

[0035] In some embodiments, semiconductor substrate 122 is a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, or some other suitable type of substrate. In some embodiments, semiconductor substrate 122 and upper base structure 110 share a common semiconductor element. For example, semiconductor substrate 122 may be or include single crystal silicon, and upper base structure 110 may be or include polycrystalline silicon, such that semiconductor substrate 122 and upper base structure 110 share silicon. In some embodiments, semiconductor substrate 122 and upper base structure 110 have a single crystal lattice and a polycrystalline lattice, respectively.

[0036] The hard mask 126 is located above the upper base structure 110 and includes a lower hard mask layer 128 and an upper hard mask layer 130. In an alternative embodiment, the lower hard mask layer 128 and / or the upper hard mask layer 130 are omitted. The lower hard mask layer 128 and the upper hard mask layer 130 are vertically stacked, wherein the upper hard mask layer 130 is located above the lower hard mask layer 128. In addition, the lower hard mask layer 128 and the upper hard mask layer 130 are different dielectrics. For example, the lower hard mask layer 128 can be or include silicon oxide, and the upper hard mask layer 130 can be or include silicon nitride. However, other suitable dielectrics are also possible. In some embodiments, the lower hard mask layer 128 is or includes the same dielectric material as the lower base dielectric layer 112 and / or the upper base dielectric layer 114. In addition, in some embodiments, the upper hard mask layer 130 is or includes the same dielectric material as the intermediate base dielectric layer 116.

[0037] The emitter 132 is located above the hard mask 126 and extends downward through the hard mask 126 and the upper base structure 110 to directly contact the lower base structure 108. The emitter 132 is or includes a doped semiconductor material having an opposite doping type to the base 106 and / or the same doping type as the collector 118. For example, the emitter 132 can be P-type and the base 106 can be N-type, or vice versa. In addition, the emitter 132 has a band gap that is different from the band gap of the lower base structure 108. Therefore, the emitter 132 and the lower base structure 108 define a heterojunction at the interface where the emitter 132 and the lower base structure 108 are in direct contact. In some embodiments, the emitter 132 has a higher band gap than the lower base structure 108. In addition, in some embodiments, the emitter 132 has the same band gap as the upper base structure 110. The emitter 132 can, for example, be or include polysilicon and / or some other suitable semiconductor material.

[0038] In some embodiments, the emitter 132 and the upper base structure 110 are the same semiconductor material. For example, both the emitter 132 and the upper base structure 110 can be doped polysilicon. In some embodiments, the emitter 132 and the semiconductor substrate 122 share a common semiconductor element. For example, the emitter 132 can be or include polysilicon, and the semiconductor substrate 122 can be or include single crystal silicon. In some embodiments, the emitter 132 and the semiconductor substrate 122 have a polycrystalline lattice and a single crystal lattice, respectively.

[0039] The sidewall spacer structure 134 laterally separates the emitter 132 from the hard mask 126 and the upper base structure 110. The sidewall spacer structure 134 can be or include silicon nitride and / or some other suitable dielectric material. In some embodiments, the sidewall spacer structure 134 is or includes the same dielectric material as the upper hard mask layer 130 and / or as the intermediate base dielectric layer 116.

[0040] In some embodiments, the lower base dielectric layer 112 and the upper base dielectric layer 114 have a separate first thickness T1 of about 160 angstroms, about 100-115 angstroms, about 100-160 angstroms, about 40-100 angstroms, or some other suitable value. In some embodiments, the intermediate base dielectric layer 116 has a second thickness T2 of about 30 angstroms, about 50 angstroms, about 10-50 angstroms, about 25-75 angstroms, or some other suitable value. If the first thickness T1 and / or the second thickness T2 are too large (e.g., above the above ranges and / or values), the lower base structure 108 may be too thick, and thus the base 106 may have a high resistance. The high resistance, in turn, may adversely affect the conduction frequency of the BJT 102, the maximum oscillation frequency of the BJT 102, and other suitable parameters of the BJT 102. If the first thickness T1 and / or the second thickness T2 are too small (e.g., below the above ranges and / or values), the lower base structure 108 and the multilayer base dielectric film 104 may be too thin, and thus the leakage current may be high. This, in turn, may adversely affect the performance of the BJT 102. In addition, if the second thickness T2 is too small (e.g., less than about 10 angstroms or some other suitable value), the intermediate base dielectric layer 116 may be too thin to be used as an etch stop layer when forming the lower base structure 108. Therefore, the control of the opening in which the lower base structure 108 is formed may be poor. This, in turn, may result in damage to the collector 118 and / or may result in a smaller contact area 120.

[0041] Reference Figure 2A and Figure 2B , provides Figure 1 200A and 200B are top view layouts of some different embodiments of BJT 102. For example, Figure 1 The cross-sectional view 100 may be along Figure 2A and Figure 2B The sidewall spacer structure 134 extends in a first closed path to surround the emitter 132, and the upper base structure 110 extends in a second closed path to surround the sidewall spacer structure 134. Figure 2A In FIG. 1 , the sidewall spacer structure 134 and the upper base structure 110 are in the shape of a ring. Figure 2B In the embodiment, the sidewall spacer structure 134 and the upper base structure 110 are in the shape of square rings. In other embodiments, other suitable shapes are also possible.

[0042] The outer boundary of the lower base structure 108 is shown in dashed lines, and the contact region 120 is located between the outer boundary of the lower base structure 108 and the sidewall spacer structure. Figure 2A In FIG. 1 , the outer boundary of the lower base structure 108 is circular, so that the contact region 120 is annular. Figure 2BIn the embodiment, the outer boundary of the lower base structure 108 is a square, so that the contact region 120 is a square ring. In other embodiments, other suitable shapes are also possible.

[0043] In some embodiments, the thickness T of the contact region 120 is c is about 10-50 nanometers, about 10-30 nanometers, about 30-50 nanometers, or some other suitable amount. c If the thickness T is too small (e.g., less than about 10 nanometers or some other suitable value), the contact region 120 may be small, and thus the contact resistance between the lower base structure 108 and the upper base structure 110 may be high. As a result, the overall resistance of the base 106 may be high, and thus the performance of the BJT 102 may be poor. For example, the conduction frequency and / or the maximum oscillation frequency may be low. ... c If the thickness is too large (eg, greater than about 50 nanometers or some other suitable value), the semiconductor layer forming the upper base structure 110 may collapse into the opening in which the lower base structure 108 is formed.

[0044] Reference FIG. 3A to FIG. 3E , provides Figure 1 Some different alternative embodiments of the BJT 102 are cross-sectional views 300A-300E.

[0045] exist Figure 3A In the embodiment of the present invention, the lower base dielectric layer 112 is omitted, so that the multilayer base dielectric film 104 has two layers instead of three layers. In addition, the intermediate base dielectric layer 116 is more appropriately referred to as the lower base dielectric layer. By omitting the lower base dielectric layer 112, the material cost can be reduced. In an alternative embodiment, the multilayer base dielectric film can include four or more base dielectric layers.

[0046] exist Figure 3B 1 , a lateral etch stop layer 302 is located below the upper base structure 110 and extends into the upper base dielectric layer 114 to the intermediate base dielectric layer 116. The lateral etch stop layer 302 is a different dielectric than the lower base dielectric layer 112 and the upper base dielectric layer 114, and may be, for example, or include silicon nitride, silicon carbide, silicon oxynitride, or some other suitable dielectric. In some embodiments, the lateral etch stop layer 302 is or includes silicon nitride, while the lower base dielectric layer 112 and the upper base dielectric layer 114 are or include silicon oxide, or vice versa. In some embodiments, the lateral etch stop layer 302 is or includes the same dielectric as the intermediate base dielectric layer 116.

[0047] The lateral etch stop layer 302 can be highly controlled in positioning using photolithography. For example, a process for forming the lateral etch stop layer 302 can include: 1) patterning the upper base dielectric layer 114 using photolithography to form an opening for the lateral etch stop layer 302; 2) depositing the lateral etch stop layer 302 covering the upper base dielectric layer 114 and filling the opening; and 3) etching back the lateral etch stop layer 302. However, other suitable methods are also possible. Because the lateral etch stop layer 302 can be highly controlled in positioning, the lateral etch stop layer 302 can increase the control of the contact area 120. For example, as shown in detail below, the formation of the lower base structure 108 can include lateral etching of the upper base dielectric layer 114 below the semiconductor layer forming the upper base structure 110. The lateral etch stop layer 302 can provide an etch stop for the lateral etching to increase the control of the degree of the lateral etching, which increases the control of the contact area 120.

[0048] exist Figure 3C , the upper base structure 110 wraps around the top corners of the upper base dielectric layer 114. In addition, the upper base dielectric layer 114 has an increased thickness compared to the lower base dielectric layer 112. In an alternative embodiment, the lower base dielectric layer 112 and the upper base dielectric layer 114 have the same thickness. In an alternative embodiment, the lower base dielectric layer 112 has an increased thickness compared to the upper base dielectric layer 114.

[0049] exist Figure 3D In the embodiment of the present invention, the lower base structure 108 directly contacts the upper base structure 110 at both the bottom surface of the upper base structure 110 and the sidewalls of the upper base structure 110. Therefore, the contact area 120 between the lower base structure 108 and the upper base structure 110 wraps around the bottom corner of the upper base structure 110 and can be larger than when it is located at the bottom surface of the upper base structure 110. Because the contact area 120 can be larger, the contact resistance between the lower base structure 108 and the upper base structure 110 can be lower, and thus the overall resistance of the base 106 can be lower. This in turn can increase the conduction frequency of the BJT 102, the maximum oscillation frequency of the BJT 102, and other suitable parameters of the BJT 102.

[0050] The liner layer 304 separates the sidewall spacer structure 134 from the hard mask 126 and the upper base structure 110. The liner layer 304 is a different dielectric than the intermediate base dielectric layer 116, and may be, for example, or include silicon oxide and / or some other suitable dielectric. In some embodiments, the liner layer 304 is or includes silicon oxide, while the intermediate base dielectric layer 116 is or includes silicon nitride, or vice versa. In some embodiments, the liner layer 304 is or includes the same dielectric as the lower base dielectric layer 112 and / or the upper base dielectric layer 114.

[0051] During the formation of the BJT 102, the liner layer 304 may have a lateral segment extending from the sidewall of the semiconductor layer forming the upper base structure 110 along the bottom surface of the sidewall spacer structure 134. In addition, during the formation of the BJT 102, the liner layer 304 and the upper base dielectric layer 114 may be etched vertically and laterally to form an opening in which the lower base structure 108 is deposited. The lateral etching may remove the lateral segment so that the opening exposes the sidewall of the semiconductor layer. In addition, the lateral etching may extend the opening below the semiconductor layer. Because the lower base structure 108 is deposited in the opening and the upper base structure 110 is formed of the semiconductor layer, the formation of the opening as described above may result in the formation of the lower base structure 108 on both the bottom surface of the upper base structure 110 and the sidewall of the upper base structure 110.

[0052] exist Figure 3E In the embodiment of the present invention, the multi-layer base dielectric film 104 is replaced by the base dielectric layer 306, and the upper base structure 110 wraps the top corner of the base dielectric layer 306 from the top surface of the base dielectric layer 306 to the sidewall of the base dielectric layer 306. In addition, the lower base structure 108 is an ellipse with a curved profile similar to an oval. However, in alternative embodiments, other suitable profiles are also possible.

[0053] As shown in detail below, because the upper base structure 110 wraps around the top corners of the base dielectric layer 306 and because of the method by which the BJT 102 may be formed, the contact area 120 may be larger. The method may, for example, include: 1) patterning the base dielectric layer 306 to form a groove along the top of the base dielectric layer 306; 2) depositing a semiconductor layer covering the base dielectric layer 306 and lining the groove; 3) patterning the semiconductor layer to form an opening exposing the base dielectric layer 306; 4) vertically and laterally etching the base dielectric layer 306 to extend the opening vertically to the semiconductor substrate 122 and to extend the opening laterally below the semiconductor layer; 5) depositing the lower base structure 108 at the bottom of the opening; and 6) patterning the semiconductor layer to form the upper base structure 110. However, other suitable methods for forming the BJT 102 are also possible.

[0054] Due to the recess, the spacing between the bottom surface of the semiconductor layer and the semiconductor substrate 122 is reduced. It has been recognized that by reducing the spacing, etching can more effectively remove the base dielectric layer 306 from the bottom surface of the semiconductor layer. Therefore, more of the bottom surface is exposed in the opening than would otherwise be the case. Because more of the bottom surface is exposed, the contact area 120 is larger when the lower base structure 108 is deposited in the opening. Due to the larger contact area 120, the contact resistance between the lower base structure 108 and the upper base structure 110 is lower, and the overall resistance of the base 106 is lower. This, in turn, increases the conduction frequency of the BJT 102, the maximum oscillation frequency of the BJT 102, and other suitable parameters of the BJT 102.

[0055] The base dielectric layer 306 may be, for example, or include silicon oxide, silicon oxynitride, some other suitable dielectric, or any combination of the foregoing. In some embodiments, the base dielectric layer 306 is the same as the lower base dielectric layer 112 and / or the upper base dielectric layer 114 described. In some embodiments, the thickness T of the base dielectric layer 306 is about 250-400 angstroms, about 250-325 angstroms, about 325-400 angstroms, about 350 angstroms, or some other suitable value. If the thickness T is too small (e.g., less than about 250 angstroms or other suitable values), the leakage current may be high. This in turn may adversely affect the performance of the BJT 102. If the thickness T is too large (e.g., greater than about 400 angstroms or some other suitable value), the lower base structure 108 may be too thick, and thus the base 106 may have a high resistance. The high resistance may, in turn, adversely affect the conduction frequency of the BJT 102 , the maximum oscillation frequency of the BJT 102 , and other suitable parameters of the BJT 102 .

[0056] Reference Figure 4A and Figure 4B , provides Figure 1 Cross-sectional views 400A, 400B of some embodiments of a BJT, wherein the semiconductor substrate 122 is a bulk substrate. Figure 4A The cross-sectional view 400A may be, for example, along Figure 4B The cross-sectional view 400B is taken along line B, and Figure 4B The cross-sectional view 400B may be, for example, along Figure 4A The cross-sectional view 400A is taken along line B.

[0057] The first trench isolation structure 124 extends into the semiconductor substrate 122 to a first depth, and the second trench isolation structure 402 overlapping the first trench isolation structure 124 extends into the semiconductor substrate 122 to a second depth greater than the first depth. The first trench isolation structure 124 and the second trench isolation structure 402 surround and divide the collector 118. In addition, the first trench isolation structure 124 and the second trench isolation structure 402 are or include dielectrics, and electrically isolate the BJT 102 from other semiconductor devices (not shown) on the semiconductor substrate 122. The first trench isolation structure 124 can be, for example, an STI and / or other suitable trench isolation structure, and / or the second trench isolation structure 402 can be, for example, a DTI and / or other suitable trench isolation structure.

[0058] Specific reference Figure 4B , the first trench isolation structure 124 includes a segment 124s that separates a collector contact region 404 from a portion of the collector 118 where the collector 118 is in direct contact with the lower base structure 108. The collector contact region 404 is located above the collector 118 and is a doped region of the semiconductor substrate 122, and the collector contact region 404 has the same doping type as the collector 118, but a higher doping concentration than the collector 118. The collector contact region 404 facilitates electrical coupling of the collector 118 to an interconnect structure (not shown).

[0059] Reference Figure 5A and Figure 5B , provides Figure 4A and Figure 4B Cross-sectional views 500A, 500B of some alternative embodiments of the BJT 102 of FIG. 1 , wherein the semiconductor substrate 122 is an SOI substrate. Figure 4A and Figure 4B , Figure 5A The cross-sectional view 500A may be, for example, along Figure 5B The cross-sectional view 500B is taken along line B, and Figure 5B The cross-sectional view 500B may be, for example, along Figure 5A The semiconductor substrate 122 includes a handle substrate 502 , a buried dielectric layer 504 , and a device layer 506 .

[0060] The buried dielectric layer 504 is located above the handle substrate 502 and may be, for example, or include silicon oxide and / or some other suitable dielectric. The handle substrate 502 may be, for example, or include single crystal silicon and / or some other suitable type of semiconductor. The device layer 506 is located above the buried dielectric layer 504 and accommodates the collector 118. The device layer 506 may be, for example, or include single crystal silicon and / or some other suitable type of semiconductor.

[0061] The collector 118 extends from the multi-layer base dielectric film 104 to the buried dielectric layer 504. In addition, the second trench isolation structure 402 extends from the first trench isolation structure 124 to the buried dielectric layer 504. Therefore, the collector 118 is completely separated from the doped regions of other devices (not shown) in the semiconductor substrate 122 by the first trench isolation structure 124 and the second trench isolation structure 402 and the buried dielectric layer 504. This provides a high degree of electrical isolation between the BJT 102 and the other devices, and thus the performance of the BJT 102 can be improved.

[0062] Although using Figure 1 An embodiment of the BJT 102 is shown in Figure 4A and Figure 4B as well as Figure 5A and Figure 5B , but you can use FIG. 3A to FIG. 3E In any of the embodiments of the BJT 102. In addition, although the Figure 1 The BJT 102 describes Figure 2A and Figure 2B Top view 200A, 200B, but Figure 2A and Figure 2B Top view of 200A, 200B is suitable for FIG. 3A to FIG. 3E , Figure 4A , Figure 4B , Figure 5A and Figure 5B Any one of the BJTs 102. For example, FIG. 3A to FIG. 3E , Figure 4A , Figure 4B , Figure 5A and Figure 5B The BJT 102 in any one of the above may have a Figure 2A and Figure 2B Top view in any one of them.

[0063] Reference Figure 6 , a cross-sectional view 600 of some embodiments of an integrated circuit (IC) chip including a first BJT 102a and a second BJT 102b is provided, wherein the first BJT 102a and the second BJT 102b share a multi-layer base dielectric film 104 and are covered by an interconnect structure 602. The first BJT 102a and the second BJT 102b are located on a semiconductor substrate 122 and are electrically separated from each other by a first trench isolation structure 124 and a second trench isolation structure 402.

[0064] The first BJT 102a and the second BJT 102b are respectively connected to Figure 5A and Figure 5BThe BJT 102 is shown and described as the same, but may alternatively have other suitable configurations. In an alternative embodiment, the first BJT 102a and the second BJT 102b are each the same as shown and described. Figure 1 , FIG. 3A to FIG. 3E , Figure 4A and Figure 4B In some embodiments, the first BJT 102a and the second BJT 102b each have a Figure 2A and Figure 2B Similar to the first BJT 102a and the second BJT 102b, the semiconductor substrate 122 and the first trench isolation structure 124 and the second trench isolation structure 402 are as shown in FIG. Figure 5A and Figure 5B As shown, but may alternatively have other suitable configurations. In an alternative embodiment, the semiconductor substrate 122 is Figure 4A and Figure 4B The first trench isolation structure 124 and the second trench isolation structure 402 are shown and described as Figure 4A and Figure 4B Shown and described.

[0065] In some embodiments, the first BJT 102a is an NPN-type BJT, and the second BJT 102b is a PNP-type BJT, or vice versa. For example, the collector 118 of the first BJT 102a and the emitter 132 of the first BJT 102a may be N-type, and the base 106 of the first BJT 102a may be P-type. In addition, the collector 118 of the second BJT 102b and the emitter 132 of the second BJT 102b may be P-type, and the base 106 of the second BJT 102b may be N-type. In alternative embodiments, both the first BJT 102a and the second BJT 102b are NPN-type BJTs or PNP-type BJTs.

[0066] The interconnect structure 602 covers and is electrically coupled to the first BJT 102a and the second BJT 102b. The interconnect structure 602 includes a plurality of conductive lines 604, a plurality of contacts 606, and a plurality of vias 608. The conductive lines 604, the contacts 606, and the vias 608 are stacked in an interconnect dielectric layer 610 and define a conductive path leading out of the first BJT 102a and the second BJT 102b. The contacts 606 extend from the base 106, the emitter 132, and the collector contact region 404. The conductive lines 604 and the vias 608 are located above and electrically coupled to the contacts 606. Although the interconnect structure 602 is shown as having two levels of conductive lines and a single level of vias, in alternative embodiments, the interconnect structure 602 may include additional levels of conductive lines and / or additional levels of vias.

[0067] The contact 606 may be, for example, or include tungsten and / or some other suitable conductive material. The conductor 604 and the via 608 may be, for example, or include copper, aluminum, copper, aluminum, some other suitable conductive material, or any combination thereof. The interconnect dielectric layer 610 may be, for example, or include silicon oxide and / or some other suitable dielectric.

[0068] Reference Figures 7 to 18 , a series of cross-sectional views 700-1800 of some embodiments of a method for forming a BJT including a plurality of base dielectric layers are provided. The method can be used, for example, according to Figure 1 The BJT can be formed using the embodiments shown and described in or other suitable embodiments.

[0069] like Figure 7 As shown in the cross-sectional view 700 of FIG. 70 , a first trench isolation structure 124 and a second trench isolation structure 402 are formed. The first trench isolation structure 124 and the second trench isolation structure 402 overlap and extend into the semiconductor substrate 122 to a first depth D1 and a second depth D2 greater than the first depth D1, respectively. In addition, the first trench isolation structure 124 and the second trench isolation structure 402 surround and divide the device region 122d of the semiconductor substrate 122, and then the collector 118 is formed at the device region 122b. The first trench isolation structure 124 is or includes a dielectric, and may be, for example, an STI or some other suitable type of trench isolation structure. Similarly, the second trench isolation structure 402 is or includes a dielectric, and may be, for example, a DTI or some other suitable type of trench isolation structure. The semiconductor substrate 122 may be, for example, or include single crystal silicon and / or some other suitable semiconductor material.

[0070] Still like Figure 7 As shown in the cross-sectional view 700 of FIG. 1 , the collector 118 is formed in the semiconductor substrate 122. The collector 118 is a doped region of the semiconductor substrate 122 having P-type doping or N-type doping. The collector 118 may be formed, for example, by ion implantation and / or some other suitable doping process.

[0071] like Figure 8 As shown in the cross-sectional view 800 of , the multi-layer base dielectric film 104 is deposited on the semiconductor substrate 122. The multi-layer base dielectric film 104 includes a lower base dielectric layer 112, an upper base dielectric layer 114, and an intermediate base dielectric layer 116. The lower base dielectric layer 112 and the upper base dielectric layer 114 are respectively located below and above the intermediate base dielectric layer 116, so that the intermediate base dielectric layer 116 is buried in the multi-layer base dielectric film 104. In addition, the lower base dielectric layer 112 and the upper base dielectric layer 114 are different dielectrics from the intermediate base dielectric layer 116, and in some embodiments, are the same dielectric.

[0072] The lower base dielectric layer 112 and the upper base dielectric layer 114 may be, for example, or include silicon oxide, silicon oxynitride, some other suitable dielectric, or any combination thereof. The intermediate base dielectric layer 116 may be, for example, or include silicon nitride, silicon oxynitride, silicon carbide, some other suitable dielectric, or any combination thereof. In some embodiments, the lower base dielectric layer 112 and the upper base dielectric layer 114 are silicon oxide, and the intermediate base dielectric layer 116 is silicon nitride, so that the multi-layer base dielectric film 104 is an ONO dielectric film.

[0073] In some embodiments, the lower base dielectric layer 112 and the upper base dielectric layer 114 have a separate first thickness T1 of about 160 angstroms, about 100-115 angstroms, about 100-160 angstroms, about 40-100 angstroms, or some other suitable value. In some embodiments, the intermediate base dielectric layer 116 has a second thickness T2 of about 30 angstroms, about 50 angstroms, about 10-50 angstroms, about 25-75 angstroms, or some other suitable value. If the first thickness T1 and / or the second thickness T2 are too large (e.g., higher than the above ranges and / or values), the lower base structure formed thereafter may be too thick, and the base of the BJT formed thereby may have a high resistance. The high resistance may in turn adversely affect the conduction frequency of the BJT, the maximum oscillation frequency of the BJT, and other suitable parameters of the BJT. If the first thickness T1 and / or the second thickness T2 are too small (e.g., lower than the above ranges and / or values), the multilayer base dielectric film 104 may be too thin, and therefore the leakage current may be high. This, in turn, may adversely affect the performance of the formed BJT. In addition, if the second thickness T2 is too small (e.g., less than about 10 angstroms or other suitable values), the intermediate base dielectric layer 116 may be too thin to serve as an etch stop during subsequent processing, and the control of the profile of the subsequently formed lower base structure may be poor.

[0074] The multilayer base dielectric film 104 may be deposited, for example, by a series of deposition processes corresponding to the various layers (e.g., 112, 114, and 116) of the multilayer base dielectric film 104. Each of the deposition processes may be chemical vapor deposition (CVD), physical vapor deposition (PVD), some other suitable deposition process, or any combination of the foregoing. In some embodiments, the lower base dielectric layer 112 is deposited by thermal oxidation, while the intermediate base dielectric layer 116 and the upper base dielectric layer 114 are deposited by vapor deposition.

[0075] Still like Figure 8As shown in the cross-sectional view 800 of , the first semiconductor layer 802 is deposited above the multilayer base dielectric film 104. The first semiconductor layer 802 has a doping type opposite to that of the collector 118. For example, the first semiconductor layer 802 can have a P-type doping, while the collector 118 can have an N-type doping, or vice versa. The first semiconductor layer 802 can be, for example, polysilicon and / or some other suitable semiconductor material. In some embodiments, the first semiconductor layer 802 and the semiconductor substrate 122 share a common semiconductor element and / or have the same or similar band gap. For example, the first semiconductor layer 802 and the semiconductor substrate 122 can be polysilicon and single crystal silicon, respectively, and therefore can have the same or similar band gap.

[0076] Still like Figure 8 As shown in the cross-sectional view 800 of , a multilayer hard mask film 804 is deposited above the first semiconductor layer 802. The multilayer hard mask film 804 includes a lower hard mask layer 128 and an upper hard mask layer 130. In an optional embodiment, the lower hard mask layer 128 and / or the upper hard mask layer 130 are omitted. The lower hard mask layer 128 and the upper hard mask layer 130 are vertically stacked and are different dielectrics. For example, the lower hard mask layer 128 can be or include silicon oxide, and the upper hard mask layer 130 can be or include silicon nitride. However, other suitable dielectrics are also possible. In some embodiments, the lower hard mask layer 128 is or includes the same dielectric material as the lower base dielectric layer 112 and / or the upper base dielectric layer 114. In addition, in some embodiments, the upper hard mask layer 130 is or includes the same dielectric material as the intermediate base dielectric layer 116.

[0077] like Fig. 9 As shown in the cross-sectional view 900 of , the multilayer hard mask film 804 and the first semiconductor layer 802 are patterned to form an opening 902 located above the collector 118 and exposing the multilayer base dielectric film 104. Patterning may, for example, include: 1) forming a mask 904 having a layout of the opening 902 above the multilayer hard mask film 804; 2) etching the multilayer hard mask film 804 and the first semiconductor layer 802 using the mask 904 in an appropriate position; 3) removing the mask 904. However, other suitable patterning processes are also possible. The mask 904 may, for example, be a photoresist mask formed by photolithography or some other suitable type of mask. Etching may, for example, be implemented by dry etching, but other suitable types of etching are also possible.

[0078] like Fig.10As shown in the cross-sectional view 1000 of FIG. 1 , a sidewall spacer structure 134 is formed on the sidewalls of the opening 902. The sidewall spacer structure 134 may be or include silicon nitride and / or some other suitable dielectric material. In some embodiments, the sidewall spacer structure 134 is or includes the same dielectric material as the upper hard mask layer 130 and / or the intermediate base dielectric layer 116. In some embodiments, the sidewall spacer structure 134 has a dielectric material such as Figure 2A and Figure 2B The process of forming the sidewall spacer structure 134 may include, for example: 1) depositing a spacer layer covering the multi-layer hard mask film 804 and further lining the opening 902; and 2) etching back the spacer layer. However, other suitable methods are also possible.

[0079] like Fig.11 As shown in the cross-sectional view 1100 of , a first etch is performed on the upper base dielectric layer 114 through the opening 902. The first etch vertically etches the upper base dielectric layer 114 and stops on the intermediate base dielectric layer 116 to extend the opening 902 to the intermediate base dielectric layer 116. Therefore, the intermediate base dielectric layer 116 serves as an etch stop layer. In addition, the first etch laterally etches the upper base dielectric layer 114 to extend the opening 902 below the sidewall spacer structure 134 and the first semiconductor layer 802. Therefore, the first etch undercuts the sidewall spacer structure 134 and the first semiconductor layer 802.

[0080] The first etch uses an etchant having a high etch rate for the upper base dielectric layer 114 relative to the etch rate of the intermediate base dielectric layer 116. The high etch rate may be, for example, about 10-40 times, about 20-30 times, about 20 times, or about 30 times the etch rate of the intermediate base dielectric layer 116. However, other suitable multiples are also possible. In some embodiments, the etchant also has a high etch rate for the upper base dielectric layer 114 relative to the etch rate of the upper hard mask layer 130 and / or relative to the etch rate of the sidewall spacer structure 134. The first etch may be implemented, for example, by wet etching, but other suitable types of etching are also possible. In some embodiments in which the first etch is implemented by wet etching, the etchant may be, for example, a wet etchant comprising deionized water and 1% by mass of hydrogen fluoride. However, other suitable wet etchants and / or mass percentages are also possible.

[0081] After completing the first etching, the opening 902 extends a distance D3 below the first semiconductor layer 802. The distance D3 can be, for example, about 1-10 nanometers, about 10-20 nanometers, or some other suitable amount. As will be seen below, lateral etching and using the intermediate dielectric layer 116 as an etching stop layer help to increase the contact area between the components used to form the base of the BJT. The increased contact area reduces the resistance of the base, and therefore reduces the conduction time of the BJT. This in turn enhances the conduction frequency of the BJT, the maximum oscillation frequency of the BJT, and other suitable parameters of the BJT. If the distance D3 is too small (e.g., less than about 1 nanometer or some other suitable value), the contact area may be smaller, and therefore the performance of the BJT will be poor. If the distance D3 is too large (e.g., greater than about 20 nanometers or some other suitable value), the first semiconductor layer 802 may collapse into the opening 902 during the first etching or during subsequent etching.

[0082] like Fig.12 As shown in the cross-sectional view 1200 of FIG. 1 , a second etch is performed on the intermediate base dielectric layer 116 through the opening 902. The second etch vertically etches the intermediate base dielectric layer 116 and stops on the lower base dielectric layer 112 to extend the opening 902 to the lower base dielectric layer 112. Therefore, the lower base dielectric layer 112 serves as an etch stop layer. In addition, the second etch is anisotropic and there is almost no lateral etching, so the width W of the opening 902 is o At the intermediate base dielectric layer 116, it is smaller than at the upper base dielectric layer 114. This can, for example, minimize the area of ​​the collector 118 that is exposed thereafter, and thus can minimize damage to the collector 118. By minimizing damage to the collector 118, leakage current can be reduced and the performance of the formed BJT can be enhanced. In an alternative embodiment, the second etch can be isotropic and thus can have a lateral etch. However, this may be at the expense of increased damage to the collector 118.

[0083] The second etch uses an etchant that has a high etch rate for the intermediate base dielectric layer 116 relative to the etch rate of the lower base dielectric layer 112. The high etch rate can be, for example, about 10-40 times, about 20-30 times, about 20 times, or about 30 times the etch rate of the lower base dielectric layer 112. However, other suitable multiples are also possible. In some embodiments, the etchant also has a high etch rate for the upper hard mask layer 130 and / or the sidewall spacer structure 134 relative to the etch rate of the lower base dielectric layer 112. Therefore, the thickness of the upper hard mask layer 130 and / or the height of the sidewall spacer structure 134 can be reduced. The second etch can be implemented, for example, by dry etching, but other suitable types of etching are also possible.

[0084] like Fig.13As shown in the cross-sectional view 1300 of , a third etch is performed on the lower base dielectric layer 112 through the opening 902. The third etch vertically etches the lower base dielectric layer 112 and stops on the collector 118 to extend the opening 902 to the collector 118. In addition, the third etch laterally etches the upper base dielectric layer 114 to further extend the opening 902 below the first semiconductor layer 802. In other words, the third etch further undercuts the first semiconductor layer 802.

[0085] The third etch uses an etchant having a high etch rate for the lower base dielectric layer 112 relative to the etch rate of the collector 118. The high etch rate may be, for example, about 10-40 times, about 20-30 times, about 20 times, or about 30 times the etch rate of the collector 118. However, other suitable multiples are also possible. Because the high etch rate is high relative to the etch rate of the collector 118, over-etching of the collector 118 may be low, and thus damage to the collector 118 by over-etching may be small. This may result in low leakage current, and thus the performance of the formed BJT may be enhanced.

[0086] In some embodiments, the etchant also has a high etch rate for the lower base dielectric layer 112 relative to the etch rate of the intermediate base dielectric layer 116. Therefore, the intermediate base dielectric layer 116 masks portions of the underlying base dielectric layer 112. This results in a width W of the opening 902 of o The width W at the lower base dielectric layer 112 is smaller than that at the upper base dielectric layer 114. o The collector 118 may be smaller, so the exposed area of ​​the collector 118 in the opening 902 may be smaller. Therefore, the damage to the collector 118 due to over-etching and exposure to the surrounding environment may be less. Low damage may result in low leakage current, and thus the performance of the formed BJT may be enhanced. In some embodiments, the etchant also has a high etch rate for the lower base dielectric layer 112 relative to the etch rate of the upper hard mask layer 130 and / or relative to the etch rate of the sidewall spacer structure 134.

[0087] In some embodiments, the etchant has the same etch rate for the upper base dielectric layer 114 as for the lower base dielectric layer 112. In some embodiments, the etchant has a high etch rate for the upper base dielectric layer 114 relative to the etch rate of the intermediate base dielectric layer 116, the etch rate of the upper hard mask layer 130, the etch rate of the sidewall spacer structure 134, the etch rate of the collector 118, or any combination thereof.

[0088] The third etch may be implemented, for example, by wet etching, but other suitable types of etching are also possible. In some embodiments where the third etch is implemented by wet etching, the etchant may be, for example, a wet etchant comprising deionized water and 1% by mass of hydrogen fluoride. However, other suitable wet etchants and / or mass percentages are also possible. In some embodiments, the first etch and the third etch use the same etchant.

[0089] After the third etching is completed, the opening 902 extends below the first semiconductor layer 802 by a distance D4. The distance D4 is greater than Fig.11 902 , and may be, for example, about 10-50 nanometers, about 10-30 nanometers, about 30-50 nanometers, or some other suitable amount. As will be seen below, distance D4 corresponds to the overlap between the components of the base of the BJT to be formed. The larger the distance D4, the larger the contact area between the components. If distance D4 is too small (e.g., less than about 10 nanometers or other suitable values), the contact area may be small, and therefore the performance of the BJT will be poor. If distance D4 is too large (e.g., greater than about 50 nanometers or some other suitable value), the first semiconductor layer 802 may collapse into the opening 902 and the yield may be low.

[0090] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 1 , the lower base structure 108 is deposited at the bottom of the opening 902 to partially fill the opening 902. After the deposition is completed, the lower base structure 108 is located above the collector 118 and directly contacts the collector 118. In addition, the lower base structure 108 is located below the first semiconductor layer 802 and directly contacts the first semiconductor layer 802 at the contact area 120. Fig.12 Due to the lateral etching at , the contact area 120 may be larger.

[0091] Because the contact area 120 can be larger, the contact resistance between the lower base structure 108 and the first semiconductor layer 802 (e.g., the resistance at the contact area 120) can be smaller. As described below, the upper base structure is formed by the first semiconductor layer 802, and the lower base structure 108 and the upper base structure together define the base of the formed BJT. Because the contact area 120 can be larger, the resistance between the lower base structure 108 and the upper base structure can be smaller, and thus the total resistance of the base can be smaller. Because the resistance of the base can be smaller, the current through the BJT can be larger, and thus the conduction time of the BJT can be smaller. Due to the larger current and smaller conduction time, the conduction frequency of the BJT and the maximum oscillation frequency of the BJT can be higher.

[0092] The lower base structure 108 is a semiconductor material having a different band gap than the collector 118 and the first semiconductor layer 802, so that the lower base structure 108 directly contacts the collector 118 and the first semiconductor layer 802 at a heterojunction. In some embodiments, the lower base structure 108 has a lower band gap than the collector 118 and / or the first semiconductor layer 802. In addition, the lower base structure 108 has the same doping type as the first semiconductor layer 802 and the opposite doping type as the collector 118. The lower base structure 108 may be or include, for example, silicon germanium, germanium, some other suitable semiconductor, or any combination of the foregoing.

[0093] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , a second semiconductor layer 1502 is deposited to cover the multilayer hard mask film 804 and fill the opening 902 (see, for example, FIG. 1 ). Fig.14 ). In addition, the second semiconductor layer 1502 is deposited over the lower base structure 108 and directly contacts the lower base structure 108 .

[0094] The second semiconductor layer 1502 is a semiconductor material having a different band gap than the lower base structure 108, so that the second semiconductor layer 1502 directly contacts the lower base structure 108 at a heterojunction. In some embodiments, the second semiconductor layer 1502 has a higher band gap than the lower base structure 108. In addition, in some embodiments, the second semiconductor layer 1502 has the same or similar band gap as the first semiconductor layer 802 and / or the collector 118. The second semiconductor layer 1502 has a doping type opposite to the lower base structure 108 and / or the first semiconductor layer 802. In addition, the second semiconductor layer 1502 has the same doping type as the collector 118. The second semiconductor layer 1502 can be, for example, polysilicon and / or some other suitable semiconductor material. In some embodiments, the second semiconductor layer 1502 is the same material as the first semiconductor layer 802.

[0095] like Fig.16 As shown in the cross-sectional view 1600 of the embodiment, the patterned multilayer hard mask film 804 (see for example Fig.15 ) and a second semiconductor layer 1502 (see e.g. Fig.15 ) to form hard mask 126 and emitter 132 respectively. Emitter 132 may have, for example, Figure 2A and Figure 2B, or some other suitable top layout. Patterning may, for example, include: 1) forming a mask 1602 over the second semiconductor layer 1502; 2) etching the multilayer hard mask film 804 and the second semiconductor layer 1502 using the mask 1602 in place; and 3) removing the mask 1602. However, other suitable patterning processes are also possible. The mask 1602 may be, for example, a photoresist mask formed by photolithography or some other suitable type of mask. Etching may, for example, be performed by dry etching, but other suitable types of etching are also possible.

[0096] like Fig.17 As shown in the cross-sectional view 1700, the patterned first semiconductor layer 802 (for example, see Fig.16 ) to form an upper base structure 110. The upper base structure 110 may have, for example, Figure 2A and Figure 2B The lower base structure 108 and the upper base structure 110 together define the base 106, and the base 106, the collector 118 and the emitter 132 together define the BJT 102. As described above, due to Fig.11 Due to the lateral etching of the lower base structure 108 and the upper base structure 110, the contact area 120 between the lower base structure 108 and the upper base structure 110 is larger. The larger contact area reduces the resistance of the base 106 and enhances the performance of the BJT 102. For example, the conduction frequency of the BJT 102, the maximum oscillation frequency of the BJT 102, and other suitable parameters of the BJT 102 can be enhanced by the reduced resistance.

[0097] Patterning may, for example, include: 1) forming a mask 1702 over the emitter 132; 2) etching the first semiconductor layer 802 with the mask 1702 in place; and 3) removing the mask 1702. However, other suitable patterning processes are also possible. The mask 1702 may be, for example, a photoresist mask formed by photolithography or some other suitable type of mask. The etching may, for example, be performed by dry etching, but other suitable types of etching are also possible.

[0098] like Fig.18As shown in cross-sectional view 1800 of , interconnect structure 602 is formed to cover and electrically couple to BJT 102. Interconnect structure 602 includes a plurality of conductive lines 604, a plurality of contacts 606, and a plurality of vias 608 (only one of which is shown). Conductive lines 604, contacts 606, and vias 608 are stacked in interconnect dielectric layer 610 and define a conductive path leading out of BJT 102. Contacts 606 extend from base 106 and emitter 132, and conductive lines 604 and vias 608 are located above and electrically coupled to contacts 606. Although interconnect structure 602 is shown as having two levels of conductive lines and a single level of vias, in alternative embodiments, interconnect structure 602 may include additional levels of conductive lines and / or additional levels of vias.

[0099] Although the reference method describes Figures 7 to 18 , should understand, Figures 7 to 18 The structure shown is not limited to the method, but can exist independently of the method. Figures 7 to 18 Although described as a series of steps, it should be understood that the order of the steps may be changed in other embodiments. Figures 7 to 18 What is shown and described is a set of specific steps, but some of the steps shown and / or described may be omitted in other embodiments. In addition, steps not shown and / or described may be included in other embodiments.

[0100] Reference Fig.19 , provides Figures 7 to 18 Block diagram 1900 of some embodiments of the method.

[0101] In 1902, a doped region defining a collector and having a first doping type is formed in a semiconductor substrate. See, e.g. Figure 7 .

[0102] In 1904, a multi-layer base dielectric film is deposited over a semiconductor substrate, wherein the multi-layer dielectric film includes a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer located between the lower and upper layers. See, e.g. Figure 8 .

[0103] In 1906, a first semiconductor layer is deposited over the multilayer base dielectric film and has a second doping type opposite to the first doping type. See e.g. Figure 8 .

[0104] In 1908, a hard mask layer is deposited over the first semiconductor layer. See e.g. Figure 8 .

[0105] At 1910, the hard mask layer and the first semiconductor layer are patterned to form an opening that exposes the multilayer base dielectric film and is located above the collector. See, e.g. Fig. 9 .

[0106] In 1912, sidewall spacer structures are formed on the sidewalls of the opening. See e.g. Fig.10 .

[0107] In 1914, a first etch is performed on the upper dielectric layer to extend the opening to the middle dielectric layer and to extend the opening laterally below the first semiconductor layer, wherein the middle dielectric layer serves as an etch stop layer for the first etch. See, e.g. Fig.11 .

[0108] In 1916, additional etching is performed to extend the opening through the middle dielectric layer and the lower dielectric layer to the collector. See e.g. Fig.12 and Fig.13 .

[0109] In 1918, a lower base structure is deposited at the bottom of the opening to partially fill the opening, wherein the lower base structure is a semiconductor having a second doping type and directly contacts the collector and the first semiconductor layer at the heterojunction. See, e.g. Fig.14 .

[0110] At 1920, a second semiconductor layer is deposited filling the opening above the lower base structure and covering the hard mask layer, wherein the second semiconductor layer has the first doping type. See, e.g. Fig.15 .

[0111] In 1922, the first semiconductor layer and the second semiconductor layer are patterned to form an upper base structure and an emitter, respectively, wherein the lower base structure and the upper base structure are in direct contact to define a base. See, e.g. Fig.16 and Fig.17 .

[0112] In 1924, an interconnect structure electrically coupled to the BJT is formed over the BJT defined by the collector, emitter, and base. See e.g. Fig.18 .

[0113] Although this article will Fig.19 The block diagram 1900 is shown and described as a series of steps or events, but it should be understood that the order in which such steps or events are shown should not be interpreted as limiting. For example, in addition to those steps or events shown and / or described herein, some steps may occur in a different order and / or occur simultaneously with other steps or events. In addition, all of the steps shown may not be required to implement one or more aspects or embodiments of the description herein, and one or more steps described herein may be performed in one or more separate steps and / or stages.

[0114] Reference Figures 20 to 30 , a series of cross-sectional views 2000-3000 of some embodiments of a method of forming a BJT, wherein an upper base structure and an emitter are formed in a recess. Figure 3EThe method may be used, for example, to form a BJT, according to the embodiments shown and described in FIG. 8 , or other suitable embodiments.

[0115] like Fig. 20 As shown in the cross-sectional view 2000, a first trench isolation structure 124, a second trench isolation structure 402 and a collector 118 are formed in the semiconductor substrate 122, as shown in FIG. Figure 7 as described.

[0116] Still by Fig. 20 As shown in the cross-sectional view 2000 of , a base dielectric layer 306 is deposited over the semiconductor substrate 122. The base dielectric layer 306 may be, for example, or include silicon oxide, silicon oxynitride, some other suitable dielectric, or any combination of the foregoing. In addition, the base dielectric layer 306 may be deposited, for example, by CVD, PVD, thermal oxidation, some other suitable deposition process, or any combination of the foregoing.

[0117] In some embodiments, the thickness T of the base dielectric layer 306 is about 250-400 angstroms, about 250-325 angstroms, about 325-400 angstroms, about 350 angstroms, or some other suitable value. If the thickness T is too small (e.g., less than about 250 angstroms or other suitable values), the leakage current may be high. This in turn may adversely affect the performance of the formed BJT. If the thickness T is too large (e.g., greater than about 400 angstroms or some other suitable value), the lower base structure formed thereafter may be too thick, and therefore the base of the BJT may have a high resistance. The high resistance in turn may adversely affect the conduction frequency of the BJT, the maximum oscillation frequency of the BJT, and other suitable parameters of the BJT.

[0118] like Fig.21 2100, the base dielectric layer 306 is patterned to define a recess 2102 located above the collector 118. The recess 2102 extends partially but not completely through the base dielectric layer 306, so that the base dielectric layer 306 separates the recess 2102 from the collector 118. As described below, the recess 2102 can help reduce the resistance of the formed BJT and, therefore, can help enhance the performance of the BJT.

[0119] Patterning may, for example, include: 1) forming a mask 2104 having a layout of recesses 2102 over the base dielectric layer 306; 2) etching the base dielectric layer 306 with the mask 2104 in place; and 3) removing the mask 2104. However, other suitable patterning processes are also possible. The mask 2104 may, for example, be a photoresist mask formed by photolithography or some other suitable type of mask. The etching may, for example, be performed by dry etching, but other suitable types of etching are also possible.

[0120] like Fig. 22As shown in the cross-sectional view 2200 of FIG. 22, the first semiconductor layer 802 and the multi-layer hard mask film 804 are deposited to be stacked above the base dielectric layer 306 and lined with the recess 2102 (see, for example, FIG. 22). Fig.21 ). The multilayer hard mask film 804 is located on the first semiconductor layer 802 and includes a lower hard mask layer 128 and an upper hard mask layer 130. In an alternative embodiment, the lower hard mask layer 128 and / or the upper hard mask layer 130 are omitted. Figure 8 A first semiconductor layer 802 and a multi-layer hard mask film 804 are described as being deposited.

[0121] like Fig.23 and Fig.24 As shown in the cross-sectional views 2300 and 2400, the base dielectric layer 306 is used instead of the multilayer base dielectric film 104 to implement Fig. 9 and Fig.10 Steps. Fig.23 In the embodiment, the multilayer hard mask film 804 and the first semiconductor layer 802 are patterned to form an opening 902 located above the collector 118 and exposing the base dielectric layer 306, as described with reference to FIG. Fig. 9 Described. Fig.24 In the embodiment, the sidewall spacer structure 134 is formed as in Fig.10 On the side walls of the opening 902 described.

[0122] like Fig.25 2500, the base dielectric layer 306 is etched through the opening 902. The etch vertically etches the base dielectric layer 306 and stops on the collector 118 to extend the opening 902 to the collector 118. In addition, the etch laterally etches the base dielectric layer 306 to extend the opening 902 below the sidewall spacer structure 134 and the first semiconductor layer 802. Therefore, the etch undercuts the sidewall spacer structure 134 and the first semiconductor layer 802.

[0123] Relative to the etching rate of the collector 118, the etching adopts an etchant having a high etching rate for the base dielectric layer 306, so the overetching of the collector 118 is low. Due to the lower overetching, the damage to the collector 118 by overetching may be less. The high etching rate can be, for example, about 10-40 times, about 20-30 times, about 20 times, or about 30 times the etching rate of the collector 118. However, other suitable multiples are also possible. In some embodiments, the etchant also has a high etching rate for the base dielectric layer 306 relative to the etching rate of the upper hard mask layer 130 and / or relative to the etching rate of the sidewall spacer structure 134. Etching can be implemented, for example, by wet etching, but other suitable types of etching are also possible. In some embodiments where etching is implemented by wet etching, the etchant can be, for example, a wet etchant including deionized water and 1% by mass of hydrogen fluoride. However, other suitable wet etchants and / or mass percentages are also possible.

[0124] After the etching is completed, the bottom of the opening 902 has an elliptical profile (eg, a profile with a high aspect ratio) extending below the first semiconductor layer 802. Fig.21 The groove 2102 formed in Fig.21 ), the first semiconductor layer 802 wraps around the top corners of the base dielectric layer 306 and extends below the top surface of the base dielectric layer 306. As a result, the interval S between the bottom surface of the first semiconductor layer 802 and the semiconductor substrate 122 is reduced. Because the interval S is reduced, the bottom of the opening 902 has a more elliptical profile compared to the case where the groove 2102 is not formed.

[0125] It should be appreciated that by reducing the spacing S, the etching can more effectively remove the base dielectric layer 306 from the bottom surface of the first semiconductor layer 802. Therefore, more of the bottom surface is exposed in the opening 902. As will be seen below, this results in an increase in the contact area between the components of the base of the formed BJT. The increased contact area reduces the resistance of the base and, therefore, reduces the conduction time of the BJT. This, in turn, enhances the conduction frequency of the BJT, the maximum oscillation frequency of the BJT, and other suitable parameters of the BJT.

[0126] like Figures 26 to 30 As shown in the cross-sectional views 2600-3000, the implementation Figures 14 to 18 Steps. Fig.26 In the embodiment, the lower base structure 108 is deposited to partially fill the opening 902 at the bottom of the opening 902, as described with respect to Fig.14 Described. Fig.21 The groove formed at Fig.21) allows more of the first semiconductor layer 802 to be exposed in the opening 902, thereby making the contact area 120 between the lower base structure 108 and the first semiconductor layer 802 larger and enhancing the performance of the formed BJT. Fig. 27 In the embodiment, the second semiconductor layer 1502 is deposited to cover the multilayer hard mask film 804 and fill the hard mask film 804 as described above. Fig.15 The opening 902 described (see e.g. Fig.26 ).exist Fig.28 In the process, the multilayer hard mask film 804 (see for example Fig. 27 ) and a second semiconductor layer 1502 (see e.g. Fig. 27 ) to form respectively as about Fig.16 The hard mask 126 and the emitter 132 are described. Fig.29 In the process, the first semiconductor layer 802 is patterned (see for example Fig.28 ) to form Fig.17 The upper base structure 110 is depicted. The lower base structure 108 and the upper base structure 110 together define the base 106, and the base 106, the collector 118, and the emitter 132 together define the BJT 102. Fig.30 , the interconnect structure 602 is formed to cover and electrically couple to Fig.18 BJT 102 as described.

[0127] Although the reference method describes Figures 20 to 30 , but it should be understood that Figures 20 to 30 The structure shown is not limited to this method, but can be used independently of this method. Figures 20 to 30 Although described as a series of steps, it should be understood that the order of the steps may be changed in other embodiments. Figures 20 to 30 What is shown and described is a set of specific steps, but some of the steps shown and / or described may be omitted in other embodiments. In addition, steps not shown and / or described may be included in other embodiments.

[0128] Reference Fig.31 , provides Figures 20 to 30 Block diagram 3100 of some embodiments of the method.

[0129] In 3102, a doped region defining a collector and having a first doping type is formed in a semiconductor substrate. See, e.g. Fig. 20 .

[0130] In 3104, a base dielectric layer is deposited over the semiconductor substrate. See e.g. Fig. 20 .

[0131] In 3106, the base dielectric layer is patterned to form a recess above the collector. See, e.g. Fig.21 .

[0132] In 3108, a first semiconductor layer is deposited over the base dielectric layer and has a second doping type opposite to the first doping type. See e.g. Fig. 22 .

[0133] In 3110, a hard mask layer is deposited over the first semiconductor layer. See e.g. Fig. 22 .

[0134] In 3112, the hard mask layer and the first semiconductor layer are patterned to form an opening that exposes the base dielectric layer and is located above the collector. See, e.g. Fig.23 .

[0135] In 3114, a sidewall spacer structure is formed on the sidewalls of the opening. See, e.g. Fig.24 .

[0136] In 3116, the base dielectric layer is etched to extend the opening to the collector and to extend the opening laterally below the first semiconductor layer. See e.g. Fig.25 .

[0137] In 3118, a lower base structure is deposited to partially fill the opening at the bottom of the opening, wherein the lower base structure is a semiconductor having the second doping type and directly contacts the collector and the first semiconductor layer at the heterojunction. See e.g. Fig.26 .

[0138] In 3120, a second semiconductor layer is deposited to fill the opening above the lower base structure and cover the hard mask layer, wherein the second semiconductor layer has the first doping type. See, e.g. Fig. 27 .

[0139] In 3122, the first semiconductor layer and the second semiconductor layer are patterned to form an upper base structure and an emitter, respectively, wherein the lower base structure and the upper base structure are in direct contact to define a base. See, e.g. Fig.28 and Fig.29 .

[0140] In 3124, an interconnect structure is formed over and electrically coupled to the BJT defined by the collector, emitter, and base. See e.g. Fig.30 .

[0141] Although here Fig.31The block diagram 3100 is shown and described as a series of steps or events, but it should be understood that the order in which such steps or events are shown should not be interpreted as limiting. For example, in addition to those steps or events shown and / or described herein, some steps may occur in a different order and / or occur simultaneously with other steps or events. In addition, all of the steps shown may not be required to implement one or more aspects or embodiments of the description herein, and one or more steps described herein may be performed in one or more separate steps and / or stages.

[0142] The present invention provides a BJT, comprising: a substrate; a dielectric film located on the substrate and including a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer located between the lower dielectric layer and the upper dielectric layer; a lower base structure located on the intermediate dielectric layer and protruding to the substrate through the intermediate dielectric layer and the lower dielectric layer; an upper base structure located on the lower base structure, wherein the lower base structure and the upper base structure are different semiconductors and are in direct contact at a heterojunction; and an emitter located on the upper base structure and extending through the upper base structure to the lower base structure. In some embodiments, the dielectric film includes a first dielectric and a second dielectric, wherein the lower dielectric layer and the upper dielectric layer include the first dielectric, and wherein the intermediate dielectric layer includes the second dielectric. In some embodiments, the lower base structure includes germanium, wherein the upper base structure is essentially composed of silicon. In some embodiments, the upper base structure has an outer sidewall facing away from the emitter and an inner sidewall facing the emitter, wherein the sidewall of the lower base structure is located on the intermediate dielectric layer laterally located between the inner sidewall and the outer sidewall and laterally spaced apart from the inner sidewall and the outer sidewall. In some embodiments, the lower base structure has a T-shaped profile. In some embodiments, the emitter is a semiconductor and directly contacts the lower base structure at a heterojunction. In some embodiments, a top surface of the lower base structure and a top surface of the upper dielectric layer are substantially flat. In some embodiments, the substrate includes a doped region defining a collector and located below the lower base structure, wherein the doped region has a doping type opposite to that of the lower base structure and the upper base structure.

[0143] In some embodiments, the present invention provides another BJT, comprising: a semiconductor substrate; a multilayer dielectric film located above the semiconductor substrate and including a first dielectric layer buried in the multilayer dielectric film; an upper base structure located above the multilayer dielectric film; a lower base structure embedded in the multilayer dielectric film and extending through the multilayer dielectric film to the semiconductor substrate, wherein the lower base structure has a first sidewall located below the upper base structure and located above the first dielectric layer, wherein the lower base structure also has a second sidewall that is laterally offset from the first sidewall and faces and abuts the sidewall of the first dielectric layer, wherein the lower base structure and the upper base structure are different semiconductors; and an emitter extending through the upper base structure to the lower base structure. In some embodiments, the multilayer dielectric film is an ONO film, wherein the first dielectric layer includes a nitride. In some embodiments, the BJT also includes a sidewall spacer structure that laterally separates the emitter from the upper base structure, wherein the second sidewall is located below the sidewall spacer structure. In some embodiments, the first and second sidewalls are annular. In some embodiments, the width of the lower base structure decreases discretely from top to bottom. In some embodiments, the lower base structure has a lower bandgap than the upper base structure. In some embodiments, the emitter and upper base structures include polycrystalline semiconductor material.

[0144] In some embodiments, the present invention provides another BJT, comprising: a semiconductor substrate; a dielectric film located on the semiconductor substrate; a lower base structure embedded in the dielectric film and contacting the semiconductor substrate; an upper base structure located on the lower base structure and the dielectric film, wherein the upper base structure wraps the top corner of the dielectric film from the top surface of the dielectric film to the sidewall of the dielectric film; wherein the upper base structure extends to the lower base structure along the sidewall of the dielectric film, and wherein the lower base structure and the upper base structure are different semiconductors; and an emitter extending through the upper base structure to the lower base structure. In some embodiments, the lower base structure has a lower band gap than the upper base structure. In some embodiments, the emitter and the upper base structure include polycrystalline semiconductor material. In some embodiments, the dielectric film is an ONO film. In some embodiments, the BJT further comprises: a sidewall spacer structure that laterally separates the emitter from the upper base structure, wherein the bottom surface of the sidewall spacer structure is recessed relative to the top surface of the dielectric film. In some embodiments, the bottom surface of the upper base structure and the bottom surface of the emitter are substantially flat and recessed relative to the top surface of the dielectric film. In some embodiments, the lower base structure has a curved elliptical profile.

[0145] In some embodiments, the present invention provides a method for forming a BJT, the method comprising: depositing a film including a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer located between the lower dielectric layer and the upper dielectric layer on a substrate; depositing a first semiconductor layer on the film; patterning the first semiconductor layer to form an opening exposing the film; performing a first etching on the upper dielectric layer through the opening to extend the opening to the intermediate dielectric layer, wherein the first etching stops on the intermediate dielectric layer and laterally undercuts the first semiconductor layer; performing additional etching to extend the opening to the substrate; forming a lower base structure and an emitter stacked and filled in the opening, wherein the lower base structure and the emitter are semiconductors; and patterning the first semiconductor layer to form an upper base structure. In some embodiments, the first etching comprises wet etching. In some embodiments, the formation of the lower base structure comprises depositing a lower base structure directly contacting the bottom surface of the first semiconductor layer at the bottom of the opening. In some embodiments, the additional etching is performed by: performing a second etching on the intermediate dielectric layer to extend the opening to the lower dielectric layer, wherein the second etching stops on the lower dielectric layer; and performing a third etching on the lower dielectric layer to extend the opening to the substrate, wherein the third etching stops on the substrate; wherein the second and third etchings are performed by dry etching and wet etching, respectively. In some embodiments, the method also includes forming a doped semiconductor region in the substrate, wherein the doped semiconductor region defines a collector and has the same doping type as the emitter, and wherein the opening is formed to be located above the doped semiconductor region.

[0146] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A bipolar junction transistor (BJT), comprising: substrate; a dielectric film located on the substrate and comprising a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer located between the lower dielectric layer and the upper dielectric layer; a lower base structure located above the middle dielectric layer and protruding to the substrate through the middle dielectric layer and the lower dielectric layer; an upper base structure located above the lower base structure, wherein the lower base structure and the upper base structure are different semiconductors and contact at a heterojunction; and an emitter located above the upper base structure and extending through the upper base structure to the lower base structure, wherein the first portion of the lower base structure located in the lower dielectric layer has a width that decreases discretely from top to bottom, The upper base structure wraps around the top corner of the dielectric film from the top surface of the dielectric film to the sidewall of the dielectric film, and the upper base structure extends along the sidewall of the dielectric film to the lower base structure.

2. The bipolar junction transistor according to claim 1, wherein: The dielectric film includes a first dielectric and a second dielectric, and wherein the lower dielectric layer and the upper dielectric layer include the first dielectric, and wherein the intermediate dielectric layer includes the second dielectric.

3. The bipolar junction transistor according to claim 1, wherein: The lower base structure includes germanium, and wherein the upper base structure consists essentially of silicon.

4. The bipolar junction transistor according to claim 1, wherein: The upper base structure has an outer sidewall facing away from the emitter and an inner sidewall facing the emitter, and wherein the sidewall of the lower base structure is located above the intermediate dielectric layer, and the intermediate dielectric layer is laterally located between the inner sidewall and the outer sidewall and is laterally spaced apart from the inner sidewall and the outer sidewall.

5. The bipolar junction transistor according to claim 1, wherein: The lower base structure has a T-shaped profile.

6. The bipolar junction transistor according to claim 1, wherein: The emitter is a semiconductor and directly contacts the lower base structure at a heterojunction.

7. The bipolar junction transistor according to claim 1, wherein: A top surface of the lower base structure and a top surface of the upper dielectric layer are substantially flat.

8. The bipolar junction transistor according to claim 1, wherein: The substrate includes a doped region defining a collector and underlying the lower base structure, and wherein the doped region has an opposite doping type to the lower base structure and the upper base structure.

9. A bipolar junction transistor (BJT), comprising: Semiconductor substrate; A dielectric film, located on the semiconductor substrate; a lower base structure embedded in the dielectric film and contacting the semiconductor substrate; an upper base structure located above the lower base structure and the dielectric film, wherein the upper base structure wraps around a top corner of the dielectric film from a top surface of the dielectric film to a sidewall of the dielectric film, wherein the upper base structure extends along the sidewall of the dielectric film to the lower base structure, and wherein the lower base structure and the upper base structure are different semiconductors; and An emitter extends through the upper base structure to the lower base structure.

10. The bipolar junction transistor according to claim 9, wherein: The lower base structure has a lower bandgap than the upper base structure.

11. The bipolar junction transistor according to claim 9, wherein: The emitter and the upper base structure include polycrystalline semiconductor material.

12. The bipolar junction transistor according to claim 9, wherein: The dielectric film is an oxide-nitride-oxide (ONO) film.

13. The bipolar junction transistor according to claim 9, further comprising: A sidewall spacer structure laterally separates the emitter from the upper base structure, wherein a bottom surface of the sidewall spacer structure is recessed relative to a top surface of the dielectric film.

14. The bipolar junction transistor according to claim 9, wherein: A bottom surface of the upper base structure and a bottom surface of the emitter are substantially flat and recessed relative to a top surface of the dielectric film.

15. The bipolar junction transistor according to claim 9, wherein: The lower base structure has a curved elliptical profile.

16. A method of forming a bipolar junction transistor (BJT), the method comprising: Depositing a film including a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer between the lower dielectric layer and the upper dielectric layer on a substrate; depositing a first semiconductor layer over the film; patterning the first semiconductor layer to form an opening exposing the film; performing a first etch on the upper dielectric layer through the opening to extend the opening to without passing through the middle dielectric layer, wherein the first etch stops on the middle dielectric layer and laterally undercuts the first semiconductor layer; performing at least one additional etch to extend the opening to the substrate; forming a lower base structure and an emitter stacked in and filling the opening, wherein the lower base structure and the emitter are semiconductors; and patterning the first semiconductor layer to form an upper base structure, wherein the first etching exposes a portion of the bottom surface of the first semiconductor layer when the lateral undercut is performed without passing through the intermediate dielectric layer, and the lower base structure contacts the portion of the bottom surface, The upper base structure wraps around the top corner of the film from the top surface of the film to the side wall of the film, and the upper base structure extends along the side wall of the film to the lower base structure.

17. The method according to claim 16, wherein: The first etching includes wet etching.

18. The method according to claim 16, wherein: The forming of the lower base structure includes depositing the lower base structure directly contacting a bottom surface of the first semiconductor layer at a bottom of the opening.

19. The method according to claim 16, wherein: The performing of the at least one additional etch comprises: performing a second etch on the middle dielectric layer to extend the opening to the lower dielectric layer, wherein the second etch stops on the lower dielectric layer; and performing a third etching on the lower dielectric layer to extend the opening to the substrate, wherein the third etching stops on the substrate; The second etching and the third etching are performed by dry etching and wet etching respectively.

20. The method of claim 16, further comprising: A doped semiconductor region is formed in the substrate, wherein the doped semiconductor region defines a collector and has the same doping type as the emitter, and wherein the opening is formed above the doped semiconductor region.

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