Chip carrier plate and manufacturing method thereof, and chip packaging structure

Abstract

The embodiment of the invention provides a chip carrier plate and a manufacturing method thereof, a chip packaging structure, and a manufacturing method of the chip carrier plate, and the method comprises the steps: forming a first protection layer on a first surface of a glass substrate, forming a plurality of first through holes in the first protection layer, carrying out the laser induction of the glass substrate through the first through holes, and forming a plurality of induction regions, and in the induction area, etching the glass substrate to form a plurality of second through holes penetrating through the glass substrate, and forming conductive connection parts in the second through holes. The first protection layer with the first through hole is manufactured on one side of the glass substrate, the first protection layer exposes the area, needing laser induction, on the glass substrate, the area, not needing laser induction, on the glass substrate is protected, and it is avoided that when the glass substrate is etched subsequently, etching damage is caused to other positions of the surface of the glass substrate. Therefore, the thickness of the glass substrate can be ensured, and the surface quality such as roughness of the surface of the glass substrate can be ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, in particular to a chip carrier plate, a manufacturing method thereof and a chip packaging structure. BACKGROUND

[0002] With the rapid development of high-performance chips and their packaging technology, chip carrier plates are gradually replacing organic substrates due to their superior physical, chemical and electrical properties. In the packaging process, glass can better withstand higher temperatures than organic substrates, and has a similar thermal expansion coefficient to silicon, thereby reducing stress warping problems caused by thermal mismatch. In addition, the high flatness and low roughness of the glass surface can achieve more dense wiring, the extremely low dielectric constant and dielectric loss of the glass material can improve signal transmission speed and signal integrity, and the chemical stability of the glass material is excellent, which can effectively resist environmental erosion such as moisture, acid and alkali.

[0003] TGV (Through Glass Via, glass via) is one of the cores of the chip carrier plate, and the hole forming and filling of TGV are currently still production difficulties. SUMMARY

[0004] In order to overcome the technical problems mentioned in the above technical background, the embodiments of the present application provide a manufacturing method of a chip carrier plate, comprising: forming a first protective layer on a first surface of a glass substrate; forming a plurality of first through holes on the first protective layer; forming a plurality of induced regions by laser induction on the glass substrate through the first through holes; forming a plurality of second through holes penetrating the glass substrate by etching the glass substrate in the induced regions; forming a conductive connecting part in the second through holes.

[0005] In some embodiments, before forming a plurality of first through holes on the first protective layer, the manufacturing method further comprises: forming a second protective layer on a second surface of the glass substrate; wherein the bottom of the first through hole is shielded by the second protective layer.

[0006] In some embodiments, the second protective layer comprises a conductive material; Preferably, the conductive connecting part is formed in the second through hole by electroplating; Preferably, the first protective layer comprises a conductive material; Preferably, the materials of the first protective layer and the second protective layer are the same; Preferably, the material of the second protective layer comprises one or a combination of gold, platinum, palladium, iridium, titanium, tantalum, and nickel.

[0007] In some embodiments, the forming the conductive connection portion in the second via by electroplating comprises: forming conductive connection material in the second via and on a side of the first protective layer facing away from the glass substrate by electroplating; and removing the first protective layer, the second protective layer, and the conductive connection material outside the second via, and the conductive connection material in the second via is the conductive connection portion.

[0008] In some embodiments, before forming the conductive connection portion in the second via, the manufacturing method further comprises: forming a seed layer on at least an inner wall of the second via; and forming the conductive connection portion in the second via on a surface of the seed layer by electroplating; Preferably, the seed layer is formed on the inner wall of the second via and on a side of the first protective layer facing away from the glass substrate. Preferably, the first protective layer comprises a non-conductive material. Preferably, the first protective layer and the second protective layer are made of the same material.

[0009] In some embodiments, the first protective layer comprises one or a combination of polyimide, polytetrafluoroethylene, photoresist, and Ajinomoto Build-up Film. In some embodiments, the forming the conductive connection portion in the second via by electroplating comprises: forming conductive connection material in the second via and on a side of the seed layer facing away from the glass substrate outside the second via by electroplating; and removing the first protective layer, the second protective layer, and the conductive connection material and the seed layer outside the second via, and the conductive connection material and the seed layer in the second via are the conductive connection portion.

[0010] In some embodiments, before forming the plurality of first vias on the first protective layer, the manufacturing method further comprises: forming a first circuit layer connected to the conductive connection portion on the first surface of the glass substrate, and forming a second circuit layer connected to the conductive connection portion on the second surface of the glass substrate; Preferably, the first circuit layer comprises at least one conductive circuit. Preferably, the first circuit layer comprises a plurality of conductive circuit layers and a dielectric layer arranged between two adjacent conductive circuit layers, and the two adjacent conductive circuit layers are electrically connected through through holes of the dielectric layer. Preferably, the second circuit layer comprises at least one conductive circuit layer. Preferably, the second circuit layer comprises a plurality of conductive circuit layers and a dielectric layer arranged between two adjacent conductive circuit layers, and the two adjacent conductive circuit layers are electrically connected through through holes of the dielectric layer. Preferably, the manufacturing method further comprises, after manufacturing the first circuit layer connected with the conductive connecting part on the first surface of the glass substrate and manufacturing the second circuit layer connected with the conductive connecting part on the second surface of the glass substrate: forming a solder mask layer on the side of the first circuit layer and the second circuit layer away from the glass substrate, and forming a plurality of windows on the solder mask layer, the windows exposing part of the surface of the first circuit layer and the second circuit layer; manufacturing a surface treatment layer on the surface of the first circuit layer and the second circuit layer exposed in the windows.

[0011] In some embodiments, the first through hole is formed on the first protective layer by laser cutting. Alternatively, the first through hole is formed on the first protective layer by a mask process.

[0012] Another object of the embodiments of the present application is to provide a chip carrier, comprising: a glass substrate, the glass substrate being provided with a plurality of second through holes; a conductive connecting part arranged in each of the second through holes; a first circuit layer arranged on one side of the glass substrate and connected with one end of the conductive connecting part; and a second circuit layer arranged on the other side of the glass substrate and connected with the other end of the conductive connecting part.

[0013] Still another object of the embodiments of the present application is to provide a chip packaging structure, comprising: a main board; a chip carrier manufactured by the manufacturing method of any of the above embodiments or the chip carrier of any of the above embodiments, the chip carrier being arranged on one side of the main board and electrically connected with the main board; and a chip arranged on the side of the chip carrier away from the main board and electrically connected with the chip carrier. The chip carrier and the manufacturing method thereof and the chip packaging structure provided by the embodiments of the present application have the following beneficial effects: The chip carrier manufacturing method provided by the embodiment of the present application comprises the following steps: manufacturing a first protective layer with a first through hole on one side of a glass substrate; the first protective layer exposes a region on the glass substrate that needs to be induced by laser; and the region on the glass substrate that does not need to be induced by laser is protected, so as to avoid etching damage to other positions on the surface of the glass substrate in the subsequent etching of the glass substrate. This can ensure the thickness of the glass substrate and the surface quality such as the roughness of the surface of the glass substrate. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0015] Figure 1 is a step flow chart of the chip carrier manufacturing method provided by an embodiment of the present application; Figure 2 is a structure diagram corresponding to step S1 in the chip carrier manufacturing method provided by an embodiment of the present application; Figure 3 is a structure diagram corresponding to step S2 in the chip carrier manufacturing method provided by an embodiment of the present application; Figure 4 is a structure diagram corresponding to step S3 in the chip carrier manufacturing method provided by an embodiment of the present application; Figure 5 is a structure diagram corresponding to step S4 in the chip carrier manufacturing method provided by an embodiment of the present application; Figure 6 is a structure diagram corresponding to substep S51 of step S5 in the chip carrier manufacturing method provided by an embodiment of the present application; Figure 7 is a structure diagram corresponding to substep S52 of step S5 in the chip carrier manufacturing method provided by an embodiment of the present application; Figure 8 is a structure diagram corresponding to step S6 in the chip carrier manufacturing method provided by an embodiment of the present application; Figure 9 is a structure diagram corresponding to step S7 in the chip carrier manufacturing method provided by an embodiment of the present application; Figure 10 is a structure diagram corresponding to step S8 in the chip carrier manufacturing method provided by an embodiment of the present application; Figure 11 is a flow chart of step S5 in the chip carrier manufacturing method provided by another embodiment of the present application; Figure 12 is a structure diagram corresponding to substep S511' of step S5 in the method for manufacturing the chip carrier provided in another embodiment of the present application; Figure 13 is a structure diagram corresponding to substep S512' of step S5 in the method for manufacturing the chip carrier provided in another embodiment of the present application; Figure 14 is a structure diagram corresponding to substep S52' of step S5 in the method for manufacturing the chip carrier provided in another embodiment of the present application; Figure 15 is a structure diagram corresponding to substep S21'' of step S2 in the method for manufacturing the chip carrier provided in another embodiment of the present application; Figure 16 is a structure diagram corresponding to substep S22'' of step S2 in the method for manufacturing the chip carrier provided in another embodiment of the present application; Figure 17 is a structure diagram corresponding to substep S23'' of step S2 in the method for manufacturing the chip carrier provided in another embodiment of the present application; Figure 18 is a structure diagram corresponding to substep S24'' of step S2 in the method for manufacturing the chip carrier provided in another embodiment of the present application; Figure 19 is a structure diagram of the chip package structure provided in another embodiment of the present application. Legend of reference signs: 400 - chip package structure; 300 - chip, 200 - mainboard; 100 - chip carrier; 10 - glass substrate, 11 - first surface, 12 - second surface, 13 - second through hole, 14 - induced area; 20 - first protective layer, 21 - first through hole; 30 - second protective layer; 40 - conductive connecting part, 41 - conductive connecting material; 50 - seed layer; 61 - first circuit layer, 62 - second circuit layer, 63 - conductive circuit, 64 - dielectric layer; 70 - solder resist layer, 71 - window; 80 - surface treatment layer, 81 - conductive connecting bump; 91 - mask, 92 - third photoresist material layer, 921 - exposed area, 922 - non-exposed area, 923 - third photoresist pattern. DETAILED DESCRIPTION In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings for the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0016] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application.

[0017] It should be noted that similar reference numbers and letters represent similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. It should be noted that different features in the embodiments of the present application can be combined with each other without conflict.

[0018] For easy understanding, the X-axis, Y-axis and Z-axis which are orthogonal to each other are shown in the drawings. The direction along the X-axis is referred to as the X direction, the direction along the Y-axis is referred to as the Y direction, and the direction along the Z-axis is referred to as the Z direction. The Z direction is the normal direction with respect to the plane including the X direction and the Y direction. In addition, the case where various elements are observed in parallel with the plane including the X direction and the Y direction is referred to as a plan view. Alternatively, the plane of the X direction and the Y direction is a plane parallel to the display surface of the display panel, and the Z direction is a direction parallel to the thickness direction of the display panel.

[0019] For some elements, the terms "upper" or "above" are used when describing the position of an element in the Z direction, and the terms "lower" or "below" are used when describing the position of an element in the opposite direction. In addition, when the terms "upper", "above", "lower", "below", "relative" and the like are used to define the positional relationship between two elements, they not only include the state where the two elements are directly connected, but also include the state where the two elements are separated by a gap or other elements. In addition, the terms "first", "second", "third" and the like are only used for differentiation and cannot be understood as indicating or implying relative importance.

[0020] In the manufacturing process of the chip carrier, the chemical properties of part of the area of the glass are changed by using laser-induced glass, and then in the etching process, the etching rates of the induced area and the non-induced area change obviously, so that the induced area can be etched and removed, and a via hole is manufactured.

[0021] In the etching process, due to the action of the etching solution, not only the induced area is etched away, but also the surface of the non-induced area can be partially etched away, resulting in the thickness of the entire glass being thinned, and also causing quality problems such as rough and concave glass surface.

[0022] As shown in Figure 1 , the embodiment of the present application provides a chip carrier manufacturing method, which comprises: Step S1, as shown in Figure 2 , a first protective layer 20 is manufactured on the first surface 11 of the glass substrate 10; Step S2, as shown in Figure 3 , a plurality of first through holes 21 are formed on the first protective layer 20; Step S3, as shown in Figure 4 , the glass substrate 10 is laser-induced through the first through holes 21 to form a plurality of induced areas 14; Step S4, as shown in Figure 5 , the glass substrate 10 is etched at the induced areas 14 to form a plurality of second through holes 13 penetrating the glass substrate 10; and Step S5, as shown in Figure 6 and Figure 7 , a conductive connection part 40 is formed in the second through hole 13.

[0023] In the thickness direction of the glass substrate 10, the first through hole 21 corresponds to the position of the induced area 14 and the second through hole 13.

[0024] The chip carrier manufacturing method provided by the embodiment of the present application can protect the area of the glass substrate 10 that does not need laser induction and etching by manufacturing a first protective layer 20 with a first through hole 21 on one side of the glass substrate 10, and the first protective layer 20 exposes the area of the glass substrate 10 that needs laser induction and etching, thereby avoiding etching damage to other positions on the surface of the glass substrate 10 during subsequent etching of the glass substrate 10. This can ensure the thickness of the glass substrate 10 while ensuring the surface roughness and other surface quality of the glass substrate 10.

[0025] Laser induction is an advanced process that uses high-energy laser beams to interact with materials, inducing physical or chemical changes in the materials to achieve specific processing or preparation purposes. The core of this process is "induction", that is, triggering the change of the material itself by the energy of the laser, rather than traditional mechanical force or chemical corrosion.

[0026] The implementation of laser induction mainly depends on the following three key steps: Energy absorption: the material absorbs laser energy of a specific wavelength, converting light energy into heat, electricity or chemical energy.

[0027] State change: The absorbed energy causes the material to locally reach a specific condition, triggering changes such as melting, vaporization, oxidation, crystallization, or breaking / reforming of chemical bonds.

[0028] Precise control: By controlling the power, spot size, scanning path, and action time of the laser, the area and degree of material change are precisely controlled to achieve the desired structure or function.

[0029] As shown in Figure 2 , the glass substrate 10 also has a second surface 12 arranged opposite to the first surface 11.

[0030] The second via hole 13 produced in step S4 connects the first surface 11 and the second surface 12.

[0031] In some embodiments of the present application, as shown in Figure 1 , step S1 further includes: as shown in Figure 2 , producing a second protective layer 30 on the second surface 12 of the glass substrate 10.

[0032] As shown in Figure 5 , the bottom of the second via hole 13 produced in step S4 is shielded by the second protective layer 30.

[0033] The purpose of this arrangement is that one side of the second via hole 13 is shielded, so that the second via hole 13 can be essentially a blind hole, thus facilitating the formation of a conductive connection part 40 inside it, and the second protective layer 30 acts as a physical connection bridge (including conductive bridges and non-conductive bridges) of the second surface 12 of the glass substrate 10 to carry the conductive connection part 40. At the same time, the second protective layer 30 can also protect the second surface 12 of the glass substrate 10 in step S4, avoiding damage to the second surface 12 of the glass substrate 10 in step S4.

[0034] In some embodiments of the present application, as shown in Figure 6 and Figure 7 , the production method further includes step S5: Step S51, as shown in Figure 6 , forms a conductive connection part 40 at least in the second via hole 13; further including: Step S52, as shown in Figure 7 , remove the first protective layer 20 and the second protective layer 30 to expose the first surface 11 and the second surface 12 of the glass substrate 10, and expose the opposite ends of the conductive connection part 40.

[0035] As shown in Figure 7 , the structure obtained after step S5 is that the second via hole 13 of the glass substrate 10 is filled with the conductive connection part 40, and the two ends of the conductive connection part 40 are flush with the first surface 11 and the second surface 12, respectively.

[0036] As shown in Figure 1 some embodiments of the present application, the manufacturing method further comprises: Step S6, as shown in Figure 8 forming a first circuit layer 61 connected with the conductive connecting part 40 on the first surface 11 of the glass substrate 10, and forming a second circuit layer 62 connected with the conductive connecting part 40 on the second surface 12 of the glass substrate 10; and Step S7, as shown in Figure 9 forming a solder resist layer 70 on the side of the first circuit layer 61 and the second circuit layer 62 away from the glass substrate 10, and forming a plurality of openings 71 on the solder resist layer 70, the openings 71 exposing part of the surface of the first circuit layer 61 and the second circuit layer 62.

[0037] As shown in Figure 1 some embodiments of the present application, the manufacturing method further comprises: Step S8, as shown in Figure 10 forming a surface treatment layer 80 on the surface exposed by the first circuit layer 61 and the second circuit layer 62.

[0038] In some embodiments of the present application, in Step S4, the glass substrate 10 is etched by wet etching to remove the inducing area 14 and form a plurality of second through holes 13 penetrating the glass substrate 10.

[0039] In some embodiments of the present application, in Figure 2 the first through hole 21 is formed on the first protective layer 20 by laser cutting.

[0040] In some embodiments of the present application, the material of the first protective layer 20 and the second protective layer 30 is preferably selected to be not easily damaged by etching solution in Step S4.

[0041] In some embodiments of the present application, the first protective layer 20 can be a conductive material or a non-conductive material.

[0042] In some embodiments, the first protective layer 20 comprises a conductive material. In some optional embodiments, the first protective layer 20 comprises a metal material.

[0043] In some embodiments, the first protective layer 20 comprises one or more of gold (Au), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), tantalum (Ta), nickel (Ni), etc.

[0044] In some embodiments, the first protective layer 20 is a single layer of material or multiple layers of material. In some alternative embodiments, the first protective layer 20 includes one or more of a layer of gold (Au), a layer of platinum (Pt), a layer of palladium (Pd), a layer of iridium (Ir), a layer of titanium (Ti), a layer of tantalum (Ta), a layer of nickel (Ni), or the like.

[0045] In some embodiments, the second protective layer 30 can be an electrically conductive material or an electrically non-conductive material.

[0046] In some embodiments, the second protective layer 30 includes an electrically conductive material. In some alternative embodiments, the second protective layer 30 includes a metallic material.

[0047] In some embodiments, the second protective layer 30 includes one or more of a combination of gold (Au), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), tantalum (Ta), nickel (Ni), or the like.

[0048] In some embodiments, the second protective layer 30 is a single layer of material or multiple layers of material. In some alternative embodiments, the second protective layer 30 includes one or more of a layer of gold (Au), a layer of platinum (Pt), a layer of palladium (Pd), a layer of iridium (Ir), a layer of titanium (Ti), a layer of tantalum (Ta), a layer of nickel (Ni), or the like.

[0049] In some embodiments, as shown in FIG. 2A, the thickness H1 of the first protective layer 20 is less than or equal to 10 micrometers. The thickness H1 of the first protective layer 20 is avoided to be too large, so as to avoid increasing the difficulty of manufacturing the first via hole 21 in step S2 and increasing the difficulty of removing the first protective layer 20 in step S5. Figure 2

[0050] In some alternative embodiments, the thickness H1 of the first protective layer 20 is greater than or equal to 1 micrometer and less than or equal to 10 micrometers. The thickness H1 of the first protective layer 20 is avoided to be too small, so as to facilitate ensuring that the first protective layer 20 is completely formed on the first surface 11 of the glass substrate 10, so as to effectively protect the first surface 11 of the glass substrate 10.

[0051] In some alternative embodiments, the thickness H1 of the first protective layer 20 is greater than or equal to 1 micrometer and less than or equal to 8 micrometers. In some alternative embodiments, the thickness H1 of the first protective layer 20 is greater than or equal to 1 micrometer and less than or equal to 6 micrometers. In some alternative embodiments, the thickness H1 of the first protective layer 20 is greater than or equal to 1 micrometer and less than or equal to 5 micrometers. In some alternative embodiments, the thickness H1 of the first protective layer 20 is greater than or equal to 1 micrometer and less than or equal to 4 micrometers.

[0052] In some embodiments, as shown in FIG. 2A, the thickness H2 of the second protective layer 30 is less than or equal to 10 micrometers. The thickness H2 of the second protective layer 30 is avoided to be too large, so as to avoid increasing the difficulty of manufacturing the second via hole 22 in step S4 and increasing the difficulty of removing the second protective layer 30 in step S7. Figure 2 ​As shown, the thickness H2 of the second protective layer 30 is less than or equal to 10 microns. The thickness H2 of the second protective layer 30 is avoided to be too large, so as to avoid increasing the difficulty of removing the second protective layer 30 in step S5.

[0053] In some optional embodiments, the thickness H2 of the second protective layer 30 is greater than or equal to 1 micron and less than or equal to 10 microns. The thickness H2 of the second protective layer 30 is avoided to be too small, so as to facilitate ensuring that the second protective layer 30 is completely formed on the second surface 12 of the glass substrate 10, so as to effectively protect the second surface 12 of the glass substrate 10.

[0054] In some optional embodiments, the thickness H2 of the second protective layer 30 is greater than or equal to 1 micron and less than or equal to 8 microns. In some optional embodiments, the thickness H2 of the second protective layer 30 is greater than or equal to 1 micron and less than or equal to 6 microns. In some optional embodiments, the thickness H2 of the second protective layer 30 is greater than or equal to 1 micron and less than or equal to 5 microns. In some optional embodiments, the thickness H2 of the second protective layer 30 is greater than or equal to 1 micron and less than or equal to 4 microns.

[0055] In some embodiments, in step S51, the conductive connecting part 40 is formed in the second through hole 13 by electroplating.

[0056] In step S51, in the electroplating process, the second protective layer 30 can be used as a cathode. The anode ions in the electroplating solution are deposited on the surface of the cathode. Therefore, the anode material is gradually deposited on the surface of the second protective layer 30 exposed in the second through hole 13 as the conductive connecting material 41 in the second through hole 13. Further, the conductive connecting part 40 is obtained in the second through hole 13. The conductive connecting part 40 includes the conductive connecting material 41 in the second through hole 13.

[0057] In the embodiments of the present application, the second protective layer 30 is used as an anode and shields the bottom of the second through hole 13, so that the conductive connecting part 40 and the conductive connecting material 41 can be effectively and completely filled in the second through hole 13, especially for the second through hole 13 with a high aspect ratio, which simplifies the difficulty of manufacturing the conductive connecting part 40 in the second through hole 13.

[0058] In some embodiments, the second protective layer 30 includes a nickel material. In some embodiments, the second protective layer 30 includes at least one nickel layer.

[0059] In some embodiments, the first protective layer 20 comprises a non-conductive material. In some optional embodiments, the first protective layer 20 comprises a non-metallic material. In some embodiments, the first protective layer 20 comprises one or a combination of Polyimide (PI), Polytetrafluoroethylene (PTFE), Photoresist, ABF (Ajinomoto Build-up Film) material.

[0060] In some optional embodiments, the first protective layer 20 comprises one or a combination of Polyimide (PI) layer, Polytetrafluoroethylene (PTFE) layer, Photoresist layer, ABF (Ajinomoto Build-up Film) layer.

[0061] In some embodiments, the second protective layer 30 comprises a non-conductive material. In some optional embodiments, the second protective layer 30 comprises a non-metallic material. In some embodiments, the second protective layer 30 comprises one or a combination of Polyimide (PI), Polytetrafluoroethylene (PTFE), Photoresist, ABF (Ajinomoto Build-up Film) material.

[0062] In some optional embodiments, the second protective layer 30 comprises one or a combination of Polyimide (PI) layer, Polytetrafluoroethylene (PTFE) layer, Photoresist layer, ABF (Ajinomoto Build-up Film) layer.

[0063] In some embodiments, referring to FIG. 5, step S5 comprises step S51’, and step S51’ comprises: Figure 11 As shown in FIG. 5, step S511’ forms a seed layer 50 on at least the inner wall of the second through hole 13; and As shown in FIG. 5, step S511’ forms a seed layer 50 on at least the inner wall of the second through hole 13; and Figure 12 As shown in FIG. 5, step S511’ forms a seed layer 50 on at least the inner wall of the second through hole 13; and As shown in FIG. 5, step S511’ forms a seed layer 50 on at least the inner wall of the second through hole 13; and Figure 13 As shown in FIG. 5, step S511’ forms a seed layer 50 on at least the inner wall of the second through hole 13; and

[0064] The purpose of such arrangement is that the second protective layer 30 is a non-conductive material and cannot be used as a cathode in the electroplating process. Therefore, the seed layer 50 is formed on the inner wall (inner bottom wall and / or inner side wall) of the second through hole 13, and the seed layer 50 is a conductive material and can be used as a cathode to provide a physical base layer for the reduction and adhesion of the anode material.

[0065] In some embodiments, as shown in step S511', a seed layer 50 is formed on the inner wall of the second through hole 13 and the side surface of the first protective layer 20 facing away from the glass substrate 10. Figure 12

[0066] As shown in steps S5 and S52', in some embodiments, step S5 further comprises step S52': removing the first protective layer 20, the second protective layer 30, and the seed layer 50 and the conductive connecting material 41 outside the second through hole 13, to obtain the conductive connecting part 40 in the second through hole 13 and the seed layer 50 between the conductive connecting part 40 and the inner side wall of the second through hole 13. At this time, since the seed layer 50 is also a conductive material, it can be part of the conductive connecting part 40 in the second through hole 13. Figure 11 Figure 14

[0067] The material of the seed layer 50 is not limited as long as it can be used as a cathode in the electroplating process.

[0068] In some embodiments, the seed layer 50 comprises one or more of gold (Au), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), tantalum (Ta), nickel (Ni), copper (Cu), aluminum (Al), etc.

[0069] In some embodiments, the seed layer 50 is a single layer material or a multi-layer material. In some optional embodiments, the seed layer 50 comprises a laminated combination of one or more of a gold (Au) layer, a platinum (Pt) layer, a palladium (Pd) layer, an iridium (Ir) layer, a titanium (Ti) layer, a tantalum (Ta), a nickel (Ni), a copper (Cu) layer, an aluminum (Al) layer, etc.

[0070] The method of making the seed layer 50 is also not limited as long as it can be formed at least on the inner wall of the second through hole 13.

[0071] In some embodiments, in step S511', the seed layer 50 is formed at least on the inner wall of the second through hole 13 by physical vapor deposition, chemical vapor deposition, or electroless plating.

[0072] In some optional embodiments, a copper layer is formed at least on the inner wall of the second through hole 13 by chemical copper plating, and the copper layer serves as the seed layer 50.

[0073] The materials of the first protective layer 20 and the second protective layer 30 can be the same or different.

[0074] ​​​In some embodiments, the first protective layer 20 and the second protective layer 30 are made of the same material. This allows the first protective layer 20 and the second protective layer 30 to be fabricated simultaneously in step S1, thereby reducing the number of process steps.

[0075] In some alternative embodiments, the materials of the first protective layer 20 and the second protective layer 30 both include conductive materials.

[0076] like Figure 6 and Figure 12 As shown, since the first protective layer 20 includes a conductive material, in step S51, the anode material (i.e., the conductive connection material 41) is also formed on the surface of the first protective layer 20 facing away from the glass substrate 10.

[0077] In some embodiments, the first protective layer 20 and the second protective layer 30 are made of different materials.

[0078] In some embodiments, the second protective layer 30 may include a conductive material, and the first protective layer 20 may include a non-conductive material. This arrangement is intended so that, in step S51, the anolyte material can be attached only within the through-hole as the conductive connection portion 40, and no anolyte material will be attached to the surface of the first protective layer 20 facing away from the glass substrate 10. Therefore, the process of removing the first protective layer 20 and the second protective layer 30 in the subsequent step S52 can be simplified.

[0079] In other embodiments, the first protective layer 20 may include a conductive material, and the second protective layer 30 may include a non-conductive material.

[0080] In some embodiments of this application, both the first protective layer 20 and the second protective layer 30 comprise conductive materials. For example... Figure 6 and Figure 12 As shown, the anode material (i.e., the conductive connection material 41) is simultaneously attached to the second through hole 13 and the side surface of the first protective layer 20 facing away from the glass substrate 10.

[0081] In some embodiments, in step S52, the first protective layer 20, the second protective layer 30, and the anode material on opposite sides of the glass substrate 10 are removed by mechanical removal. Specifically, grinding or cutting can be used to remove the first protective layer 20, the second protective layer 30, and the anode material outside the second through hole 13 on opposite sides of the glass substrate 10.

[0082] In some embodiments, the first protective layer 20, the second protective layer 30, and other seed layer 50, anode material, etc. on the opposite sides of the glass substrate 10 are removed by mechanical removal in step S52'. Specifically, the first protective layer 20, the second protective layer 30, and other seed layer 50, anode material, etc. on the opposite sides of the glass substrate 10 can be removed by grinding or cutting.

[0083] In some embodiments of the present application, as shown in FIG. 6, the first circuit layer 61 includes at least one conductive circuit 63 in step S6. Figure 8

[0084] In some embodiments, as shown in FIG. 6, the first circuit layer 61 includes multiple conductive circuits 63 and a dielectric layer 64 arranged between adjacent two conductive circuits 63, and the adjacent two conductive circuits 63 are electrically connected via a through hole (not shown) of the dielectric layer 64. Figure 8

[0085] In some embodiments, the step of forming the first circuit layer 61 connected with the conductive connecting part 40 on the first surface 11 of the glass substrate 10 in step 6 includes: alternately fabricating the conductive circuit 63 and the dielectric layer 64 on the first surface 11 of the glass substrate 10.

[0086] In some embodiments of the present application, as shown in FIG. 6, the second circuit layer 62 includes at least one conductive circuit 63 in step S6. Figure 8

[0087] In some embodiments, the second circuit layer 62 includes multiple conductive circuits 63 and a dielectric layer 64 arranged between adjacent two conductive circuits 63, and the adjacent two conductive circuits 63 are electrically connected via a through hole (not shown) of the dielectric layer 64.

[0088] In some embodiments, the step of forming the second circuit layer 62 connected with the conductive connecting part 40 on the second surface 12 of the glass substrate 10 in step 6 includes: alternately fabricating the conductive circuit 63 and the dielectric layer 64 on the second surface 12 of the glass substrate 10.

[0089] In this step S6, the conductive circuit 63 in the first circuit layer 61 and the second circuit layer 62 is fabricated by forming a conductive material layer on the surface of the first protective layer 20 (or the dielectric layer 64), forming a photoresist material layer on the conductive material layer, exposing and developing the photoresist material layer to form a photoresist pattern, and etching the conductive material layer to remove the unshielded part of the conductive material layer to obtain the conductive circuit 63.

[0090] ​​​The via hole of the dielectric layer 64 in the first circuit layer 61 and the second circuit layer 62 and the via hole are made by the following way: forming a dielectric material layer on the surface of the conductive circuit 63, and forming a photoresist material layer on the dielectric material layer, exposing and developing the photoresist material layer to form a photoresist pattern, and etching the dielectric material layer with the photoresist pattern as a shield to remove the unshielded part of the dielectric material layer to obtain the via hole. The via hole exposes a part of the conductive circuit 63. In this step, the dielectric material layer can be formed on the surface of the conductive circuit 63 by coating or pressing.

[0091] In some embodiments, the first circuit layer 61 and the second circuit layer 62 are connected through the conductive connection 40 in the second via hole 13 to realize the vertical interconnection of the double-sided circuit of the chip carrier 100.

[0092] In some embodiments, in step S7, the window 71 can be formed on the solder mask layer 70 by one photomask process.

[0093] Specifically, step S7 can include: forming a solder mask material layer on the side of the first circuit layer 61 and the second circuit layer 62 away from the glass substrate 10, forming a photoresist material layer on the side of the solder mask material layer away from the glass substrate 10, exposing and developing the photoresist material layer to form a photoresist pattern, etching the solder mask material layer with the photoresist pattern as a shield to remove the unshielded part of the solder mask material layer to obtain the window 71. The window 71 exposes a part of the conductive circuit 63.

[0094] In some embodiments, in step S8, the surface treatment layer 80 formed is used to protect the part of the conductive circuit 63 exposed from the window 71. For example, for materials prone to oxidation, such as copper, the surface treatment layer 80 can be used to prevent copper oxidation. In addition, the surface treatment layer 80 can also be used to improve the connection stability between the conductive circuit 63 and the subsequent conductive connection bump 81 (see Figure 19 ).

[0095] In some embodiments, the surface treatment layer 80 can include one or more of the following: OSP (Organic Solderability Preservative), ENIG (Electroless Nickel Immersion Gold), ENIPIG (Electroless Nickel Immersion Palladium Immersion Gold), ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold), and chemical tin (which can be made by electroplating or electroless plating).

[0096] As shown in FIG. 2, in some embodiments of the present application, a first via hole 21 is formed on the first protective layer 20 in step S2 by using a photomask process. Figures 15 to 18

[0097] The purpose of this arrangement is to improve production efficiency by etching the entire surface of the first protective layer 20 at the same time, compared with the method of cutting the first protective layer 20 to form the first via hole 21 by using a laser.

[0098] Specifically, step S2 includes: Step S21'', as shown in FIG. 3, a photoresist material layer (third photoresist material layer 92) is formed on the first protective layer 20. Figure 15 Step S22'', as shown in FIG. 4, the third photoresist material layer 92 is exposed, and exposed areas 921 and non-exposed areas 922 are formed on the third photoresist material layer 92. Step S23'', as shown in FIG. 5, the exposed third photoresist material layer 92 is developed, and the exposed areas 921 (for the third photoresist material layer 92 of positive photoresist material) or the non-exposed areas 922 (for the third photoresist material layer 92 of negative photoresist material) are removed, to form a third photoresist pattern 923. Figure 16 Step S24'', as shown in FIG. 6, the first protective layer 20 is etched with the third photoresist pattern 923 as a shield, and the parts not shielded by the third photoresist pattern 923 are removed, to obtain the first via hole 21. Step S24'', as shown in FIG. 6, the first protective layer 20 is etched with the third photoresist pattern 923 as a shield, and the parts not shielded by the third photoresist pattern 923 are removed, to obtain the first via hole 21. Figure 17 Step S24'', as shown in FIG. 6, the first protective layer 20 is etched with the third photoresist pattern 923 as a shield, and the parts not shielded by the third photoresist pattern 923 are removed, to obtain the first via hole 21. Step S24'', as shown in FIG. 6, the first protective layer 20 is etched with the third photoresist pattern 923 as a shield, and the parts not shielded by the third photoresist pattern 923 are removed, to obtain the first via hole 21. Figure 18 Step S24'', as shown in FIG. 6, the first protective layer 20 is etched with the third photoresist pattern 923 as a shield, and the parts not shielded by the third photoresist pattern 923 are removed, to obtain the first via hole 21. Step S24'', as shown in FIG. 6, the first protective layer 20 is etched with the third photoresist pattern 923 as a shield, and the parts not shielded by the third photoresist pattern 923 are removed, to obtain the first via hole 21.

[0099] In some embodiments, the first protective layer 20 can be etched to form the first through hole 21 by wet etching in step S24''. In some embodiments, the first protective layer 20 can be etched to form the first through hole 21 by dry etching in step S24''. The specific etching method depends on the material of the first protective layer 20.

[0100] The chip carrier 100 is manufactured by the manufacturing method of any of the above embodiments. Figure 9

[0101] As shown in Figures 3 to 5 The chip carrier intermediate structure comprises: a glass substrate 10 having a first surface 11; and a first protective layer 20 disposed on the first surface 11 and having a plurality of first through holes 21.

[0102] The chip carrier intermediate structure provided by the embodiments of the present application can protect the part of the first surface 11 of the glass substrate 10 other than the part corresponding to the first through hole 21, so as to avoid etching damage to other positions of the first surface 11 of the glass substrate 10 in subsequent etching of the glass substrate 10. This can ensure the thickness of the glass substrate 10 and the surface quality such as the roughness of at least the first surface 11 of the glass substrate 10.

[0103] In some embodiments, as shown in Figure 5 and Figure 6 The glass substrate 10 further has a plurality of second through holes 13 penetrating therethrough, and a projection of the second through hole 13 on the first surface 11 is at least partially within a projection of the first through hole 21 on the first surface 11.

[0104] In some embodiments, as shown in Figures 2 to 6 The chip carrier intermediate structure further comprises a second protective layer 30, the glass substrate 10 further has a second surface 12 opposite to the first surface 11, and the second protective layer 30 is disposed on the second surface 12 and seals a bottom of the second through hole 13.

[0105] In some embodiments, as shown in Figure 12 The chip carrier intermediate structure further comprises a seed layer 50, and the seed layer 50 is disposed at least on an inner wall of the second through hole 13. In some specific embodiments, the seed layer 50 is disposed at least on an inner bottom wall and / or an inner side wall of the second through hole 13.

[0106] In some embodiments, as shown in Figure 12 ​As shown, in the intermediate structure of the chip carrier, the seed layer 50 is also disposed on the side surface of the first protective layer 20 facing away from the glass substrate 10.

[0107] like Figure 19 As shown, this application embodiment also provides a chip packaging structure 400, which includes a motherboard 200, a chip carrier 100 manufactured by the chip carrier manufacturing method described in the above embodiments, or a chip carrier 100 as described in the above embodiments, wherein the chip carrier 100 is disposed on one side of the motherboard 200 and electrically connected to the motherboard 200, and a chip 300 disposed on the side of the chip carrier 100 away from the motherboard 200 and electrically connected to the chip carrier 100.

[0108] In some embodiments, such as Figure 19 As shown, the side of the chip carrier 100 facing the motherboard 200, that is, the side of the second circuit layer 62 facing away from the glass substrate 10, is also provided with conductive connection protrusions 81. The conductive connection protrusions 81 are electrically connected to the motherboard 200 and to the second circuit layer 62.

[0109] In some embodiments, such as Figure 19 As shown, the side of the chip carrier 100 opposite to the motherboard 200, that is, the side of the first circuit layer 61 opposite to the glass substrate 10, is also provided with conductive connection protrusions 81. The conductive connection protrusions 81 are electrically connected to the chip 300 and to the first circuit layer 61.

[0110] In some embodiments, the material of the conductive connection bump 81 is not limited. In some embodiments, the material of the conductive connection bump 81 may include one or a combination of materials such as copper (Cu), nickel (Ni), tin (Sn), and silver (Ag).

[0111] In some alternative embodiments, the material of the conductive connecting protrusion 81 may include Sn, or SnAg alloy, or Cu and SnAg alloy, or Cu, Ni and SnAg, etc.

[0112] In some embodiments, the conductive connecting protrusions 81 can be fabricated by electroplating, printing, or ball implantation.

[0113] This application embodiment also provides a chip carrier 100, which includes a glass substrate 10, a conductive connection portion 40, a first circuit layer 61 and a second circuit layer 62. The glass substrate 10 is provided with a plurality of second through holes 13, and the conductive connection portions 40 are respectively disposed in the second through holes 13. The first circuit layer 61 is disposed on one side of the glass substrate 10 and connected to one end of the conductive connection portion 40, and the second circuit layer 62 is disposed on the other side of the glass substrate 10 and connected to the other end of the conductive connection portion 40.

[0114] The specific features of the chip carrier 100 can refer to the foregoing embodiments, and will not be described again.

[0115] The technical features of the above embodiments can be combined in any manner. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combinations of the technical features do not contradict, they should be considered as the scope of the description.

[0116] The above embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for manufacturing a chip carrier board, characterized in that, include: A first protective layer is formed on the first surface of the glass substrate; Multiple first through holes are formed on the first protective layer; Laser induction is performed on the glass substrate through the first through hole to form multiple induction regions; In the induction region, the glass substrate is etched to form a plurality of second through holes penetrating the glass substrate; A conductive connection is formed within the second through hole.

2. The manufacturing method as described in claim 1, characterized in that, Before forming a plurality of first through holes on the first protective layer, the manufacturing method further includes: A second protective layer is formed on the second surface of the glass substrate; The bottom of the first through hole is shielded by the second protective layer.

3. The manufacturing method as described in claim 2, characterized in that, The second protective layer includes a conductive material; Preferably, the conductive connection portion is formed in the second through hole by electroplating; Preferably, the first protective layer comprises a conductive material; Preferably, the first protective layer and the second protective layer are made of the same material; Preferably, the material of the second protective layer includes one or a combination of gold, platinum, palladium, iridium, titanium, tantalum, and nickel.

4. The manufacturing method as described in claim 3, characterized in that, The method of forming the conductive connection portion in the second through hole by electroplating includes: Conductive connection material is formed in the second through-hole and on the side of the first protective layer opposite to the glass substrate by electroplating; and, Remove the first protective layer, the second protective layer, and the conductive connecting material located outside the second through hole. The conductive connecting material located inside the second through hole is the conductive connecting portion.

5. The manufacturing method as described in claim 2, characterized in that, Before forming a conductive connection portion within the second through hole, the manufacturing method further includes: At least a seed layer is formed on the inner wall of the second through hole; and The conductive connection portion is formed on the surface of the seed layer within the second through hole by electroplating. Preferably, the seed layer is formed on the inner wall of the second through hole and on the side of the first protective layer opposite to the glass substrate; Preferably, the first protective layer comprises a non-conductive material; Preferably, the first protective layer and the second protective layer are made of the same material.

6. The manufacturing method as described in claim 5, characterized in that, The first protective layer includes one or a combination of polyimide, polytetrafluoroethylene, photoresist, and Ajinomoto multilayer insulating film; The method of forming the conductive connection portion in the second through hole by electroplating includes: A conductive connection material is formed inside and outside the second through hole, on the side of the seed layer opposite to the glass substrate, using electroplating; and, Remove the first protective layer, the second protective layer, the conductive connecting material located outside the second through hole, and the seed layer located inside the second through hole; the conductive connecting material and the seed layer constitute the conductive connecting portion.

7. The manufacturing method as described in claim 2, characterized in that, Before forming a plurality of first through holes on the first protective layer, the manufacturing method further includes: A first circuit layer connected to the conductive connection portion is formed on the first surface of the glass substrate, and a second circuit layer connected to the conductive connection portion is formed on the second surface of the glass substrate. Preferably, the first circuit layer includes at least one layer of conductive circuitry; Preferably, the first circuit layer includes multiple conductive circuits and a dielectric layer disposed between two adjacent conductive circuits, wherein the two adjacent conductive circuits are electrically connected through through holes in the dielectric layer. Preferably, the second circuit layer includes at least one layer of conductive lines; Preferably, the second circuit layer includes multiple conductive circuits and a dielectric layer disposed between two adjacent conductive circuits, wherein the two adjacent conductive circuits are electrically connected through through holes in the dielectric layer. Preferably, the manufacturing method further includes, after forming a first circuit layer connected to the conductive connection portion on the first surface of the glass substrate, and forming a second circuit layer connected to the conductive connection portion on the second surface of the glass substrate: Solder resist layers are formed on the side of the first circuit layer and the second circuit layer away from the glass substrate, and a plurality of openings are formed on the solder resist layers, the openings exposing part of the surface of the first circuit layer and the second circuit layer. A surface treatment layer is made on the exposed surfaces of the first circuit layer and the second circuit layer within the window.

8. The manufacturing method according to any one of claims 1 to 7, characterized in that, The first through hole is formed on the first protective layer by laser cutting; Alternatively, the first through-hole can be formed on the first protective layer using a photomask process.

9. A chip carrier board, characterized in that, include: A glass substrate, wherein the glass substrate is provided with a plurality of second through holes; Conductive connection parts are respectively disposed in the second through hole; A first circuit layer is disposed on one side of the glass substrate and connected to one end of the conductive connection portion; and The second circuit layer is disposed on the other side of the glass substrate and connected to the other end of the conductive connection portion.

10. A chip packaging structure, characterized in that, include: Motherboard; The chip carrier board is manufactured by the manufacturing method of any one of claims 1 to 8 or the chip carrier board as described in claim 9, wherein the chip carrier board is disposed on one side of the motherboard and is electrically connected to the motherboard. as well as The chip is disposed on the side of the chip carrier away from the motherboard and is electrically connected to the chip carrier.

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