Switching regulator control

Abstract

This disclosure relates to switching regulator control. A method for operating a hysteresis-synthetic current-mode switching regulator is disclosed. In the switching regulator, based on the voltages in the upper and lower windows (V... W+ V W‑ The ramp voltage (V) oscillates between ) R The PWM pulses (PWM) are generated by the PWM generator (20; Figure 7). The ramp voltage depends on the control voltage (V). C ), control voltage (V C ) depends on the current (I) through the inductor (6) L The method includes: determining whether a given time period (T) is equal to or greater than a given time period when no PWM pulse is generated. REFRESH Whether the time period (T) has elapsed, if affirmatively determined, for a given duration (ΔT), such that the ramp voltage is pulled up to the upper window voltage (V). W+ ) or pull up to the upper window voltage (V W+ The above applies, and as the given duration elapses, the ramp voltage decreases until the rising edge of the PWM pulse is generated.

Description

Technical Field

[0001] This invention relates to switching regulator control, and more particularly to the control of a hysteresis synthetic current mode switching regulator. Background Technology

[0002] A switching regulator can be used to convert one DC voltage to another. For example, a buck converter can be used to step down the voltage, a boost converter can be used to step up the voltage, and a buck-boost converter can be used to gradually decrease or gradually increase the voltage.

[0003] Switching regulators typically use pulse width modulation (PWM) to control the switching in the power stage, thereby varying the current through the inductor. The duty cycle of the PWM signal is controlled based on the inductor current, and changing the duty cycle is used to adjust the output voltage.

[0004] Instead of directly sensing the inductor current, the switching regulator synthesizes inductor current information by measuring the voltage across the inductor. This can be used to generate a sawtooth signal whose value is proportional to the inductor current. The upper and lower limits of the sawtooth signal can be maintained within a hysteresis window with upper and lower limits. A control voltage is used to vary the level of the hysteresis window, based on feedback from the output and a reference voltage. This arrangement of synthesizing hysteresis control and current information is called "synthetic current hysteresis control". Summary of the Invention

[0005] According to a first aspect of the invention, a method for operating a hysteresis synthetic current mode switching regulator is provided, wherein a PWM pulse is generated by a PWM generator based on a ramp voltage, the ramp voltage being within an upper and lower window voltage range. - It oscillates between these values ​​and depends on the control voltage, which in turn depends on the current I flowing through the inductor. L The method includes: determining whether a given time period T is equal to or greater than a certain threshold when no PWM pulses are generated. REFRESH The method further includes determining whether the time period T has elapsed, and if so, for a given duration ΔT, pulling the ramp voltage up to or above the upper window voltage. The method also includes: as the given duration elapses, reducing the ramp voltage until the rising edge of the PWM pulse is generated.

[0006] When the switching frequency decreases, this can be used to mitigate one or more problems that may occur under low load.

[0007] For example, a given time period can be equal to the discharge time of the bootstrap capacitor, which can be between 200 and 800 microseconds, or between 400 and 600 microseconds. Therefore, the bootstrap capacitor can be refreshed when the load is light and the switching frequency decreases. A given time period can be between 5 and 50 microseconds, for example, 50 microseconds. This can help avoid switching in the audio frequency range (i.e., 20Hz to 20kHz).

[0008] Lowering the ramp voltage can include reducing the ramp voltage at a certain rate such that the energy (or charge) stored in the inductor is equal to or greater than the energy (or charge) output by the inductor during the PWM pulse. Lowering the ramp voltage can also include adjusting the gain of a transconductance amplifier that generates the ramp voltage independently of the output voltage.

[0009] In response to a decrease in ramp voltage, a first amount of energy (or charge) can be extracted from the inductor, the first amount of energy (or charge) being greater than or equal to a second amount of energy (or charge), and the second amount of energy (or charge) being supplied to the inductor from the period starting at the rising edge of the PWM pulse.

[0010] The rate at which the ramp voltage decreases can depend on the gain of the first transconductance amplifier. The first transconductance value can be set to a value that is greater than or equal to twice the gain of the second transconductance amplifier, during which the ramp voltage increases from the rising edge of the PWM pulse.

[0011] The method may include: causing the switching regulator to enter a state during which the current I through the inductor... L It is maintained for a given period of time so that a first quantity of energy (or charge) is equal to or greater than a second quantity of energy (or charge).

[0012] The switching regulator can operate in both PWM and PFM modes (at different times). In this document, the term "PWM pulse" is intended to cover PFM pulses generated in PFM mode.

[0013] According to a second aspect of the invention, a method for operating a hysteresis synthetic current mode switching regulator is provided, wherein a PWM pulse is generated by a PWM generator based on a ramp voltage, the ramp voltage oscillating between upper and lower window voltages and depending on a control voltage, the control voltage depending on the current I through an inductor. L The method includes: in response to a decrease in ramp voltage, extracting a first amount of energy from an inductor, the first amount of energy being greater than or equal to a second amount of energy, the second amount of energy being supplied to the inductor during a period starting from the rising edge of the PWM pulse.

[0014] The rate at which the ramp voltage decreases can depend on the gain of the first transconductance amplifier. The first transconductance value can be set to a value that is greater than or equal to twice the gain of the second transconductance amplifier, during which the ramp voltage increases from the rising edge of the PWM pulse.

[0015] The method may include: causing the switching regulator to enter a state during which the current I through the inductor... L It is maintained for a given period of time so that a first quantity of energy (or charge) is equal to or greater than a second quantity of energy (or charge).

[0016] The method includes: determining whether a time period T equal to or greater than a given time period has elapsed in the absence of a PWM pulse being generated, and, if affirmatively determined, causing the ramp voltage to be pulled up to or above the upper window voltage for a given duration ΔT. The method further includes: causing the ramp voltage to decrease as the given duration elapses until the rising edge of a PWM pulse is generated.

[0017] According to a third aspect of the invention, an apparatus configured to perform the method of the first or second aspect is provided.

[0018] According to a fourth aspect of the invention, a control circuit for controlling a hysteresis synthetic current mode switching regulator is provided, wherein a PWM pulse is generated by a PWM generator based on a ramp voltage V. R It oscillates between the upper and lower window voltages and depends on the control voltage V. C Control voltage V C Depending on the current through the inductor (6). The device is configured to: determine whether a period of time equal to or greater than a given time has elapsed without a PWM pulse being generated; if affirmatively determined, for a given duration, cause the ramp voltage to be pulled up to or above the upper window voltage. The device is configured to: as the given duration elapses, cause the ramp voltage to decrease until the rising edge of the PWM pulse is generated.

[0019] The device can be configured to set a first control signal, which is provided to the control stage of the switching regulator, such that the ramp voltage is pulled up to or above the upper window voltage. The device can also be configured to set a second control signal, which is provided to the control stage of the pulse frequency modulation control circuit and the switching regulator, such that the ramp voltage V... R It is pulled up to the upper window voltage or above.

[0020] According to a fifth aspect of the invention, a switching regulator including a control stage is provided. The control stage includes: a synthesized ramp generator circuit for generating a ramp voltage, the synthesized ramp generator circuit including a transconductance amplifier, a voltage ramp node, a modulator capacitor connected between the voltage ramp node and a reference level node, a first switch between the output of the transconductance amplifier and the voltage ramp node, and a second switch between a voltage reference level and the voltage ramp node; a hysteresis control section circuit for controlling the oscillation of the ramp voltage between upper and lower window voltages, and generating first and second signals for setting and resetting PWM signals, respectively; and a latch for using the first and second signals to generate PWM pulses. The switching regulator also includes control circuitry of a third aspect, configured to: receive PWM pulses from the control stage and provide control signals to the control stage to control the gain of the transconductance amplifier and control the first and second switches.

[0021] The switching regulator may also include a power stage for gradually increasing and / or decreasing the input voltage to provide the output voltage.

[0022] The switching regulator can be a buck controller, a boost controller, and / or a buck-boost controller.

[0023] The switching regulator may also include (multiple) bootstrap capacitors.

[0024] According to a sixth aspect of the present invention, a monolithic integrated circuit is provided, which includes the device of the third or fourth aspect or the switching regulator of the fifth aspect.

[0025] According to a seventh aspect of the invention, a system is provided, comprising a device of the third or fourth aspect, a switching regulator of the fifth aspect, and / or a monolithic integrated circuit of the sixth aspect, and including a host controller for controlling the device, the switching regulator, and / or the monolithic integrated circuit. The host controller may include a microcontroller, a system-on-a-chip (SoC), or other form of processor-based or logic-based controller.

[0026] According to an eighth aspect of the invention, an electronic system is provided, comprising a power supply, devices of the third or fourth aspect, a switching regulator of the fifth aspect, a monolithic integrated circuit of the sixth aspect, and a load of the seventh aspect. The electronic system may be a portable (e.g., handheld or laptop) electronic device, such as a mobile phone, tablet computer, or laptop computer, and the load may be an electronic circuit device within the portable electronic device. The electronic system may be a lighting system, and the load may be (multiple) lighting elements, such as (multiple) LEDs. The electronic system may be a motor vehicle system, and the load may be, for example, an electronic control unit. The power supply may be a battery. Attached Figure Description

[0027] Some embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which:

[0028] Figure 1 This is the circuit diagram of a hysteresis synthesized ramp-down converter;

[0029] Figures 2A to 2D Plots of inductor current versus time and ramp voltage versus time are shown for buck converters, boost converters, three-state buck-boost converters, and two-state buck-boost converters, respectively.

[0030] Figure 3A It is a plot of the inductor current relative to the control voltage;

[0031] Figure 3B The diagram illustrates the discontinuous conduction mode (DCM) of the operation.

[0032] Figure 3C This is a circuit diagram of a DCM implementation method;

[0033] Figure 4 This is the circuit diagram of a hysteresis synthesized current buck-boost converter;

[0034] Figure 5 It is a diagram. Figure 4 The timing diagram shown illustrates the bootstrap capacitor refresh of the buck-boost converter when there is no load.

[0035] Figure 6 It is a diagram. Figure 4 The timing diagram for audio band suppression of the buck-boost converter shown is illustrated.

[0036] Figure 7 This is the circuit diagram of the system, which includes a hysteresis synthesized ramp buck converter and a controller for the buck converter;

[0037] Figure 8 This is a flowchart of the process of controlling the buck converter;

[0038] Figure 9 It is a diagram. Figure 7 The timing diagram of the bootstrap capacitor refresh cycle in the system shown;

[0039] Figure 10 It is a diagram. Figure 7 Timing diagram of audio band suppression in the system shown;

[0040] Figure 11A , Figure 11B and Figure 11C The figure illustrates the simulation of a buck-boost hysteresis synthesized current converter in buck mode;

[0041] Figure 12A , Figure 12B and Figure 12C The figure illustrates the simulation of a buck-boost hysteresis synthesized current converter in boost mode;

[0042] Figure 13A , Figure 13B and Figure 13C The figure illustrates the simulation of a buck-boost hysteresis synthesized current converter in buck mode;

[0043] Figure 14 This is a schematic block diagram of a buck-boost converter;

[0044] Figure 15 This is a schematic block diagram of a buck-boost converter;

[0045] Figure 16 This is a schematic block diagram of a boost converter;

[0046] Figure 17 This is a table illustrating the state of the switching regulator and the gate control signals;

[0047] Figure 18A This is the state diagram of the buck converter;

[0048] Figure 18B The diagram illustrates the simulated inductor current of the buck converter, as well as the REFRESH and ABS signals.

[0049] Figure 18C This is a table illustrating the status of the buck converter and the gate control signals;

[0050] Figure 19A This is the state diagram of a two-switch buck converter;

[0051] Figure 19B This is a table illustrating the status of a two-switch buck converter and its gate control signals;

[0052] Figure 20A This is the state diagram of the boost converter;

[0053] Figure 20B The diagram illustrates the simulated inductor current of the boost converter, as well as the REFRESH and ABS signals.

[0054] Figure 20C This is a table illustrating the status of the boost converter and the gate control signals;

[0055] Figure 21A This is the state diagram of a two-switch boost converter;

[0056] Figure 21B This is a table illustrating the status of two-switch boost converters and their gate control signals;

[0057] Figure 22A This is the state diagram of a buck-boost converter;

[0058] Figure 22B The diagram illustrates the simulated inductor current of the buck-boost converter, as well as the REFRESH and ABS signals.

[0059] Figure 22C This is a table illustrating the status of a buck-boost converter and its gate control signals;

[0060] Figure 23 This is a schematic plot of inductor current versus time, illustrating the charge removed from and added to the inductor during an ABS-PWM cycle, which can result in a buck-boost output voltage V. OUT The increase;

[0061] Figure 24A This is a schematic plot of inductor current versus time, illustrating the charge removed from and added to the inductor during an ABS-PWM cycle with an extended ABS duration. This can help reduce or even avoid buck-boost output voltage V. OUT The increase;

[0062] Figure 24B This is a schematic plot of inductor current versus time, illustrating the charge removed from and added to the inductor during the ABS-ABS T2-PWM cycle. This can help reduce or even avoid buck-boost output voltage V. OUT The increase;

[0063] Figure 24C This is the state diagram of a buck-boost converter, which uses an additional T2 period to reduce or avoid the buck-boost output voltage V. OUT The increase;

[0064] Figure 24D This is a table illustrating the status of the buck-boost converter and the gate control signals;

[0065] Figure 25 It is a schematic block diagram of a buck-boost converter including a power controller IC, off-chip FETs, and bootstrap capacitors;

[0066] Figure 26 This is a schematic block diagram of a buck-boost converter including a power converter IC, which includes an on-chip power stage and an off-chip bootstrap capacitor.

[0067] Figure 27This is a schematic block diagram of a buck converter including a power converter IC, which includes an on-chip power stage and an off-chip bootstrap capacitor; and

[0068] Figure 28 This is a schematic block diagram of a buck converter including a power converter IC, which includes an on-chip power stage and an off-chip bootstrap capacitor. Detailed Implementation

[0069] introduction

[0070] The following section will describe DC-DC converters primarily in the form of hysteresis synthesized current buck converters. However, these comments and techniques can be applied to other forms of DC-DC converters, such as boost converters and buck-boost converters.

[0071] In the following text, the same parts are indicated by the same reference numerals.

[0072] refer to Figure 1 This paper presents a hysteresis synthesis current-mode switching regulator 1 in the form of a hysteresis synthesis ramp-down converter.

[0073] The buck converter 1 includes a control stage 2 and a power stage 3.

[0074] Buck converter 1 receives input voltage V from external voltage source 4 (such as a battery). IN Buck converter 1 will convert the input voltage V IN Gradually reduce to lower the output voltage V OUT Provided to external loads 5 (such as microprocessor-based devices, memory, or other electronic devices that require a specific voltage).

[0075] Power stage 3 uses an inductor L O and resistance R L An energy storage element in the form of an inductor 6. Using first and second switches Q1 and Q2, the voltage across the inductor 6 is varied across the input voltage V. IN Switching between ground (GND), the first and second switches Q1 and Q2 are arranged in a totem-pole configuration at the input voltage V. IN Between and ground (GND). Switches Q1 and Q2 are in the form of suitable power transistors, such as power MOSFETs. The common node 7 between switches Q1 and Q2 is connected to the first node (“phase node”) of inductor 6. The second node of inductor 6 is connected to the output node 8.

[0076] The current i through inductor 6 LThe sensed current is fed into comparator 9. Comparator 9 acts as a zero-crossing detector and outputs a zero-crossing detector signal ZCD, which is fed into gate driver 10. Switches Q1 and Q2 are controlled by gate driver 10, which provides first and second gate drive signals UGD and LGD to the first (high-side) and second (low-side) switches Q1 and Q2, respectively. Gate driver 10 is controlled by a pulse width modulation (PWM) signal from control stage 2. The output voltage Vo is also sensed and fed back to control circuit 2 as feedback voltage FB.

[0077] Control stage 2 includes a synthesized ramp generator circuit 11, which includes a transconductance (or "gm") amplifier 12 and a modulator capacitor C. R The inductor voltage V is sensed using transconductance amplifier 12. O To synthesize inductor current information and generate a value related to the inductor current i L Proportional sawtooth voltage ramp V R Inductor voltage V O The inverting input of amplifier 12 is provided, and the non-inverting input is connected to a pair of switches S1 and S2 at V. IN Switching between GND and V, the pair of switches S1 and S2 are arranged in a totem pole configuration on V. IN It is connected to GND and controlled by PWM and nPWM (for "PWM bar") respectively.

[0078] Hysteresis control circuit 13 includes an error amplifier 14, which receives a voltage reference V from a voltage source 15. REF It also receives the feedback signal FB and outputs the control voltage V. C .

[0079] Control voltage V C The voltage is supplied to the first and second voltage level generators 16 and 17 to generate the upper and lower window levels V. W+ V W- Upper and lower window levels V W+ V W- The voltage ramp V is provided to the inverting input of the first comparator 18 and the non-inverting input of the second comparator 19. R It is provided to both the non-inverting input of the first comparator 18 and the inverting input of the second comparator 19.

[0080] The outputs of the first and second comparators 18 and 19 are respectively provided to the reset R input and set S input of the SR latch 20. The Q output of the latch 20 is provided as a PWM signal to the gate driver 10.

[0081] The buck converter 1 enables peak-valley current mode control. Inductor current information is synthesized by sensing the inductor voltage through transconductance amplifier 12 to generate a converter with respect to the inductor current i. L Proportional sawtooth voltage ramp V R Compared to sensed current, synthesized current exhibits superior noise immunity. The steady-state frequency is controlled by manipulating a hysteresis window relative to the duty cycle. Hysteresis control allows for frequency variation during transient conditions to improve transient response. The frequency is controlled by the voltage V. C It rises during ramp-up, while the control voltage V C It descends on an inclined plane.

[0082] Synthetic slope V R vs I L

[0083] Also refer to Figure 2A , enters modulator capacitor C R The current is proportional to the voltage across inductor 6. Therefore, the modulator ramp voltage V R With inductor current i L Proportional. Ramp voltage V R With control signal V C Centered on, and therefore the inductor current is related to the control signal V C Proportional.

[0084] refer to Figure 2B , Figure 2C and Figure 2D The voltage ramp V is shown for a boost converter, a three-state buck-boost converter, and a two-state buck-boost converter, respectively. R and inductor current i L The behavior.

[0085] Discontinuous conduction mode (DCM) operation

[0086] refer to Figure 3A , Figure 3B and Figure 3C In hysteresis current-mode control with synthesized current sensing information, the pulse width modulation (PWM) ramp and the inductor current i L Proportional, and when the control signal V C Above the CCM threshold V THRESH (For example, it could be 1.45V) When the controller operates in Continuous Conductive Mode (CCM) mode.

[0087] When the control signal V C Decrease to CCM threshold V THRESH As the slope descends, the gradient gradually becomes shallower to allow for period stretching in the DCM.

[0088] Special Reference Figure 3B When the voltage ramp V R Reach or pass through the lower window V W- At that time, a new switching cycle (i.e., the rising edge of the PWM) begins.

[0089] Once the control voltage V C Drops below threshold V THRESH (e.g., 1.45V), voltage ramp V R The slope decreases to zero, and the voltage ramp V R It will not pass through the lower window, toggle stop V W- And switch to stop.

[0090] When the output voltage V OUT Drop to target voltage V TARGET When the control voltage V is below, C From threshold V THRESH It begins to rise, and this causes the ramp voltage V to rise. R It starts to decline again. Once the ramp voltage V R Reaching or crossing the lower window threshold V W- Then, a new switching cycle will begin.

[0091] Special Reference Figure 3A Once a zero crossover is detected, a time-period extension will occur. In a non-ideal system, the inductor current I... L Relative to control voltage V C Three operating regions are exhibited: (1) the CCM region, in which the inductor current operates in continuous conduction mode; (2) the zero-crossing region, in which the inductor current operates in discontinuous conduction mode but at the switching frequency of CCM; and (3) the time-extended region, in which the inductor current operates in discontinuous conduction mode while extending the switching time. The inductor current is not allowed to drop to zero.

[0092] Also refer to Figure 1 Switches Q1 and Q2 can have three states, namely:

[0093] State I: PWM=HIGH; ZCD latch is cleared.

[0094] Q1=ON and Q2=OFF, causing the inductor current to ramp up.

[0095] State II: PWM=LOW; ZCD=LOW

[0096] Q1=OFF and Q2=ON

[0097] State III: PWM=LOW; ZCD=LOW->HIGH

[0098] Q1=Q2=OFF, causing the inductor current to be kept at 0.

[0099] Special Reference Figure 3C To implement PFM control, PFM control logic 21 is provided, which includes a second transconductance amplifier 22 that receives a threshold voltage V at its non-inverting input. THRESH And receives the control signal V at its inverting input. C The output of the second transconductance amplifier 22 is fed to the non-inverting input of the first comparator 18 and the inverting input of the second comparator 19 via the third switch S3 controlled by nPWM (PWM bar) through node 23.

[0100] When V C Higher than V THRESH At that time, the output of the second transconductance amplifier 22 is clamped to zero. When V C Below V THRESH At that time, the output of the second transconductance amplifier 22 is related to g. M_PFM (V) IN -V OUT The voltage is proportional to the voltage. When PWM is HIGH, S3 is open; and when PWM is LOW, S3 is closed. Therefore, when V... C Decrease to V THRESH The following, and when PWM is LOW, the output will cause V R decline.

[0101] Hysteresis synthesized current buck-boost converter

[0102] refer to Figure 4 The diagram illustrates a buck-boost controller that includes an off-chip power stage 24. The power stage 24 includes first and second high-side NMOS switches M1 and M2, and third and fourth low-side NMOS switches M3 and M4.

[0103] Using NMOS transistors for high-side switches M1 and M2 requires a bootstrap gate driver. One way to achieve this is by using a bootstrap capacitor C. BOOT1 C BOOT2 During each switching cycle, these capacitors C BOOT1 C BOOT2 They were all filled.

[0104] bootstrap capacitor C BOOT1 C BOOT2 A level-shifting power supply is provided for the high-side switches M1 and M2. Whenever phase nodes LX1 and LX2 switch, the bootstrap capacitor C... BOOT1 C BOOT2 Everything will be refreshed.

[0105] Bootstrap capacitor refresh cycle

[0106] Also refer to Figure 5 When the load is light, the switching frequency drops to a very low level. Between two switching cycles, the bootstrap capacitor C... BOOT1 C BOOT2 Discharge.

[0107] Therefore, after the inactive period, a refresh loop is added to allow the bootstrap capacitor C to... BOOT1 C BOOT2 Fully charged. During the refresh cycle, phase nodes LX1 and LX2 are pulled down for a limited time, which allows the bootstrap capacitor C to be fully charged. BOOT1 C BOOT2 Recharge.

[0108] In boost mode operation, at the start of the refresh cycle, the low-side gate signal LG1 is only turned on after the high-side gate signal UG1 has been turned off and detected as off. Therefore, the second phase node LX2 is pulled down first, and thus the input voltage V... IN A positive current is generated across inductor L for approximately 30 to 40 ns.

[0109] For the time after the refresh, when the first phase node LX1 is reconnected to the input voltage V IN At this time, only parasitic capacitance keeps the second phase node LX2 below the threshold. This causes energy to be placed in the inductor L until the node voltage of the second phase node LX2 equals the voltage of the first phase node LX1. The voltage of the second phase node LX2 continues to rise until it is lower than the output voltage V. OUT A larger diode voltage is applied, and the energy in the inductor is dumped to the output.

[0110] Therefore, the output voltage can rise under no-load / light-load conditions.

[0111] Audio band suppression (ABS)

[0112] In DCM operation, as the load current decreases, the switching frequency decreases to maintain regulation. For loads below a certain value, the switching frequency may fall into the audio frequency range (i.e., 20 Hz to 20 kHz). One way to avoid switching in the audio range is to maintain a minimum load at the output and accept a loss in efficiency.

[0113] The refresh loop can be used to perform audio band suppression.

[0114] Also refer to Figure 6 If for 1 / F AUDIO If no switching loop occurs during a time period, a refresh loop is introduced. Therefore, for time periods ≤ 1 / F... AUDIO The phase node is always pulled down.

[0115] However, this implementation has drawbacks. Even with both phase nodes LX1 and LX2 pulled down during the refresh cycle, significantly less energy is placed in the inductor L compared to a normal PWM pulse. The time interval between cycles where a large amount of energy exists in the inductor or output can be greater than 1 / F. AUDIO This results in audio noise. Moreover, as mentioned above, the small current pulse injected into the inductor L through the refresh cycle can be net positive, thereby driving a higher output.

[0116] Combine ABS and refresh cycle

[0117] refer to Figure 7 The power management system 31 is shown.

[0118] The power management system 31 includes a control stage 32, a zero-cross detector 9, a gate driver 10, PFM control logic 33, and ABS control logic 34. The ABS control logic 34 is provided with a timer unit 35, a register 36, and an interface 37.

[0119] Control level 32 is similar to Figure 1 The control stage 2 shown, in addition to employing a variable gain transconductance amplifier 38, provides additional switches S4 and S5 to provide a voltage ramp V at node 39. R Additional controls.

[0120] Specifically, the fourth switch S4 is located between the output of the transconductance amplifier 38 and node 39, and is controlled by a low-active-ramp pull-up signal nREFRESH (or REFRESH bar). The fifth switch S5 is located between the upper window level voltage V. W+ Between node 39 and node 39, it is controlled by the highly effective slope pull-up signal REFRESH.

[0121] The PFM control logic 33 includes first and second inverters 41 and 42 that receive PWM and ABS signals respectively. The PFM control logic 33 also includes a two-input AND gate 43. The outputs of inverters 41 and 42 are fed into AND gate 43 as inputs. The output of AND gate 43 controls a third switch S3.

[0122] The ABS control block 34 receives PWM signals from latch 20 and generates ABS and REFRESH signals. The control block 34 is provided with a programmable register 36 for specifying a time period.

[0123] As will be explained in more detail below, the power management system 31 can be modeled as a finite state machine (FSM) which includes a REFRESH state, an ABS state, one or more PWM cycle states (e.g., buck ON, buck OFF, boost ON), and a three-state. The PWM cycle may also include a so-called "T2 period," which may be fixed or variable. Transitions between states occur in response to the REFRESH, ABS, PWM, and ZCD signals. In different states, the gate driver 10 applies appropriate combinations of gate drive signals UG, LG, UG1, UG2, LG1, LG2 to one or more pairs of high-side and low-side transistors M1, M2, M3, M4, which may be on-chip or off-chip (i.e., on the same chip as the control level).

[0124] Also refer to Figure 8 The operation of the ABS controller 34 will now be described.

[0125] If the time period is T REFRESH If there is no PWM pulse, the refresh cycle is started by setting REFRESH on controller 34 (steps S1 and S2). During the refresh cycle, ramp V R Pulled up and kept in the upper window V W+ Nearby or above.

[0126] Controller 34 waits for a period ΔT (step S4). After ΔT elapses, controller 34 then resets REFRESH and sets ABS (step S5). During ABS, ramp V... R With output V O The rate of decrease is proportional. When the slope V R Descend to the lower window V W- At this point, a new PWM cycle begins, and the ABS is reset (steps S6 and S7).

[0127] ABS time is determined by slope V R The rate of decrease is determined by this. During ABS, the gain of the gm amplifier is changed to g. M_ABS (Also referred to in this document as the "first transconductance amplifier gain value"), to control the duration of ABS and indirectly control the output voltage V. O The energy extracted from the output during ABS is equal to the energy supplied to the output during the PWM cycle. This allows for energy balancing.

[0128] Specifically, adjust g M_ABSThe value is set so that the energy (or charge) extracted from the inductor generated by the ABS is greater than or equal to the energy (or charge) returned by the PWM cycle. Since energy (or charge) may be lost, the energy extracted from the inductor is typically higher than the energy (or charge) returned (e.g., 0% to 20%). However, if the loss is negligible, the extracted energy (or current) is the same as the returned energy (or current).

[0129] Therefore, to achieve this goal, for buck or boost converters, g M_ABS Take at least g M_PWM twice the value of (i.e., g) M_ABS ≥2g M_PWM In this article, g M_PWM Also known as the "second transconductance amplifier gain value". For a buck-boost converter, energy (or charge) depends not only on g M_ABS Furthermore, it also depends on the duration of the T2 period between the end of the sloping down and the start of the PWM pulse.

[0130] During testing, g can be adjusted, for example, using a trimming resistor. M_ABS The value of is the energy flowing through the inductor during the test. This can be performed at the factory (i.e., before use) or on-site.

[0131] Refresh Loop

[0132] refer to Figure 7 and Figure 9 The power management system 31 can help prevent the output from rising when there is no load or the load is very light.

[0133] Immediately following the refresh cycle, during ABS, the inductor current i is... L Set it to a negative value, and then the PWM loop begins. The duration of ABS is determined by the window size and the synthesis ramp V. R The ramp rate is controlled by adjusting the ramp rate (i.e., g). M_ABS The energy input to inductor 6 can be controlled, and the energy or charge taken from the output can be indirectly controlled. It can be adjusted to eliminate the energy or charge dumped at the output during the refresh cycle.

[0134] like Figure 9 As shown, the zero current and the inductor current i LThe shaded area between the two is a measure of charge Q. Therefore, the area or charge Q1 drawn from inductor 6 should be greater than or equal to the returned charge Q2. The period during which charge Q1 is drawn extends from the rising edge of the ABS pulse until the inductor current crosses zero, following the rising edge of the PWM pulse. The period during which charge Q2 is returned extends from the zero current crossover to the next zero crossover, following the falling edge of the PWM pulse. The time of the zero crossover is detected and represented by ZCD.

[0135] ABS

[0136] refer to Figure 7 and Figure 10 The power management system 31 can implement ABS. Specifically, if there is no PWM cycle for a time period equal to / (audio frequency), a refresh cycle is introduced. Therefore, T REFRESH =1 / (audio frequency).

[0137] Following the refresh cycle, for the ABS cycle, the inductor current is set to negative, followed by the PWM cycle. The duration of the ABS is determined by the window size and the synthesized ramp V. R Ramp rate control. This is achieved by adjusting the ramp V during ABS. R The rate (i.e., g) M_ABS The energy put into the input and the energy taken from the output can be balanced.

[0138] like Figure 10 As shown, the zero current and the inductor current i L The shaded area between the two is a measure of charge Q. Therefore, the area or charge Q3 extracted from inductor 6 should be greater than or equal to the returned charge Q4. The period during which charge Q3 is extracted extends from the rising edge of ABS until the inductor current crosses zero, following the rising edge of the PWM pulse. The period during which charge Q4 is returned extends from the zero current crossover to the next zero crossover, following the falling edge of the PWM pulse. The time of the zero crossover is detected and represented by ZCD.

[0139] Simulation results

[0140] Top-level simulations were performed on a buck-boost hysteresis synthesized current converter operating in ABS mode. CadenceVirtuoso (RTM) was used as the simulation software.

[0141] When the REFRESH signal is high, V RThe ABS is pulled high. ABS is set on the negative edge of REFRESH. This initiates a negative inductor current cycle. ABS is terminated by the PWM pulse. The rate of REFRESH determines whether it is an ABS cycle. The amount of energy taken from the output during an ABS cycle is greater than or equal to the energy returned in the following PWM cycle. This helps ensure that the output does not rise even under no-load conditions.

[0142] buck mode

[0143] refer to Figure 11A , Figure 11B and Figure 11C If in time period 1 / F AUDIO If there is no PWM loop inside, a refresh loop is issued. During REFRESH, the internal synthesized ramp V... R Pulled up and clamped to the upper window VWP (or "V"). W+ "Above. The falling edge of REFRESH triggers the ABS cycle."

[0144] During ABS, the converter issues a buck shutdown cycle: ramp V R Released and with output voltage V O The inductor current decreases proportionally. L Also related to the output voltage V O The rate of decrease is proportional. Slope V R Once it drops to the lower hysteresis window VRM (or "V") W- Below this, the PWM pulse goes high. The rise of the PWM will terminate the ABS pulse.

[0145] The PWM starts a buck-on cycle, and the buck-on cycle is terminated when the ramp V rises above the upper window VWP. The descent of the PWM pulse starts the buck-off cycle, which is terminated by a zero crossover, i.e., ZCD becomes HIGH.

[0146] Boost mode

[0147] refer to Figure 12A , Figure 12B and Figure 12C During REFRESH, slope V R It is pulled up and clamped above the upper window VWP. This is followed by an ABS cycle.

[0148] During ABS, the converter issues a buck shutdown cycle, and ramp V R Released. Ramp V R With respect to the output voltage V O The inductor current decreases proportionally. LIt also decreases at a rate proportional to the output voltage. Ramp V R Once the voltage drops below the lower hysteresis window VRM, the PWM pulse will go high. The high PWM pulse will terminate the ABS pulse.

[0149] PWM starts boosting and begins the cycle, and when the ramp V... R When the voltage rises above the upper window VWP, it terminates the boost-on cycle. The boost-off cycle is initiated when the PWM pulse goes low, and terminated when the ZCD goes high.

[0150] Buck-boost mode

[0151] refer to Figure 13A , Figure 13B and Figure 13C During REFRESH, slope V R It is pulled up and clamped above the upper window VWP. This is followed by an ABS cycle.

[0152] During ABS, the converter issues a buck shutdown cycle. During ABS, ramp V R It is released, and it decreases at a rate proportional to the output voltage Vo. The inductor current also decreases at a rate proportional to the output voltage. (Ramp V) R The voltage drops below the lower hysteresis window VRM and a PWM pulse is generated. The PWM pulse terminates the ABS pulse.

[0153] PWM starts boosting and begins the cycle, and when the ramp V... R When the voltage rises above the upper window VWP, the boost cycle ends.

[0154] In three-phase buck-boost mode, at the end of the boost on-phase, the controller enters the boost off-phase for a fixed period T2. For light load current, during the T2 phase, the ramp V... R It is clamped above the upper hysteresis window. After a fixed period T2, the buck shutdown cycle is initiated and terminated by ZCD.

[0155] Switch regulator

[0156] As previously described, REFRESH and ABS controls can be used in a variety of different switching regulators. For example, a switching regulator can take the form of a power controller IC (excluding on-chip power transistors), a power converter (including a controller and on-chip power transistors, but excluding on-chip inductors), or a power module (including a controller, on-chip power transistors, and on-chip inductors). Furthermore, a switching regulator can be a buck converter, a boost converter, or a buck-boost converter.

[0157] Buck-Boost Converter

[0158] refer to Figure 14 The first power management system 1401 is shown.

[0159] The power management system 1401 includes a switching regulator 1402 in the form of a buck-boost converter 1402 having an off-chip inductor 6. The switching regulator 1402 includes a controller 1403 and a digital core 1404.

[0160] The controller 1403 includes a control stage 32 and a power stage (not shown), which includes the zero-crossing detector 9, gate driver 10, control stage 32, and PFM control logic 33 as described above. The digital core 1404 includes ABS control 34, register 35, and timer 36.

[0161] The digital core 1404, including the operation of the ABS control 34, can be controlled by the host 44 via the I2C and SMPI bus interfaces, such as in the form of a microcontroller or a system-on-a-chip (SoC).

[0162] Controller 1403 generates ramp V R Window voltage V W+ V W- It also controls the switching between PWM and PFM modes. The digital core 1404 generates ABS and REFRESH signals. The digital core 1404 can communicate with the host 42 via SPMI and I2C ports. Audio band suppression (i.e., switching between the first and second modes) can be enabled and disabled via appropriate instructions through these communication channels. If for values ​​greater than or equal to T... REFRESH If no PWM pulse occurs within time T, then for a duration ΔT, the REFRESH signal goes high, initiating the REFRESH->ABS->PWM state transition. If audio band suppression mode is disabled, then the refresh time T... REFRESH The maximum time the bootstrap capacitor can retain its charge is typically around 500 μs. If audio band suppression is enabled, a shorter refresh time T is used. REFRESH Specifically, less than or equal to 50 μs (50 μs corresponds to 20 kHz).

[0163] boost converter

[0164] refer to Figure 15 The second power management system 1501 is shown.

[0165] The power management system 1501 includes a switching regulator 1502 in the form of a boost converter 1502 having an off-chip inductor 6. The switching regulator 1502 includes a controller 1503 and a digital core 1504.

[0166] The controller 1503 includes a control stage 32 and a power stage (not shown), which includes the zero-crossing detector 9, gate driver 10, control stage 32, and PFM control logic 33 as described above. The digital core 1404 includes ABS control 34, register 35, and timer 36.

[0167] The digital core 1504, including the operation of the ABS control 34, can be controlled by the host 44 via the I2C and SMPI bus interfaces, such as in the form of a microcontroller or SoC.

[0168] Controller 1503 generates ramp V R Window voltage V W+ V W- It also controls the switching between PWM and PFM modes. The digital core 1504 generates ABS and REFRESH signals. The digital core 1504 can communicate with the host 42 via SPMI and I2C ports. Audio band suppression (i.e., switching between the first and second modes) can be turned on and off via appropriate instructions through these communication channels. If for values ​​greater than or equal to T... REFRESH If no PWM pulse occurs within time T, then for a duration ΔT, the REFRESH signal goes high, initiating the REFRESH->ABS->PWM state transition. If audio band suppression mode is disabled, then the refresh time T... REFRESH The maximum time the bootstrap capacitor can retain its charge is typically around 500 μs. If audio band suppression is enabled, a shorter refresh time T is used. REFRESH Specifically, less than or equal to 50 μs.

[0169] Buck-boost converter with external power transistors and bootstrap capacitors

[0170] refer to Figure 16 The third power management system 1601 is shown.

[0171] The power management system 1601 includes a switching regulator 1602 in the form of a boost converter 1602 with an off-chip inductor 6. The switching regulator 1602 includes a controller 1603 and a digital core 1604.

[0172] The controller 1603 includes the zero-crossing detector 9, gate driver 10, control stage 32, and PFM control logic 33 as described above. The digital core 1404 includes ABS control 34, register 35, and timer 36.

[0173] The power stage 1623 is off-chip and includes first and second high-side NMOS switches M1 and M2, and third and fourth low-side NMOS switches M3 and M4. The power stage 1623 includes a bootstrap capacitor C. BOOT1C BOOT2 .

[0174] The digital core 1604 can be controlled by a host 44 via I2C and SMPI bus interfaces, such as a microcontroller or SoC.

[0175] Controller 1603 generates ramp V R Window voltage V W+ V W- It also controls the switching between PWM and PFM modes. The digital core 1604 generates ABS and REFRESH signals. The digital core 1604 can communicate with the host 42 via SPMI and I2C ports. Audio band suppression (i.e., switching between the first and second modes) can be turned on and off via appropriate instructions through these communication channels. If for values ​​greater than or equal to T... REFRESH If no PWM pulse occurs within time T, then for a duration ΔT, the REFRESH signal goes high, initiating the REFRESH->ABS->PWM state transition. If audio band suppression mode is disabled, then the refresh time T... REFRESH The maximum time the bootstrap capacitor can retain its charge is typically around 500 μs. If audio band suppression is enabled, a shorter refresh time T is used. REFRESH Specifically, less than or equal to 50 μs.

[0176] ABS

[0177] refer to Figure 16 and Figure 17 The ABS "buck-off" phase is timed to establish a negative inductor current, which is combined with subsequent PWM pulses to provide an overall negative current contribution to the output. This helps prevent the ABS pulses from overcharging the output when there is no load.

[0178] Figures 18A to 18C More details are provided for the PWM loop for buck operation.

[0179] Figure 18A It is aimed at Figure 16 The state diagram 1800 of the buck-boost controller is shown.

[0180] refer to Figure 16 and Figures 18A to 18C The state transitions of a buck-boost controller operating in buck mode will now be described.

[0181] In CCM mode, the inductor current is continuous. Starting from the Buck-OFF state 1801, when the PWM goes high, the FSM transitions to the Buck-ON state 1802. The inductor current ramps up. When the PWM goes low, the FSM transitions to the Buck-OFF state 1801, and the inductor current decreases. This state transition continues as long as the inductor current is above zero.

[0182] In Buck-OFF state 1801, ZCD goes high if the inductor current crosses zero.

[0183] If PWM is low and ZCD is high, the FSM transitions to tri-state 1803. The PWM signal has higher priority than ZCD. The system will remain in tri-state 1803 until either PWM or REFRESH goes high. If the load is moderate, REFRESH will not go high. This is the operation in PFM mode (DCM mode). In PFM mode, the FSM transitions between Buck-ON 1801, Buck-OFF 1802, and tri-state 1803. PWM has higher priority than REFRESH.

[0184] If the load is light, REFRESH can go high in tri-state 1803. A high REFRESH causes a transition to refresh state 1804. After a period in refresh state 1804, ABS goes high. ABS going high causes the state machine to transition from refresh state 1804 to ABS state 1805. In ABS state 1805, the current in the inductor ramps down. Since the current in the inductor was zero during refresh state 1804, the current in the inductor becomes negative when transitioning from refresh state 1804 to ABS state 1805, and the ramp remains negative until the PWM signal goes high. When the PWM goes high, FSM transitions from ABS state 1804 to Buck-ON state 1801. Therefore, during the REFRESH cycle, FSM transitions between Buck-ON, Buck-OFF, tri-state, refresh, and ABS states 1801, 1802, 1803, 1804, and 1805.

[0185] Figure 18B The simulated inductor current as a function of time is output. Figure 18B yes Figure 11C The enlarged view shows the state of the simulated buck-boost controller.

[0186] Figure 18BThe buck-boost controller is shown to transition from refresh state 1804 to ABS state 1805 in response to ABD, and to Buck-ON state 1801 and Buck-OFF state 1802 in response to PWM (not shown) and nPWM (not shown), respectively.

[0187] Figure 18C This is a table showing the gate drive signals UG1, LG1, UG2, and LG2 when the buck-boost controller is in each state.

[0188] The ABS method can also be used in buck controllers ( Figure 25 ) and boost controller ( Figure 26 )middle.

[0189] Figure 19A and Figure 19B More details are given for the PWM loop for two-switch buck operation.

[0190] Figure 19A This refers to state diagram 1900 for the buck controller.

[0191] refer to Figure 19A The state transitions of the buck controller will now be described.

[0192] Starting from Buck-ON state 1901, when the PWM goes low, the FSM transitions to Buck-OFF state 1902. The inductor current ramps down. When the PWM goes high, the FSM transitions to Buck-ON state 1901, and the inductor current increases.

[0193] If PWM is high and ZCD is high, the FSM transitions to tri-state 1903. The system remains in tri-state 1903 until either PWM or REFRESH goes high. If the load is moderate, REFRESH will not go high. This is the operation in PFM mode (DCM mode). In PFM mode, the FSM transitions between Buck-ON 1901, Buck-OFF 1902, and tri-state 1903. PWM has higher priority than REFRESH.

[0194] Figure 19B This is a table showing the gate drive signals UG1, LG1, UG2, and LG2 when the buck controller is in each state.

[0195] In this case, refresh state 1904 can only be used to pull up the internal ramp V. R This can only occur for a short period, i.e., tens of nanoseconds. This can be followed by ABS, and during ABS, the refresh capacitor is also recharged.

[0196] Figures 20A to 20CMore details about the PWM loop for boost operation are provided.

[0197] Figure 20A It is aimed at Figure 16 The state diagram of the buck-boost controller is shown below.

[0198] The state machine includes Boost-ON, Boost-OFF, tri-state, refresh, and ABS states 2001, 2002, 2003, 2004, and 2005.

[0199] Figure 20B yes Figure 12C The image is an enlarged view, and the state of the simulated buck-boost controller is shown.

[0200] Figure 20B The buck-boost controller is shown to transition from ABS state 2005 to Boost-ON state 2001 in response to PWM (not shown), and to Boost-OFF state 2002 in response to nPWM (not shown).

[0201] Figure 20C This is a table showing the gate drive signals UG1, LG1, UG2, and LG2 when the buck-boost controller is in each state.

[0202] Figure 21A and Figure 21B More details are given for the PWM loop for two-switch boost operation.

[0203] Figure 21A It is aimed at Figure 26 The state diagram of the boost controller is shown below.

[0204] refer to Figure 21A and Figure 26 The state transitions of the boost controller will now be described.

[0205] Starting from the Boost-ON state 2101, when the PWM goes low, the FSM transitions to the Boost-OFF state 2102. The inductor current ramps down. When the PWM goes high, the FSM transitions to the Buck-ON state 2101, and the inductor current increases.

[0206] If PWM is high and ZCD is high, the FSM transitions to tri-state 2103. The system remains in tri-state 2103 until either PWM or REFRESH goes high. If the load is moderate, REFRESH will not go high. This is the operation in PFM mode (DCM mode). In PFM mode, the FSM transitions between Boost-ON 2101, Boost-OFF 2102, and tri-state 2103. PWM has higher priority than REFRESH.

[0207] Figure 21B This is a table showing the gate drive signals UG1, LG1, UG2, and LG2 when the buck controller is in each state.

[0208] In this case, refresh state 2104 can only be used to pull up the internal ramp V. R This can only occur for a short period of time, i.e., tens of nanoseconds. This can be followed by ABS, and during ABS, the refresh capacitor is also recharged.

[0209] Figures 22A to 22C More details are provided for the PWM loop for buck-boost operation.

[0210] Figure 22A yes Figure 16 The state diagram of the buck-boost controller is shown below.

[0211] The state machine includes Boost-ON, T2 period, Buck-OFF, tri-state, refresh, and ABS states 2201, 2202, 2203, 2204, 2205, and 2206.

[0212] Figure 22B yes Figure 13C The image is an enlarged view, and the state of the simulated buck-boost controller is shown.

[0213] Figure 22B The buck-boost controller is shown to transition from ABS state 2205 to Boost-ON state 2201 in response to PWM (not shown), and to T2 period 2202 in response to nPWM (not shown), and to Buck-OFF state 2203 after the T2 period has elapsed.

[0214] Figure 22C This is a table showing the gate drive signals UG1, LG1, UG2, and LG2 when the buck-boost controller is in each state.

[0215] Figure 23 yes Figure 22B The diagram shows a current-time plot.

[0216] Also refer to Figure 23 In reference Figures 22A to 22C In the simulation described, the charge Q5 extracted from the inductor is less than the charge Q6 returned during the PWM. Therefore, the output voltage V OUT It can be increased as described above.

[0217] Figure 24A and 24B The diagram illustrates methods for reducing or even avoiding the output voltage V. OUT Two additional methods.

[0218] Figure 24A The illustration shows a modified current-time plot where a longer ABS period is used. This extends the time during which charge Q7 is drawn from the inductor, and thus increases the amount of charge Q7 drawn from the inductor to meet the requirement that the amount of charge Q7 drawn from the inductor is less than the amount of charge Q8 returned during the PWM period. Figure 24B The illustration shows a modified current-time plot where an additional T2 period state (hereinafter referred to as "ABS T2 period") can be used to extend the time during which charge Q9 is drawn from the inductor, and thus increase the amount of charge Q9 drawn from the inductor so that the amount of charge Q9 drawn from the inductor is less than the amount of charge Q returned during the PWM period. 10 Requirements.

[0219] refer to Figure 24B , Figure 24C and Figure 24D In addition to Boost-ON, T2 period, Buck-OFF, tri-state, refresh, and ABS states 2401, 2402, 2403, 2404, 2405, and 2406, an additional ABS T2 period state 2407 is provided after ABS state 2406 and Boost-ON state 2401.

[0220] Buck-boost converter with on-chip power transistors and off-chip bootstrap capacitors

[0221] refer to Figure 25 The fourth power management system 2301 is shown.

[0222] The power management system 2501 includes a switching regulator 2502 in the form of a buck-boost converter 2502 having an off-chip inductor 6. The switching regulator 2502 includes a controller 2503 and a digital core 2504.

[0223] The controller 2503 includes the zero-crossing detector 9, gate driver 10, control stage 32, and PFM control logic 33 as described above. The digital core 1404 includes ABS control 34, register 35, and timer 36.

[0224] Power stage 2523 includes on-chip first and second high-side NMOS switches M1, M2 and third and fourth low-side NMOS switches M3, M4. Power stage 2523 includes off-chip bootstrap capacitor C. BOOT1 C BOOT2 .

[0225] The digital core 2504 can be controlled by a host 44 via I2C and SMPI bus interfaces, such as a microcontroller or SoC.

[0226] Controller 2503 generates ramp V R Window voltage V W+ V W- It also controls the switching between PWM and PFM modes. The digital core 2504 generates ABS and REFRESH signals. The digital core 2504 can communicate with the host 42 via SPMI and I2C ports. Audio band suppression (i.e., switching between the first and second modes) can be turned on and off via appropriate instructions through these communication channels. If for values ​​greater than or equal to T... REFRESH If no PWM pulse occurs within time T, then for a duration ΔT, the REFRESH signal goes high, initiating the REFRESH->ABS->PWM state transition. If audio band suppression mode is disabled, then the refresh time T... REFRESH The maximum time the bootstrap capacitor can retain its charge is typically around 500 μs. If audio band suppression is enabled, a shorter refresh time T is used. REFRESH Specifically, less than or equal to 50 μs.

[0227] Buck converter with on-chip power transistors and off-chip bootstrap capacitors

[0228] refer to Figure 26 The fifth power management system 2601 is shown.

[0229] The power management system 2601 includes a switching regulator 2602 in the form of a buck converter 2602 having an off-chip inductor 6. The switching regulator 2602 includes a controller 2203 and a digital core 2604.

[0230] The controller 2603 includes the zero-crossing detector 9, gate driver 10, control stage 32, and PFM control logic 33 as described above. The digital core 2604 includes ABS control 34, register 35, and timer 36.

[0231] The power stage 2623 includes an on-chip first high-side NMOS switch M1 and a third low-side NMOS switch M3. The power stage 2623 also includes an off-chip bootstrap capacitor C. BOOT .

[0232] The digital core 2604 can be controlled by a host 44 via I2C and SMPI bus interfaces, such as a microcontroller or SoC.

[0233] Controller 2603 generates ramp V R Window voltage V W+ V W- It also controls the switching between PWM and PFM modes. The digital core 2604 generates ABS and REFRESH signals. The digital core 2604 can communicate with the host 42 via SPMI and I2C ports. Audio band suppression (i.e., switching between the first and second modes) can be turned on and off via appropriate instructions through these communication channels. If for values ​​greater than or equal to T... REFRESH If no PWM pulse occurs within time T, then for a duration ΔT, the REFRESH signal goes high, initiating the REFRESH->ABS->PWM state transition. If audio band suppression mode is disabled, then the refresh time T... REFRESH The maximum time the bootstrap capacitor can retain its charge is typically around 500 μs. If audio band suppression is enabled, a shorter refresh time T is used. REFRESH Specifically, less than or equal to 50 μs.

[0234] Buck converter with on-chip power transistors and no bootstrap capacitor

[0235] refer to Figure 27 The sixth power management system 2701 is shown.

[0236] The power management system 2301 includes a switching regulator 2702 in the form of a buck converter 2702 having an off-chip inductor 6. The switching regulator 2702 includes a controller 2703 and a digital core 2704.

[0237] The controller 2703 includes the zero-crossing detector 9, gate driver 10, control stage 32, and PFM control logic 33 as described above. The digital core 2704 includes ABS control 34, register 35, and timer 36.

[0238] The power stage 2723 includes an on-chip first high-side NMOS switch M1 and a third low-side NMOS switch M3.

[0239] The digital core 2704 can be controlled by a host 44 via I2C and SMPI bus interfaces, such as a microcontroller or SoC.

[0240] Controller 2703 generates ramp V R Window voltage V W+ V W-It also controls the switching between PWM and PFM modes. The digital core 2704 generates ABS and REFRESH signals. The digital core 2704 can communicate with the host 42 via SPMI and I2C ports. Audio band suppression (i.e., switching between the first and second modes) can be turned on and off via appropriate instructions through these communication channels. If for values ​​greater than or equal to T... REFRESH If no PWM pulse occurs within time T, then for a duration ΔT, the REFRESH signal goes high, initiating the REFRESH->ABS->PWM state transition. If audio band suppression mode is disabled, then the refresh time T... REFRESH The maximum time the bootstrap capacitor can retain its charge is typically around 500 μs. If audio band suppression is enabled, a shorter refresh time T is used. REFRESH Specifically, less than or equal to 50 μs.

[0241] Boost converter with on-chip power transistors and no bootstrap capacitor

[0242] refer to Figure 28 The sixth power management system 2801 is shown.

[0243] The power management system 2801 includes a switching regulator 2802 in the form of a boost converter 2802 having an off-chip inductor 6. The switching regulator 2802 includes a controller 2803 and a digital core 2804.

[0244] The controller 2803 includes the zero-crossing detector 9, gate driver 10, control stage 32, and PFM control logic 33 as described above. The digital core 2804 includes ABS control 34, register 35, and timer 36.

[0245] The power stage 2823 includes an on-chip first high-side NMOS switch M1 and a third low-side NMOS switch M3.

[0246] The digital core 2804 can be controlled by a host 44 via I2C and SMPI bus interfaces, such as a microcontroller or SoC.

[0247] Controller 2803 generates ramp V R Window voltage V W+ V W- It also controls the switching between PWM and PFM modes. The digital core 2804 generates ABS and REFRESH signals. The digital core 2804 can communicate with the host 42 via SPMI and I2C ports. Audio band suppression can be turned on and off (i.e., switching between the first and second modes) via appropriate instructions through these communication channels. If for values ​​greater than or equal to T... REFRESHIf no PWM pulse occurs within time T, then for a duration ΔT, the REFRESH signal goes high, initiating the REFRESH->ABS->PWM state transition. If audio band suppression mode is disabled, then the refresh time T... REFRESH The maximum time the bootstrap capacitor can retain its charge is typically around 500 μs. If audio band suppression is enabled, a shorter refresh time T is used. REFRESH Specifically, less than or equal to 50 μs.

[0248] Revise

[0249] It will be understood that various modifications can be made to the embodiments described above. Such modifications may involve equivalent and other features known in the design, manufacture, and use of power management and its components, and may be used in place of or supplement to the features already described herein. A feature of one embodiment may be replaced or supplemented by a feature of another embodiment.

[0250] A simpler ramp generator circuit can be used, which employs a resistor connected in series with the capacitor across the inductor. The voltage across the capacitor can be used as the ramp. However, in this method, noise in the switching node (LX) can affect the ramp voltage.

[0251] PFM operation can be omitted, so the power management system can operate only in continuous conduction mode (CCM).

[0252] Although the claims have been formulated as specific combinations of features in this application, it should be understood that the scope of this invention also includes any novel feature or any novel combination of features, or any generalization thereof, explicitly or implicitly disclosed herein, whether or not it relates to the same invention currently claimed in any claim, and whether or not it solves the same technical problem as this invention. The applicant hereby notifies that new claims may be filed against these features and / or combinations thereof during the proceedings of this application or any further applications derived therefrom.

Claims

1. A method for operating a hysteresis synthetic current mode switching regulator, wherein the PWM pulse is generated by a PWM generator (20) based on a ramp voltage V R The ramp voltage V is generated. R Upper window voltage V W+ With lower window voltage V W- It oscillates between these values ​​and depends on the control voltage V. C The control voltage V C Depends on the current I through the inductor (6) connected to the output node L The method includes: Determine whether the time interval T is equal to or greater than a given time period T when no PWM pulses are generated. REFRESH Has the time period T elapsed, wherein the given time period T REFRESH Related to audio frequency or the discharge time of bootstrap capacitors; When it is certain that, for a given duration ΔT, the ramp voltage is pulled up to or above the upper window voltage; as well as When the given duration has elapsed, the ramp voltage is reduced until the rising edge of the PWM pulse is generated.

2. The method according to claim 1, wherein the given time period T REFRESH Between 400 and 600 microseconds or between 5 and 50 microseconds.

3. The method according to claim 1 or 2, wherein the ramp voltage V is reduced. R include: The ramp voltage is reduced at a certain rate so that the energy stored in the inductor (6) is equal to or greater than the energy output by the inductor during the PWM pulse.

4. The method of claim 3, wherein the ramp voltage V is reduced. R include: Adjust the gain of the transconductance amplifier (38), which is related to the output voltage V. OUT The ramp voltage is generated unrelatedly.

5. The method of claim 1, wherein in response to reducing the ramp voltage V R A first amount of energy is extracted from the inductor (6), the first amount of energy is greater than or equal to a second amount of energy, and the second amount of energy is provided to the inductor from the time period starting from the zero current crossover.

6. An apparatus configured to perform the method of any one of claims 1 to 5.

7. A control circuit for controlling a hysteresis synthetic current mode switching regulator, wherein the PWM pulse is generated by a PWM generator (20) based on a ramp voltage V. R The ramp voltage V is generated. R Upper window voltage V W+ With lower window voltage V W- It oscillates between these values ​​and depends on the control voltage V. C The control voltage V C Depends on the current I through the inductor (6) connected to the output node L The control circuit is configured to: Determine whether the time interval T is equal to or greater than a given time period T when no PWM pulses are generated. REFRESH Has the time period T elapsed, wherein the given time period T REFRESH Related to audio frequency or the discharge time of bootstrap capacitors; When it is affirmatively determined, for a given duration ΔT, the ramp voltage is pulled up to or above the upper window voltage; and When the given duration has elapsed, the ramp voltage is reduced until the rising edge of the PWM pulse is generated.

8. The control circuit according to claim 7, wherein the control circuit is configured to set a first control signal REFRESH, the first control signal REFRESH being provided to the control stage (32) of the switching regulator, such that the ramp voltage V R Pulled up to the upper window voltage V W+ Or pull up to the upper window voltage V W+ above.

9. The control circuit according to claim 8, wherein the control circuit is configured to set a second control signal ABS, the second control signal ABS being provided to the pulse frequency modulation control circuit (33) and the control stage (32) being provided to the switching regulator, such that the ramp voltage V R Pulled up to the upper window voltage V W+ Or pull up to the upper window voltage V W+ above.

10. A switching regulator, comprising: Control level (32), including: - Synthetic ramp generator circuit (11) is used to generate ramp voltage V R The synthetic ramp generator circuit includes: Transconductance amplifier (38); Voltage ramp node (39); Modulator capacitor (C) R ), is connected between the voltage ramp node and the reference level node (GND); A first switch (S4) is located between the output of the transconductance amplifier and the voltage ramp node; and The second switch (S5) is located between the upper window voltage V. W+ Between and the voltage ramp node; - Hysteresis control circuit (13) is used to control the ramp voltage at the upper window voltage V W+ With lower window voltage V W- The oscillation between them generates a first signal and a second signal, respectively, for setting and resetting the PWM signal; and - A latch (20) for generating a PWM pulse using the first signal and the second signal; and According to any one of claims 7 to 9, the control circuit (34) is configured to receive the PWM pulse from the control stage and provide control signals REFRESH and ABS to the control stage for controlling the gain of the transconductance amplifier and controlling the first switch and the second switch.

11. The switching regulator according to claim 10, further comprising: Power stage, used to gradually increase and / or decrease the input voltage to provide the output voltage.

12. The switching regulator according to claim 10 or 11, wherein the switching regulator is a buck controller, a boost controller, and / or a buck-boost controller.

13. The switching regulator according to claim 10, further comprising: One or more bootstrap capacitors.

14. A monolithic integrated circuit comprising a switching regulator according to any one of claims 10 to 13.

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