Clock gating cell and integrated circuit

Abstract

Clock gating cells and integrated circuits are provided. The clock gating cell can include a first 2-input logic gate configured to receive a clock input and a first signal and generate a second signal, an inverter configured to receive the second signal and generate a clock output, and a 3-input logic gate including a second 2-input logic gate, the 3-input logic gate configured to generate the first signal. The first 2-input logic gate and the second 2-input logic gate form a set-reset (SR) latch through cross-coupling, the 3-input logic gate includes a feedback transistor configured to exclusively receive an internal signal of the first 2-input logic gate, and activation of the feedback transistor by the internal signal is configured to avoid a race condition by preventing pull-up or pull-down of a first node at which the first signal is generated.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0136905 filed on October 30, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a clock gating cell, and more particularly, to a low-power clock gating cell and an integrated circuit including the clock gating cell. Background Art

[0004] Integrated circuits that process digital signals can operate synchronously with a clock signal. For example, an integrated circuit may include a digital circuit that generates an output signal by processing an input signal in response to the rising and / or falling edges of a clock signal. When a clock edge does not occur, the operation of the digital circuit may be interrupted. Clock gating can refer to stopping or resuming the operation of a digital circuit by selectively providing a clock signal, and clock gating can be used to reduce the power consumption of a digital circuit.

[0005] An integrated circuit may include a clock gating circuit, i.e., a clock gating unit, which selectively outputs a clock signal in response to a control signal, wherein the clock gating unit may be required to stop and resume supply of the clock signal to prevent malfunction of a digital circuit receiving the clock signal, and at the same time may be required to have high efficiency, for example, reduced area and low power consumption. Summary of the Invention

[0006] Example embodiments provide a clock gating unit for performing clock gating with reduced area and low power consumption, and an integrated circuit including the same.

[0007] According to an aspect of an example embodiment, there is provided an integrated circuit including a clock gating unit, wherein the clock gating unit includes: a first 2-input logic gate configured to receive a clock input and a first signal and generate a second signal; an inverter configured to receive the second signal and generate a clock output; and a 3-input logic gate including a second 2-input logic gate configured to generate the first signal, wherein the first 2-input logic gate and the second 2-input logic gate form a set-reset (SR) latch by cross-coupling, the 3-input logic gate including a feedback transistor configured to exclusively receive an internal signal of the first 2-input logic gate, and the feedback transistor, when activated by the internal signal, is configured to avoid a race condition by preventing a first node from being pulled up or down at which the first signal is generated.

[0008] According to an aspect of an example embodiment, there is provided a clock gating unit including: a first NAND gate configured to receive a clock input and a first signal and generate a second signal; an inverter configured to receive the second signal and generate a clock output; and a 2-1 OR NAND (OAI) gate including a second NAND gate configured to generate the first signal, wherein the first NAND gate and the second NAND gate form a set-reset (SR) latch by cross-coupling, and wherein the 2-1 OAI includes: a first n-channel field effect transistor (NFET) configured to receive an inverted enable input; a second NFET configured to receive the second signal; a third NFET configured to receive the clock input; and a fourth NFET connected in series with the third NFET between a first node at which the first signal is generated and a ground node, the fourth NFET configured to exclusively receive an internal signal of the first NAND gate to avoid a race condition.

[0009] According to an aspect of an example embodiment, a clock gating unit is provided, comprising: a first NOR gate configured to receive a clock input and a first signal and generate a second signal; an inverter configured to receive the second signal and generate a clock output; and a 2-1 AND-NOR (AOI) gate, the 2-1 AOI gate including a second NOR gate, the 2-1 AOI gate configured to generate the first signal, wherein the first NOR gate and the second NOR gate form a set-reset (SR) latch by cross-coupling, and wherein the 2-1 AOI gate comprises: a first p-channel a field effect transistor (PFET) configured to receive an enable input; a second PFET configured to receive the second signal; a third PFET configured to receive the clock input; and a fourth PFET connected in series with the third PFET between a first node at which the first signal is generated and a positive power supply node, wherein the fourth PFET is configured to exclusively receive an internal signal of the first NOR gate, and activation of the fourth PFET is configured to avoid a race condition. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and / or other aspects will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating an example of a clock gating unit according to an example embodiment;

[0012] Figure 2 is a block diagram illustrating a clock gating unit according to an example embodiment;

[0013] Figure 3 is a timing diagram illustrating an example of the operation of a clock gating unit according to an example embodiment;

[0014] Figures 4A to 4D is a circuit diagram illustrating an example of a clock gating unit according to an example embodiment;

[0015] Figure 5A and Figure 5B is a circuit diagram illustrating an example of a clock gating unit according to an example embodiment;

[0016] Figure 6 is a block diagram illustrating an example of a clock gating unit according to an example embodiment;

[0017] Figure 7 is a timing diagram illustrating an example of the operation of a clock gating unit according to an example embodiment;

[0018] Figures 8A to 8Eis a circuit diagram illustrating an example of a clock gating unit according to an example embodiment;

[0019] Figures 9A to 9C is a circuit diagram illustrating an example of a clock gating unit according to an example embodiment;

[0020] Figure 10 is a block diagram illustrating an example of an integrated circuit including a clock gating unit according to example embodiments;

[0021] Figure 11 is a flowchart of a method of manufacturing an integrated circuit according to example embodiments. DETAILED DESCRIPTION

[0022] Here, logic "1" may correspond to a high voltage, for example, a positive power supply voltage VDD or a voltage close to the positive power supply voltage VDD, and may be referred to as a high level or an active state, while logic "0" may correspond to a low voltage, for example, a ground potential or a voltage close to the ground potential, and may be referred to as a low level or an inactive state. In addition, a ground node may refer to a node to which a ground potential (or a negative power supply voltage) is applied, and a positive power supply node may refer to a node to which a positive power supply voltage VDD is applied. In addition, in this specification, a transistor may have any structure that provides a complementary transistor (for example, an n-channel transistor and a p-channel transistor), and as a non-limiting example, may be implemented as a planar field effect transistor (FET), a fin field effect transistor (FinFET), a gate-all-around field effect transistor (GAAFET), a vertical field effect transistor (VFET), and the like.

[0023] Figure 1 is a block diagram illustrating an example of a clock gating unit according to an example embodiment. In some embodiments, the clock gating unit 10 may be included in an integrated circuit manufactured by a semiconductor process and may be referred to as a clock gating circuit or an integrated clock gating unit.

[0024] Reference Figure 1, the clock gating unit 10 can receive a clock input C_IN and an enable input E_IN, and generate a clock output C_OUT. The clock output C_OUT can oscillate like the clock input C_IN, or be maintained at a constant voltage level according to the enable input E_IN. For example, the clock gating unit 10 can be in an enabled state in response to an activated enable input E_IN, and can generate a clock output C_OUT that oscillates according to the clock input C_IN in the enabled state. In addition, the clock gating unit 10 can be in a disabled state in response to an inactivated enable input E_IN, and can generate a clock output C_OUT with a specific level (e.g., logic "1" or logic "0") in the disabled state. In this specification, it can be considered that the clock gating unit 10 in the enabled state provides the clock output C_OUT, while the clock gating unit 10 in the disabled state stops providing the clock output C_OUT.

[0025] In order to prevent malfunction of the digital circuit receiving the clock output C_OUT, the clock gating unit 10 may stop or resume the provision of the clock output C_OUT in synchronization with the clock input C_IN. Figures 2 to 5B As described, the clock gating unit 10 can stop or resume providing the clock output C_OUT in response to the rising edge of the clock input C_IN, and provide the clock output C_OUT to a digital circuit that operates in response to the rising edge of the clock output C_OUT, such as a positive edge triggered flip-flop. In addition, in some embodiments, as described below with reference to Figures 6 to 9C As described, the clock gating unit 10 can stop or resume the provision of the clock output C_OUT in response to the falling edge of the clock input C_IN, and provide the clock output C_OUT to a digital circuit that operates in response to the falling edge of the clock output C_OUT, for example, a negative edge triggered flip-flop. In order to operate synchronously with the clock input C_IN, the clock gating unit 10 may include a set-reset (SR) latch structure and may latch the enable input E_IN according to the clock input C_IN. Figure 1 As shown, the clock gating unit 10 may include a first 2-input logic gate G11 , a 3-input logic gate 12 , and an inverter G14 .

[0026] The first 2-input logic gate G11 can receive a clock input C_IN and a first signal S1 and generate a second signal S2 by performing a logic operation on the clock input C_IN and the first signal S1. The first 2-input logic gate G11 can be cross-coupled with a second 2-input logic gate G12 provided by the 3-input logic gate 12 to form an SR latch. In some embodiments, the first 2-input logic gate G11 and the second 2-input logic gate G12 can be NAND gates, while in some other embodiments, they can be NOR gates. The second signal S2 generated by the first 2-input logic gate G11 can be provided to an inverter G14, and the inverter G14 can generate a clock output C_OUT by inverting the second signal S2.

[0027] The 3-input logic gate 12 may receive an enable input E_IN, a clock input C_IN, and a second signal S2, and generate a first signal S1 by performing a logic operation on the enable input E_IN, the clock input C_IN, and the second signal S2 according to the second 2-input logic gate G12 and the third 2-input logic gate G13. Figure 1 The 3-input logic gate 12 is shown to include a second 2-input logic gate G12 and a third 2-input logic gate G13, but Figure 1 The equivalent circuit of the 3-input logic gate 12 is shown, and the 3-input logic gate 12 can provide the same Figure 1 The second 2-input logic gate G12 and the third 2-input logic gate G13 shown, connected together and receiving input signals, have the same functions. For example, in a 3-input logic gate 12, the second 2-input logic gate G12 and the third 2-input logic gate G13 may share at least one component, such as at least one transistor, and may not be separated from each other. In some embodiments, the second 2-input logic gate G12 may include a NAND gate, and the third 2-input logic gate G13 may include an OR gate. Thus, the 3-input logic gate 12 may include a 2-1 OAI (OR-AND-INVERTER) gate. Furthermore, in some embodiments, the second 2-input logic gate G12 may include a NOR gate, and the third 2-input logic gate G13 may include an AND gate. Thus, the 3-input logic gate 12 may be a 2-1 AOI (AND-OR-INVERTER) gate.

[0028] like Figure 1As shown, the clock gating unit 10 can omit a circuit element that oscillates according to the oscillation of the clock input C_IN (for example, an inverter for generating an inverted clock input) in the deactivated state, so the clock gating unit 10 can exhibit reduced power consumption in the deactivated state. In addition, as described below with reference to the accompanying drawings, the number of transistors receiving the clock input C_IN can be reduced, and since the input capacitance of the clock input C_IN is reduced, not only the power consumption of the clock input C_IN can be reduced, but also the delay of the clock input C_IN can be reduced.

[0029] like Figure 1 As shown, the 3-input logic gate 12 may include a feedback transistor FT1. The feedback transistor FT1 may receive the internal signal INT of the first 2-input logic gate G11 and may be controlled by the internal signal INT. To avoid race conditions, the feedback transistor FT1 may prevent the first node N1 from being pulled down (or discharged) or pulled up (or charged) in response to the internal signal INT, generating a first signal S1 at the first node N1. Only the feedback transistor FT1 may receive the internal signal INT of the first 2-input logic gate G11, and additional components other than the feedback transistor FT1 may be omitted from the first 2-input logic gate G11 and the 3-input logic gate 12 to avoid race conditions. In other words, in addition to the structure for outputting the internal signal INT to the outside, the first 2-input logic gate G11 may only have a structure for logic operations; and in addition to the feedback transistor FT1, the 3-input logic gate 12 may only have a structure for logic operations. Therefore, race conditions in the clock gating unit 10 can be easily avoided, resulting in a reduced area and high operational reliability.

[0030] Figure 2 is a block diagram illustrating an example of a clock gating unit according to an example embodiment, Figure 3 is a timing diagram illustrating an example of the operation of a clock gating unit according to an example embodiment. In detail, Figure 2 The block diagram shows the Figure 1 The clock gating unit 20 of the example of the clock gating unit 10 generates a clock output C_OUT of logic “0” in the disabled state, Figure 3 The timing diagram shows the Figure 2 For ease of explanation, the signal that changes with time in the clock gating unit 20 is Figure 3 The propagation delay can be ignored in the timing diagram and the above reference Figure 1 The same description is given Figure 2 and Figure 3 Description.

[0031] Reference Figure 2 ,and Figure 1 Similar to the clock gating unit 10 of FIG. 1 , the clock gating unit 20 may include a first NAND gate G21, a 2-1OAI gate 22, and an inverter G24, and may further include a NOR gate G25. The NOR gate G25 may receive the clock enable E and the test enable SE, generate an inverted enable input / E_IN, and provide the inverted enable input / E_IN to the 2-1OAI gate 22. In other embodiments, Figure 2 Unlike the example shown in FIG. 1 , the NOR gate G25 can be omitted, so the clock gating unit 20 can directly receive the inverted enable input / E_IN from the outside. In addition, in other embodiments, Figure 2 Different from the example shown, the clock gating unit 20 may include an inverter that replaces the NOR gate G25 to generate a clock signal. Figure 1 The enable input E_IN of the MOSFET is used to generate the inverted enable input / E_IN.

[0032] The first NAND gate G21 can form an SR latch (or SR NAND latch) together with the second NAND gate G22 provided by the 2-1OAI gate 22. Figure 2 As shown, the first NAND gate G21 and the second NAND gate G22 can be cross-coupled via the first node N1 and the second node N2. When the first signal S1 is a logic "1," the first NAND gate G21 can generate the second signal S2 based on the clock input C_IN. When the first signal S1 is a logic "0," the first NAND gate G21 can generate the second signal S2 regardless of the clock input C_IN. The 2-1OAI gate 22 can generate the first signal S1 by performing a logical operation on the inverted enable input / E_IN, the clock input C_IN, and the second signal S2 using the second NAND gate G22 and the OR gate G23.

[0033] Reference Figure 3 , the clock input C_IN can oscillate with a period T_CLK. Before time point t31, the clock enable E and / or the test enable SE can be logic "1". Therefore, the inverted enable input / E_IN can be logic "0", and the clock gating unit 20 can be in an enabled state. Due to the second NAND gate G22, the first signal S1 can be logic "1", and the second signal S2 can be the same as the inverted version of the clock input C_IN. Therefore, the clock output C_OUT can be the same as the clock input C_IN (for example, a delayed version of the clock input C_IN).

[0034] At time point t31, the clock enable E and the test enable SE can be changed to logic "0". Therefore, the inverting enable input / E_IN can be changed to logic "1", and the clock gating unit 20 can enter the disabled state. Since the clock input C_IN is logic "1", the first signal S1 can remain at logic "1", and the second signal S2 and the clock output C_OUT can also remain at logic "0" and logic "1", respectively. Next, at time point t32, a falling edge of the clock input C_IN can occur, so through the first NAND gate G21, the second signal S2 and the clock output C_OUT can be changed to logic "1" and logic "0", respectively. In addition, through the second NAND gate G22, the first signal S1 can be changed to logic "0", so due to the first NAND gate G21, the second signal S2 can remain at logic "1" regardless of the clock input C_IN. Therefore, when the clock gating unit 20 is in the disabled state, the clock output C_OUT can remain at logic "0".

[0035] At time point t33, the clock enable E and / or the test enable SE may be changed to logic "1". Therefore, the inverting enable input / E_IN may be changed to logic "0", and the clock gating unit 20 may enter the enabled state. Since the clock input C_IN and the second signal S2 are logic "1", the first signal S1 may remain at logic "0", and therefore, the second signal S2 and the clock output C_OUT may also remain at logic "1" and logic "0", respectively. Next, at time point t34, a falling edge of the clock input C_IN may occur, and therefore, through the second NAND gate G22, the first signal S1 may be changed to logic "1". However, since the clock input C_IN is logic "0", the second signal S2 and the clock output C_OUT may remain at logic "1" and logic "0", respectively. Next, at time point t35, a rising edge of the clock input C_IN may occur, and since the first signal S1 is logic "1", the second signal S2 and the clock output C_OUT may be changed to logic "0" and logic "1", respectively.

[0036] At time t36, the clock enable E and the test enable SE may transition to logic "0." Consequently, the inverted enable input / E_IN may transition to logic "1," and the clock gating unit 20 may enter a disabled state. Since the second signal S2 is logic "1," the first signal S1 may transition to logic "0" through the second NAND gate G22. Consequently, regardless of the clock input C_IN, the second signal S2 and the clock output C_OUT may maintain logic "1" and logic "0," respectively.

[0037] At time point t37, the clock enable E and / or the test enable SE may transition to logic "1." Therefore, the inverted enable input / E_IN may transition to logic "0," and the clock gating unit 20 may enter an enabled state. Although the first signal S1 may transition to logic "1" via the OR gate G23 and the second NAND gate G22, the clock input C_IN is logic "0," and thus, the second signal S2 and the clock output C_OUT may maintain logic "1" and logic "0," respectively. Next, at time point t38, a rising edge of the clock input C_IN may occur, and the second signal S2 and the clock output C_OUT may transition to logic "0" and logic "1," respectively.

[0038] As described above, when the clock gating unit 20 enters the disabled state, the clock output C_OUT can remain at logic "0" after a falling edge synchronized with the clock input C_IN. Furthermore, when the clock gating unit 20 enters the enabled state, the clock output C_OUT can oscillate after a rising edge synchronized with the clock input C_IN. Thus, the clock gating unit 20 can provide the clock output C_OUT to a digital circuit (e.g., a positive-edge-triggered flip-flop) that operates in response to a rising edge of the clock output C_OUT, and prevent malfunctions caused by race conditions that affect clock gating in the digital circuit.

[0039] Return to reference Figure 2 , the 2-1OAI gate 22 may include a feedback transistor FT2, and only the feedback transistor FT2 receives the internal signal INT of the first NAND gate G21 to avoid a race condition. For example, when a rising edge of the clock input C_IN occurs in the enabled state of the clock gating unit 20, based on factors including the slew rate of the rising edge and the gate delay difference between the first NAND gate G21 and the OR gate, the rising edge of the signal output by the OR gate G23 may occur earlier than the falling edge of the second signal S2, or may appear near the falling edge of the second signal S2. Therefore, the voltage level of the first signal S1 that needs to be maintained at logic "1" may be unstable, resulting in possible errors in the clock output C_OUT. The feedback transistor FT2 can avoid this race condition by preventing the first node N1 from being generated by the first signal S1 from being pulled down (or discharged) according to the internal signal INT. The following will refer to Figures 4A to 4D 、 Figure 5A and Figure 5B An example of the clock gating cell 20 including the feedback transistor FT2 will be described.

[0040] Figures 4A to 4D is a circuit diagram illustrating an example of a clock gating unit according to example embodiments. Figures 4A to 4D The circuit diagram shows the Figure 2of the clock gating unit 20. Hereinafter, in the discussion of the clock gating unit 40a, Figures 4A to 4D the repetitive description and the description identical to that given above with reference to Figure 2 and Figure 3 will be omitted.

[0041] With reference to Figure 4A , the clock gating unit 40a can include a first NAND gate G41a, a 2-1 OA I gate 42a, an inverter G44a, and a NOR gate G45a. The 2-1 OA I gate 42a can include a first n-channel field effect transistor (NFET) N41a, a second NFET N42a, and a third NFET N43a for receiving an inverted enable input / E_IN, a second signal S2, and a clock input C_IN, respectively, and can further include a fourth NFET N44a for receiving an internal signal INT as a feedback transistor. As shown in Figure 4A , the fourth NFET N44a can be connected in series with the third NFET N43a between a first node N1 at which the first signal S1 is generated and a ground node, and only the fourth NFET N44a receives the internal signal INT of the first NAND gate G41a. In addition, the second NFET N42a can be connected in series with the third NFET N43a and the fourth NFET N44a between the first node N1 and the ground node. In the clock gating unit 40a of Figure 4A , the second NFET N42a, the third NFET N43a, and the fourth NFET N44a can be sequentially connected in series with each other between the first node N1 and the ground node, and a drain of the first NFET N41a can be connected to a source of the second NFET N42a and a drain of the third NFET N43a, and a source of the first NFET N41a can be connected to the ground node. As shown in Figure 4A , the 2-1 OA I gate 42a can further include a first p-channel field effect transistor (PFET) P41a, a second PFET P42a, and a third PFET P43a for receiving the inverted enable input / E_IN, the second signal S2, and the clock input C_IN, respectively.

[0042] The series configuration of the second NFET N42a, the third NFET N43a, and the fourth NFET (feedback transistor) N44a can be referred to as an NFET stack. The NFET stack is configured to hold the first signal S1 at a stable voltage level based on the internal signal INT, the state of the N46a will not change due to the race condition described above with reference to Figure 3 , and the second signal S2 will not generate jitter due to the race condition.

[0043] The first NAND gate G41a may include a fifth NFET N45a and a sixth NFET N46a for receiving a clock input C_IN and a first signal S1, respectively, and the fifth NFET N45a and the sixth NFET N46a may be connected in series to each other between a second node N2 at which the second signal S2 is generated and a ground node. An internal signal INT may be generated at a node to which the source of the fifth NFET N45a and the drain of the sixth NFET N46a are connected. Therefore, although the first signal S1 may be logic "1", the internal signal INT may be logic "0" due to the turned-on sixth NFET N46a, and therefore, the fourth NFET N44a is turned off. Therefore, the discharge (or pull-down) of the first node N1 may be prevented, and a race condition may be avoided. As described above, the internal signal INT may be provided only to the fourth NFET N44a. Figure 4A As shown, the first NAND gate G41a may further include a fourth PFET P44a and a fifth PFET P45a for receiving the clock input C_IN and the first signal S1, respectively.

[0044] Reference Figure 4B The clock gating unit 40b may include a first NAND gate G41b, a 2-1OAI gate 42b, an inverter G44b, and a NOR gate G45b. The 2-1OAI gate 42b may include a first NFET N41b, a second NFET N42b, a third NFET N43b, and a fourth NFET N44b for receiving the inverted enable input / E_IN, the second signal S2, the clock input C_IN, and the internal signal INT, respectively. Furthermore, the first NAND gate G41b may include a fifth NFET N45b and a sixth NFET N46b for receiving the clock input C_IN and the first signal S1, respectively. Furthermore, the first NAND gate G41b may include a fourth PFET P44b and a fifth PFET P45b for receiving the clock input C_IN and the first signal S1, respectively.

[0045] and Figure 4A Compared to the 2-1OAI gate 42a, the third NFET N43b and the fourth NFET N44b are differently arranged at Figure 4B 2-1OAI gate 42b. For example, Figure 4BAs shown, the second NFET N42b, the fourth NFET N44b, and the third NFET N43b may be sequentially connected in series with each other between the first node N1 and the ground node, and the drain of the first NFET N41b may be connected to the source of the second NFET N42b and the drain of the fourth NFET N44b, and the source of the first NFET N41b may be connected to the ground node. Figure 4A As described, the fourth NFET N44b is a feedback transistor controlled by the internal signal INT, and the feedback transistor is configured to prevent the first node N1 from discharging in response to the internal signal INT, thereby avoiding reference Figure 3 Describes the race condition.

[0046] Reference Figure 4C The clock gating unit 40c may include a first NAND gate G41c, a 2-1OAI gate 42c, an inverter G44c, and a NOR gate G45c. The 2-1OAI gate 42c may include a first NFET N41c, a second NFET N42c, a third NFET N43c, and a fourth NFET N44c for receiving an inverted enable input / E_IN, a second signal S2, a clock input C_IN, and an internal signal INT, respectively. Furthermore, the first NAND gate G41c may include a fifth NFET N45c and a sixth NFET N46c for receiving the clock input C_IN and the first signal S1, respectively. Furthermore, the first NAND gate G41c may include a fourth PFET P44c and a fifth PFET P45c for receiving the clock input C_IN and the first signal S1, respectively.

[0047] and Figure 4A Compared to the 2-1OAI gate 42a, the first NFET N41c, the second NFET N42c, the third NFET N43c and the fourth NFET N44c are differently arranged at Figure 4C 2-1OAI gate 42c. For example, Figure 4CAs shown, the third NFET N43c, the fourth NFET N44c, and the second NFET N42c can be sequentially connected in series between the first node N1 and the ground node, and the drain of the first NFET N41c can be connected to the first node N1 (i.e., the drain of the third NFET N43c), and the source of the first NFET N41c can be connected to the source of the fourth NFET N44c and the drain of the second NFET N42c. As described above with reference to FIG4A, the fourth NFET N44c is a feedback transistor controlled by the internal signal INT. The feedback transistor is configured to avoid a race condition by preventing the discharge of the first node N1.

[0048] Reference Figure 4D The clock gating unit 40d may include a first NAND gate G41d, a 2-1OAI gate 42d, an inverter G44d, and a NOR gate G45d. The 2-1OAI gate 42d may include a first NFET N41d, a second NFET N42d, a third NFET N43d, and a fourth NFET N44d for receiving the inverted enable input / E_IN, the second signal S2, the clock input C_IN, and the internal signal INT, respectively. Furthermore, the first NAND gate G41d may include a fifth NFET N45d and a sixth NFET N46d for receiving the clock input C_IN and the first signal S1, respectively. Furthermore, the first NAND gate G41d may include a fourth PFET P44d and a fifth PFET P45d for receiving the clock input C_IN and the first signal S1, respectively.

[0049] and Figure 4C Compared to the 2-1OAI gate 42c, the third NFET N43d and the fourth NFET N44d may be arranged differently. Figure 4D 2-1OAI gate 42d. For example, Figure 4D As shown, the fourth NFET N44d, the third NFET N43d, and the second NFET N42d may be sequentially connected in series with each other between the first node N1 and the ground node, and the drain of the first NFET N41d may be connected to the first node N1 (i.e., the drain of the fourth NFET N44d), and the source of the first NFET N41d may be connected to the source of the third NFET N43d and the drain of the second NFET N42d. As described above with reference to Figure 4A As depicted, the fourth NFET N44d is a feedback transistor controlled by the internal signal INT. The feedback transistor is configured to avoid a race condition by preventing discharge of the first node N1.

[0050] Figure 5A and Figure 5B is a circuit diagram illustrating an example of a clock gating unit according to an example embodiment. In detail, Figure 5A and Figure 5B The circuit diagrams show Figure 2 As described above, in the clock gating unit 20 Figures 4A to 4D In the clock gating units 40a to 40d, the second NFET, the third NFET and the fourth NFET (eg, Figure 4A The second NFET N42a, the third NFET N43a, and the fourth NFET N44a) may be connected in series with each other between the first node N1 and the ground node, and Figure 5A and Figure 5B In the clock gating units 50a and 50b, the second NFET (eg, Figure 5A The second NFET N52a) may not be connected to the third NFET and the fourth NFET (eg, Figure 5A The third NFET N53a and the fourth NFET N54a) are connected in series between the first node N1 and the ground node. Figure 5A and Figure 5B In the description of the above, repeated descriptions and the above references will be omitted. Figures 4A to 4D The description given is the same as the description given.

[0051] Reference Figure 5A The clock gating unit 50a may include a first NAND gate G51a, a 2-1OAI gate 52a, an inverter G54a, and a NOR gate G55a. The 2-1OAI gate 52a may include a first NFET N51a, a second NFET N52a, a third NFET N53a, and a fourth NFET N54a for receiving an inverted enable input / E_IN, a second signal S2, a clock input C_IN, and an internal signal INT, respectively. Furthermore, the first NAND gate G51a may include a fifth NFET N55a and a sixth NFET N56a for receiving a clock input C_IN and a first signal S1, respectively. Furthermore, the first NAND gate G51a may include a fourth PFET P54a and a fifth PFET P55a for receiving a clock input C_IN and a first signal S1, respectively.

[0052] like Figure 5AAs shown, the second NFET N52a and the first NFET N51a can be connected in series with each other between the first node N1 and the ground node. For example, the drain of the first NFET N51a can be connected to the source of the second NFET N52a, and the source of the first NFET N51a can be connected to the ground node, the drain of the second NFET N52a can be connected to the first node N1, and the source of the second NFET N52a can be connected to the drain of the first NFET N51a. In addition, the third NFET N53a and the fourth NFET N54a can be sequentially connected in series with each other between the first node N1 and the ground node. The fourth NFET N54a is a feedback transistor controlled by the internal signal INT. The feedback transistor is configured to avoid a race condition by preventing the discharge of the first node N1.

[0053] Reference Figure 5B The clock gating unit 50b may include a first NAND gate G51b, a 2-1OAI gate 52b, an inverter G54b, and a NOR gate G55b. The 2-1OAI gate 52b may include a first NFET N51b, a second NFET N52b, a third NFET N53b, and a fourth NFET N54b for receiving the inverted enable input / E_IN, the second signal S2, the clock input C_IN, and the internal signal INT, respectively. Furthermore, the first NAND gate G51b may include a fifth NFET N55b and a sixth NFET N56b for receiving the clock input C_IN and the first signal S1, respectively. Furthermore, the first PFET P51b, the second PFET P52b, and the third PFET P53b may also be configured to receive the inverted enable input / E_IN, the second signal S2, and the clock input C_IN, respectively. Furthermore, the first NAND gate G51b may include a fifth NFET N55b and a sixth NFET N56b for receiving the clock input C_IN and the first signal S1, respectively. Furthermore, the first PFET P54b and the fifth PFET P55b may be configured to receive the clock input C_IN and the first signal S1, respectively.

[0054] and Figure 5A Compared to the 2-1OAI gate 52a, the third NFET N53b and the fourth NFET N54b may be arranged differently in Figure 5B 2-1OAI gate 52b. For example, Figure 5B As shown, the fourth NFET N54b and the third NFET N53b can be sequentially connected in series between the first node N1 and the ground node, and the drain of the second NFET N52b can be connected to the first node N1 (i.e., the drain of the fourth NFET N54b). The fourth NFET N54b is a feedback transistor controlled by the internal signal INT. The feedback transistor is configured to avoid a race condition by preventing the discharge of the first node N1.

[0055] Figure 6is a block diagram illustrating an example of a clock gating unit according to an example embodiment, Figure 7 is a timing diagram illustrating an example of the operation of a clock gating unit according to an example embodiment. In detail, Figure 6 The block diagram shows the Figure 1 The clock gating unit 60 of the example of the clock gating unit 10 generates a clock output C_OUT of logic “1” in the disabled state, and Figure 7 The timing diagram shows the Figure 6 For ease of explanation, the signal that changes with time in the clock gating unit 60 is Figure 7 The propagation delay can be ignored in the timing diagram and the above reference Figure 1 The description given is the same as the description given.

[0056] Reference Figure 6 , the clock gating unit 60 may include Figure 1 The clock gating unit 10 of FIG. 1 may include a first NOR gate G61, a 2-1 AOI gate 62, and an inverter G64, and may further include an OR gate G65. The OR gate G65 may receive the clock enable E and the test enable SE, generate an enable input E_IN, and provide the enable input E_IN to the 2-1 AOI gate 62. In some embodiments, Figure 6 Different, OR gate G65 can be omitted, so the clock gating unit 60 can directly receive the enable input E_IN from the outside. In addition, in some embodiments, as shown below with reference to Figure 8E and Figure 9C As depicted, the OR gate G65 may be coupled to the 2-1 AOI gate 62 by sharing at least one transistor with the 2-1 AOI gate 62 .

[0057] The first NOR gate G61 can form an SR latch (or SRNOR latch) together with the second NOR gate G62 provided by the 2-1 AOI gate 62. Figure 6 As shown, the first NOR gate G61 and the second NOR gate G62 can be cross-coupled via the first node N1 and the second node N2. When the first signal S1 is a logic "0", the first NOR gate G61 can generate the second signal S2 based on the clock input C_IN. When the first signal S1 is a logic "1", the first NOR gate G61 can generate the second signal S2 regardless of the clock input C_IN. The 2-1 AOI gate 62 can generate the first signal S1 by performing a logical operation on the enable input E_IN, the clock input C_IN, and the second signal S2 based on the second NOR gate G62 and the AND gate G63.

[0058] Reference Figure 7, the clock input C_IN can oscillate with a period T_CLK. Before time point t71, the clock enable E and / or the test enable SE can be logic "1". Therefore, the enable input E_IN can be logic "1", and the clock gating unit 60 can be in an enabled state. Due to the second NOR gate G62, the first signal S1 can be logic "0", and the second signal S2 can be the same as the inverted version of the clock input C_IN. Therefore, the clock output C_OUT can be the same as the clock input C_IN (for example, a delayed version of the clock input C_IN).

[0059] At time point t71, the clock enable E and the test enable SE may be changed to logic "0". Therefore, the enable input E_IN may be changed to logic "0", and the clock gating unit 60 may enter the disabled state. Since the clock input C_IN is logic "0", the first signal S1 may remain at logic "0", and the second signal S2 and the clock output C_OUT may also remain at logic "1" and logic "0", respectively. Next, at time point t72, a rising edge of the clock input C_IN may occur, and therefore, through the first NOR gate G61, the second signal S2 and the clock output C_OUT may be changed to logic "0" and logic "1", respectively. In addition, through the second NOR gate G62, the first signal S1 may be changed to logic "1", and therefore, due to the first NOR gate G61, the second signal S2 may remain at logic "0" regardless of the clock input C_IN. As a result, when the clock gating unit 60 is in the disabled state, the clock output C_OUT may remain at logic "1".

[0060] At time point t73, the clock enable E and / or the test enable SE may be changed to logic "1". Therefore, the enable input E_IN may be changed to logic "1", and the clock gating unit 60 may enter the enabled state. Since the clock input C_IN and the second signal S2 are logic "0", the first signal S1 may remain at logic "1", and therefore, the second signal S2 and the clock output C_OUT may remain at logic "0" and logic "1", respectively. Next, at time point t74, a rising edge of the clock input C_IN may occur, and therefore, through the second NOR gate G62, the first signal S1 may be changed to logic "0". However, since the clock input C_IN is logic "1", the second signal S2 and the clock output C_OUT may remain at logic "0" and logic "1", respectively. Next, at time point t75, a falling edge of the clock input C_IN may occur, and since the first signal S1 is logic "0", the second signal S2 and the clock output C_OUT may be changed to logic "1" and logic "0", respectively.

[0061] At time t76, the clock enable E and the test enable SE may transition to logic "0." Consequently, the enable input E_IN may transition to logic "0," and the clock gating unit 60 may enter a disabled state. Since the first signal S1 transitions to logic "1" through the AND gate G63 and the second NOR gate G62, and the clock input C_IN is logic "1," the second signal S2 and the clock output C_OUT may maintain logic "0" and logic "1," respectively.

[0062] At time point t77, the clock enable E and / or the test enable SE may transition to logic "1." Thus, the enable input E_IN may transition to logic "1," and the clock gating unit 60 may enter an enabled state. Although the first signal S1 may transition to logic "0" via the AND gate G63 and the second NOR gate G62, the clock input C_IN is logic "1," and thus, the second signal S2 and the clock input C_IN may maintain logic "0" and logic "1," respectively. Next, at time point t78, a falling edge of the clock input C_IN may occur, and the second signal S2 and the clock output C_OUT may transition to logic "1" and logic "0," respectively.

[0063] As described above, when the clock gating unit 60 enters the disabled state, the clock output C_OUT may remain at logic "1" after a rising edge synchronized with the clock input C_IN. When the clock gating unit 60 enters the enabled state, the clock output C_OUT may oscillate after a falling edge synchronized with the clock input C_IN. Therefore, the clock gating unit 60 can provide the clock output C_OUT to a digital circuit (e.g., a negative-edge-triggered flip-flop) that operates in response to a falling edge of the clock output C_OUT, and prevent malfunctions in the digital circuit due to clock gating.

[0064] Return to reference Figure 6 , the 2-1AOI gate 62 may include a feedback transistor FT6, only the feedback transistor FT6 receives the internal signal INT of the first NOR gate G61 to avoid a race condition. For example, when the falling edge of the clock input unit C_IN occurs in the enabled state of the clock gating unit 60, based on factors including the slew rate of the falling edge and the gate delay difference between the first NOR gate G61 and the AND gate G63, the falling edge of the signal output by the AND gate G63 may occur earlier than the rising edge of the second signal S2, or may appear near the rising edge of the second signal S2. Therefore, the voltage level of the first signal S1 that needs to be maintained at logic "0" may be unstable, resulting in possible errors in the clock output C_OUT. The feedback transistor FT6 can avoid this race condition by preventing the first node N1 from being pulled up (or charged). The following will refer to Figures 8A to 8E and Figures 9A to 9C An example of a clock gating cell 60 including a feedback transistor FT62 is described.

[0065] Figures 8A to 8E is a circuit diagram illustrating an example of a clock gating unit according to an example embodiment. In detail, Figures 8A to 8E The circuit diagram shows the Figure 6 Hereinafter, when describing the clock gating unit 60, Figures 8A to 8E When the above reference is omitted Figure 6 and Figure 7 The description given is a duplicate of the description.

[0066] Reference Figure 8A , the clock gating unit 80a may include a first NOR gate G81a, a 2-1AOI gate 82a, an inverter G84a, and an OR gate G85a. The 2-1AOI gate 82a may include a first PFET P81a, a second PFET P82a, and a third PFET P83a for receiving the enable input E_IN, the second signal S2, and the clock input C_IN, respectively, and may further include a fourth PFET P84a for receiving the internal signal INT as a feedback transistor. Figure 8A As shown, the fourth PFET P84a can be connected in series with the third PFET P83a between the first node N1 where the first signal S1 is generated and the positive power supply node, and only the fourth PFET P84a receives the internal signal INT of the first NOR gate G81a. In addition, the second PFET P82a can be connected in series with the third PFET P83a and the fourth PFET P84a between the first node N1 and the positive power supply node. Figure 8A In the clock gating unit 80a, the second PFET P82a, the third PFET P83a, and the fourth PFET P84a may be sequentially connected in series with each other between the first node N1 and the positive power supply node, and the drain of the first PFET P81a may be connected to the source of the second PFET P82a and the drain of the third PFET P83a, and the source of the first PFET P81a may be connected to the positive power supply node. Figure 8A As shown, the 2-1 AOI gate 82a may further include a first NFET N81a, a second NFET N82a, and a third NFET N83a for receiving the enable input E_IN, the second signal S2, and the clock input C_IN, respectively.

[0067] The first NOR gate G81a may include a fifth PFET P85a and a sixth PFET P86a for receiving the clock input C_IN and the first signal S1, respectively, and the fifth PFET P85a and the sixth PFET P86a may be connected in series with each other between the second node N2 at which the second signal S2 is generated and the positive power supply node. An internal signal INT may be generated at a node where the source of the fifth PFET P85a and the drain of the sixth PFET P86a are connected. Therefore, although the first signal S1 may be logic "0", the internal signal INT may be logic "0" due to the turned-off sixth PFET P86a, and therefore, the fourth PFET P84a is turned off. Therefore, charging (or pulling up) of the first node N1 may be prevented, and reference to the positive power supply node may be avoided. Figure 7 As described above, the internal signal INT can be provided only to the fourth PFET P84a. Figure 8A As shown, the first NOR gate G81a may further include a fourth NFET N84a and a fifth NFET N85a for receiving the clock input C_IN and the first signal S1, respectively.

[0068] Reference Figure 8B The clock gating unit 80b may include a first NOR gate G81b, a 2-1AOI gate 82b, an inverter G84b, and an OR gate G85b. The 2-1OAI gate 82b may include a first PFET P81b, a second PFET P82b, a third PFET P83b, and a fourth PFET P84b for receiving the enable input E_IN, the second signal S2, the clock input C_IN, and the internal signal INT, respectively. Furthermore, the first NFET N81b, the second NFET N82b, and the third NFET N83b may be respectively received. Furthermore, the first NOR gate G81b may include a fifth PFET P85b and a sixth PFET P86b for receiving the clock input C_IN and the first signal S1, respectively. Furthermore, the first NOR gate G81b may include a fourth NFET N84b and a fifth NFET N85b for receiving the clock input C_IN and the first signal S1, respectively.

[0069] and Figure 8A Compared to the 2-1 AOI gate 82a, the third PFET P83b and the fourth PFET P84b may be arranged differently in Figure 8B 2-1OAI gate 82b. For example, Figure 8BAs shown, the second PFET P82b, the fourth PFET P84b, and the third PFET P83b may be sequentially connected in series with each other between the first node N1 and the positive power supply node, the drain of the first PFET P81b may be connected to the source of the second PFET P82b and the drain of the fourth PFET P84b, and the source of the first PFET P81b may be connected to the positive power supply node. Figure 8A As described, the fourth PFET P84b is a feedback transistor and can prevent the charging of the first node N1 in response to the internal signal INT. Figure 7 Describes the race condition.

[0070] Reference Figure 8C The clock gating unit 80c may include a first NOR gate G81c, a 2-1 AOI gate 82c, an inverter G84c, and an OR gate G85c. The 2-1 AOI gate 82c may include a first PFET P81c, a second PFET P82c, a third PFET P83c, and a fourth PFET P84c for receiving the enable input E_IN, the second signal S2, the clock input C_IN, and the internal signal INT, respectively. Furthermore, the first NFET N81c, the second NFET N82c, and the third NFET N83c may be respectively received. Furthermore, the first NOR gate G81c may include a fifth PFET P85c and a sixth PFET P86c for receiving the clock input C_IN and the first signal S1, respectively. Furthermore, the first NOR gate G81c may include a fourth NFET N84c and a fifth NFET N85c for receiving the clock input C_IN and the first signal S1, respectively.

[0071] and Figure 8A Compared to the 2-1 AOI gate 82a, the first PFET P81c, the second PFET P82c, the third PFET P83c and the fourth PFET P84c may be arranged differently. Figure 8C 2-1 AOI gate 82c. For example, Figure 8C As shown, the third PFET P83c, the fourth PFET P84c and the second PFET P82c may be sequentially connected in series with each other between the first node N1 and the positive power supply node, the drain of the first PFET P81c may be connected to the first node N1 (i.e., the drain of the third PFET P83c), and the source of the first PFET P81c may be connected to the source of the fourth PFET P84c and the drain of the second PFET P82c. Figure 8AAs described, the fourth PFET P84c is a feedback transistor and can prevent the charging of the first node N1 in response to the internal signal INT. Figure 7 Describes the race condition.

[0072] Reference Figure 8D The clock gating unit 80d may include a first NOR gate G81d, a 2-1AOI gate 82d, an inverter G84d, and an OR gate G85d. The 2-1OAI gate 82d may include a first PFET P81d, a second PFET P82d, a third PFET P83d, and a fourth PFET P84d for receiving the enable input E_IN, the second signal S2, the clock input C_IN, and the internal signal INT, respectively. Furthermore, the first NFET N81d, the second NFET N82d, and the third NFET N83d may be respectively received. Furthermore, the first NOR gate G81d may include a fifth PFET P85d and a sixth PFET P86d for receiving the clock input C_IN and the first signal S1, respectively. Furthermore, the first NFET N84d and the fifth NFET N85d may be respectively received.

[0073] and Figure 8C Compared to the 2-1 AOI gate 82c, the third PFET P83d and the fourth PFET P84d may be arranged differently in Figure 8D 2-1AOI gate 82d. For example, Figure 8D As shown, the fourth PFET P84d, the third PFET P83d and the second PFET P82d may be sequentially connected in series with each other between the first node N1 and the positive power supply node, the drain of the first PFET P81d may be connected to the first node N1 (i.e., the drain of the fourth PFET P84d), and the source of the first PFET P81d may be connected to the source of the third PFET P83d and the drain of the second PFET P82d. As described above with reference to Figure 8A As described, the fourth PFET P84d is a feedback transistor and can prevent the charging of the first node N1 in response to the internal signal INT. Figure 7 Describes the race condition.

[0074] Reference Figure 8EThe clock gating unit 80e may include a first NOR gate G81e, a logic circuit 82e, and an inverter G84e. The logic circuit 82e may include a second PFET P82e, a third PFET P83e, a fourth PFET P84e, a second NFET N82e, and a third NFET N83e. The logic circuit 82e may also include a seventh PFET P87e, an eighth PFET P88e, a sixth NFET N86e, and a seventh NFET N87e. Furthermore, the first NOR gate G81e may include a fifth PFET P85e, a sixth PFET P86e, a fourth NFET N84e, and a fifth NFET N85e.

[0075] and Figure 8A Compared with the clock gating unit 80a, Figure 8A The 2-1 AOI gate 82a and the OR gate G85a can be combined by sharing at least one transistor Figure 8E To this end, as Figure 8E As shown, the logic circuit 82e may include a seventh PFET P87e and a sixth NFET N86e for receiving the clock enable E, and an eighth PFET P88e and a seventh NFET N87e for receiving the test enable SE. Figure 8E In the clock gating unit 80e of FIG. 1 , the clock enable E and the test enable SE may be referred to as the first enable input and the second enable input, respectively. It will be understood that in a similar manner to Figure 8E The clock gating unit 80e Figure 8B 、 Figure 8C and Figure 8D In the clock gating units 80b, 80c and 80d, since the first PFETs P81b, P81c and P81d are replaced by two PFETs connected in series with each other, and the first NFETs N81b, N81c and N81d are replaced by two NFETs connected in parallel with each other, a logic circuit for receiving a clock enable E and a test enable SE can be implemented.

[0076] Figures 9A to 9C is a circuit diagram illustrating an example of a clock gating unit according to an example embodiment. In detail, Figures 9A to 9C The circuit diagrams show Figure 6 An example of a clock gating unit 60. Figures 8A to 8E The clock gating units 80a to 80e, in Figures 9A to 9C In the clock gating units 90a, 90b and 90c, the second PFET (eg, Figure 9A The second PFET P92a) may not be connected to the third PFET and the fourth PFET (eg, Figure 9A The third PFET P93a and the fourth PFET P94a) are connected in series between the first node N1 and the positive power supply node. Figures 9A to 9C In the description of the above, repeated descriptions and the above references will be omitted. Figures 8A to 8E The description given is the same as the description given.

[0077] Reference Figure 9A The clock gating unit 90a may include a first NOR gate G91a, a 2-1 AOI gate 92a, an inverter G94a, and an OR gate G95a. The 2-1 AOI gate 92a may include a first PFET P91a, a second PFET P92a, a third PFET P93a, and a fourth PFET P94a for receiving the enable input E_IN, the second signal S2, the clock input C_IN, and the internal signal INT, respectively. Furthermore, the first NFET N91a, the second NFET N92a, and the third NFET N93a may be respectively received. Furthermore, the first NOR gate G91a may include a fifth PFET P95a and a sixth PFET P96a for receiving the clock input C_IN and the first signal S1, respectively. Furthermore, the first NOR gate G91a may include a fourth NFET N94a and a fifth NFET N95a for receiving the clock input C_IN and the first signal S1, respectively.

[0078] like Figure 9A As shown, the second PFET P92a and the first PFET P91a can be connected in series with each other between the first node N1 and the positive power supply node. For example, the drain of the first PFET P91a can be connected to the source of the second PFET P92a, and the source of the first PFET P91a is connected to the positive power supply node, the drain of the second PFET P92a can be connected to the first node N1, and the source of the second PFET P92a can be connected to the drain of the first PFET P91a. In addition, the third PFET P93a and the fourth PFET P94a can be sequentially connected in series with each other between the first node N1 and the positive power supply node. The fourth PFET P94a is a feedback transistor and can prevent the charging of the first node N1 in response to the internal signal INT. Therefore, the reference Figure 7 Describes the race condition.

[0079] Reference Figure 9BThe clock gating unit 90b may include a first NOR gate G91b, a 2-1 AOI gate 92b, an inverter G94b, and an OR gate G95b. The 2-1 AOI gate 92b may include a first PFET P91b, a second PFET P92b, a third PFET P93b, and a fourth PFET P94b for receiving the enable input E_IN, the second signal S2, the clock input C_IN, and the internal signal INT, respectively. Furthermore, the first NFET N91b, the second NFET N92b, and the third NFET N93b may be respectively received. Furthermore, the first NOR gate G91b may include a fifth PFET P95b and a sixth PFET P96b for receiving the clock input C_IN and the first signal S1, respectively. Furthermore, the first NOR gate G91b may include a fourth NFET N94b and a fifth NFET N95b for receiving the clock input C_IN and the first signal S1, respectively.

[0080] and Figure 9A Compared to the 2-1 AOI gate 92a, the third PFET P93b and the fourth PFET P94b may be arranged differently in Figure 9B 2-1AOI gate 92b. For example, Figure 9B As shown, the fourth PFET P94b and the third PFET P93b may be sequentially connected in series with each other between the first node N1 and the positive power supply node, and the drain of the second PFET P92b may be connected to the first node N1 (i.e., the drain of the fourth PFET P94b). The fourth PFET P94b is a feedback transistor and may prevent the first node N1 from being charged in response to the internal signal INT. Thus, the reference Figure 7 Describes the race condition.

[0081] Reference Figure 9C The clock gating unit 90c may include a first NOR gate G91c, a logic circuit 92c, and an inverter G94c. The logic circuit 92c may include a second PFET P92c, a third PFET P93c, a fourth PFET P94c, a second NFET N92c, and a third NFET N93c. It may also include a seventh PFET P97c, an eighth PFET P98c, a sixth NFET N96c, and a seventh NFET N97c. Furthermore, the first NOR gate G91c may include a fifth PFET P95c, a sixth PFET P96c, a fourth NFET N94c, and a fifth NFET N95c.

[0082] and Figure 9A Compared with the clock gating unit 90a, Figure 9AThe 2-1 AOI gate 92a and the OR gate G95a can be combined by sharing at least one transistor Figure 9C To this end, as Figure 9C As shown, the logic circuit 92c may include a seventh PFET P97c and a sixth NFET N96c for receiving a clock enable E, and an eighth PFET P98c and a seventh NFET N97c for receiving a test enable SE. Figure 9C In the clock gating unit 90c of FIG. 1 , the clock enable E and the test enable SE may be referred to as the first enable input and the second enable input, respectively. It will be understood that in a similar Figure 9C The clock gating unit 90c Figure 9B In the clock gating unit 90b, since the first PFET P91b is replaced by two PFETs connected in series, and the first NFET N91b is replaced by two NFETs connected in parallel, a logic circuit for receiving a clock enable E and a test enable SE can be implemented.

[0083] Figure 10 1 is a block diagram illustrating an example of an integrated circuit including a clock gating unit according to an example embodiment. In some embodiments, the clock gating unit described above with reference to the accompanying drawings may be included in an integrated circuit for processing a digital signal. Figure 10 As shown, the integrated circuit 100 may include a first clock gating cell CGC1 , a second clock gating cell CGC2 , a power controller PC, a first combinatorial logic block CL1 , a second combinatorial logic block CL2 , and a plurality of flip-flops PF1 , PF2 , NF1 , and NF2 .

[0084] The power controller PC can control the power of the integrated circuit 100 and can generate a first clock enable E1 and a second clock enable E2. For example, the power controller PC can reduce power consumption by generating an inactive first clock enable E1 using a digital circuit including at least one first positive-edge-triggered flip-flop PF1, a first combinational logic block CL1, and at least one second positive-edge-triggered flip-flop PF2. Furthermore, the power controller PC can reduce power consumption by generating an inactive second clock enable E2 using a digital circuit including at least one first negative-edge-triggered flip-flop NF1, a second combinational logic block CL2, and at least one second negative-edge-triggered flip-flop NF2.

[0085] The first clock gating unit CGC1 can receive the clock input C_IN and can stop or resume the provision of the first clock output C_OUT1 based on the first clock enable E1. Figure 2As described, the first clock gating unit CGC1 can generate a first clock output C_OUT1 maintained at logic "0" in a disabled state. Therefore, the first clock output C_OUT1 can be provided to a positive edge triggered flip-flop, for example, at least one first positive edge triggered flip-flop PF1 and at least one second positive edge triggered flip-flop PF2. In addition, the second clock gating unit CGC2 can receive a clock input C_IN and can stop or resume providing the second clock output C_OUT2 based on the second clock enable E2. For example, as described above with reference to Figure 6 As described, the second clock gating unit CGC2 can generate a second clock output C_OUT2 maintained at logic "1" in the disabled state. Therefore, the second clock output C_OUT2 can be provided to negative-edge-triggered flip-flops, for example, at least one first negative-edge-triggered flip-flop NF1 and at least one second negative-edge-triggered flip-flop NF2.

[0086] Figure 11 is a flow chart of a method for manufacturing an integrated circuit according to an example embodiment. In detail, Figure 11 The flowchart shows a method for manufacturing an integrated circuit IC (eg, Figure 10 Method of integrated circuit 100).

[0087] In some embodiments, the clock gating unit may be defined as a standard cell. A standard cell is a unit of layout included in an integrated circuit IC and may be simply referred to as a cell. The integrated circuit IC may include a plurality of different standard cells, each of which may provide a unique function. The standard cell may have a structure that conforms to preset rules based on the semiconductor process used to manufacture the integrated circuit IC. For example, the standard cell may have a constant length or several times a constant length in a plane perpendicular to the direction of the stacked layers.

[0088] The standard cell library (or cell library) D2 may include information about standard cells, such as functional information, characteristic information, layout information, etc., and may include information about clock gating cells. As described above with reference to the accompanying drawings, the clock gating cells defined by the standard cell library D2 can provide not only high operational reliability but also high efficiency, such as reduced area and low power consumption.

[0089] In operation S10, a logic synthesis operation may be performed to generate a netlist D3 from the RTL data D1. For example, a semiconductor design tool (e.g., a logic synthesis tool) may refer to a standard cell library D2 and perform logic synthesis based on the RTL data D1 composed of VHSIC Hardware Description Language (VHDL) and Verilog, thereby generating a bitstream or netlist D3. The standard cell library D2 may include information about the expected performance of the clock gating cell, and the standard cell may be included in the integrated circuit IC with reference to such information during the logic synthesis process.

[0090] In operation S20, a place and route (P&R) operation for generating layout data D4 from the netlist D3 may be performed. Figure 11 As shown, the P&R operation S20 may include a plurality of sub-operations S21, S22, and S23. In sub-operation S21, an operation for placing a standard cell may be performed. For example, a semiconductor design tool (e.g., a P&R tool) may place a plurality of standard cells according to a netlist D3 with reference to a standard cell library D2. For example, a semiconductor design tool may place a layout of a clock gating cell defined by a netlist D3 with reference to a standard cell library D2. In sub-operation S22, an operation for generating an interconnection may be performed. The interconnection may electrically connect the output pins and input pins of the standard cell and may include, for example, at least one path and at least one conductive pattern. In sub-operation S23, an operation for generating layout data D4 may be performed. The layout data D4 may have, for example, a GDSII format and may include geometric information about the standard cell and the interconnection.

[0091] In operation S30, optical proximity correction (OPC) may be performed. OPC may refer to an operation for forming a pattern of a desired shape by correcting distortion, such as refraction, caused by light characteristics in photolithography included in a semiconductor process for manufacturing the integrated circuit IC, and the pattern on the mask may be determined by applying OPC to the layout data D4. In some embodiments, the layout of the integrated circuit IC may be modified to a limited extent in operation S30, and the limited modification of the integrated circuit IC in operation S30 is post-processing for optimizing the structure of the integrated circuit IC and may be referred to as design polishing.

[0092] In operation S40, an operation for manufacturing a mask may be performed. For example, when OPC is applied to the layout data D4, a pattern on the mask may be defined to form patterns to be formed on a plurality of layers, and at least one mask (or photomask) for forming each pattern of the plurality of layers may be manufactured.

[0093] In operation S50, operations for manufacturing the integrated circuit IC may be performed. For example, the integrated circuit IC may be manufactured by patterning a plurality of layers using at least one mask manufactured in operation S40. Figure 11 As shown, operation S50 may include sub-operations S51 and S52. In sub-operation S51, a front-end-of-the-line (FEOL) process may be performed. FEOL processes may refer to processes for forming various components (e.g., transistors, capacitors, and resistors) on a substrate during the manufacturing process of an integrated circuit (IC). For example, FEOL processes may include processes for planarizing and cleaning the wafer, processes for forming trenches, processes for forming wells, processes for forming gate lines, processes for forming sources and drains, and the like. In sub-operation S52, a back-end-of-the-line (BEOL) process may be performed. BEOL processes may refer to processes for interconnecting various components (e.g., transistors, capacitors, and resistors) during the manufacturing process of an integrated circuit (IC). For example, BEOL processes may include processes for silicided gates, source and drain regions, processes for adding dielectrics, processes for planarization, processes for forming holes, processes for adding metal layers, processes for forming vias, and processes for forming a passivation layer. Next, the integrated circuit (IC) may be packaged in a semiconductor package and used as part of various applications. As described above, due to the desirable characteristics of the clock gating unit, the integrated circuit IC may exhibit high performance and high efficiency, and thus the performance and efficiency of an application including the integrated circuit IC may be improved.

[0094] While example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit comprising: Clock gating unit, Wherein, the clock gating unit includes: a first 2-input logic gate configured to receive a clock input and a first signal and output a second signal; an inverter configured to receive the second signal and generate a clock output; and a 3-input logic gate including a second 2-input logic gate, the 3-input logic gate being configured to generate the first signal, wherein the first 2-input logic gate and the second 2-input logic gate are cross-coupled to form a set-reset latch, wherein the 3-input logic gate includes a feedback transistor configured to exclusively receive an internal signal of the first 2-input logic gate, wherein the internal signal is generated inside the first 2-input logic gate and is different from the clock input, the first signal, and the second signal, and Wherein activation of the feedback transistor by the internal signal is configured to avoid a race condition by preventing a pull-up or pull-down of a first node at which the first signal is generated.

2. The integrated circuit according to claim 1 , further comprising: at least one positive edge-triggered flip-flop configured to receive the clock output from the clock gating unit, wherein the first 2-input logic gate is a first NAND gate, and the second 2-input logic gate is a second NAND gate, The 3-input logic gate is a 2-1 OR-NAND gate, and The feedback transistor is an n-channel field effect transistor configured to prevent the pull-down of the first node.

3. The integrated circuit of claim 1 , further comprising: at least one negative-edge-triggered flip-flop configured to receive the clock output from the clock gating unit, wherein the first 2-input logic gate is a first NOR gate, and the second 2-input logic gate is a second NOR gate, The 3-input logic gate is a 2-1 AND-NOR gate, and The feedback transistor is a p-channel field effect transistor configured to prevent the pull-up of the first node.

4. A clock gating unit, comprising: a first NAND gate configured to receive a clock input and a first signal and generate a second signal; an inverter configured to receive the second signal and generate a clock output; as well as a 2-1 NAND gate, wherein the 2-1 NAND gate includes a second NAND gate, and the 2-1 NAND gate is configured to generate the first signal. wherein the first NAND gate and the second NAND gate are cross-coupled to form a set-reset latch, and Wherein, the 2-1 or NAND gate includes: a first n-channel field effect transistor configured to receive an inverting enable input; a second n-channel field effect transistor configured to receive the second signal; a third n-channel field effect transistor configured to receive the clock input; and a fourth n-channel field effect transistor, the fourth n-channel field effect transistor being connected in series with the third n-channel field effect transistor between a first node at which the first signal is generated and a ground node, the fourth n-channel field effect transistor being configured to exclusively receive an internal signal of the first NAND gate to avoid a race condition.

5. The clock gating unit according to claim 4, wherein: The second n-channel field effect transistor is connected in series with the third n-channel field effect transistor and the fourth n-channel field effect transistor between the first node and the ground node.

6. The clock gating unit according to claim 5, wherein: The second n-channel field effect transistor, the third n-channel field effect transistor, and the fourth n-channel field effect transistor are sequentially connected in series with each other between the first node and the ground node, The drain terminal of the first n-channel field effect transistor is connected to both the source terminal of the second n-channel field effect transistor and the drain terminal of the third n-channel field effect transistor, and A source terminal of the first n-channel field effect transistor is connected to the ground node.

7. The clock gating unit according to claim 5, wherein: The second n-channel field effect transistor, the fourth n-channel field effect transistor, and the third n-channel field effect transistor are sequentially connected in series with each other between the first node and the ground node, The drain terminal of the first n-channel field effect transistor is connected to both the source terminal of the second n-channel field effect transistor and the drain terminal of the fourth n-channel field effect transistor, and A source terminal of the first n-channel field effect transistor is connected to the ground node.

8. The clock gating unit according to claim 5, wherein: The third n-channel field effect transistor, the fourth n-channel field effect transistor, and the second n-channel field effect transistor are sequentially connected in series with each other between the first node and the ground node, A drain terminal of the first n-channel field effect transistor is connected to a drain terminal of the third n-channel field effect transistor, and A source terminal of the first n-channel field effect transistor is connected to both a source terminal of the fourth n-channel field effect transistor and a drain terminal of the second n-channel field effect transistor.

9. The clock gating unit according to claim 5, wherein: The fourth n-channel field effect transistor, the third n-channel field effect transistor, and the second n-channel field effect transistor are sequentially connected in series with each other between the first node and the ground node, A drain terminal of the first n-channel field effect transistor is connected to a drain terminal of the fourth n-channel field effect transistor, and A source terminal of the first n-channel field effect transistor is connected to both a source terminal of the third n-channel field effect transistor and a drain terminal of the second n-channel field effect transistor.

10. The clock gating unit according to claim 4, wherein: The drain terminal of the first n-channel field effect transistor is connected to the source terminal of the second n-channel field effect transistor, The source terminal of the first n-channel field effect transistor is connected to the ground node, and A drain terminal of the second n-channel field effect transistor is connected to the first node.

11. The clock gating unit according to claim 10, wherein: The third n-channel field effect transistor and the fourth n-channel field effect transistor are sequentially connected in series with each other between the first node and the ground node.

12. The clock gating unit according to claim 10, wherein: The fourth n-channel field effect transistor and the third n-channel field effect transistor are sequentially connected in series with each other between the first node and the ground node.

13. The clock gating unit according to claim 4, wherein: The 2-1 OR NAND gate further includes: a first p-channel field effect transistor configured to receive the inverted enable input; a second p-channel field effect transistor configured to receive the second signal; and A third p-channel field effect transistor is configured to receive the clock input.

14. The clock gating unit according to claim 4, wherein: The first NAND gate includes a fifth n-channel field effect transistor and a sixth n-channel field effect transistor, wherein the fifth n-channel field effect transistor and the sixth n-channel field effect transistor are connected in series between a second node where the second signal exists and the ground node. The fifth n-channel field effect transistor is configured to receive the clock input, The sixth n-channel field effect transistor is configured to receive the first signal, and The internal signal is present at a third node interconnecting the fifth n-channel field effect transistor and the sixth n-channel field effect transistor.

15. The clock gating unit according to claim 14, wherein: The drain terminal of the fifth n-channel field effect transistor is connected to the second node, and A source terminal of the sixth n-channel field effect transistor is connected to the ground node.

16. The clock gating unit according to claim 14, wherein: The first NAND gate further includes: a fourth p-channel field effect transistor configured to receive the clock input; and A fifth p-channel field effect transistor is configured to receive the first signal.

17. A clock gating unit, comprising: a first NOR gate configured to receive a clock input and a first signal and generate a second signal; an inverter configured to receive the second signal and generate a clock output; as well as a 2-1 AND-NOR gate, the 2-1 AND-NOR gate including a second NOR gate, the 2-1 AND-NOR gate being configured to generate the first signal, wherein the first NOR gate and the second NOR gate are cross-coupled to form a set-reset latch, and Wherein, the 2-1 AND-NOR gate includes: a first p-channel field effect transistor configured to receive an enable input; a second p-channel field effect transistor configured to receive the second signal; a third p-channel field effect transistor configured to receive the clock input; and a fourth p-channel field effect transistor connected in series with the third p-channel field effect transistor between a first node at which the first signal is generated and a positive power supply node, wherein the fourth p-channel field effect transistor is configured to exclusively receive an internal signal of the first NOR gate, and activation of the fourth p-channel field effect transistor is configured to avoid a race condition.

18. The clock gating unit according to claim 17, wherein: The second p-channel field effect transistor is connected in series with the third p-channel field effect transistor and the fourth p-channel field effect transistor between the first node and the positive power supply node.

19. The clock gating unit according to claim 17, wherein: The drain terminal of the first p-channel field effect transistor is connected to the source terminal of the second p-channel field effect transistor, The source terminal of the first p-channel field effect transistor is connected to the positive power supply node, and A drain terminal of the second p-channel field effect transistor is connected to the first node.

20. The clock gating unit according to claim 17, wherein: The first NOR gate includes a fifth p-channel field effect transistor and a sixth p-channel field effect transistor, the fifth p-channel field effect transistor and the sixth p-channel field effect transistor are connected in series with each other between a second node where the second signal is present and the positive power supply node, The fifth p-channel field effect transistor is configured to receive the clock input, The sixth p-channel field effect transistor is configured to receive the first signal, and The internal signal exists at a node interconnecting the fifth p-channel field effect transistor and the sixth p-channel field effect transistor.

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