Adjustable memory operation settings based on memory subsystem operation requirements

Abstract

The present disclosure relates to adjustable memory operation settings based on memory subsystem operation requirements. A priority of each operation requirement of a set of operation requirements of a memory subsystem may be determined. A programming operation setting for a programming operation to be performed at the memory subsystem may be determined based on the priority of each operation requirement. A request to perform the programming operation at the memory subsystem may be received. In response to receiving the request to perform the programming operation, the programming operation may be performed at the memory subsystem based on the programming operation setting.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly to adjustable memory operating settings based on memory subsystem operating requirements. Background Art

[0002] The memory subsystem may be a storage device, a memory module, and a mixture of a storage device and a memory module. The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, a host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the invention

[0003] In one aspect, the present disclosure relates to a method, comprising: determining a priority of each operation requirement of a set of operation requirements of a memory subsystem; determining a programming operation setting for a programming operation to be performed at the memory subsystem based on the priority of each operation requirement; receiving a request to perform the programming operation at the memory subsystem; and in response to receiving the request to perform the programming operation, performing, by a processing device, the programming operation at the memory subsystem based on the programming operation setting.

[0004] In another aspect, the present disclosure relates to a system comprising: a memory component; and a processing device operatively coupled to the memory component to: determine a priority of each operation requirement of a set of operation requirements of the memory component; determine a background management operation setting for a background management operation to be performed at the memory component based on each priority of each operation requirement; and schedule the background management operation to be performed at the memory component based on the background management operation setting.

[0005] In yet another aspect, the present disclosure relates to a non-transitory computer-readable medium comprising instructions which, when executed by a processing device, cause the processing device to: determine a priority of each operation requirement of a set of operation requirements for a memory subsystem, the set of operation requirements comprising an operating temperature of the memory subsystem, a time period during which data will be retained at the memory subsystem, program performance of the memory subsystem, or persistence of the memory subsystem; determine a programming operation setting for a programming operation to be performed at the memory subsystem based on the priority of each operation requirement, the programming operation setting comprising an initial write mode of host data stored at the memory subsystem, a subsequent write mode of the host data stored at the memory subsystem, a read voltage, or a rate at which host data will be written to the memory subsystem; receive a request to perform the programming operation at the memory subsystem; and in response to receiving the request to perform the programming operation, perform the programming operation at the memory subsystem based on the programming operation setting. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the accompanying drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is shown.

[0008] Figure 2 is a flow chart of an example method for adjusting programming operation settings based on memory subsystem operation requirements according to some embodiments of the present disclosure.

[0009] Figure 3 is a flow chart of an example method for adjusting background management operation settings based on memory subsystem operation requirements according to some embodiments of the present disclosure.

[0010] Figure 4 Adjusting memory operation settings based on memory subsystem operation requirements is shown according to some embodiments of the present disclosure.

[0011] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0012] Aspects of the present disclosure are directed to adjustable memory operation settings based on memory subsystem operation requirements. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory components (also referred to below as a "memory device"). The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0013] A conventional memory subsystem may perform various operations relative to one or more memory components included in the memory subsystem. For example, programming operations such as read operations, programming (i.e., write) operations, and erase operations may be performed at one or more memory components to program host data at the memory subsystem. In another example, background management operations such as garbage collection operations, data refresh operations, and wear leveling operations may be performed at one or more memory components to manage data stored at the memory subsystem. Memory operations such as the previously described programming operations and background management operations may be associated with one or more operation settings that affect the performance of the memory operations. For example, a read operation that retrieves data from the memory subsystem may be associated with a read voltage setting that indicates a voltage to be applied to a block of data of the memory subsystem during the process of retrieving the data. In another example, a garbage collection operation may be associated with a garbage collection frequency setting that indicates the frequency with which a garbage collection operation will be performed at the memory subsystem.

[0014] Conventional memory subsystems may be used by a host system with a wide variety of applications. Therefore, conventional memory subsystems may be subject to a wide variety of host operating requirements. For example, a first memory subsystem may be used in a cellular phone, while a second memory subsystem may be used in a surveillance camera. The operating requirements of a cellular phone (e.g., high program performance) may be different from the operating requirements of a surveillance camera (e.g., long-term data retention). However, conventional memory subsystems do not provide a mechanism for configuring memory operating settings according to the operating requirements of the host system. According to the example described above, the memory operating settings of the first memory subsystem may be the same as the memory operating settings of the second memory subsystem, but the cellular phone and the surveillance camera may have different operating requirements. Therefore, memory operations at the memory subsystem are not performed according to the operating requirements of the host system, which may reduce the performance of the memory subsystem and increase the latency of read and / or write operations.

[0015] Aspects of the present disclosure address the above and other deficiencies by having a memory subsystem that provides adjustable memory operation settings based on the operating requirements of a host system. By adjusting the memory operation settings based on the operating requirements of the host system, a mechanism is provided for performing memory operations according to the operating requirements of the host system. For example, the priority of each operation requirement of a set of operation requirements associated with the operating environment of the host system can be determined. Based on the priority of each operation requirement, a memory operation setting that causes the memory operation to be performed at the memory subsystem can be determined. In some instances, the memory operation can be a programming operation. In response to a request from the host system to perform a programming operation, the programming operation can be performed based on the memory operation setting. In other instances, the memory operation can be a background management operation. The background management operation can be scheduled and / or performed based on the memory operation setting.

[0016] Advantages of the present disclosure include, but are not limited to, improved performance of a memory subsystem because memory operations at the memory subsystem will be performed according to the operational requirements of the host system. By performing memory operations according to the operational requirements of the host system, the overall read and / or write latency of the memory subsystem may be reduced because programming operations may be performed with fewer errors. In addition, background management operations may be scheduled and performed to improve the performance of the background management operations, thereby improving the performance of the memory subsystem as a whole. In addition, by improving the performance of the background management operations, the overall read and / or write latency of the memory subsystem may be reduced. By reducing the read and / or write latency of the memory subsystem, the memory subsystem may be able to meet quality of service (QoS) requirements associated with various operational requirements at the memory subsystem.

[0017] Figure 1 An example computing environment 100 is shown that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0018] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage devices (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0019] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. The host system 120 uses the memory subsystem 110 to, for example, write data to and read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including, for example, electrical, optical, magnetic, etc. connections.

[0020] The host system 120 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices including a memory and a processing device. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a fiber channel, a serial attached SCSI (SAS), etc. The physical host interface may be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access a memory component (e.g., a memory device 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0021] The memory devices may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0022] Examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory. Each of memory devices 130 may include one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., triple-level cells (TLC) or quad-level cells (QLC)). In some embodiments, a particular memory component may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. Each of the memory cells may store one or more bits of data used by host system 120. In addition, the memory cells of memory device 130 may be grouped into memory pages or memory blocks, which may refer to units of a memory component for storing data.

[0023] Although non-volatile memory components such as NAND-type flash memory are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), magnetic random access memory (MRAM), "NOR" (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells.

[0024] The memory subsystem controller 115 may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0025] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0026] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include the memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0027] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0028] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0029] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130 .

[0030] The memory subsystem 110 includes an operation setting component 113 that can determine one or more memory operation settings based on the operation requirements of the host system. In some embodiments, the memory subsystem controller 115 includes at least a portion of the operation setting component 113. For example, the memory subsystem controller 115 can include a processor 117 (processing device) that is configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the operation setting component 113 is part of the host system 120, an application, or an operating system.

[0031] The operation setting component 113 may determine a priority for each operation requirement of a set of operation requirements of the memory subsystem. Each operation requirement of the set of operation requirements may correspond to an operating environment of the host system. Based on the priority of each operation requirement, the operation setting component 113 may determine a memory operation setting for a memory operation to be performed at the memory subsystem. The memory operation setting may be determined so that when a memory operation is performed based on the memory operation setting, one or more operation requirements associated with a higher priority than other operation requirements are satisfied. Additional details about the operation of the operation setting component 113 are described below.

[0032] Figure 2 2 is a flow chart of an example method 200 for adjusting programming operation settings based on memory subsystem operating system requirements according to some embodiments of the present disclosure. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by Figure 1 The operation setting component 113 is executed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, the illustrated embodiment should be understood as an example only, and the illustrated process can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0033] At operation 210, the processing device determines a priority of each operation requirement of a set of operation requirements of the memory subsystem. Each operation requirement of the set of operation requirements can be associated with a host system (e.g., Figure 1The set of operating requirements may correspond to the operating environment of the host system 120 of the memory subsystem. In some embodiments, the set of operating requirements may include at least one of the operating temperature of the memory subsystem, the time period that data will be retained at the memory subsystem, the program performance of the memory subsystem, or the persistence of the memory subsystem. In the same or alternative embodiments, the operating requirements may include any other operating requirements of the memory subsystem.

[0034] The priority of each operating requirement may include a rating or weighting for each operating requirement. In one embodiment, the priority of each operating requirement may include rating each operating requirement based on the impact of the operating requirement on the performance of the memory subsystem. In some embodiments, the operating requirement may affect the performance of the memory subsystem if the operating requirement affects at least the read and / or write latency of the memory subsystem, affects the useful life of the memory subsystem, etc. For example, the operating environment of the host system may be a car operating at cold temperatures (e.g., temperatures that rarely exceed 50°F). Based on the operating environment of the host system, the operating temperature of the memory subsystem may have a greater impact on the performance of the memory subsystem than other operating requirements for the memory subsystem. As such, the operating temperature of the memory subsystem may be associated with a higher priority than other operating requirements for the memory subsystem.

[0035] In other embodiments, the priority of each operating requirement may include an indication of whether each operating requirement has priority or does not have priority. In one embodiment, one or more operating requirements that have a greater impact on the performance of the memory subsystem may be associated with a priority, while other operating requirements are not associated with a priority. According to the example described above, the operating temperature of the memory subsystem may be associated with a priority, while other operating requirements of the memory subsystem are not associated with a priority.

[0036] In some embodiments, the priority of each operating requirement may be determined based on a set of operating requirement priorities received from a host system. In one embodiment, a user of the host system may provide a priority for one or more operating requirements of the set of operating requirements based on an operating environment of the host system. According to the example previously described, the operating environment of the host system may be an automobile operating at cold temperatures. Based on the operating environment, the host system may provide an indication to the processing device that the operating temperature of the memory subsystem has a higher priority than other operating requirements of the memory subsystem. In some embodiments, the indication may include a ranking of the priorities of the operating requirements, wherein the operating temperature of the memory subsystem is associated with a higher priority. In other embodiments, the indication may provide that the operating temperature of the memory subsystem is associated with a priority, while other operating requirements of the memory subsystem are not associated with a priority.

[0037] In some embodiments, a priority of each operating requirement may be determined based on an indication of an operating environment of the host system. The processing device may receive an indication of an operating environment of the host system. Based on the received operating environment, a priority may be assigned to each operating requirement of the set of operating requirements, wherein a higher priority is assigned to an operating requirement that has a greater impact on the performance of the memory subsystem than other operating requirements of the set of operating requirements.

[0038] According to the previously described example, the operating environment of the host system may be an automobile operating at a cold temperature. The host system may provide an indication to the processing device that the host system is operating at a cold temperature. Based on the indication that the host system is operating at a cold temperature, the processing device may assign a priority to each operating requirement of the set of operating requirements. For example, based on the indication that the host system is operating at a cold temperature, a higher priority may be assigned to the operating temperature of the memory subsystem compared to other operating requirements.

[0039] In another example, the operating environment of the host system may be a surveillance camera, where the surveillance camera will capture surveillance image footage for at least a 24-hour period and store the captured surveillance image footage for a given time period. The host system may provide an indication of the operating environment to the processing device. Based on the indication that the host system may be a surveillance camera, the processing device may assign a priority to each operation requirement of the set of operation requirements. For example, a higher priority may be assigned to an operation requirement having a time period for which data will be retained at the memory subsystem than to other operation requirements, because the time period for which data will be retained may have a greater impact on the performance of the memory subsystem relative to the operating environment of the host system than to other operation requirements.

[0040] In some embodiments, one or more parameter values ​​may be received from the host system. The one or more received parameter values ​​may correspond to one or more priorities for each set of operational requirements. According to the previously described example, the operating environment of the host system may be a car operating at a cold temperature. The host system may provide a parameter value for the average operating temperature (e.g., 50°F) of the host system. In addition, for example, when the driver operates the car, the temperature of the car may periodically increase to a warm temperature (e.g., a temperature exceeding 50°F). In this example, the host system may provide an estimated parameter value corresponding to the amount of time that the host system will operate at a temperature exceeding 50°F. In another example, the host system may provide an estimated parameter value corresponding to a number of write operation requests that the host system will transmit to the memory subsystem when the temperature of the car is below 50°F.

[0041] At operation 220, the processing device determines a programming operation setting for a programming operation to be performed at the memory subsystem based on the priority of each operation requirement. The programming operation may include a read operation, a write operation, or an erase operation. The programming operation setting may include an initial write mode of host data stored at the memory subsystem, a subsequent write mode of host data stored at the memory subsystem, a read voltage, or a rate at which data will be written to the memory subsystem. The initial write mode may correspond to the first bit number per memory cell of the memory subsystem used to store host data when the data is initially written to the memory subsystem. The subsequent write mode may correspond to the second bit number per memory cell of the memory subsystem used to store host data initially written to the memory subsystem in the initial write mode and rewritten in the subsequent write mode. In other embodiments, the programming operation setting may include any setting corresponding to the programming operation. In some embodiments, the programming operation setting may also be determined based on one or more parameter values ​​corresponding to the priority of each operation requirement received from the host system.

[0042] According to the previously described example, the operating environment of the host system may be a car operating at cold temperatures. A higher priority may be assigned to the operating temperature of the memory subsystem compared to other operating requirements of the memory subsystem. The processing device may also have received from the host system a parameter value for the average operating temperature of the host system, a parameter value corresponding to an estimate of the amount of time the host system will operate at a temperature exceeding 50°F, and a parameter value corresponding to an estimate of a number of write operation requests that the host system will transmit to the memory subsystem when the temperature of the car is below 50°F. Based on the priority of the operating requirements and the received parameter values, the processing device may determine one or more programming operation settings for the programming operation to be performed at the memory subsystem. For example, the processing device may determine that when the host data is received when the temperature of the car is below 50°F, the initial write mode of the host data stored at the memory subsystem is set to the SLC write mode (i.e., the host data will be stored at a data block with SLC). The processing device may further determine that when the temperature of the host system exceeds 50°F, the subsequent write mode of the host data stored at the memory subsystem is set to the TLC write mode (i.e., the host data will be stored at a data block with TLC).

[0043] In some embodiments, the processing device may determine a parameter value threshold corresponding to at least one operation requirement of the set of operation requirements. The parameter value threshold may indicate a parameter value range associated with the operation requirement, wherein a first programming operation setting is to be applied to the programming operation. In response to determining that the parameter value has exceeded the parameter value threshold, the processing device may determine to apply a second programming operation setting to the programming operation. According to the example described above, the processing device may determine that when the temperature of the host system exceeds 50°F, an initial write mode of host data stored at the memory subsystem is set to an SLC write mode, and a subsequent write mode is set to a TLC write mode. The processing device may further determine that in response to an operating temperature of the host system exceeding or satisfying a parameter value threshold, such as a higher temperature (e.g., 70°F), a subsequent write mode is to be set to a QLC write mode.

[0044] At operation 230, the processing device receives a request to perform a programming operation at the memory subsystem. For example, the host system may provide a request to cause a programming operation to read, write, or erase data stored at the memory subsystem. At operation 240, the processing device performs a programming operation at the memory subsystem based on a programming operation setting in response to receiving the request to perform a programming operation. According to the example described above, the operating environment of the host system may be a car operating at cold temperatures. The processing device may receive a request to perform a write operation to write host data to the memory subsystem. When the request to perform a write operation is received, the temperature of the car may be below 50°F. Based on the programming operation setting determined at operation 220, the processing device may perform a write operation in an SLC write mode to write host data to the memory subsystem.

[0045] Figure 3 is a flow chart of an example method 300 for adjusting background management operation settings based on memory subsystem operation requirements according to some embodiments of the present disclosure. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The operation setting component 113 is executed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, the illustrated embodiment should be understood as an example only, and the illustrated process can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0046] At operation 310, the processing device determines a priority of each operation requirement of a set of operation requirements of the memory subsystem. Each operation requirement of the set of operation requirements can be associated with a host system (e.g., Figure 1 In some embodiments, the set of operating requirements may include at least one of an operating temperature of the memory subsystem, a time period for which data will be retained at the memory subsystem, program performance of the memory subsystem, or persistence of the memory subsystem. In other embodiments, the operating requirements may include any other operating requirements of the memory subsystem. Figure 2 As discussed, in some embodiments, the priority of each operation requirement may include a rating or weighting for each operation requirement. In other embodiments, the priority of each operation requirement may include an indication of whether each operation requirement has priority.

[0047] In some embodiments, the priority of each operating requirement may be determined based on a set of operating requirement priorities received from the host system according to the previously described embodiments. In other embodiments, the priority of each operating requirement may be determined based on an indication of the operating environment of the host system as previously described. As previously described, the processing device may similarly receive one or more parameters corresponding to one or more priorities of each set of operating requirements.

[0048] At operation 320, the processing device determines background management operation settings for background management operations to be performed at the memory component based on the priority of each operation requirement. The background management operation may include a garbage collection operation, a data refresh operation, or a data wear leveling operation. The background management operation settings may include the execution frequency of each of the garbage collection operation, the data refresh operation, or the data wear leveling operation, the garbage collection operation write mode, the data refresh operation write mode, the portion of the data block of the memory subsystem to be subjected to the garbage collection operation, the data refresh operation, or the data wear leveling operation, etc. In other embodiments, the background management operation settings may include any settings corresponding to the background management operation. In some embodiments, the background management operation may also be determined based on one or more parameter values ​​corresponding to the priority of each operation requirement received from the host system.

[0049] In one example, the operating environment of the host system may be an automobile that operates at cold temperatures (e.g., temperatures that rarely exceed 50°F). The operating temperature of the memory subsystem may be assigned a higher priority than other operating requirements of the memory subsystem. The processing device may also have received a parameter value from the host system indicating the amount of time the automobile was cold during operation of the automobile. Based on the priority of the operating requirement and the received parameter value, the processing device may determine one or more background management operation settings for background management operations to be performed at the memory subsystem. For example, the processing device may determine the frequency with which a data refresh operation will be performed at the memory subsystem. In some embodiments, according to the previously described embodiments, the processing device may determine a parameter value threshold corresponding to at least one operating requirement of the set of operating requirements.

[0050] At operation 330, the processing device schedules the background management operation to be performed at the memory component based on the background management operation settings. According to the previously described example, at operation 320, the processing device may determine the setting corresponding to the frequency at which the data refresh operation will be performed at the memory subsystem based on the priority of each operation requirement and the received parameter value corresponding to the priority. Based on the determined setting, the processing device may schedule the data refresh operation to be performed at the determined frequency.

[0051] In some embodiments, the background management operation setting does not correspond to the execution frequency of the background management operation setting. In such embodiments, the processing device may schedule the background management operation to be executed according to a default frequency. The processing device may also cause the background management operation to be executed based on the background management operation setting determined at operation 320. For example, instead of determining the frequency at which the data refresh operation is to be performed, the processing device may determine a set of data blocks of the memory subsystem to be subjected to the data refresh operation. The processing device may schedule the data refresh operation to be executed according to the default frequency setting, wherein the data refresh operation is to be executed at the determined set of data blocks based on the determined background management operation setting.

[0052] Figure 4 4 shows adjusting memory operation settings 402 based on memory subsystem operation requirements 404 according to some embodiments of the present disclosure. The memory subsystem operation requirements 404 may each be associated with a host system (e.g., Figure 1 In some embodiments, the memory subsystem operating requirements 404 may include the operating temperature of the memory subsystem, the time period that data will be retained at the memory subsystem, the program performance of the memory subsystem, or the persistence of the memory subsystem.

[0053] A priority 406 for each memory subsystem operation requirement 404 may be determined by the processing device. In some embodiments, each priority 406 may be determined based on a set of operation requirement priorities received from the host system. In other embodiments, each priority 406 may be determined based on an indication of an operating environment of the host system received from the host system. In response to receiving the indication of the operating environment of the host system, each priority 406 may be assigned to each operation requirement, wherein an operation requirement having a greater impact on the performance of the memory subsystem is assigned a higher priority than other operation requirements of the set of operation requirements.

[0054] One or more memory operation settings 402 may be determined based on each priority 406 of the set of operation requirements 404. In some embodiments, the memory operation settings 402 may be default operation settings. According to previously described embodiments, one or more default operation settings may be modified based on each priority 406 of the set of operation requirements 404.

[0055] In one example, the operating environment of the host system may be a cellular phone. Based on the operating environment of the host system, operating requirement 3 (e.g., program performance operating requirement 404) may have a higher priority 406 than other operating requirements 404, such as the operating temperature of the memory subsystem, the time period during which data will be kept at the memory subsystem, or the persistence of the memory subsystem. Therefore, as seen in the illustrated example, the priority 406 of operating requirement 3 is higher than the priority 406 of other operating requirements 404. Based on the priority 406 of operating requirement 3, operating setting 3 and operating setting 6 may be determined. In addition, based on the priority 406 of other operating requirements 404, one or more of operating settings 402 may be determined. For example, operating setting 1 may be determined based on the priority 406 of operating requirement 1 and operating requirement 4. In another example, operating setting 402 is not determined based on the priority 406 of the one or more operating requirements 404. For example, operating setting 2 and operating setting 4 are determined based on the priority 406 of each operating requirement 404. In such examples, operational setting 2 and operational setting 4 may be the default operational settings.

[0056] Figure 5 An example machine of computer system 500 is shown, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, execute the operating system to execute the corresponding Figure 1In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0057] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is illustrated, the term "machine" shall also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0058] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0059] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 502 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 to communicate via a network 520.

[0060] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein. The instructions 526 may also reside, in whole or in part, within the main memory 504 and / or within the processing device 502 during execution thereof by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0061] In one embodiment, the instructions 526 include instructions for implementing a corresponding operation setting component (e.g., Figure 1 The functional instructions of the operation setting component 113 of the present invention are provided. Although the machine-readable storage medium 524 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing the one or more instruction sets. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0062] Some portions of the previous detailed description have been presented with respect to algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively communicate the substance of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that produces a desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0063] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0064] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0065] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0066] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0067] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It should be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A method for adjusting memory operation, comprising: receiving, by a memory subsystem controller of a memory subsystem from a host system coupled to the memory subsystem, an indication of a temperature of one or more operating environments of the host system; determining, by the memory subsystem controller, a level of impact of each of a set of operating requirements of the memory subsystem on performance of the memory subsystem based on the indicated temperature of the one or more operating environments of the host system; assigning, by the memory subsystem controller, a corresponding priority to each operation requirement of the set of operation requirements based on the impact level determined for each operation requirement of the set of operation requirements; determining, by the memory subsystem controller, a program operation setting for a program operation to be performed at the memory subsystem based on each respective priority level; receiving, by the memory subsystem controller, a request to perform a programming operation at the memory subsystem; as well as In response to receiving the request to perform the program operation, the program operation is performed at the memory subsystem by the memory subsystem controller based on the program operation settings.

2. The method of claim 1 , wherein assigning the respective priority to each of the set of operating requirements based on an indicated temperature of the one or more operating environments of the host system comprises: An operation requirement associated with a lower programming operation latency is assigned a higher priority than other operation requirements of the set of operation requirements. 3 . The method of claim 1 , wherein the respective priority of each operation requirement is further assigned based on a set of operation requirement priorities received from the host system.

4. The method according to claim 3, further comprising: A parameter value corresponding to a priority of the received set of operation requirement priorities is received, and wherein the programming operation settings are further determined based on the received parameter value.

5. The method of claim 1 , wherein each operating requirement of the set of operating requirements corresponds to at least one of: an operating temperature of the memory subsystem, a time period that data will be retained at the memory subsystem, program performance of the memory subsystem, or persistence of the memory subsystem.

6. The method of claim 1 , wherein the programming operation setting corresponds to at least one of: an initial write pattern of host data stored at the memory subsystem, a subsequent write pattern of the host data stored at the memory subsystem, a read voltage, or a rate at which host data is to be written to the memory subsystem.

7. The method of claim 1 , wherein determining the programming operation setting comprises: A parameter value threshold corresponding to at least one operating requirement of the set of operating requirements is determined.

8. The method of claim 1, wherein the respective priorities are further assigned based on usage of the host system in the one or more operating environments.

9. A system for adjusting memory operations, comprising: Memory components; as well as a processing device operatively coupled to the memory component to: receiving, from a host system coupled to a memory subsystem, an indication of a temperature of one or more operating environments of the host system; determining a level of impact of each of a set of operating requirements of the memory subsystem on performance of the memory subsystem based on the indicated temperature of the one or more operating environments of the host system; assigning a corresponding priority to each operation requirement of the set of operation requirements based on the impact level determined for each operation requirement of the set of operation requirements; determining, based on each respective priority, a background management operation setting for a background management operation to be performed at the memory component; and A background management operation is scheduled to be performed at the memory component based on the background management operation settings.

10. The system of claim 9, wherein to assign the respective priority to each of the set of operating requirements based on the indicated temperature of the one or more operating environments of the host system, the processing device is to: An operation requirement associated with a lower programming operation latency is assigned a higher priority than other operation requirements of the set of operation requirements.

11. The system of claim 9, wherein the respective priority of each operation requirement is further assigned based on a set of operation requirement priorities received from the host system.

12. The system of claim 11, wherein the processing device further: A parameter value corresponding to the received priority of the set of operation requirement priorities is received, and wherein the background management operation setting is further determined based on the received parameter value.

13. The system of claim 9, wherein each operating requirement of the set of operating requirements corresponds to at least one of: an operating temperature of the memory component, a time period that data will be retained at the memory component, program performance of the memory component, or persistence of the memory component.

14. The system of claim 9, wherein the background management operation comprises at least one of the following: a garbage collection operation, a data refresh operation, or a data wear leveling operation.

15. The system of claim 9, wherein respective priorities are further assigned based on usage of the host system in the one or more operating environments.

16. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to: receiving, from a host system coupled to a memory subsystem, an indication of a temperature of one or more operating environments of the host system; determining a level of impact on performance of the memory subsystem by each of a set of operating requirements of the memory subsystem based on an indicated temperature of the one or more operating environments of the host system, the set of operating requirements including an operating temperature of the memory subsystem, a period of time that data is to be retained at the memory subsystem, program performance of the memory subsystem, or persistence of the memory subsystem; assigning a corresponding priority to each operation requirement of the set of operation requirements based on the impact level determined for each operation requirement of the set of operation requirements; determining, based on each respective priority level, a program operation setting for a program operation to be performed at the memory subsystem, the program operation setting including an initial write pattern for host data stored at the memory subsystem, a subsequent write pattern for the host data stored at the memory subsystem, a read voltage, or a rate at which host data is to be written to the memory subsystem; receiving a request to perform a programming operation at the memory subsystem; as well as In response to receiving the request to perform the program operation, the program operation is performed at the memory subsystem based on the program operation settings.

17. The non-transitory computer-readable medium of claim 16, wherein to assign the respective priority to each of the set of operating requirements based on the indicated temperature of the one or more operating environments of the host system, the processing device is to: An operation requirement associated with a lower programming operation latency is assigned a higher priority than other operation requirements of the set of operation requirements.

18. The non-transitory computer-readable medium of claim 16, wherein the respective priority of each operation requirement is further assigned based on a set of operation requirement priorities received from the host system.

19. The non-transitory computer readable medium of claim 18, wherein the processing device further: A parameter value corresponding to a priority of the received set of operation requirement priorities is received, and wherein the programming operation settings are further determined based on the received parameter value.

20. The non-transitory computer readable medium of claim 16, wherein the programming operation comprises at least one of a read operation, a write operation, or an erase operation.

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