A board-level three-dimensional chip packaging structure and a preparation method thereof

Abstract

The application discloses a preparation method of a board-level three-dimensional chip packaging structure, which comprises the following steps: preparing a chip packaging substrate and making the substrate have an exposed first redistribution layer; providing a plurality of first chip groups, flip-chip mounting the first chip groups on the first redistribution layer and performing plastic packaging to form a first plastic packaging layer; opening the first plastic packaging layer to form a tapered slot between every two adjacent first chip groups and a plurality of through holes on a side of one of the first chip groups away from another first chip group, and making the tapered slot and the through holes extend to the first redistribution layer respectively; manufacturing a second redistribution layer on a surface of the first plastic packaging layer, a slot wall of the tapered slot and a hole wall of the through hole; providing a plurality of second chip groups, flip-chip mounting the second chip groups on the second redistribution layer and performing plastic packaging to form a second plastic packaging layer; and manufacturing an electrical connection structure to electrically lead out the first chip groups and the second chip groups. The application is beneficial to the expansion of the four sides of the board-level three-dimensional chip packaging structure and the conduction of the three-dimensional structure, and can effectively reduce warping.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit packaging technology, in particular to a board-level three-dimensional chip packaging structure and a preparation method thereof. BACKGROUND

[0002] With the trend of miniaturization and integration of electronic products, the high density of microelectronic packaging technology has gradually become the mainstream in the new generation of electronic products. In order to adapt to the development of the new generation of electronic products, especially the development of products such as mobile phones, notebooks, and smart wearable devices, chips are developing in the direction of higher density, faster speed, smaller size, and lower cost.

[0003] In the packaging process, due to the difference in the thermal expansion coefficients of materials such as plastic, silicon, and metal, the volume changes of these materials are not synchronized, resulting in stress and warping. Among them, the difference in the thermal expansion coefficients of the chip and the injection molding material is the main reason for the stress generated during the cooling process of the injection molding material, which causes warping in the packaging technology.

[0004] In addition, in the chip fan-out packaging process, it is usually necessary to drill holes in the plastic encapsulation layer of the covered flip-chip and then electroplate conductive pillars to achieve electrical lead-out of the flip-chip. However, this process method is not conducive to the expansion of the four sides of the chip packaging structure and the conduction of the subsequent three-dimensional structure. SUMMARY

[0005] The purpose of the present application is to provide a preparation method of a board-level three-dimensional chip packaging structure and a board-level three-dimensional chip packaging structure prepared by the preparation method. The preparation method is beneficial to the expansion of the four sides of the board-level three-dimensional chip packaging structure and the conduction of the three-dimensional structure, and can effectively reduce warping.

[0006] To achieve this purpose, the present application adopts the following technical solutions:

[0007] On the one hand, a preparation method of a board-level three-dimensional chip packaging structure is provided, comprising the following steps:

[0008] Preparation of a chip packaging substrate, and making one side of the chip packaging substrate have an exposed first redistribution layer;

[0009] Providing a plurality of first chip groups, flip-chipping the first chip groups on the first redistribution layer and plastic encapsulating to form a first plastic encapsulation layer;

[0010] Laser drilling treatment is performed on the first plastic encapsulation layer to form a tapered slot between each adjacent two first chip groups and a plurality of vias on the side of one of the first chip groups away from the other first chip group, and the tapered slot and the via extend to the first redistribution layer, respectively;

[0011] A second redistribution layer is made on the surface of the first plastic sealing layer, the sidewall of the tapered groove and the via hole;

[0012] A plurality of second chip groups are provided, and the second chip groups are flip-chip mounted on the second redistribution layer and sealed to form a second plastic sealing layer;

[0013] The I / O ports of the first chip group and the second chip group are electrically led out by making an electric connection structure.

[0014] The first plastic sealing layer of the first chip group flip-chip mounted on the first redistribution layer is processed to form a tapered groove between every two adjacent first chip groups and a plurality of via holes on the side of one of the first chip groups away from the other first chip group, and a second redistribution layer is made on the sidewall of the tapered groove and the first plastic sealing layer, and a conductive column is made in the via hole, so that the second redistribution layer is directly electrically connected with the first redistribution layer, facilitating the expansion of the chip packaging structure around and the conduction of the subsequently mounted second chip group. At the same time, the opening of the tapered groove is beneficial to stress release and warpage reduction.

[0015] As a preferred embodiment of the preparation method of the board-level three-dimensional chip packaging structure, a glass carrier plate is provided, a temporary bonding glue is attached to one side of the glass carrier plate, and a first seed layer and a first redistribution layer are made on the temporary bonding glue to obtain the chip packaging substrate. Specifically, the first seed layer is made by vacuum sputtering, then a photosensitive dry film is attached, and after exposure and development, the first redistribution layer is made by electroplating, and then the residual photosensitive dry film is removed. The first seed layer can improve the adhesion of the first redistribution layer;

[0016] After the first chip group is coated with nano metal powder and flip-chip mounted on the first redistribution layer, sintering is performed from the side of the glass carrier plate away from the first chip group by laser to form a metal connection layer for fixed connection between the I / O port of the first chip group and the first redistribution layer, and then sealing is performed.

[0017] The glass carrier plate is used to make the chip packaging substrate, and after the glass carrier plate is removed without dismounting and bonding, the warpage of the board-level three-dimensional chip packaging structure can be further reduced. At the same time, another purpose of using the glass carrier plate is to use the characteristics of the glass carrier plate to perform sintering from the back of the glass carrier plate, so that the first chip group coated with nano metal powder is stably fixed on the first redistribution layer after being flip-chip mounted on the first redistribution layer, avoiding the offset of the first chip group in the subsequent sealing process and affecting the packaging effect, and the first redistribution layer is not damaged during the chip sintering and fixing process, improving the product yield.

[0018] The nano metal powder can be nano copper powder or nano titanium alloy powder, and preferably is nano copper powder. The nano metal powder is electrostatically adsorbed on the I / O port of the chip, and is filled between the I / O port of the chip and the first redistribution layer after being melted in the laser sintering process, so as to realize the flip fixing of the first chip set.

[0019] Further, before the second redistribution layer is made, a second seed layer is prepared by vacuum sputtering, the second seed layer is located on the surface of the first plastic encapsulation layer, the two side walls of the tapered groove and the hole wall of the via, after the second seed layer is made, a photosensitive dry film is attached, after exposure and development, the second redistribution layer is made by electroplating, and then the residual photosensitive dry film is removed, thereby obtaining the second redistribution layer. The adhesion of the second redistribution layer can be improved by the first seed layer.

[0020] As a preferred scheme of the preparation method of the board-level three-dimensional chip packaging structure, the electrical connection structure is prepared by the following steps:

[0021] The second plastic encapsulation layer is treated by laser drilling, and a conductive pillar is made at the drilling position and a third redistribution layer connected with the conductive pillar is made on the surface of the second plastic encapsulation layer;

[0022] A solder resist layer is made on the third redistribution layer, and the solder resist layer is drilled to expose the pad area of the third redistribution layer;

[0023] A plurality of metal bumps are provided, and the metal bumps are implanted into the pad area.

[0024] Further, the second plastic encapsulation layer is treated by laser drilling, and a third seed layer is made on the surface of the second plastic encapsulation layer and the hole wall of the drilling position by vacuum sputtering. After the photosensitive ink is made on the third seed layer on the surface of the second plastic encapsulation layer, exposure and development are performed, and then a conductive pillar is made at the drilling position by electroplating and a third redistribution layer connected with the conductive pillar is made on the surface of the second plastic encapsulation layer. The residual photosensitive dry film is removed.

[0025] As another preferred scheme of the preparation method of the board-level three-dimensional chip packaging structure, the electrical connection structure is prepared by the following steps:

[0026] The glass carrier plate and the temporary bonding glue are removed by debonding;

[0027] A solder resist layer is made on the first redistribution layer, and the solder resist layer is drilled to expose the pad area of the first redistribution layer;

[0028] A plurality of metal bumps are provided, and the metal bumps are implanted into the pad area.

[0029] In the above two preferred solutions, the plate-level three-dimensional chip packaging structure can be cut after the metal bumps are implanted to obtain a three-dimensional chip packaging unit. The cutting position can be located at the first plastic encapsulation layer and the second plastic encapsulation layer near the via position of the first chip group, and the circuit is not damaged.

[0030] In the present application, the first seed layer, the second seed layer and the third seed layer can be a single metal layer such as a copper metal layer, or a layer of copper metal layer covered on a titanium metal layer; the preparation methods of the first seed layer, the second seed layer and the third seed layer, and the first redistribution layer, the second redistribution layer and the third redistribution layer are conventional techniques in the art, and will not be described in detail.

[0031] In another aspect, a plate-level three-dimensional chip packaging structure is provided, which is prepared by the preparation method and comprises:

[0032] A chip packaging substrate, one side of the chip packaging substrate having an exposed first redistribution layer;

[0033] A plurality of first chip groups are inverted on the chip packaging substrate and electrically connected with the first redistribution layer;

[0034] A first plastic encapsulation layer is located on the side of the first redistribution layer exposed and encapsulates the first chip groups, a tapered slot extending to the first redistribution layer is formed on the first plastic encapsulation layer and between every two adjacent first chip groups, and a plurality of vias extending to the first redistribution layer are formed on the first plastic encapsulation layer and spaced apart from the outer circumferences of the adjacent two first chip groups;

[0035] A second redistribution layer is located on the first plastic encapsulation layer and extends to the slot wall of the tapered slot and the hole wall of the via and is electrically connected with the first redistribution layer;

[0036] A plurality of second chip groups are inverted on the second redistribution layer;

[0037] A second plastic encapsulation layer is located on the second plastic encapsulation layer and encapsulates the second chip groups;

[0038] An electrical connection structure is electrically connected with the first redistribution layer or the second redistribution layer to electrically lead out the first chip groups and the second chip groups.

[0039] In the present application, the tapered slot can effectively reduce the warping phenomenon of the plate-level three-dimensional chip packaging structure, and is beneficial to the expansion of the four sides of the chip packaging structure and the conduction of the subsequent packaged second chip groups.

[0040] The chip packaging substrate comprises a glass carrier plate, a temporary bonding glue attached to one side of the glass carrier plate, a first seed layer on the temporary bonding glue, and a first redistribution layer on the first seed layer. By using the characteristics of the glass carrier plate, the first chip group with nano metal powder can be sintered and fixed by laser from the back of the glass carrier plate, avoiding the damage of the first redistribution layer caused by directly welding the I / O port of the first chip group on the first redistribution layer. Meanwhile, the use of the glass carrier plate can effectively reduce the warping of the flip chip packaging structure.

[0041] Further, the board-level three-dimensional chip packaging structure further comprises a metal connecting layer between the I / O port of the chip and the first redistribution layer, for electrically connecting the I / O port of the chip and the first redistribution layer. The metal connecting layer is formed by sintering the nano metal powder on the I / O port of the chip by laser from the back of the glass carrier plate.

[0042] Preferably, the metal connecting layer is made of copper or titanium alloy, and more preferably, made of copper.

[0043] As one preferred embodiment of the board-level three-dimensional chip packaging structure, a plurality of holes are formed in the second plastic encapsulation layer, the holes penetrating through the second plastic encapsulation layer and exposing the second redistribution layer, and the electrically connecting structure comprises:

[0044] a conductive column in the hole, and a third redistribution layer on the second plastic encapsulation layer and electrically connected with the conductive column;

[0045] a solder resist layer on the second plastic encapsulation layer and covering the third redistribution layer, the solder resist layer having a hole exposing a pad area of the third redistribution layer;

[0046] a plurality of metal bumps protruding from the surface of the solder resist layer, the metal bumps being implanted in the pad area and electrically connected with the third redistribution layer.

[0047] Further, a third seed layer is further included, the third seed layer being on the inner wall of the hole of the second plastic encapsulation layer and on the surface of the second plastic encapsulation layer.

[0048] Specifically, a third seed layer is further included, the third seed layer being on the surface of the second plastic encapsulation layer and on the hole wall of the hole, the third redistribution layer being on the third seed layer on the surface of the second plastic encapsulation layer, and the conductive column being in the hole, the third seed layer improving the adhesion of the third redistribution layer and the conductive column.

[0049] As another preferred embodiment of the board-level three-dimensional chip packaging structure, the electrically connecting structure comprises:

[0050] solder resist layer, located on the side of the first redistribution layer exposed after the chip packaging substrate removes the glass carrier plate and the temporary bonding glue, the solder resist layer is provided with holes for exposing the pad area of the first redistribution layer;

[0051] a plurality of metal bumps protruding from the surface of the solder resist layer, the metal bumps are implanted in the pad area and electrically connected with the first redistribution layer.

[0052] The chip packaging substrate in the technical solution is the first redistribution layer after the temporary bonding.

[0053] Compared with the above technical solution, the technical solution does not need to make a third seed layer and a third redistribution layer, saves the manufacturing steps, and improves the production efficiency.

[0054] In the above two parallel technical solutions, the metal bumps in the electrical connection structure are tin solder, silver solder or gold-tin alloy solder, preferably tin solder.

[0055] In the above technical solution, the via hole is a cylindrical hole or a conical hole, or in each chip packaging unit, the side of the via hole close to the chip set is a bevel, and the opposite side is an arc surface extending in the vertical direction, which is convenient for making the second seed layer and the second redistribution layer. The bevel can be a plane or an arc surface.

[0056] The beneficial effects of the present application are as follows: the first plastic encapsulation layer of the first chip set invertedly covered on the first redistribution layer is processed to form a conical groove between each adjacent two first chip sets and a plurality of via holes on the side of one of the first chip sets away from the other first chip set, and a second redistribution layer is made on the first plastic encapsulation layer, the two side walls of the conical groove and the hole walls of the via holes, so that the second redistribution layer is directly electrically connected with the first redistribution layer, which is convenient for the expansion of the periphery of the three-dimensional chip packaging structure and the conduction of the subsequently mounted chip sets in the three-dimensional structure. At the same time, the conical groove is beneficial to release stress and reduce warpage. BRIEF DESCRIPTION OF DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0058] Figure 1 is a cross-sectional view of the glass carrier plate after the first redistribution layer is made according to the first embodiment of the present application.

[0059] Figure 2is the section view schematic diagram of the first chip group flip-chip on the first redistribution layer and after plastic package of the embodiment one of the present application.

[0060] Figure 3 is the section view schematic diagram of the first plastic package layer after opening the tapered groove and via of the embodiment one of the present application.

[0061] Figure 4 is the section view schematic diagram of the second redistribution layer after making the second redistribution layer on the surface of the first plastic package layer, the tapered groove wall and the via wall of the embodiment one of the present application.

[0062] Figure 5 is the section view schematic diagram of the second chip group flip-chip on the second redistribution layer of the embodiment one of the present application.

[0063] Figure 6 is the section view schematic diagram of the second plastic package layer after making of the embodiment one of the present application.

[0064] Figure 7 is the section view schematic diagram of the second plastic package layer after opening of the embodiment one of the present application.

[0065] Figure 8 is the section view schematic diagram of the conductive column and the third redistribution layer after making of the embodiment one of the present application.

[0066] Figure 9 is the section view schematic diagram of the solder resist layer and the metal bump after making on the third redistribution layer of the embodiment one of the present application.

[0067] Figure 10 is the section view schematic diagram of the glass carrier plate after removing of the embodiment two of the present application.

[0068] Figure 11 is the section view schematic diagram of the solder resist layer and the metal bump after making on the first redistribution layer of the embodiment two of the present application.

[0069] In the figure:

[0070] 11, glass carrier plate; 12, first redistribution layer; 20, first chip group; 30, first plastic package layer; 31, tapered groove; 32, via; 40, second redistribution layer; 50, second chip group; 60, second plastic package layer; 71, conductive column; 72, third redistribution layer; 73, solder resist layer; 74, metal bump. DETAILED DESCRIPTION

[0071] The technical solutions of the present application are further illustrated by specific embodiments and the accompanying drawings.

[0072] In the drawings, only for example, the representation is a schematic diagram, not a physical diagram, and cannot be understood as a limitation of the patent; in order to better illustrate the embodiments of the present application, some components in the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0073] The same or similar reference numerals in the drawings of the embodiments of the present application correspond to the same or similar components; in the description of the present application, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore the positional relationship described in the drawings is only for example, and cannot be understood as a limitation of the patent, for those skilled in the art, the specific meaning of the above terms can be understood according to the specific situation.

[0074] In the description of the present application, unless otherwise explicitly specified and limited, if the term "connection" and the like appear to indicate the connection relationship between components, the term should be broadly understood, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication or interaction relationship between two components. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific situation.

[0075] Embodiment one

[0076] The preparation method of the board-level three-dimensional chip packaging structure of the present embodiment is as follows:

[0077] S10, referring to Figure 1 , a glass carrier plate 11 is provided, a temporary bonding glue is attached to one side of the glass carrier plate 11, and a first seed layer (a titanium metal layer is first made, and then a copper metal layer is made) is made on the temporary bonding glue by vacuum sputtering method;

[0078] S20, a photosensitive dry film is attached on the first seed layer, and after exposure and development, the first heavy wiring layer 12 is made by electroplating;

[0079] S30, the residual photosensitive dry film is removed, and the first seed layer exposed to the first heavy wiring layer 12 is etched off;

[0080] S40, referring to Figure 2 , a plurality of first chip groups 20 are provided, the I / O port of the first chip group 20 is coated with nano copper powder, and then inverted on the first heavy wiring layer 12;

[0081] S50. Laser is used to sinter the back of the glass substrate 11 to fix the first chipset 20 onto the first redistribution layer 12.

[0082] S60. The first chipset 20 is encapsulated to form a first encapsulation layer 30;

[0083] S70, Reference Figure 3 A tapered groove 31 is formed on the first molding compound 30 located between each two adjacent first chipsets 20, and a plurality of vias 32 are formed on the first molding compound 30 located on the side of one first chipset 20 away from the other first chipset 20, and the tapered groove 31 and the vias 32 extend to the first redistribution layer 12 respectively.

[0084] S80. A second seed layer is formed on the surface of the first molding layer 30, the wall of the tapered groove 31, and the wall of the via 32 by vacuum sputtering.

[0085] S90, Reference Figure 4 A photosensitive dry film is attached to the second seed layer located on the surface of the first molding layer 30 and the wall of the tapered groove 31. After exposure and development, the second redistribution layer 40 is made by electroplating on the surface of the first molding layer 30, the wall of the tapered groove 31, and the wall of the via 32.

[0086] S100: Remove the residual photosensitive dry film and etch away the second seed layer exposed on the second redistribution layer 40;

[0087] S110, Reference Figure 5 A plurality of second chipsets 50 are provided, the second chipsets 50 are flip-chip mounted on the second redistribution layer 40 and then encapsulated to form a shape as shown in the figure. Figure 6 The second molding layer 60 is shown;

[0088] S120, Reference Figure 7 The second molding layer 60 is made into an opening, and a third seed layer is made on the wall of the opening and the surface of the second molding layer 60 by vacuum sputtering.

[0089] S130, Reference Figure 8 A photosensitive dry film is attached to the third seed layer on the surface of the second molding layer 60. After exposure and development, conductive pillars 71 are made at the opening position by electroplating, and a third redistribution layer 72 is made on the third seed layer on the surface of the second molding layer 60.

[0090] S140, Remove the residual photosensitive dry film and etch away the third seed layer exposed on the third overlay layer 72;

[0091] S150, Reference Figure 9Photosensitive ink is coated on the third wiring layer 72, and after curing, a solder resist layer 73 is formed. Holes are made in the solder resist layer 73 to expose the pad area of ​​the third wiring layer 72.

[0092] S160, Provide a number of solder balls (metal bumps 74) and implant the solder balls into the pad area.

[0093] The board-level three-dimensional chip packaging structure obtained by the fabrication method of this embodiment is as follows: Figure 9 As shown, it includes:

[0094] A chip packaging substrate, wherein one side of the chip packaging substrate has an exposed first redistribution layer 12;

[0095] A plurality of first chipsets 20 are flip-chip mounted on the chip packaging substrate and electrically connected to the first redistribution layer 12;

[0096] The first molding compound 30 is located on the exposed side of the first redistribution layer 12 and covers the first 20 chipset. A tapered groove 31 extending to the first redistribution layer 12 is formed on the first molding compound 30 and between every two adjacent first chipset 20. A plurality of vias 32 extending to the first redistribution layer 12 are formed on the first molding compound 30 at intervals near the outer periphery of two adjacent first chipset 20.

[0097] The second rewiring layer 40 is located on the first molding layer 30 and extends to the wall of the tapered groove 31 and the wall of the via 32, and is electrically connected to the first rewiring layer 12.

[0098] Several second chipsets 50 are flip-chip mounted on the second overlay layer 40;

[0099] The second molding layer 60 is located on the second molding layer 60 and covers the second chipset 50;

[0100] An electrical connection structure is electrically connected to the first rewiring layer 12 or the second rewiring layer 40 to electrically bring out the first chipset 20 and the second chipset 50.

[0101] The chip packaging substrate includes a glass substrate 11, a temporary bonding adhesive attached to one side of the glass substrate 11, a first seed layer on the temporary bonding adhesive, and a first redistribution layer 12 on the first seed layer.

[0102] The board-level three-dimensional chip packaging structure also includes a metal interconnect layer, which is located between the I / O port of the chip in the first chipset 20 and the first redistribution layer 12, for electrically connecting the I / O port of the chip to the first redistribution layer 12.

[0103] The second molding layer 60 has a plurality of holes that penetrate the second molding layer 60 and expose the second redistribution layer 40. The electrical connection structure includes:

[0104] The conductive post 71 located within the hole and the third rewiring layer 72 located on the second molding layer 60 and electrically connected to the conductive post 71;

[0105] A solder mask layer 73 is located on the second molding compound layer 60 and covers the third redistribution layer 72. The solder mask layer 73 has holes that expose the pad areas of the third redistribution layer 72.

[0106] Several metal bumps 74 protrude from the surface of the solder mask layer 73, and the metal bumps 74 are embedded in the pad area and electrically connected to the third wiring layer 72.

[0107] It also includes a third seed layer, which is located on the inner wall of the pores of the second molding layer 60 and on the surface of the second molding layer 60.

[0108] The first molding layer 30 and the second molding layer 60 near the via 32 of the board-level three-dimensional chip packaging structure are cut to form a chip packaging unit.

[0109] In each chip packaging unit, the via 32 has a sloping side near the chipset and an arc-shaped surface extending vertically on the opposite side.

[0110] In this embodiment, each chip packaging unit formed after dicing includes two first chip groups 20 and two second chip groups 50.

[0111] Example 2

[0112] The fabrication method of the board-level three-dimensional chip packaging structure in this embodiment is as follows (steps S10-S110 in this embodiment are the same as steps S10-S110 in the above embodiment 1, and can be referred to the corresponding figures in the steps of the above embodiment 1, and the same components use the same figure references):

[0113] S10. Provide a glass substrate 11, apply temporary bonding adhesive to one side of the glass substrate 11, and fabricate a first seed layer on the temporary bonding adhesive by vacuum sputtering (first fabricate a titanium metal layer, then fabricate a copper metal layer).

[0114] S20. A photosensitive dry film is attached to the first seed layer, and after exposure and development, the first superwire layer 12 is made by electroplating.

[0115] S30, Remove the residual photosensitive dry film and etch away the first seed layer exposed on the first redistribution layer 12;

[0116] S40. Provide a plurality of first chipsets 20, and after coating the I / O ports of the first chipsets 20 with nano copper powder, flip-mount them onto the first redistribution layer 12.

[0117] S50. Laser is used to sinter the back of the glass substrate 11 to fix the first chipset 20 onto the first redistribution layer 12.

[0118] S60. The first chipset 20 is encapsulated to form a first encapsulation layer 30;

[0119] S70, a tapered groove 31 is formed on the first molding compound 30 located between each two adjacent first chipsets 20, and a plurality of vias 32 are formed on the first molding compound 30 located on the side of one first chipset 20 away from the other first chipset 20, and the tapered groove 31 and the vias 32 extend to the first redistribution layer 12 respectively.

[0120] S80. A second seed layer is formed on the surface of the first molding layer 30, the wall of the tapered groove 31, and the wall of the via 32 by vacuum sputtering.

[0121] S90. A photosensitive dry film is attached to the second seed layer located on the surface of the first molding layer 30 and the wall of the tapered groove 31. After exposure and development, a second redistribution layer 40 is made by electroplating on the surface of the first molding layer 30, the wall of the tapered groove 31, and the wall of the via 32.

[0122] S100: Remove the residual photosensitive dry film and etch away the second seed layer exposed on the second redistribution layer 40;

[0123] S110. Provide a plurality of second chipsets 50, flip-chip onto the second redistribution layer 40 and encapsulate them to form a second encapsulation layer 60.

[0124] S120, Reference Figure 10 Disassemble and remove the glass carrier plate 11 and temporary bonding adhesive;

[0125] S130, Reference Figure 11 Photosensitive ink is coated on the first redistribution layer 12, and after curing, a solder resist layer 73 is formed. Holes are made in the solder resist layer 73 to expose the pad area of ​​the first redistribution layer 12.

[0126] S140. Provide a number of solder balls (metal bumps 74) and implant the solder balls into the pad area of ​​the first overlay layer 12.

[0127] In this embodiment, the first seed layer on one side of the first redistribution layer 12 exposed after debonding can be etched first to expose the first redistribution layer 12, and then the above steps S130 and S140 can be performed.

[0128] The board-level three-dimensional chip packaging structure obtained by the fabrication method of this embodiment is as follows: Figure 11 As shown, it is basically the same as the board-level three-dimensional chip packaging structure obtained in Embodiment 1 above, except for the electrical connection structure (the electrical connection structure in this embodiment is directly connected to the first wiring layer) and the chip packaging substrate (the structure of the chip packaging substrate is also changed accordingly).

[0129] Specifically, the electrical connection structure in this embodiment includes a solder mask layer 73 located on the side of the first redistribution layer 12 exposed after the glass carrier 11 and temporary bonding adhesive are removed from the chip packaging substrate, away from the first chipset 20. The solder mask layer 73 has holes that expose the pad area of ​​the first redistribution layer 12.

[0130] Several metal bumps 74 protrude from the surface of the solder mask layer 73, and the metal bumps 74 are embedded in the pad area and electrically connected to the first redistribution layer 12.

[0131] Example 3

[0132] This embodiment is basically the same as the second embodiment above. The difference is that a third wiring layer is made on the surface of the first seed layer exposed after debonding, and then a solder mask layer and metal bumps are made. The details will not be repeated.

[0133] It should be stated that the above-described specific embodiments are merely preferred embodiments of the present invention and the technical principles employed. Those skilled in the art should understand that various modifications, equivalent substitutions, and variations can be made to the present invention. However, such variations, as long as they do not depart from the spirit of the present invention, should be within the scope of protection of the present invention. Furthermore, some terminology used in this specification and claims is not limiting, but merely for ease of description.

Claims

1. A method for fabricating a board-level three-dimensional chip packaging structure, characterized in that, Includes the following steps: A glass substrate is provided, a temporary bonding adhesive is applied to one side of the glass substrate, and a first seed layer and a first redistribution layer are formed on the temporary bonding adhesive to obtain a substrate for chip packaging. A plurality of first chipsets are provided. After the first chipsets are coated with nano-metal powder and flip-chipped onto the first redistribution layer, laser is used to sinter the glass substrate away from the first chipsets to form a metal connection layer that fixes the I / O ports of the first chipsets to the first redistribution layer. Then, plastic encapsulation is performed to form a first plastic encapsulation layer. The first molding layer is made into a tapered groove between each pair of adjacent first chipsets and a plurality of vias on the side of one first chipet away from the other first chipet, and the tapered groove and the vias extend to the first redistribution layer respectively. A second rewiring layer is formed on the surface of the first molding layer, the wall of the tapered groove, and inside the via; A plurality of second chipsets are provided, and the second chipsets are flip-chip mounted on the second redistribution layer and then encapsulated to form a second encapsulation layer; By fabricating an electrical connection structure, the I / O ports of the first chipset and the second chipset are electrically brought out.

2. The method for fabricating a board-level three-dimensional chip packaging structure according to claim 1, characterized in that, The electrical connection structure is manufactured using the following steps: The second molding layer is made into an opening, and a conductive post is made at the opening position. A third seed layer and a third redistribution layer connected to the conductive post are sequentially made on the surface of the second molding layer. A solder mask layer is fabricated on the third wiring layer, and holes are made in the solder mask layer to expose the pad area of ​​the third wiring layer. A plurality of metal bumps are provided, and the metal bumps are implanted into the pad area.

3. The method for fabricating a board-level three-dimensional chip packaging structure according to claim 1, characterized in that, The electrical connection structure is manufactured using the following steps: Disconnect the bond and remove the glass substrate and the temporary bonding adhesive; A solder mask layer is fabricated on the first overlay layer, and holes are made in the solder mask layer to expose the pad area of ​​the first overlay layer. A plurality of metal bumps are provided, and the metal bumps are implanted into the pad area.

4. A board-level three-dimensional chip packaging structure, fabricated using the method described in any one of claims 1-3, characterized in that, include: A chip packaging substrate, wherein one side of the chip packaging substrate has an exposed first wiring layer; Several first chipsets are flip-chip mounted on the chip packaging substrate and electrically connected to the first redistribution layer; A first molding layer is located on the exposed side of the first redistribution layer and covers the first chipset. A tapered groove extending to the first redistribution layer is formed on the first molding layer and between every two adjacent first chipsets. A plurality of vias extending to the first redistribution layer are formed on the first molding layer at intervals near the outer periphery of two adjacent first chipsets. The second wiring layer is located on the first molding layer and extends to the wall of the tapered groove and the wall of the via and is electrically connected to the first wiring layer. Several second chipsets are flip-chip mounted on the second overlay layer; The second molding layer is located on the first molding layer and covers the second chipset; An electrical connection structure is electrically connected to the first or second overlay layer to electrically bring out the first and second chipsets.

5. The board-level three-dimensional chip packaging structure according to claim 4, characterized in that, The chip packaging substrate includes a glass substrate, a temporary bonding adhesive attached to one side of the glass substrate, a first seed layer on the temporary bonding adhesive, and a first redistribution layer on the first seed layer.

6. The board-level three-dimensional chip packaging structure according to claim 5, characterized in that, The second molding layer has a plurality of holes that penetrate the second molding layer and expose the second redistribution layer. The electrical connection structure includes: A conductive post located within the hole and a third wiring layer located on the second molding layer and electrically connected to the conductive post; A solder mask layer is located on the second molding layer and covers the third wiring layer. The solder mask layer has holes that expose the pad areas of the third wiring layer. A plurality of metal bumps protruding from the surface of the solder mask layer are embedded in the pad area and electrically connected to the third wiring layer.

7. The board-level three-dimensional chip packaging structure according to claim 4, characterized in that, The electrical connection structure includes: A solder resist layer is located on the side of the first redistribution layer exposed after the glass carrier and the temporary bonding adhesive are removed from the chip packaging substrate, away from the first chipset. The solder resist layer has holes that expose the pad area of ​​the first redistribution layer. A plurality of metal bumps protruding from the surface of the solder mask layer are embedded in the pad area and electrically connected to the first redistribution layer.

8. The board-level three-dimensional chip packaging structure according to any one of claims 4-7, characterized in that, It also includes a metal interconnect layer, which is located between the chip's I / O port and the first rewiring layer, for electrically connecting the chip's I / O port and the first rewiring layer.

9. The board-level three-dimensional chip packaging structure according to any one of claims 4-7, characterized in that, The via is a cylindrical hole or a conical hole; Alternatively, in each chip packaging unit, the via is sloped on the side closest to the chipset, and the opposite side is an arc-shaped surface extending vertically.

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