Semiconductor die, semiconductor device, and insulated gate bipolar transistor module

Abstract

Semiconductor dies, semiconductor devices, and insulated-gate bipolar transistor (IGBT) modules are disclosed. A semiconductor die (510) includes a semiconductor body (100). The semiconductor body (100) includes a first active portion (191) and a second active portion (192). The first active portion (191) includes a first source region (111). The second active portion (192) includes a second source region (112). A gate structure (150) extends from a first surface (101) into the semiconductor body (100). The gate structure (150) has a longitudinal gate extension (1g) along a first transverse direction (291). A first load pad (311) and the first source region (111) are electrically connected. A second load pad (312) and the second source region (112) are electrically connected. A gap (230) transversely separates the first load pad (311) and the second load pad (312). The longitudinal extension of the gap (230) in the lateral direction is parallel to or deviates from the first direction (291) by no more than 60 degrees. The connection structure (390) electrically connects the first load pad (311) and the second load pad (312). The connection structure (390) is formed in a groove extending from the first surface (101) into the semiconductor body (100) and / or is formed in a wiring layer formed on the first surface (101).

Description

Technical Field

[0001] Examples of this disclosure relate to semiconductor dies having at least two load pads electrically connected to the source region. This disclosure further relates to power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or IGBT (Insulated-Gate Bipolar Transistor) modules.

[0002] IGBTs combine the gate drive characteristics of MOSFETs with the high current and low saturation voltage capabilities of bipolar transistors. In an IGBT module, multiple IGBTs are connected in parallel to achieve a current handling capacity on the order of 100A.

[0003] There is a need for semiconductor dies that can be used efficiently and variably on circuit boards, component groups and / or in IGBT modules. Summary of the Invention

[0004] Embodiments of this disclosure relate to a semiconductor die, including a semiconductor body, a gate structure, a first load pad, a second load pad, and an interconnect structure. The semiconductor body includes a first active portion and a second active portion. The first active portion includes a first source region. The second active portion includes a second source region. The gate structure extends from a first surface into the semiconductor body and has a longitudinal gate extension along a first transverse direction. The first load pad and the first source region are electrically connected. The second load pad and the second source region are electrically connected. A gap laterally separates the first load pad and the second load pad. The longitudinal extension of the gap in the transverse direction is parallel to the first direction or deviates from the first direction by no more than 60 degrees. The interconnect structure electrically connects the first load pad and the second load pad. The interconnect structure is formed in a recess extending from the first surface into the semiconductor body and / or is formed in a wiring layer formed on the first surface.

[0005] Another embodiment of this disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor body, a first load pad, a second load pad, a metal structure, a first load connection structure, and a pad connection structure. The semiconductor body includes a first active portion and a second active portion. The first active portion includes a first source region. The second active portion includes a second source region. The first load pad and the first source region are electrically connected. The second load pad and the second source region are electrically connected. A gap laterally separates the first load pad and the second load pad. The first load connection structure connects the first load pad and the metal structure. The pad connection structure electrically connects the first load pad and the second load pad. The pad connection structure has a longitudinal extension at an angle of at least 45 degrees to the first load connection structure. The pad connection structure contacts the first load pad and the second load pad at a side positioned opposite the semiconductor body.

[0006] Another embodiment of this disclosure relates to an IGBT module. The IGBT module includes a semiconductor device, a metal structure, and a wiring connection structure. The semiconductor device includes a semiconductor body, a first load pad, and a second load pad. The semiconductor body includes a first active portion and a second active portion. The first active portion includes a first source region. The second active portion includes a second source region. The first load pad and the first source region are electrically connected. The second load pad and the second source region are electrically connected. The first load pad and the second load pad are laterally separated. The wiring connection structure electrically connects the first load pad and the second load pad via the metal structure. The wiring connection structure includes bonding wiring. The bonding wiring of the wiring connection structure has an inductance of up to 20 nH.

[0007] Those skilled in the art will recognize the additional features and advantages when reading the following detailed description and when viewing the accompanying drawings. Attached Figure Description

[0008] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of semiconductor dies, semiconductor devices, and IGBT modules, and, together with the description, serve to explain the principles of the embodiments. Further embodiments are described in the following detailed description and claims.

[0009] Figures 1A to 1B The figures illustrate a schematic plan view and a schematic cross-sectional view of a semiconductor die portion according to an embodiment. The semiconductor die portion includes a first load pad and a second load pad on the front side, and a connection structure connecting the first load pad and the second load pad.

[0010] Figures 2A to 2B The figures illustrate a schematic cross-sectional view and a schematic plan view of a semiconductor die portion having a connection structure formed in a trench, according to an embodiment.

[0011] Figures 3A to 3B The illustrations show a schematic cross-sectional view and a schematic plan view of a semiconductor die portion having multiple interconnect structures formed in trenches according to an embodiment.

[0012] Figures 4A to 4B The illustrations show a schematic cross-sectional view and a schematic plan view of a semiconductor die portion having a connection structure extending between two trench electrode structures, according to an embodiment.

[0013] Figures 5A to 5B The illustrations show a schematic cross-sectional view and a schematic plan view of a semiconductor die portion having a connection structure formed in a wiring plane according to an embodiment.

[0014] Figure 6The illustration shows a schematic cross-sectional view of a portion of a semiconductor device including a pad connection structure with bonding wiring, according to an embodiment.

[0015] Figures 7A to 7C The figure shows a schematic plan view of a semiconductor device having a pad connection structure including bonding wiring, according to a further embodiment.

[0016] Figures 8A to 8C The illustration shows a schematic plan view of a portion of an IGBT module according to an embodiment, including a short wiring connection structure between a load pad and a metal structure.

[0017] Figures 9A to 9B The figure shows a portion of an IGBT module having multiple IGBT semiconductor dies according to another embodiment. Detailed Implementation

[0018] In the following detailed description, reference is made to the accompanying drawings, which form part of this document, and which illustrate specific embodiments of semiconductor dies, semiconductor devices, and IGBT modules that can be practiced therein by way of illustration. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. For example, features illustrated or described for one embodiment may be used in other embodiments or combined with other embodiments to produce yet another further embodiment. It is intended that this disclosure include such modifications and variations. Examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Unless otherwise stated, corresponding elements in different drawings are indicated by the same reference numerals.

[0019] The terms “having,” “containing,” “including,” and “including” are open-ended and indicate the presence of the stated structure, element, or feature but do not exclude the presence of additional elements or features. The quantifiers “a,” “one,” and the pronoun “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0020] The term "electrically connected" describes a permanent low-resistance connection between electrically connected components, such as a direct ohmic contact between related components or a low-resistance connection via a metal and / or heavily doped semiconductor material. An ohmic contact is a non-rectified electrical junction with linear or near-linear current-voltage characteristics. The term "electrically coupled" includes one or more intermediate elements adapted for signal and / or power transmission that can be connected between electrically coupled components, such as electrically decoupled elements that can be controlled to temporarily provide a low-resistance connection in a first state and temporarily provide a high-resistance connection in a second state.

[0021] The range given for physical dimensions includes boundary values. For example, the range for parameter y from a to b is read as a≤y≤b. The same applies to ranges with a boundary value such as "at most" and "at least".

[0022] The main components of a layer or structure derived from a chemical compound or alloy are elements whose atoms form the chemical compound or alloy. For example, copper and aluminum are the main components of copper-aluminum alloys.

[0023] The term “on” is not interpreted as meaning “directly on”. Rather, if an element is “on” another element (e.g., a layer is “on” another layer or on a substrate), then a further component (e.g., a further layer) may be located between the two elements (e.g., if a layer is “on” a substrate, then a further layer may be located between that layer and the substrate).

[0024] Regarding the structure and doped regions formed in the substrate, if the minimum distance between the second region and the first substrate main surface at the front side of the substrate is greater than the maximum distance between the first region and the first substrate main surface, then the second region is "below" the first region. The second region is "directly below" the first region, where the vertical projections of the first and second regions onto the first substrate main surface overlap. The vertical projection is orthogonal to the first substrate main surface.

[0025] The Safe Operating Area (SOA) defines the voltage and current conditions under which a semiconductor device can be expected to operate without self-damage. The SOA is given by published maximum values ​​for device parameters such as maximum continuous load current, maximum gate voltage, and others.

[0026] The term "power semiconductor device" refers to a semiconductor device having a high voltage blocking capability of at least 30V (e.g., 100V, 600V, 3.3kV or higher) and a nominal on-state current or forward current of at least 1A (e.g., 10A or higher).

[0027] A semiconductor die includes the semiconductor portion of a semiconductor device and further structures typically formed at the wafer level. For example, a semiconductor die may include front-side metallization on a front side and back-side metallization on a side opposite the front side. The front-side metallization may include one or more metal pads. Load current can flow from the metal pads through the semiconductor die to the back-side metallization or from the back-side metallization to the metal pads.

[0028] A semiconductor device includes at least one semiconductor die and at least one further structure formed after separating the semiconductor die from a wafer composite. For example, the semiconductor device may include the semiconductor die, terminals, and bonding wiring connecting the terminals to metal pads on the semiconductor die.

[0029] According to an embodiment, a semiconductor die may include a semiconductor body having a first active portion including a first source region and a second active portion including a second source region.

[0030] On the front side, the semiconductor body may have a first surface having a flat surface segment that is coplanar in a horizontal plane. On the back side, the semiconductor body may have a flat second surface that may be substantially parallel to the first surface. Side surface regions may connect the edges of the first and second surfaces. The horizontal cross-section of the semiconductor body may be polygonal, for example, approximately rectangular. For example, the semiconductor body may have the shape of a regular polygonal (e.g., rectangular or hexagonal) prism with or without rounded edges. The first surface may extend laterally along a plane spanned by a lateral direction and may have a thickness along a vertical direction perpendicular to the lateral direction. The vertical extension or thickness of the semiconductor body may range from 20 μm to 700 μm.

[0031] The semiconductor body may include single-crystal semiconductor materials such as silicon (Si), germanium (Ge), and silicon-germanium (SiGe). In addition to the main components, the semiconductor body may also include dopant atoms such as phosphorus (P), boron (B), and / or arsenic (As). The semiconductor material may include further impurities such as hydrogen (H), fluorine (F), and / or oxygen (O).

[0032] The semiconductor body may include a first active portion and a second active portion. The first and second active portions are defined in a horizontal plane and extend from a first surface to a second surface. The first and second active portions are laterally separated from each other. The semiconductor body may include more than two active portions, such as four, six, or eight active portions, wherein each active portion is laterally separated from an adjacent active portion.

[0033] The active portion conducts at least a major portion of the load current, such as the collector current of an IGBT. Each active portion includes a surface portion of a first surface where the load current enters or exits the semiconductor body, for example, via a load contact structure. The surface area of ​​each active portion may be defined by a minimum convex polygon or minimum rectangle comprising all load contact structures assigned to the respective active portion. Alternatively, the surface area may be defined by an area in which the load pads are in direct contact with the semiconductor body. Each active portion may have a rectangular or approximately rectangular shape in a horizontal plane. Passive portions of the semiconductor body may laterally separate adjacent active portions and may laterally separate active portions from side surface areas. Passive portions do not contain load contact structures. The minimum distance between two load contact structures of two adjacent active portions is at least twice, for example, at least ten times, the average distance between two adjacent load contact structures in the same active portion.

[0034] The source region is the heavily doped region of the first conductivity type within the semiconductor body. In addition to the source region, each active portion may also include further doped regions, which, among other things, include the semiconductor portion of the insulated-gate FET (field-effect transistor) used for the control portion of the IGBT.

[0035] The gate structure can extend from the first surface into the semiconductor body. The gate structure can have a longitudinal gate extension along a first transverse direction and a gate width along a second transverse direction orthogonal to the first direction. The longitudinal gate extension is greater than the gate width, for example, at least ten times the gate width. The gate structure can include a conductive gate electrode and a gate dielectric separating the gate electrode from the semiconductor body.

[0036] A semiconductor die may include a plurality of parallel gate structures. For example, a first plurality of gate structures may extend at least from one side of a first active portion to an opposite side, and a second plurality of gate structures may extend from one side of a second active portion to an opposite side.

[0037] The semiconductor die may include a first load pad electrically connected to a first source region. The first load pad may be in direct contact with a first surface, wherein the first load pad and the first source region may form a low-resistance ohmic contact. Alternatively, a first load contact structure may extend vertically from the first load pad to or into the semiconductor body, wherein the first load contact structure and the first source region form a low-resistance ohmic contact. The first load contact structure may extend through the interlayer dielectric between the first load pad and the semiconductor body.

[0038] The semiconductor die may include a second load pad electrically connected to a second source region. The second load pad may be in direct contact with the first surface, wherein the second load pad and the second source region can form a low-resistance ohmic contact. Alternatively, a second load contact structure may extend vertically from the second load pad through an interlayer dielectric into or into the semiconductor body, wherein the second load contact structure and the second source region form a low-resistance ohmic contact.

[0039] When the semiconductor die is in the ON state, a portion of the load current enters or leaves the semiconductor die through the first load pad and the second load pad. The load pad can be the front emitter pad of the IGBT. The load current can flow from the first and second load pads on the front side through the semiconductor body to the second surface on the back side of the semiconductor body, or in the opposite direction.

[0040] The gap can laterally separate the first load pad and the second load pad. The longitudinal extension of the gap in the lateral direction can be parallel to a first direction, or it can deviate from the first direction in a horizontal plane by no more than 60 degrees, 45 degrees, or 30 degrees. For example, the gap can travel parallel to or nearly parallel to the gate structure. The connection structure electrically connects the first load pad and the second load pad. The connection structure can be formed in a groove extending from the first surface into the semiconductor body. Alternatively or additionally, the connection structure can be formed in a wiring layer formed on the first surface. For example, a portion of the interlayer dielectric can be formed between the connection structure and the semiconductor body, and the connection structure can be separated from the semiconductor body.

[0041] Load pads arranged in a transverse direction orthogonal to the longitudinal direction of the gate structure can be decoupled to some extent at the die level. In other words, the load pads can be electrically isolated at the die level, or they can be electrically connected only through a path with relatively high impedance, such as through a moderately doped region in the semiconductor body. Decoupling may cause the load pads to have slightly different potentials in operating modes. During certain operating states, such as in a short-circuit state, decoupling can promote and / or amplify oscillations in at least a portion of the load current path of the semiconductor die. The connection structure directly connects the first and second load pads at the die level. The impedance of the connection structure can be selected independently of other parameters of the semiconductor die, such as the doping concentration in the doped region in the connection path between the first and second load pads. The impedance of the connection structure can be selected to suppress and / or dampen oscillations without adversely affecting other device characteristics.

[0042] For example, the impedance can be selected such that during the operation of the semiconductor die within the SOA, the maximum potential difference between the first and second load pads is below a critical level. The resistance of the connection structure can be up to 100 mΩ. For example, the resistance can be up to 10 mΩ or up to 1 mΩ. According to another example, the inductance of the connection structure can be up to 20 nH or up to 2 nH. By way of example, the connection structure can combine a resistance of up to 100 mΩ and an inductance of up to 20 nH, a resistance of up to 10 mΩ and an inductance of up to 20 nH, a resistance of up to 10 mΩ and an inductance of up to 2 nH, or a resistance of up to 1 mΩ and an inductance of up to 2 nH. According to a further example, the damping constant of the connection structure can be in the range from 0.1 mΩ / nH to 20 mΩ / nH, for example, in the range from 0.5 mΩ / nH to 5 mΩ / nH.

[0043] Connecting the first and second load pads at the die level provides greater flexibility in how the semiconductor die can be electrically connected to device terminals or to other devices and / or conductive structures within sub-assemblies (e.g., IGBT modules). For example, providing a connection structure at the die level facilitates the connection to the first and second load pads, and the extension wiring carrying the load current can extend parallel to the gate structure. In particular, the connection structure can be combined with load pads comprising a copper base and load extension wiring traveling parallel to the gate structure without increasing the tendency for oscillation.

[0044] According to an embodiment, the connection structure may include a trench connection structure extending into the semiconductor body. For example, the trench connection structure may extend from a first surface into the semiconductor body. The trench connection structure may include a conductive portion and an insulating portion. The insulating portion may separate the conductive portion from the semiconductor body.

[0045] Trench connection structures can be efficiently formed at the wafer level by at least partially using processes that define and form gate structures or other trench structures. The formation of the trench connection structure and the formation of the gate structure and / or other trench structures can share one or more processes. For example, a single trench etch mask can define the gate structure and / or further trench structures and trench connection structures. A single trench etch process can simultaneously form trenches for the gate structure and / or further trench structures, as well as one or more trenches for the connection structure. The insulating portion of the trench connection structure can be formed by using at least some of the processes applied to form the gate dielectric. For example, a single deposition process or a single oxidation process can form at least a portion of the gate dielectric and / or additional trench dielectric and the insulating portion of the trench connection structure. The conductive portion of the trench connection structure can be formed by using at least one of the processes for forming the gate electrode and / or passive trench electrode. For example, a further single deposition and / or patterning process can form the gate electrode and / or passive trench electrode, as well as the conductive portion of the trench connection structure.

[0046] Furthermore, forming interconnect structures in trenches can have only a low impact on area efficiency or no negative impact at all. For example, the interconnect structures can be formed primarily or entirely outside any active portion. For instance, a trench interconnect structure between a first load pad and a second load pad can be exclusively formed in the portion of the semiconductor body that separates the first and second active portions.

[0047] The conductive portion of the trench connection structure may include doped polysilicon, allowing the impedance of the trench connection structure to be finely tuned by adjusting the doping concentration and geometry of the trench connection structure.

[0048] According to an embodiment, the longitudinal extension of the trench connection structure can travel parallel to the longitudinal extension of the gap. The resistance and / or inductance of the trench connection structure can be quite low. Under any operating condition, the potential distribution across the first load pad and the second load pad can be quite uniform.

[0049] According to another embodiment, the longitudinal extension of the trench connection structure may be inclined at, for example, at least 30 degrees, relative to the longitudinal extension of the gap. For example, the longitudinal extension of the trench connection structure may be orthogonal to the longitudinal extension of the gap. For example, the longitudinal extension may be orthogonal to the longitudinal extension of the gap and to the longitudinal extension of the gate structure.

[0050] According to an embodiment, the connection structure may include multiple trench connection structures. For example, the connection structure may include multiple trench connection structures that travel orthogonally to the longitudinal extension of the gap. The trench connection structures can be efficiently configured to have approximately the same width as the gate structure and / or further trench structures.

[0051] According to an embodiment, the semiconductor die may include a passive trench electrode extending into the semiconductor body. A trench dielectric may electrically decouple the passive trench electrode from the semiconductor body. The passive trench electrode may be electrically connected to a predetermined potential. For example, the passive trench electrode may be a source trench electrode electrically connected to the potential of the emitter load pad of an IGBT or power MOSFET.

[0052] Passive trench electrodes and trench dielectrics form a passive trench structure. A semiconductor die may include multiple parallel passive trench structures. For example, multiple first passive trench structures may extend from at least one side of a first active portion to an opposite side, and multiple second passive trench structures may extend from one side of a second active portion to an opposite side.

[0053] The groove connection structure can be efficiently integrated with the passive groove structure. The groove connection structure, the first passive groove structure closest to the gap, and the second passive groove structure closest to the gap can form a ladder-like structure, wherein the first passive groove structure closest to the gap and the second passive groove structure closest to the gap form a horizontal bar, and the groove connection structure forms a ladder.

[0054] According to an embodiment, the gap between the first load pad and the second load pad may have a gap width extending along a direction orthogonal to the longitudinal direction of the gap. For example, the gap width may be obtained along a second transverse direction orthogonal to the first direction. The gap width may be at least 2 μm. For example, the gap between the first load pad and the second load pad does not contain any further conductive structure above the first surface, and the gap width may be at least 2 μm. According to another example, a further conductive structure is formed in the gap on the semiconductor body, wherein the gap width is at least 10 μm. For example, a portion of a metal gate wiring may be formed on the first surface in the gap.

[0055] According to an embodiment, the connecting structure may have a maximum extension along the gap width (in other words, an extension orthogonal to the longitudinal direction of the gap). The maximum extension of the connecting structure may be at most ten times the gap width, for example, at most twice the gap width.

[0056] According to another embodiment, the connection structure may include a connecting line. The connecting line may be formed on a first surface of the semiconductor body. The connecting line may be formed outside the gap. The connecting line may be separable from the semiconductor body. For example, a portion of an interlayer dielectric structure may separate the connecting line from the semiconductor body.

[0057] For example, the interconnect may include a main portion extending parallel to the outer edge of the first surface in an edge portion of the semiconductor body, wherein the edge portion separates the active portion from the side surface region. A further portion of the interconnect may extend laterally from the main portion below the first and second load pads. Vertical vias may electrically connect the first and second load pads to the further portion of the interconnect. Alternatively or additionally, one or more passive first trench electrodes and one or more passive second trench electrodes may extend below the interconnect, and vertical vias may electrically connect the respective passive trench electrodes to the interconnect. The interconnect may have the sole purpose of connecting the first and second load pads.

[0058] According to an embodiment, a semiconductor die includes a first passive trench electrode extending from a first surface into a first active portion. A first trench contact structure electrically connects a first load pad to the first passive trench electrode. The first trench contact structure extends vertically through an interlayer dielectric between the first load pad and the first passive trench electrode. A semiconductor die may include a second passive trench electrode extending from a first surface into a second active portion. A second trench contact structure electrically connects a second load pad and the second passive trench electrode. The second trench contact structure extends vertically through an interlayer dielectric between the second load pad and the semiconductor body.

[0059] Source interconnects can be formed on a first surface between the active portion and the side surface region. The source interconnects and a first passive trench electrode can be electrically connected. For example, a via can extend vertically from the source interconnects to the first passive trench electrode. The source interconnects and a second passive trench electrode can be electrically connected. For example, a via can extend vertically from the source interconnects to the second passive trench electrode.

[0060] The connection structure may include a sub-section of a source interconnect, wherein the sub-section extends from a first passive trench electrode closest to the gap to a second passive trench electrode closest to the gap. The connection structure can be efficiently formed by modifying the existing layout.

[0061] According to embodiments, the semiconductor body may further include a drift region, a body region, and a collector region. The drift region may include a relatively lightly doped drift band of a first conductivity type. The drift band may extend horizontally through the entire semiconductor body or almost through the entire semiconductor body. The dopant distribution and vertical extension of the drift band are designed to withstand at least a major portion of the nominal blocking voltage of the semiconductor die. Alternatively, or in addition to the drift band, the drift region may include a compensation structure, such as a superjunction structure, wherein the superjunction structure may include a plurality of p-doped pillars and n-doped pillars, wherein the p-doped pillars and n-doped pillars form a vertical pn junction, and wherein in the horizontal cross-section of the superjunction structure, the surface integral across the p-dopant concentration deviates from the surface integral across the n-dopant concentration by no more than 20%, for example, no more than 5%.

[0062] The first body region in the first active portion can form a first pn junction with the drift structure and a second pn junction with the first source region. The second body region in the second active portion can form a further first pn junction with the drift structure and a further second pn junction with the second source region.

[0063] The collector region may have a second conductivity type, or may include several laterally separated bands of the second conductivity type. The collector region and the drift region may form one or more third pn junctions. The drift region is formed between the collector region on one side and the body region on the opposite side. The drift region can separate the collector region on one side and the body region on the opposite side.

[0064] The drift region may include further doped regions of two conductivity types. For example, the drift region may include an intermediate band of a first conductivity type between the bulk region and the drift region band. The intermediate band may separate at least a portion of the bulk region band from the drift region band. The maximum dopant concentration in the intermediate band may be at least twice the minimum dopant concentration in the drift region band. For example, the maximum dopant concentration in the intermediate band may be at least ten times the minimum dopant concentration in the drift region band.

[0065] The drift region may include a buffer layer of a first conductivity type on a side opposite the body region. The buffer layer can separate the drift region band and the collector region. The maximum dopant concentration in the buffer layer may be at least twice the minimum dopant concentration in the drift region band. For example, the maximum dopant concentration in the buffer layer may be at least ten times the minimum dopant concentration in the drift region band. The drift region may include an intermediate region of a second conductivity type. Each intermediate region may be formed along or near one of the gate structures. The intermediate regions can separate at least a portion of the body region band from the drift region band. The drift region band and each intermediate region may form one or more pn junctions.

[0066] According to embodiments, the semiconductor device may include any of the semiconductor dies described above. The semiconductor device may further include a first load terminal, a gate terminal, and a second load terminal. The first load terminal may be electrically connected or coupled to a first load pad and a second load pad, for example, via metal clamps and / or bonding wiring (e.g., circular bonding wiring or strip bonding wiring). The second load terminal may be electrically connected or coupled to a back-side metallization formed on a second surface of the semiconductor body, for example, via a solder layer. The back-side metallization and the collector region may form a low-resistance ohmic contact. The gate terminal may be electrically connected or coupled to a gate pad, for example, via bonding wiring. The gate pad may be electrically connected or coupled to a gate electrode in the gate structure. The semiconductor device may be a reverse-blocking IGBT or a reverse-conducting IGBT.

[0067] According to an embodiment, a semiconductor device may include a semiconductor body, a first load pad, a second load pad, a metal structure, a first load connection structure, and a pad connection structure.

[0068] The semiconductor body may include a first active portion and a second active portion. The first active portion may include a first source region. The second active portion may include a second source region. A first load pad and the first source region may be electrically connected. A second load pad and the second source region may be electrically connected. A gap may laterally separate the first load pad and the second load pad. A first load connection structure may connect the first load pad and a metal structure. A pad connection structure may electrically connect the first load pad and the second load pad. The connection structure may have a longitudinal extension at an angle of at least 45° to the first load connection structure. The connection structure may contact the first load pad and the second load pad at a side positioned opposite the semiconductor body.

[0069] The connection structure directly connects the first and second load pads. The impedance of the connection structure can be selected independently of other routing connections between the load pads and further structures. The impedance of the connection structure can be selected to suppress and / or dampen oscillations—oscillations that may occur in at least a portion of the load current path under certain operating conditions—without adversely affecting other routing parameters.

[0070] The gate structure can extend from the first surface into the semiconductor body. The gate structure can have a longitudinal gate extension along the lateral direction. The longitudinal gate extension can have an angle of less than 45 degrees relative to the longitudinal extension of the first load connection structure. The longitudinal gate extension is greater than a gate width orthogonal to the longitudinal gate extension, for example, at least ten times the gate width. The gate structure can include a conductive gate electrode and a gate dielectric separating the gate electrode from the semiconductor body. The semiconductor die can include multiple parallel gate structures.

[0071] According to an embodiment, the first load connection structure may include at least one load bonding wire. For example, the first load connection structure may include at least two load bonding wires, such as four, five, or six load bonding wires. All load bonding wires of the first load connection structure may be arranged in electrical parallel. All load bonding wires of the first load connection structure may be of the same type, the same material, and / or the same cross-sectional area. For example, the load bonding wires may be circular bonding wires or strip bonding wires.

[0072] At least above the first load pad, the load connection structure (e.g., one or more bonding wires) may extend approximately parallel to the longitudinal extension of the gap. The load connection structure may travel parallel to or approximately parallel to the gate structure formed in the semiconductor body. The load connection structure may further contact the top surface of the third load pad of the semiconductor device. The connection structure may at least partially compensate for the effects on oscillations in the load current path that may be caused by the inductance and / or resistance of the load bonding wires.

[0073] According to an embodiment, the pad connection structure may include bonding traces that directly contact a first load pad and a second load pad. The bonding traces may be circular bonding traces or strip bonding traces. The bonding traces may be attached to the exposed top surfaces of the first load pad and the second load pad. The pad connection structure can be provided efficiently by moderately modifying the wiring bonding process.

[0074] According to an embodiment, the semiconductor device may further include a second load connection structure connecting the second load pad and the metal structure. The second load connection structure may include at least one load bonding trace. For example, the second load connection structure may include two, four, five, or six load bonding traces. All load bonding traces of the second load connection structure may be electrically connected in parallel. All load bonding traces of the second load connection structure may be of the same type, the same material, and / or the same cross-sectional area. For example, the load bonding traces may be circular bonding traces or strip bonding traces.

[0075] The first load connection structure and the second load connection structure can be separate. The first load connection structure and the second load connection structure can be different entities. The first load connection structure and the second load connection structure can be made of the same material or can be made of different materials.

[0076] According to an embodiment, the electrical path of the connection structure is at least 50% shorter than the electrical path formed between the first load pad and the second load pad through the first load connection structure, the metal structure, and the second load connection structure.

[0077] According to an embodiment, the IGBT module may include at least one of the semiconductor devices and semiconductor dies described above.

[0078] According to an embodiment, an IGBT module may include a semiconductor die, a metal structure, and a wiring connection structure. The semiconductor die may include a semiconductor body, a first load pad, and a second load pad. The semiconductor body may include a first active portion and a second active portion. The first active portion may include a first source region. The second active portion may include a second source region. The first load pad and the first source region may be electrically connected. The second load pad and the second source region may be electrically connected. The first load pad and the second load pad are laterally separated. The wiring connection structure may connect the first load pad and the second load pad via the metal structure. The wiring connection structure may include bonding wiring. The bonding wiring of the wiring connection structure may have an inductance of up to 5nH (e.g., up to 2nH) and / or at least 5*10 5 s -1 The total damping constant (R / 2L) is (5E5 1 / s). The inductance of the wiring connection structure can be low enough to efficiently suppress oscillations in parts of the load current path and / or dampen oscillations in parts of the load current path.

[0079] The gate structure can extend from the first surface into the semiconductor body. The gate structure can have a longitudinal gate extension along the lateral direction. The longitudinal gate extension can have an angle of less than 45 degrees relative to the length of the wiring connection structure. The longitudinal gate extension is greater than the gate width orthogonal to the longitudinal gate extension, for example, at least ten times the gate width. The gate structure can include a conductive gate electrode and a gate dielectric separating the gate electrode from the semiconductor body. The semiconductor die can include multiple parallel gate structures.

[0080] According to an embodiment, the metal structure may include at least one of a load current plate, a Kelvin support structure, and electrode pads for a further semiconductor device. By way of example, the further semiconductor device may be a power semiconductor diode electrically connected in anti-parallel to a semiconductor die. For example, the lateral distance between the semiconductor die and the load current plate, the lateral distance between the semiconductor die and the Kelvin support structure, and / or the lateral distance between the semiconductor die and the further semiconductor device is at most 2 mm, for example, for a semiconductor device having a blocking capability of up to 1200 V.

[0081] According to an embodiment, the joint wiring of the wiring connection structure can have an inductance of up to 1nH.

[0082] Figures 1A to 1BThe figure shows a portion of a semiconductor die 510, which includes a connection structure 390 at the front side of the semiconductor die 510 electrically connecting a first load pad 311 and a second load pad 312.

[0083] Semiconductor die 510 may be a bare die of an IGBT (e.g., a reverse blocking IGBT or an RC-IGBT (reverse conducting IGBT)). The semiconductor body 100 of semiconductor die 510 may be formed primarily of a single-crystal semiconductor material, such as silicon (Si), germanium (Ge), silicon-germanium crystal (SiGe), silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs) by way of example.

[0084] The semiconductor body 100 has a first surface 101 on its front side. The semiconductor body 100 may have a rectangular shape in a horizontal plane parallel to the first surface 101. The normal to the first surface 101 defines a vertical direction, and the direction orthogonal to the vertical direction is the lateral direction. The semiconductor body 100 may include active portions 191, 192, 193, 194 defined side-by-side in the horizontal plane. The active portions 191, 192, ... are laterally separated from each other. For example, the active portions 191, 192, ... may be regularly arranged in rows and columns. A grid-like passive portion 180 laterally separates the active portions 191, 192, ... from each other and laterally separates the active portions 191, 192, ... from the side surface regions 103 at the edges of the semiconductor body 100.

[0085] In the active portions 191, 192, ..., the semiconductor body 100 includes a semiconductor portion controlling the IGBT, similar to an IGBT structure. Among other things, the first active portion 191 also includes a first source region 111 of a first conductivity type. The second active portion 192 also includes a second source region 112 of the first conductivity type. The third active portion 193 includes a third source region of the first conductivity type. The fourth active portion 194 includes a fourth source region of the first conductivity type. The source regions 111, 112, ... can extend from the first surface 101 into the semiconductor body 100. By way of example, the first conductivity type can be n-type. Alternatively, the first conductivity type can be p-type.

[0086] Gate structure 150 extends from first surface 101 into semiconductor body 100. Gate structure 150 has a longitudinal gate extension along a first transverse direction 291. Gate structure 150 may extend laterally from one side of active portions 191, 192 to the opposite side, and may extend laterally into passive portions 180 on both sides. Each gate structure 150 may extend laterally through two active portions 191, 193, 192, 194 arranged along the first direction 291 and through a segment (not shown) of passive portion 180 between two associated active portions 191, 193, 192, 194. Each source region 111, 112, ... may directly adjoin one or more gate structures 150.

[0087] The gate structure 150 may include a gate electrode 155 and a gate dielectric 159 separating the gate electrode 155 from the semiconductor body 100. The gate electrode 155 may be a uniform structure or may have a layered structure including one or more conductive layers. For example, the gate electrode 155 may include heavily doped polycrystalline silicon and / or metal elements or metal composites. The gate dielectric 159 may include a semiconductor oxide (e.g., thermally grown or deposited silicon oxide), a semiconductor nitride (e.g., deposited or thermally grown silicon nitride), a semiconductor oxide oxynitride (e.g., silicon oxynitride), and / or a stack of dielectric layers including ferroelectric materials (such as hafnium oxide HfO2 or BaTiO3).

[0088] Load pads 311, 312, ... are positioned on each active portion 191, 192, ... For example, a first load pad 311 is formed on a first active portion 191, a second load pad 312 is formed on a second active portion 192, and so on. Each load pad 311, 312, ... may have the same horizontal cross-sectional shape as the corresponding active portion 191, 192, ... The horizontal cross-sectional area of ​​each load pad 311, 312, ... may be equal to or greater than the horizontal cross-sectional area of ​​the corresponding active portion 191, 192, ... Each load pad 311, 312, ... is electrically connected at least to the source region 111, 112, ... of the corresponding active portion 191, 192, ... The load pads 311, 312, ... are separated from the gate electrode 155.

[0089] Load pads 311, 312, ... may include aluminum or copper as the sole main component or as one of several main components. For example, load pads 311, 312, ... may include copper alloys (e.g., copper-aluminum alloys (CuAl) with or without silicon (Si)) or aluminum alloys (e.g., AlSi or AlSiCu).

[0090] Gap 230 laterally separates the first load pad 311 and the second load pad 312. Gap 230 has a longitudinal extension parallel to the first direction 291. Connection structures 3901 and 3902 electrically connect the first load pad 311 and the second load pad 312. Connection structures 3901 and 3902 may include portions formed in trenches extending into the semiconductor body 100 and / or portions formed in wiring layers on the first surface 101.

[0091] Figures 2A to 2B This relates to an embodiment including a grooved connection structure 391. Figures 2A to 2B Details of an IGBT with a passive electrode trench structure 160 are also shown.

[0092] Figure 2A A semiconductor body 100 is shown having a first surface 101 on the front side and a second surface 102 on the back side. The first surface 101 and the second surface 102 are approximately parallel. The minimum distance between the first surface 101 and the second surface 102 depends on the voltage blocking capability specified for the semiconductor die 510. For example, for a silicon (Si) based semiconductor die 510 specified for a blocking voltage of approximately 1200V, the distance between the first surface 101 and the second surface 102 can range from 90μm to 120μm. Other embodiments relating to semiconductor dies with greater blocking capabilities may provide a semiconductor body 100 with a thickness of several hundred micrometers. For semiconductor dies with lower blocking voltages, the thickness for silicon (Si) can range from 35μm to 90μm.

[0093] Semiconductor body 100 includes drift region 130, source regions 111, 112, body regions 121, 122, and collector region 140. Drift region 130 may include a relatively lightly doped drift band 131 of a first conductivity type. The drift band may extend horizontally through the entire semiconductor body 100 or almost through the entire semiconductor body 100. The drift band forms a voltage sustaining layer. The dopant distribution and vertical extension of drift band 131 are selected to withstand at least a major portion of the nominal blocking voltage of semiconductor die 510. The dopant concentration in drift band 131 may gradually or progressively increase or decrease with increasing distance from the first surface 101, at least in its vertically extended portion. According to other embodiments, the dopant concentration in drift band 131 may be approximately uniform. For silicon-based IGBT dies, the average dopant concentration in drift band 131 may be 5 × 10⁻⁶. 12 (5E12) cm -3 and 1×10 15 (1E15) cm -3 Between, for example, in the range from 1×10 13(1E13) cm -3 Up to 1×10 14 (1E14) cm -3 Within the range. Between the drift region 131 and the collector region 140, the drift region 130 may include a buffer layer 139 of a first conductivity type. The buffer layer 139 can separate the drift region 131 and the collector region 140. The maximum dopant concentration in the buffer layer 139 may be at least twice as high as the maximum dopant concentration in the drift region 131.

[0094] The first body region 121 forms a first pn junction with the drift region 130 and a second pn junction with the first source region 111. The first body region 121, the first source region 111, and the first load pad 311 can be electrically connected. The second body region 122 can form a further first pn junction with the drift region 120 and a further second pn junction with the second source region 112. The second body region 122, the second source region 112, and the second load pad 312 can be electrically connected.

[0095] Collector region 140 is configured to act as a back-side emitter. For non-reverse-conducting IGBTs (e.g., standard IGBTs with reverse blocking capabilities significantly lower than forward blocking capabilities) or RC-IGBTs with forward and reverse blocking capabilities within the same order of magnitude, collector region 140 can be a continuous layer of a second conductivity type. For RC-IGBTs, collector region 140 can include a first band of a first conductivity type and a second band of a second conductivity type. The first and second bands are arranged alternately, for example, along a horizontal direction. Collector region 140 (or the first and second bands of RC-IGBT collector region 140) and back-side metallization 320 form an ohmic contact. The maximum dopant concentration in collector region 140 can be at least 1 × 10⁻⁶. 16 (1E16) cm -3 For example, at least 5×10 17 (5E17) cm -3 .

[0096] The semiconductor body 100 may also include advanced IGBT cell design elements, such as various trenches with different functions, i.e., some trench electrodes are connected to the gate potential, and some trench electrodes are connected to other potentials (such as load terminals) or even remain floating. A hole blocking layer of the same conductivity type as the source region may also be implemented between the body region and the drift region to improve device characteristics. Alternatively or additionally, a floating blocking region of the same conductivity type as the body region may be implemented in the semiconductor body 100, for example, a floating blocking region forming a pn junction with a portion of the drift region 131.

[0097] in particular, Figures 2A to 2BA passive trench structure 160 is shown extending from the first surface 101 into the semiconductor body 100. The passive trench structure 160 may be a strip structure extending parallel to the gate structure 150.

[0098] The passive trench structure 160 may include a passive trench electrode 165 and a trench dielectric 169 separating the passive trench electrode 165 from the semiconductor body 100. The passive trench electrode 165 may be a homogeneous structure or may have a layered structure including one or more conductive layers. For example, the passive trench electrode 165 may include a heavily doped polysilicon layer. The passive trench electrode 165 and the gate electrode 155 may have the same configuration and may include the same material.

[0099] The trench dielectric 169 may include a semiconductor oxide (e.g., thermally grown or deposited silicon oxide), a semiconductor nitride (e.g., deposited or thermally grown silicon nitride), or a semiconductor oxide nitride (e.g., silicon oxynitride). The trench dielectric 169 and the gate dielectric 159 may have the same configuration and / or may include the same material.

[0100] Gate structures 150 and passive trench structures 160 can alternate in a regular manner. For example, a single passive trench structure 160 can be arranged between each pair of gate structures 150. According to other embodiments, two, three, or more passive trench structures 160 can be arranged between each pair of gate structures 150. According to other embodiments, passive trench structures can be omitted, and the semiconductor die 510 can exclusively include gate structures 150.

[0101] The gate electrode 155 can be electrically connected to the metal gate wiring 330 formed on the front side of the semiconductor body 100. The passive trench electrode 165 is electrically isolated from the gate electrode 155. The passive trench electrode 165 can be electrically connected to an auxiliary structure or can be electrically floating. According to the illustrated embodiment, the passive trench electrodes 165 of the active portions 191, 192, ... are electrically connected to the load pads 311, 312, ... allocated to the active portions 191, 192, ... in which the passive trench electrodes 165 are formed.

[0102] The gap 230 between the first load pad 311 and the second load pad 312 may have a longitudinal axis parallel to the first direction 291. In other words, the longitudinal extension of the gap 230 may be parallel to the gate structure 150. The gap 230 has a gap width wg along a second direction 292 orthogonal to the first direction 291.

[0103] The trench connection structure 391 includes a conductive portion 395 and an insulating portion 399 that separates the conductive portion 395 from the semiconductor body 100. The trench connection structure 391 may be formed symmetrically with respect to a central plane in the center of the gap 230 and extends along a first direction 291. A portion of the metal gate wiring 330 may be formed in the gap 230 on the first surface 101. A portion of the interlayer dielectric 210 separates the metal gate wiring 330 from the conductive portion 395 of the trench connection structure and from the semiconductor body 100. The interlayer dielectric 210 further separates the load pads 311, 312 from the gate electrode 155 in the gate structure 150.

[0104] The first load contact structure 318 vertically connects the first load pad 311 to the first source region 111, the first body region 121, and the passive trench electrode 165 in the first active portion 191. The second load contact structure 319 vertically connects the second load pad 312 to the second source region 112, the second body region 122, and the passive trench electrode 165 in the second active portion 192.

[0105] The via 398 vertically connects the first load pad 311 and the conductive portion 395 of the connection structure, and also vertically connects the second load pad 312 and the conductive portion 395 of the connection structure. The lateral extension lc of the trench connection structure 391 along the second direction 292 is greater than the gap width wg, and less than the distance between the trench structure 150, 160 closest to the gap 230 in the first active portion 191 and the trench structure 150, 160 closest to the gap 230 in the second active portion 192.

[0106] Figures 3A to 3B A connection structure 390 is shown, comprising a plurality of trench connection structures 391 oriented parallel to each other. In the illustrated embodiment, the trench connection structures 391 are oriented such that their longitudinal axes are orthogonal to the longitudinal extension of the gate structure 150. The trench connection structures 391 and the gate structure 150 may have the same width and / or may have the same vertical extension. According to another embodiment (not shown), the angle between the longitudinal axis of the trench connection structure 391 and the second direction 292 may be 45 degrees or less, for example, 30 degrees.

[0107] exist Figures 4A to 4B In this configuration, each trench connection structure connects the passive trench structure 160 of the first active portion 191 closest to the gap 230 to the passive trench structure 160 of the second active portion 192 closest to the gap 230. The conductive portion 395 of the connection structure 390 and the passive trench electrode 165 are directly connected.

[0108] Between the passive trench structure 160 closest to the gap 230 in the first active portion 191 and the passive trench structure 160 closest to the gap 230 in the second active portion 192, the semiconductor body 100 does not contain a gate structure 150. The trench connection structure 391 and the passive trench structure 160 may have the same width and / or may have the same vertical extension.

[0109] The trench connection structure 391 and the first passive trench structure 160 on each side of the gap 230 can form a ladder-like structure, wherein the closest passive trench structure 160 in the first active portion 191 and the closest passive trench structure 160 in the second active portion 192 form a horizontal bar, and wherein the trench connection structure 391 forms a ladder.

[0110] Figures 5A to 5B A connection structure 390 is shown, including a connection line 392 formed in a wiring layer on the front side of the semiconductor body 100. The connection line 392 is formed on the semiconductor body 100 and outside the gap 230. For example, the connection line 392 is formed on a passive portion 180 between the side surface region 103 of the semiconductor body 100 and the first active portion 191 and the second active portion 192. A passive trench structure 160 extends laterally from the active portions 191, 192 below the connection line 392. A via 397 vertically connects the connection line 392 and the passive trench electrode 165.

[0111] The connecting line 392 may be a portion of the source channel 317 extending along the second lateral direction 292 of the active portions 191, 192 between the active portions 191, 192 and the side surface region 103. According to another embodiment, the connecting line 392 may be shorter than the extension of the active portions 191, 192 along the second direction, for example, at most ten times or twice the gap width wg.

[0112] Figure 6 The pad connection structure 390 of the semiconductor device 500 includes one or more bonding wires 393 attached to the exposed top surfaces of the first load pad 311 and the second load pad 312. The bonding wires 393 bridge gaps 230. A first load connection structure 315 electrically connects the first load pad 311 to a terminal and / or to another metal structure (not shown). The first load connection structure 315 may include a plurality of parallel bonding wires 394 extending approximately parallel to or slightly inclined to the longitudinal direction of the gate trench 150. A second load connection structure 316 connects the second load pad 312 to a terminal and / or to another metal structure. The second load connection structure 316 may include a plurality of parallel bonding wires 394 extending approximately parallel to or slightly inclined to the longitudinal direction of the gate structure 150.

[0113] The electrical path of the bonding wiring 393 is at least 50% shorter than the electrical path formed between the first load pad 311 and the second load pad 312 through the first load connection structure 315, the terminal or metal structure and the second load connection structure 316.

[0114] Figures 7A to 7C A semiconductor device 500 with a semiconductor die 510 is shown. The semiconductor die 510 includes: a first load pad 311 electrically connected to a first source region in a first active portion 191; a second load pad 312 electrically connected to a second source region in a second active portion 192; a third load pad 313 electrically connected to a third source region in a third active portion 193; and a fourth load pad 314 electrically connected to a fourth source region in a fourth active portion 194. A gate structure (not shown) extends parallel to a first direction 291.

[0115] Each semiconductor device 500 further includes a first load connection structure 315 that electrically connects the third load pad 313 and the first load pad 311 to terminals and / or to other metal structures. The first load connection structure 315 may include a plurality of bonding wires 394. The bonding wires may be circular bonding wires or strip bonding wires. A second load connection structure 316 connects the fourth load pad 314 and the second load pad 312 to terminals and / or to other metal structures. The second load connection structure 316 may include a plurality of bonding wires. On the semiconductor die 510, for example between bonding contacts on the load pads 311, 312, 313, 314, the bonding wires 394 may extend approximately parallel to or slightly inclined to the longitudinal direction of the gate trench structure in the semiconductor die 510.

[0116] The metal gate wiring 330 of the semiconductor die 510 may include a gate pad in the lateral center of the semiconductor die 510. According to another embodiment, the gate pad may be positioned along the edge of the semiconductor body 100 or located in a corner of the semiconductor body 100. The gate bonding wiring 335 can electrically connect the gate pad to the gate terminal of the semiconductor device or to the gate metal line of the IGBT module.

[0117] Figure 7A A pad connection structure 393 is shown, including a bonding line across the gate bonding line 335 below or above. The pad connection structure 393 may be formed near the edge of the semiconductor body 100 opposite the edge spanned by the first load connection structure 315 and the second load connection structure 316.

[0118] exist Figure 7BIn this configuration, the pad connection structure 393 includes bonding wiring that does not cross below or above the gate bonding wiring 335. The pad connection structure 393 may be formed near the edge of the semiconductor body 100 crossed by the first load connection structure 315 and the second load connection structure 316.

[0119] exist Figure 7C In the process, the pad connection structure 393 includes a first bonding wire that does not cross the gate bonding wire 335 and a second bonding wire that crosses the gate bonding wire 335 above or below it. The first bonding wire may be formed near the edge of the semiconductor body 100 that is crossed by the first load connection structure 315 and the second load connection structure 316. The second bonding wire may be formed near the edge of the semiconductor body 100 that is opposite to the edge crossed by the first load connection structure 315 and the second load connection structure 316.

[0120] Figures 8A to 8C The diagram shows a portion of an IGBT module, which includes a semiconductor die 510 having at least a first load pad 311 and a second load pad 312, a metal structure 400, and a wiring connection structure 590. A gate structure (not shown) extends parallel to a first direction 291.

[0121] The back side of the semiconductor die 510 can be soldered or sintered onto the collector plate 401. A wiring connection structure 590 can connect the first load pad 311 and the second load pad 312 via the metal structure 400. The inductance of the wiring connection structure 590 can be sufficiently low to efficiently suppress and / or dampen oscillations in the load current path, for example, at most 10nH, at most 5nH, or at most 1nH. For example, the lateral distance between the semiconductor die 510 and the metal structure 400 is at most 2 mm.

[0122] exist Figures 8A to 8B In the illustrated embodiment, the wiring connection structure 590 includes a first load connection structure 315 and a second load connection structure 316 as described above. In the illustrated embodiment, each of the first load connection structure 315 and the second load connection structure 316 may include four or more joint wirings.

[0123] exist Figure 8AIn this configuration, the metal structure 400 is a load current plate 410. A first slit 240 electrically separates the load current plate 410 from the collector plate 401. The width dm of the first slit is at most 2 mm. Orthogonal to the first direction 291, the lateral extension of the load current plate 410 is equal to or greater than the lateral extension of the semiconductor die 510. The bonding wiring of the first load connection structure 315 and the second load connection structure 316 can be formed without lateral bending. The vertical projection of each bonding wiring of the first load connection structure 315 and the second load connection structure 316 can be straight.

[0124] exist Figure 8B In this configuration, metal structure 400 serves as electrode pad 451 for a further semiconductor device 450. The further semiconductor device 450 may be a power semiconductor diode having a lateral extension orthogonal to the first direction 291 and smaller than the lateral extension of the semiconductor die 510. The back electrode of the further semiconductor device 450 may be soldered or sintered onto the collector plate 401. The bonding wiring of the first load connection structure 315 and the second load connection structure 316 may be formed with lateral bends. The lateral distance dd between the semiconductor die 510 and the further semiconductor device 450 is at most 2 mm.

[0125] exist Figure 8C In the metal structure 400, there is a Kelvin support structure 420. A second slit 250 can electrically separate the Kelvin support structure 420 from the collector plate 401. The width dk of the second slit is at most 2 mm.

[0126] The wiring connection structure 590 includes a first Kelvin-bonded wiring 591 and a second Kelvin-bonded wiring 592. The first Kelvin-bonded wiring 591 electrically connects a first load pad 311 and a Kelvin support structure 420. The second Kelvin-bonded wiring 592 electrically connects a second load pad 312 and a Kelvin support structure 420. The vertical projection of each Kelvin-bonded wiring 591, 592 can be straight. The Kelvin support structure 420 can be electrically connected to the reference input of the high-impedance input stage of a gate driver circuit that outputs a gate signal supplied to the gate electrode of the semiconductor die 510. The Kelvin support structure 420 is located outside any load current path.

[0127] The IGBT module further includes a first load connection structure 315 and a second load connection structure 316, which connect the first load pad 311 and the second load pad 312 to a load current plate 410 separated from the collector plate 401 by a first slit 240. In this embodiment, the width dm of the first slit can be greater than 2 mm because Kelvin bonding wirings 591, 592 can provide sufficiently low inductive coupling between the first load pad 311 and the second load pad 312.

[0128] Figure 9A Will Figure 7A The embodiment combines with the inter-die connection 493 between the two load pads 311, 312 of the adjacent semiconductor die 510. The inter-die connection 493 may be a further bonding connection of the same type as the bonding wiring 393 of the inter-die pad connection structure. Furthermore, Figure 9A A metal gate line 430, laterally separated from the collector plate 401, is shown. A gate wiring junction 335 electrically connects the gate metal wiring 330 to the metal gate line 430.

[0129] Figure 9B Through Kelvin junction wiring 591 and Kelvin support structure 420 Figure 7C The die-in pad connection structure is combined with the inter-die connection between the two load pads 311 and 312 of the adjacent semiconductor die 510.

[0130] According to another embodiment, the semiconductor die may include a semiconductor body, a gate structure, a first load pad, a second load pad, and an interconnect structure. The semiconductor body may include a first active portion and a second active portion. The first active portion may include a first source region. The second active portion may include a second source region.

[0131] The gate structure can extend from the first surface into the semiconductor body. The gate structure can have a longitudinal gate extension along a first transverse direction. A first load pad and a first source region can be electrically connected. A second load pad and a second source region can be electrically connected. A gap can laterally separate the first load pad and the second load pad.

[0132] The connection structure electrically connects the first load pad and the second load pad. The connection structure may be formed in a wiring layer formed on the first surface and / or may be formed in a groove extending from the first surface into the semiconductor body. The connection structure (e.g., the connection structure formed in the groove) may have a maximum lateral length extension that is at most ten times the gap width, for example, at most twice the gap width.

[0133] The longitudinal extension of the gap in the transverse direction may be orthogonal to the first direction or may deviate from the first direction by no more than 30 degrees.

Claims

1. A semiconductor die, comprising: The semiconductor body (100) includes a first active portion (191) and a second active portion (192), the first active portion (191) including a first source region (111) and the second active portion (192) including a second source region (112). A gate structure (150) extends from a first surface (101) into a semiconductor body (100), wherein the gate structure (150) has a gate extension along a first lateral direction (291); A first load pad (311) is provided, wherein the first load pad (311) and the first source region (111) are electrically connected; A second load pad (312) is electrically connected to a second source region (112), wherein a gap (230) laterally separates the first load pad (311) and the second load pad (312), wherein the gap (230) has an extension parallel to a first lateral direction (291) or has an extension deviating from the first lateral direction (291) by no more than 60 degrees. as well as A connection structure (390) electrically connects a first load pad (311) and a second load pad (312), wherein the connection structure (390) is formed in a groove extending from the first surface (101) into the semiconductor body (100) and / or is formed in a wiring layer formed on the first surface (101).

2. The semiconductor die according to claim 1, wherein, The connection structure (390) includes a trench connection structure (391) extending into the semiconductor body (100), the trench connection structure (391) including a conductive portion (395) and an insulating portion (399), the insulating portion (399) separating the conductive portion (395) from the semiconductor body (100).

3. The semiconductor die according to claim 2, wherein, The longitudinal extension of the groove connection structure (391) travels parallel to the longitudinal extension of the gap (230).

4. The semiconductor die according to claim 2, wherein, The longitudinal extension of the groove connection structure (391) is inclined relative to the longitudinal extension of the gap (230).

5. The semiconductor die according to any one of claims 2 to 4, wherein, The connection structure (390) includes multiple groove connection structures (391).

6. The semiconductor die according to any one of claims 2 to 4, further comprising: A trench electrode (165) extends into the semiconductor body (100), wherein a conductive portion (395) of the trench connection structure (391) contacts the trench electrode (165).

7. The semiconductor die according to any one of claims 1 to 4, wherein, The gap (230) has a gap width (wg) orthogonal to the first transverse direction (291), and wherein the gap width (wg) is at least 2 μm.

8. The semiconductor die according to claim 7, wherein, The connecting structure (390) has a maximum extension (lc) along a second lateral direction (292) orthogonal to the first lateral direction (291), and the maximum extension (lc) is at most ten times the gap width (wg).

9. The semiconductor die according to any one of claims 1 to 4, wherein, The connection structure (390) includes a connection line (392) formed on the semiconductor body (100), wherein the connection line (392) is formed outside the gap (230).

10. The semiconductor die according to any one of claims 1 to 4, further comprising: A first trench electrode (165) is formed in a first active portion (191) and extends into the semiconductor body (100), wherein the first trench electrode (165) and the first load pad (311) are in direct contact. A second trench electrode (165) is formed in a second active portion (192) and extends into the semiconductor body (100), wherein the second trench electrode (165) is in direct contact with the second load pad (312); A source connection line (397) is formed on the semiconductor body (100), wherein the source connection line (397) is in direct contact with the first trench electrode (165), wherein the source connection line (397) is in direct contact with the second trench electrode (165), and wherein the connection structure (390) includes a portion of the source connection line (397) extending from the first trench electrode (165) to the second trench electrode (165).

11. The semiconductor die according to any one of claims 1 to 4, in, The semiconductor body (100) further includes: Drift zone (130), The first body region (121) forms a first pn junction with the drift region (130) and a second pn junction with the first source region (111). The second body region (122) forms a further first pn junction with the drift region (130) and a further second pn junction with the second source region (112), and The collector region (140) and the drift region (130) form a third pn junction, wherein the drift region (130) separates the collector region (140) from the body region (120).

12. A semiconductor device, comprising: The semiconductor die (510) according to any one of claims 1 to 11.

13. A semiconductor device, comprising: The semiconductor body (100) includes a first active portion (191) and a second active portion (192), the first active portion (191) including a first source region (111) and the second active portion (192) including a second source region (112). A first load pad (311) is provided, wherein the first load pad (311) and the first source region (111) are electrically connected; A second load pad (312) is electrically connected to a second source region (112), and a gap (230) laterally separates the first load pad (311) and the second load pad (312). Metal structure (400); A first load connection structure (315) connects a first load pad (311) and a metal structure (400); as well as A pad connection structure (390) electrically connects a first load pad (311) and a second load pad (312), wherein the connection structure (390) has a longitudinal extension at an angle of at least 45° to the first load connection structure (315), and wherein the pad connection structure (390) contacts the first load pad (311) and the second load pad (312) on a side positioned opposite to the semiconductor body (100).

14. The semiconductor device according to claim 13, in, The first load connection structure (315) includes load bonding wiring (394).

15. The semiconductor device according to any one of claims 13 to 14, in, The pad connection structure (390) includes a bonding trace (393) in direct contact with a first load pad (311) and a second load pad (312).

16. The semiconductor device according to any one of claims 13 to 14, further comprising: The second load connection structure (316) connects the second load pad (312) and the metal structure (400), while the first load connection structure (315) and the second load connection structure (316) are separate.

17. The semiconductor device according to claim 16, in, The electrical path of the connection structure (390) is at least 50% shorter than the electrical path formed between the first load pad (311) and the second load pad (312) through the first load connection structure (315), the metal structure (400), and the second load connection structure (316).

18. An insulated gate bipolar transistor (IGBT) module, comprising: The semiconductor device (500) according to any one of claims 13 to 17 and / or the semiconductor die (510) according to any one of claims 1 to 11.

19. An insulated gate bipolar transistor (IGBT) module, comprising: Semiconductor die (510), the semiconductor die (510) includes: The semiconductor body (100) includes a first active portion (191) and a second active portion (192), the first active portion (191) including a first source region (111) and the second active portion (192) including a second source region (112). A first load pad (311) is provided, wherein the first load pad (311) and a first source region (111) are electrically connected; and A second load pad (312) is electrically connected to a second source region (112), and the first load pad (311) and the second load pad (312) are laterally separated. Metal structure (400); and A wiring connection structure (590) electrically connects a first load pad (311) and a second load pad (312) via a metal structure (400), wherein the wiring connection structure (590) includes a bonding wire (591), and wherein the bonding wire (591) of the wiring connection structure (590) has an inductance of up to 5nH and / or at least 5*10 5 s -1 The total damping constant.

20. The IGBT module according to claim 19, in, The metal structure (400) includes at least one of a load current plate (410), a Kelvin support structure (420), and an electrode pad (451) for a further semiconductor device (450).

21. The IGBT module according to any one of claims 19 to 20, in, The junction wiring (591) of the wiring connection structure (590) has an inductance of up to 1 nH.

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