An Internet of Things gateway FPGA dual configuration automatic switching method

Abstract

The application discloses a kind of Internet gateway FPGA dual configuration automatic switching techniques, it is characterized in that, two external memories are used to store configuration file, FPGA programmable chip is connected two by configuration switching circuit The external memory is transmitted control signal by configuration switching circuit;The configuration switching circuit is D flip-flop.

Description

TECHNICAL FIELD

[0001] The application relates to an Internet of Things gateway FPGA double-configuration automatic switching technology and belongs to the technical field of Internet of Things application. BACKGROUND

[0002] FPGA (Field Programmable Gate Array) can support repeated programming, and can be changed in hardware structure to adapt to different algorithm requirements and meet diversified customization requirements of the Internet of Things. At present, in the application of the FPGA, the problem that power-off information cannot be saved exists, so after each power-on, the user needs to load the designed FPGA configuration file from an external memory or an external processor into the FPGA to work. However, the processing mode is limited by a single configuration file, when the configuration file of the external memory is destroyed due to external factors or the configuration file designed by the user has an abnormal condition, the FPGA cannot work normally after the configuration file is loaded into the FPGA. In addition, if double configuration files are used, different configurations need to be switched according to requirements, so that the application expansibility of the PFGA work is limited. SUMMARY

[0003] The technical problem to be solved by the application is how to switch the configuration file of the FPGA.

[0004] In order to solve the above technical problems, the technical scheme of the application is to provide an Internet of Things gateway FPGA double-configuration automatic switching technology, characterized in that two external memories are used to store configuration files, a FPGA programmable chip is connected with the two external memories through a configuration switching circuit, and a control signal is transmitted through the configuration switching circuit; the configuration switching circuit is a D flip-flop.

[0005] The configuration switching circuit is a D flip-flop of model SN74LVC74APW, 2CLR of the D flip-flop is kept in a high level state unchanged through 4.7K to VCC3.3V, 2PRE is kept in a high level unchanged through 4.7K resistance to VCC3.3V, 2D initial state is kept in a low level through pull-down 4.7K to GND; when the FPGA is powered on, DCFG_CLK signal jumps from low level to high level, according to the truth table of the D flip-flop, when the FPGA is powered on for the first time, 2Q output of the D flip-flop is low level, that is, FPGA_SPI_CS1 output is low level, 2Q output of the D flip-flop is high level; when the FPGA loads the configuration file of the external memory through the SPI interface, when FPGA_SPI_CS1 is low level, the external memory is selected, and the FPGA configuration file is loaded through the external memory; when the configuration file in the external memory exists error, the FPGA is reset, and DCFG_CLK signal will jump once; at this time, 2CLR of the D flip-flop is kept in a high level state unchanged, 2PRE is kept in a high level unchanged, 2D and 2Q are connected together, and DCFG_CLK signal becomes high level from last time; when the current DCFG_CLK jumps, according to the truth table of the D flip-flop, 2Q output is high level, 2Q output is low level, that is, FPGA_SPI_CS2 output is low level; when the FPGA loads the configuration file of the external memory through the SPI interface, when FPGA_SPI_CS2 is low level, the external memory is selected, and the FPGA configuration file is loaded through the external memory.

[0006] The application provides a method for automatically switching a configuration file, two external memories are used to store configuration files of users, and different configurations of the FPGA are switched through an automatic switching circuit. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 It is a FPGA double configuration automatic switching principle block diagram;

[0008] Figure 2 It is a configuration switching circuit principle diagram;

[0009] Figure 3 It is an external memory one circuit structure schematic diagram;

[0010] Figure 4 It is an external memory two circuit structure schematic diagram. DETAILED DESCRIPTION

[0011] In order to make the application more obvious and easy to understand, the preferred embodiment is described in detail below with reference to the drawings.

[0012] Embodiment

[0013] The principle of automatic switching of FPGA double configuration is shown in Figure 1 The FPGA programmable chip is externally connected with a configuration switching circuit and double memories, and the control signal is connected to the external memories through the configuration switching circuit.

[0014] The configuration switching circuit is shown in Figure 2 The device adopts a D flip-flop with a model number of SN74LVC74APW, *2CLR is kept in a high level state through a 4.7K resistor to VCC 3.3V; *2PRE is kept in a high level state through a 4.7K resistor to VCC 3.3V; and 2D is in an initial state and is kept in a low level through a 4.7K pull-down resistor to GND.

[0015] When the FPGA is powered on, the DCFG_CLK signal jumps from a low level to a high level, and according to the truth table of the D flip-flop, the 2Q output is a low level, that is, the FPGA_SPI_CS1 output is a low level, and the *2Q output is a high level.

[0016] Table 1 Truth table of D flip-flop

[0017]

[0018] The FPGA loads the configuration file of the external memory through an SPI interface, and the FPGA and external memory one configuration file circuit is shown in Figure 3 When the FPGA_SPI_CS1 is a low level, the external memory one (bit number U7) is selected, and the FPGA loads the configuration file through the external memory.

[0019] When the configuration file in the external memory one has an error, the FPGA is reset, the DCFG_CLK signal jumps once, at this time, *2CLR is kept in a high level state, *2PRE is kept in a high level, 2D and *2Q are connected together, and the DCFG_CLK signal becomes a high level from the last time; when the current DCFG_CLK jumps, according to the truth table of the D flip-flop, the 2Q output is a high level, and the *2Q output is a low level, that is, the FPGA_SPI_CS2 output is a low level.

[0020] The FPGA loads the configuration file of the external memory through an SPI interface, and the FPGA and external memory two configuration file circuit is shown in Figure 4 When the FPGA_SPI_CS2 is a low level, the external memory two (bit number U8) is selected, and the FPGA loads the configuration file through the external memory.

[0021] Advantages of the present application:

[0022] The application designs a configuration switching circuit, realizes FPGA two external memory configuration switching loading, and solves the problem that FPGA cannot work normally due to single configuration exception.

[0023] A dynamic configuration changing measure is proposed according to different functional requirements, effectively improves the reliability of FPGA work, and enhances the FPGA application expansibility.

Claims

1. A method for automatically switching dual configurations of an Internet of Things gateway FPGA, characterized in that, Two external memories are used to store configuration files, and an FPGA programmable chip is connected with the two external memories through a configuration switching circuit, and a transmission control signal is transmitted through the configuration switching circuit; the configuration switching circuit is a D flip-flop; the configuration switching circuit is a D flip-flop with a model number of SN74LVC74APW, a 2CLR of the D flip-flop is kept in a high level state unchanged through a 4.7K resistor to VCC 3.3V, a 2PRE is kept in a high level unchanged through a 4.7K resistor to VCC 3.3V, and a 2D initial state is kept in a low level through a pull-down 4.7K resistor to GND; when the FPGA is powered on, a DCFG CLK signal jumps from a low level to a high level, according to a truth table of the D flip-flop, a 2Q output of the D flip-flop is low level, that is, a FPGA_SPI_CS1 output is low level, and a 2Q output of the D flip-flop is high level; the FPGA loads configuration files of the external memories through an SPI interface, when the FPGA_SPI_CS1 is low level, an external memory one is selected, and the FPGA loads the configuration files through the external memory one; when the configuration files in the external memory one have errors, the FPGA is reset, and the DCFG CLK signal jumps once; at this time, the 2CLR of the D flip-flop is kept in a high level state unchanged, the 2PRE is kept in a high level unchanged, the 2D and the 2Q are connected together, and the last DCFG CLK signal becomes high level; when the DCFG CLK jumps this time, according to the truth table of the D flip-flop, the 2Q output is high level, and the 2Q output is low level, that is, the FPGA_SPI_CS2 output is low level; the FPGA loads the configuration files of the external memories through the SPI interface, when the FPGA_SPI_CS2 is low level, an external memory two is selected, and the FPGA loads the configuration files through the external memory two.

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