Method for driving a display device

Abstract

The present disclosure relates to a method for driving a display device, wherein the display device includes pixels, the pixels include different light-emitting diodes, the pixels are commonly coupled to an initialization line, a control line, a first power line, and a second power line, and the pixels are coupled to different scan lines, the method comprising: during a first time period, supplying a scan signal with a conduction level to the scan line, supplying a control voltage with a conduction level to the control line, and supplying an initialization voltage with a low level to the initialization line; and causing the light-emitting diode to emit light during an emission period, wherein a first power voltage applied to the first power line in the first time period is higher than a second power voltage applied to the second power line in the emission period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2019-0132507, filed on October 23, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various exemplary embodiments of the present invention relate to a method of driving a display device. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between information and users is becoming more prominent. Therefore, the use of display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices is increasing.

[0005] The display device includes a plurality of pixels and can display an image using a combination of light emitted by the plurality of pixels. However, an increase in the scale or resolution of the display device leads to an increase in resistance and capacitance, thereby decreasing the level of the power supply voltage to be transmitted to the pixel, which is called a voltage ("IR") drop problem.

[0006] Therefore, in the case of a large-scale or high-resolution display device, it is necessary to supply a higher level of power supply voltage in consideration of the degree of reduction of the power supply voltage due to the IR drop.

[0007] Therefore, a peripheral control circuit (eg, a scan driver) for supplying a control signal to the pixel is also required to supply a high-level control signal to ensure the operation of the transistor. Summary of the invention

[0008] When the control circuit continuously supplies a high-level control signal, voltage stress may cause a reliability problem (eg, a lifespan problem).

[0009] Various exemplary embodiments of the present invention are directed to a display device and a method of driving the display device, which can simultaneously solve a voltage ("IR") drop problem and a reliability problem of a control circuit.

[0010] An exemplary embodiment of the present invention provides a display device. The display device includes a plurality of pixels, and each of the plurality of pixels includes: a first transistor, the first transistor includes a gate electrode coupled to a first node, a first electrode coupled to a first power line, and a second electrode coupled to a second node; a second transistor, the second transistor includes a gate electrode coupled to a scan line, a first electrode coupled to a first node, and a second electrode coupled to a third node; a third transistor, the third transistor includes a gate electrode coupled to a control line, a first electrode coupled to a third node, and a second electrode coupled to a second node; a first capacitor, the first capacitor includes a first electrode coupled to a first node and a second electrode coupled to an initialization line; a second capacitor, the second capacitor includes a first electrode coupled to a third node and a second electrode coupled to a data line; and a light emitting diode, the light emitting diode includes an anode coupled to a second node and a cathode coupled to a second power line. During a first period, a scan signal applied to the scan line has a conduction level, a control voltage applied to the control line has a conduction level, and an initialization voltage applied to the initialization line has a low level. The first power supply voltage applied to the first power line in the first period is higher than the second power supply voltage applied to the second power line in the emission period of the light emitting diode.

[0011] In an exemplary embodiment, during the second period, the scan signal may have an off level, the control voltage may have an off level, and the initialization voltage may have a low level. The first power supply voltage in the second period may be lower than the first power supply voltage in the first period.

[0012] In an exemplary embodiment, the first power supply voltage in the second period may be equal to the second power supply voltage in the emission period.

[0013] In an exemplary embodiment, the second power supply voltage in the first period may be lower than the first power supply voltage in the emission period.

[0014] In an exemplary embodiment, the frame period may sequentially include a first period, a second period, and a transmission period.

[0015] In an exemplary embodiment, the display device further includes a scan line, the pixels of the plurality of pixels may be coupled to the scan line, and emission periods of the plurality of pixels may be identical to each other.

[0016] In an exemplary embodiment, during a third period before the first period within the frame period, the scan signal may have an off level, the control voltage may have an off level, and the initialization voltage may have a low level.

[0017] In an exemplary embodiment, the initialization voltage may have a high level in a period between the third period and the first period.

[0018] In an exemplary embodiment, within the frame period, the first power supply voltage in a fourth period between the first period and the second period may be higher than the first power supply voltage in the first period and the second period.

[0019] In an exemplary embodiment, within a frame period, the data voltages may be sequentially applied to the data lines in a fifth period between the fourth period and the second period.

[0020] An exemplary embodiment of the present invention provides a method for driving a display device, the display device includes pixels, the pixels include different light-emitting diodes, the pixels are commonly coupled to an initialization line, a control line, a first power line, and a second power line, and the pixels are coupled to different scan lines. The method includes: during a first period, supplying a scan signal with a conduction level to the scan line, supplying a control voltage with a conduction level to the control line, and supplying an initialization voltage with a low level to the initialization line; and causing the light-emitting diode to emit light during an emission period. The first power supply voltage applied to the first power line in the first period is higher than the second power supply voltage applied to the second power line in the emission period.

[0021] In an exemplary embodiment, the method may further include: supplying a scan signal having an off level, supplying a control voltage having an off level, and supplying an initialization voltage having a low level during a second period. The first power supply voltage in the second period may be lower than the first power supply voltage in the first period.

[0022] In an exemplary embodiment, the first power supply voltage in the second period may be equal to the second power supply voltage in the emission period.

[0023] In an exemplary embodiment, the second power supply voltage in the first period may be lower than the first power supply voltage in the emission period.

[0024] In an exemplary embodiment, the frame period may sequentially include a first period, a second period, and a transmission period.

[0025] In an exemplary embodiment, the pixels may be coupled to the same data line.

[0026] In an exemplary embodiment, the method may further include supplying a scan signal having an off level, supplying a control voltage having an off level, and supplying an initialization voltage having a low level during a third period before the first period within the frame period.

[0027] In an exemplary embodiment, the method may further include supplying an initialization voltage having a high level in a period between the third period and the first period.

[0028] In an exemplary embodiment, within the frame period, the first power supply voltage in a fourth period between the first period and the second period may be higher than the first power supply voltage in the first period and the second period.

[0029] In an exemplary embodiment, the method may further include sequentially supplying the data voltages to the data lines in a fifth period between the fourth period and the second period within the frame period. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other exemplary embodiments, advantages and features of the present disclosure will become more apparent by describing exemplary embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0031] Figure 1 is a diagram showing an exemplary embodiment of a display device according to the present invention;

[0032] Figure 2 is a diagram showing an exemplary embodiment of a pixel according to the present invention;

[0033] Figure 3 Is shown driving Figure 2 FIG. 1 is a diagram of an exemplary embodiment of a method for obtaining pixels;

[0034] Figure 4 and Figure 5 is a diagram showing an exemplary embodiment of a method of driving a pixel in a first period according to the present invention;

[0035] Figure 6 and Figure 7 is a diagram showing an exemplary embodiment of a method of driving pixels in a fourth period and a fifth period according to the present invention;

[0036] Figure 8 and Fig. 9 is a diagram showing an exemplary embodiment of a method of driving a pixel in a second period according to the present invention;

[0037] Fig.10 and Fig.11 It shows that according to Figure 3 and a diagram of a method of driving a pixel in a second period of another exemplary embodiment of the present invention;

[0038] Fig.12 is a diagram for explaining an exemplary embodiment of the magnitude of the second power supply voltage according to the present invention; and

[0039] Fig.13 and Fig.14 is a diagram illustrating another exemplary embodiment of a method of driving a pixel in a third period according to the present invention. Specific embodiments

[0040] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice these exemplary embodiments. The present invention can be implemented in different forms and should not be construed as being limited to the exemplary embodiments set forth herein. The exemplary embodiments of the present invention can be used in combination with each other or can be used alone.

[0041] It will be understood that when an element is referred to as being “on” another element, the element can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0042] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the "first element", "first component", "first region", "first layer" or "first part" discussed below may be referred to as a second element, second component, second region, second layer or second part.

[0043] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one (kind) of ...". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when used in this specification, the terms "include" and / or "comprise" or "contain" and / or "have" illustrate the presence of stated features, regions, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or their groups.

[0044] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, relative terms are also intended to cover different orientations of the device. In an exemplary embodiment, when the device in a drawing is turned over, the element described as being on the "lower" side of the other elements will then be oriented on the "upper" side of the other elements. Therefore, depending on the specific orientation of the drawing, the exemplary term "lower" can cover both "lower" and "upper" orientations. Similarly, when the device in a drawing is turned over, the element described as being "below" or "under" other elements will then be oriented "above" other elements. Therefore, the exemplary terms "below..." or "under..." can cover both upper and lower orientations.

[0045] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0046] In order to explain the present invention clearly, some parts not related to the description are omitted, and the same reference numerals represent the same parts throughout the specification. Therefore, the reference numerals used previously may be used in different drawings.

[0047] Because the size and thickness of each configuration shown in the drawings are arbitrarily shown for better understanding and ease of description, the present invention is not limited thereto. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

[0048] Figure 1 is a diagram showing an exemplary embodiment of a display device according to the present invention.

[0049] Reference Figure 1 , an exemplary embodiment of a display device 10 according to the present invention may include a timing controller 11 , a data driver 12 , a scan driver 13 , a pixel unit 14 , and a common voltage generator 15 .

[0050] The timing controller 11 may receive the grayscale value and control signal of each image frame from an external processor. The timing controller 11 may render the grayscale value so as to correspond to the specifications of the display device 10. In an exemplary embodiment, for example, the external processor may supply a red grayscale value, a green grayscale value, and a blue grayscale value for each unit point. However, when the pixel unit 14 is in a Pentile structure, since adjacent unit points share pixels, each grayscale value may not correspond to a pixel in a one-to-one manner. In this case, it is desirable to render the grayscale value. When each grayscale value corresponds to a pixel in a one-to-one manner, it may not be necessary to render the grayscale value. The grayscale value that is rendered or not rendered may be supplied to the data driver 12. In addition, the timing controller 11 may supply a control signal suitable for its specifications to the data driver 12, the scan driver 13, the common voltage generator 15, etc. so as to display the image frame.

[0051] The data driver 12 may generate a data voltage to be supplied to the data lines DL1, DL2, DL3, ..., DLn using the grayscale value and the control signal received from the timing controller 11. In an exemplary embodiment, for example, the data driver 12 may sample the grayscale value using a clock signal, and may apply a data voltage corresponding to the grayscale value to the data lines DL1, DL2, DL3, ..., DLn in units of pixel rows. Here, n may be an integer greater than 0.

[0052] The scan driver 13 receives control signals such as a clock signal and a scan start signal from the timing controller 11, thereby generating scan signals to be supplied to the scan lines SL1, SL2, SL3, ..., SLm. The scan driver 13 can select pixels to which data voltages are to be written by supplying scan signals via the scan lines SL1 to SLm. In an exemplary embodiment, for example, the scan driver 13 can select a row of pixels to which data voltages are to be written by sequentially supplying scan signals having a conduction level to the scan lines SL1 to SLm. Here, m can be an integer greater than 0. Each level of the scan driver 13 can be configured in the form of a shift register, and can generate a scan signal by sequentially transmitting the scan start signal to the next level of the circuit under the control of the clock signal.

[0053] The pixel unit 14 may include pixels PXij, PXi(j+1), PX(i+1)j, and PX(i+1)(j+1). Each pixel may be coupled to a data line and a scan line corresponding thereto. In an exemplary embodiment, for example, when a data voltage for a single pixel row is applied from the data driver 12 to the data lines DL1 to DLn, the data voltage may be written to pixels in a row disposed in a scan line receiving a scan signal having an on level from the scan driver 13.

[0054] Pixels PXij and PXi(j+1) can be coupled to the same scan line SLi. Pixels PX(i+1)j, PX(i+1)(j+1) can be coupled to the same scan line SL(i+1). Pixels PXij and PX(i+1)j can be coupled to the same data line DLj. Pixels PXi(j+1) and PX(i+1)(j+1) can be coupled to the same data line DL(j+1). Pixels coupled to the same scan line can be represented as being arranged in the same pixel row. Pixels coupled to the same data line can be represented as being arranged in the same pixel column. Here, each of i and j can be an integer greater than 0.

[0055] In the exemplary embodiment shown, the emission periods of pixels PXij, PXi(j+1), PX(i+1)j and PX(i+1)(j+1) of the pixel unit 14 may be the same as each other. For ease of description, the display period of the black gray level is also represented as the emission period.

[0056] The common voltage generator 15 may generate a common voltage that is commonly applied to the pixels PXij, PXi(j+1), PX(i+1)j, and PX(i+1)(j+1) of the pixel unit 14 .

[0057] In an exemplary embodiment, for example, the common voltage generator 15 may supply a first power voltage through a first power line ELVDDL, may supply a second power voltage through a second power line ELVSSL, may supply an initialization voltage through an initialization line INTL, and may supply a control voltage through a control line CTL.

[0058] The common voltage generator 15 may be implemented in various forms. In an exemplary embodiment, for example, the common voltage generator 15 may be implemented in a manner in which a part or all of it is integrated with the data driver 12. In another exemplary embodiment, the common voltage generator 15 may be implemented in a manner in which a part or all of it is integrated with the timing controller 11. In another exemplary embodiment, the common voltage generator 15 may be implemented in a manner in which a part or all of it is integrated with the timing controller 11 and the data driver 12. In addition, the common voltage generator 15 may be implemented as a separate integrated chip ("IC").

[0059] Figure 2 is a diagram showing an exemplary embodiment of a pixel according to the present invention.

[0060] Reference Figure 2According to an exemplary embodiment of the pixel PXij of the present invention, the pixel PXij may include: a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor Cst, a second capacitor Cpr, and a light emitting diode LD. In addition to the coupling relationship with the data line and the scan line, Figure 1 The other pixels PXi(j+1), PX(i+1)j, and PX(i+1)(j+1) have the same configuration as the pixel PXij, and therefore repeated description will be omitted.

[0061] In the exemplary embodiment shown, transistors T1, T2 and T3 are shown as P-type transistors. Therefore, when the voltage applied to the gate electrode of the transistor has a low level, the level can be referred to as an on-level, and when the voltage applied to the gate electrode of the transistor has a high level, the level can be referred to as an off-level. Those skilled in the art can implement the exemplary embodiment shown by changing at least some of the transistors T1, T2 and T3 into N-type transistors.

[0062] The first transistor T1 may be configured such that its gate electrode is coupled to the first node N1, its first electrode is coupled to the first power line ELVDDL, and its second electrode is coupled to the second node N2. The first transistor T1 may also be referred to as a driving transistor.

[0063] The second transistor T2 may be configured such that its gate electrode is coupled to the scan line SLi, its first electrode is coupled to the first node N1, and its second electrode is coupled to the third node N3. The second transistor T2 may also be referred to as a scan transistor.

[0064] The third transistor T3 may be configured such that its gate electrode is coupled to the control line CTL, its first electrode is coupled to the third node N3, and its second electrode is coupled to the second node N2. The third transistor T3 may also be referred to as an initialization transistor.

[0065] The first capacitor Cst may be configured such that a first electrode thereof is coupled to the first node N1 and a second electrode thereof is coupled to the initialization line INTL. The first capacitor Cst may also be referred to as a storage capacitor.

[0066] The second capacitor Cpr may be configured such that a first electrode thereof is coupled to the third node N3 and a second electrode thereof is coupled to the data line DLj.

[0067] The light emitting diode LD may be configured such that its anode is coupled to the second node N2 and its cathode is coupled to the second power line ELVSSL. In an exemplary embodiment, for example, the light emitting diode LD may include an organic light emitting diode, an inorganic light emitting diode, or a quantum dot light emitting diode, etc. In an exemplary embodiment, the light emitting diode LD may include a plurality of sub-light emitting diodes coupled in series or in parallel.

[0068] When the voltage difference between the anode and cathode of the light emitting diode LD is equal to or higher than a predetermined level, the light emitting diode LD emits light. However, since the anode and cathode act like a capacitor, the voltage of the anode does not change immediately. Therefore, in order to describe in detail the time when the light emitting diode LD emits light, the capacitance Col of the light emitting diode LD is shown.

[0069] A first power voltage ELVDD may be applied to a first power line ELVDDL, a second power voltage ELVSS may be applied to a second power line ELVSSL, an initialization voltage VINT may be applied to an initialization line INTL, a control voltage VC may be applied to a control line CTL, a scan signal Si may be applied to a scan line SLi, and a data voltage Dj may be applied to a data line DLj.

[0070] The driving current path may include a first power line ELVDDL, a first electrode and a second electrode of a first transistor T1, an anode and a cathode of a light emitting diode LD, and a second power line ELVSSL. When a driving current equal to or higher than a predetermined level flows in the driving current path, the capacitor Col of the light emitting diode LD is charged, so that the light emitting diode LD can emit light.

[0071] Figure 3 Is shown driving Figure 2 Pixel method diagram. Figure 4 and Figure 5 is a diagram illustrating an exemplary embodiment of a method of driving a pixel in a first period according to the present invention. Figure 6 and Figure 7 is a diagram illustrating an exemplary embodiment of a method of driving pixels in fourth and fifth periods according to the present invention. Figure 8 and Fig. 9 is a diagram illustrating an exemplary embodiment of a method of driving a pixel in a second period according to the present invention. Fig.10 and Fig.11 It shows that according to Figure 3 and a diagram of a method of driving a pixel in a second period according to another exemplary embodiment of the present invention.

[0072] At time point t1, the second power supply voltage ELVSS may rise from the low level ELVSS1 to the high level ELVSSh, and the initialization voltage VINT may drop from the high level VINTh to the low level VINT1. At this time, the first power supply voltage ELVDD may maintain the high level ELVDDh. Moreover, the control voltage VC and the scan signals S(i-1), Si and S(i+1) may maintain the cut-off level VCh or VGH.

[0073] Therefore, the voltage difference between the anode and cathode of the light emitting diode LD is insufficient, thereby terminating the light emission of the light emitting diode LD according to the grayscale of the previous image frame. That is, the emission period EP(N-1) of the previous frame cycle is terminated. In addition, because the voltage of the first node N1 drops due to the coupling via the first capacitor Cst, the turn-on bias voltage is applied to the first transistor T1. Therefore, the hysteresis problem of the first transistor T1 can be alleviated. That is, regardless of the data voltage of the previous image frame, the first transistor T1 can have a consistent characteristic of current to gate-source voltage.

[0074] The period from time point t1 to time point t2 (i.e., the third period P3) may also be referred to as a conduction bias period. During the third period P3 before the first period P1 within the frame period FPN, the scan signals S(i-1), Si, and S(i+1) may have a cut-off level VGH, the control voltage VC may have a cut-off level VCh, and the initialization voltage VINT may have a low level VINTl.

[0075] At time point t2, the first power supply voltage ELVDD can drop from the high level ELVDDh to the low level ELVDDl, the control voltage VC can drop from the cut-off level VCh to the on-level VCl, and the voltage levels of the scan signals S(i-1), Si and S(i+1) can drop from the cut-off level VGH to the on-level VGL.

[0076] Therefore, the second transistor T2 and the third transistor T3 are turned on, and the voltages of the first node N1, the second node N2, and the third node N3 can be initialized. The charges accumulated in the first node N1, the second node N2, and the third node N3 can be discharged (leakage current) to the first power line ELVDDL through the first transistor T1. Therefore, at the time point t3, the voltages of the first node N1, the second node N2, and the third node N3 can approximately converge to the first power supply voltage ELVDD. Here, a reverse bias voltage is applied to the light emitting diode LD, whereby the light emitting diode LD does not emit light (refer to Figure 4 ).

[0077] The period from time point t2 to time point t3 (i.e., the first period P1) may also be referred to as an initialization period. During the first period P1, the scan signals S(i-1), Si, and S(i+1) applied to the scan lines may have a conduction level VGL, the control voltage VC applied to the control line CTL may have a conduction level VCl, and the initialization voltage VINT applied to the initialization line INTL may have a low level VINTl.

[0078] In order to turn on the second transistor T2 and the third transistor T3 in the initialization period, it is necessary to apply a voltage lower than the voltages of the first node N1, the second node N2 and the third node N3 to the gate electrode of the second transistor T2 and the gate electrode of the third transistor T3. That is, during the initialization period, the scan driver 13 needs to supply the scan signals S(i-1), Si and S(i+1) having a level lower than the low level ELVDD1 of the first power supply voltage ELVDD. In addition, during the initialization period, the common voltage generator 15 needs to supply the control voltage VC having a level lower than the low level ELVDD1 of the first power supply voltage ELVDD. Therefore, the reliability problem of the scan driver 13 and the common voltage generator 15 may be caused due to voltage stress.

[0079] In an exemplary embodiment of the present invention, a voltage level ELVDD1a of the first power voltage ELVDD applied to the first power line ELVDDL in the first period P1 may be higher than a voltage level ELVSS1 of the second power voltage ELVSS applied to the second power line ELVSSL in the emission period EPN of the light emitting diode LD (refer to Figure 5 ).

[0080] Because conventional technology uses a single voltage source of low level, the low level of the first power voltage ELVDD is equal to the low level of the second power voltage ELVSS. According to the exemplary embodiment shown, the low level of the first power voltage ELVDD and the low level of the second power voltage ELVSS can be supplied separately and can be different from each other.

[0081] According to the exemplary embodiment shown, even if the turn-on level VGL of the scan signal Si to be applied to the gate electrode of the second transistor T2 becomes higher than the turn-on level in the conventional technology, the second transistor T2 can be turned on. Therefore, the scan driver 13 does not have to generate the scan signals S(i-1), Si and S(i+1) with too low levels, thereby reducing the voltage stress of the scan driver 13 and improving the life of the scan driver 13.

[0082] Similarly, even if the on-level VCl of the control voltage VC to be applied to the gate electrode of the third transistor T3 becomes higher than the on-level in the conventional technology, the third transistor T3 can be turned on. Therefore, the common voltage generator 15 does not have to generate the control voltage VC with an excessively low level, thereby reducing the voltage stress of the common voltage generator 15 and improving the life of the common voltage generator 15.

[0083] At time point t4, the first power voltage ELVDD may rise from the low level ELVDD1 to the high level ELVDDh.

[0084] Reference Figure 6 , the first node N1, the second node N2, and the third node N3 can be coupled to each other through the turned-on second transistor T2 and the third transistor T3. Therefore, the first transistor T1 is coupled in a diode manner. Because the first transistor T1 is in a diode coupling state, a voltage VN1 reduced by a threshold voltage |Vth| of the first transistor T1 from the first power supply voltage ELVDD having a high level ELVDDh can be applied to the first node N1.

[0085] The period from time point t4 to time point t5 (i.e., the fourth period P4) may also be referred to as a threshold voltage compensation period. The first power supply voltage ELVDD in the fourth period P4 between the first period P1 and the second period P2 within the frame period FPN may be higher than the first power supply voltage ELVDD in the first period P1 and the second period P2.

[0086] The period from time point t5 to time point t8 (i.e., the fifth period P5) may also be referred to as a data writing period. In the fifth period P5 between the fourth period P4 and the second period P2 within the frame period FPN, data voltages D(i-1)j, Dij, and D(i+1)j may be sequentially applied to the data line DLj.

[0087] In the data writing period, the scan driver 13 may sequentially apply scan signals S(i-1), Si, and S(i+1) having a turn-on level VGL to the scan lines. In an exemplary embodiment, for example, the scan driver 13 may apply scan signals S(i-1), Si, and S(i+1) having a turn-on level VGL to the respective scan lines at intervals of one horizontal period.

[0088] In addition, the data driver 12 may sequentially apply data voltages D(i−1)j, Dij, and D(i+1)j to the data lines DLj by being synchronized with the scan driver 13 .

[0089] For convenience of explanation, a period from time point t6 to time point t7 during which the data voltage Dij and the scan signal Si having the on-level VGL are applied to the pixel PXij is described (refer to Figure 7 ).

[0090] When compared with the fourth period P4, at the time point t6 in the fifth period P5, the voltage Dj of the data line DLj changes from the reference voltage Vsus to the data voltage Dij. Here, since the second transistor T2 is in the on state and since the third transistor T3 is in the off state, the first capacitor Cst and the second capacitor Cpr can be coupled in series between the data line DLj and the initialization line INTL.

[0091] Therefore, when compared with the first node voltage VN1 in the fourth period P4, the first node voltage VN1 at the time point t7 may have a value that further reflects the voltage difference DD between the data voltage Dij based on the capacitance ratio (a) of the first capacitor Cst and the second capacitor Cpr and the reference voltage Vsus (refer to the following equations (1) to (3) and Figure 7 ).

[0092] DD=Dij–Vsus (1)

[0093] a=CprF / (CstF+CprF) (2)

[0094] VN1=ELVDDh-|Vth|+a×DD (3)

[0095] Here, CstF represents the capacitance of the first capacitor Cst, and CprF represents the capacitance of the second capacitor Cpr.

[0096] At time point t8, the initialization voltage VINT may drop to a low level VINT1. The period from time point t8 to time point t9 (i.e., the second period P2) may also be referred to as a bypass period. During the second period P2, the scan signals S(i-1), Si, and S(i+1) may have a cut-off level VGH, the control voltage VC may have a cut-off level VCh, and the initialization voltage VINT may have a low level VINT1.

[0097] Reference Figure 8 , since the initialization voltage VINT drops to the low level VINT1, the voltage of the first node N1 also drops due to the coupling of the first capacitor Cst. Therefore, the first transistor T1 is turned on, and the charge accumulated in the second node N2 can be discharged to the first power line ELVDDL through the first transistor T1, so that the voltage VN2 of the second node N2 can have a low level ELVDD1. Therefore, the capacitance Col of the light emitting diode LD is initialized, thereby improving the expression of the black grayscale or low grayscale.

[0098] According to the exemplary embodiment shown, the voltage level ELVDD1b of the first power voltage ELVDD in the second period P2 may be lower than the voltage level ELVDD1a of the first power voltage ELVDD in the first period P1 (refer to FIG. 1 ). Figure 5 and Fig. 9 In an exemplary embodiment, for example, the voltage level ELVDD1b of the first power voltage ELVDD in the second period P2 may be equal to the voltage level ELVSS1 of the second power voltage ELVSS in the emission period EPN.

[0099] If the voltage level of the first power voltage ELVDD in the second period P2 is higher than the voltage level ELVSS1 of the second power voltage ELVSS in the emission period EPN (where the threshold voltage of the light emitting diode LD is ignored), then when the second power voltage ELVSS drops to the low level ELVSS1 (at Figure 3 T10 in Fig.10 T8.5 and Fig.11 At t7.5 in FIG. 5 , a forward voltage is applied to the light emitting diode LD, which may cause an unexpected flash.

[0100] Reference Figure 3 , the second power voltage ELVSS in the second period P2 is shown as having a high level ELVSSh. However, in the second period P2, when the second power voltage ELVSS is not lower than the first power voltage ELVDD, the second power voltage ELVSS is good enough. In an exemplary embodiment, the second power voltage ELVSS may have a high level ELVSSh or a low level ELVSSl. Fig.10 At time point t8.5 in the second period P2', the second power voltage ELVSS may drop to the low level ELVSS1. Fig.11 At a time point t7.5 before the second period P2″, the second power voltage ELVSS may drop to the low level ELVSS1. However, at Fig.11 In an exemplary embodiment of the present invention, it is desirable to terminate the data writing period before the time point t7.5 to prevent erroneous writing of data due to coupling.

[0101] At time point t10, the first power supply voltage ELVDD may change from a low level ELVDD1 to a high level ELVDDh, and the second power supply voltage ELVSS may change from a high level ELVSSh to a low level ELVSS1. Therefore, a forward voltage may be applied to the light emitting diode LD, thereby enabling a drive current path. Here, the amount of drive current flowing through the first transistor T1 may be determined based on the voltage stored in the first node N1. The light emitting diode LD may emit light at a brightness corresponding to the amount of drive current.

[0102] Each frame period FPN may include a non-emission period NEPN and an emission period EPN. The emission period EP(N-1) indicates the emission period of the previous frame period. Each frame period FPN may sequentially include a first period P1, a second period P2, and an emission period EPN. Each frame period FPN may sequentially include a third period P3, a first period P1, a fourth period P4, a fifth period P5, a second period P2, and an emission period EPN.

[0103] The time point t10 may be the transmission start point of the transmission period EPN of the current frame cycle FPN, and the time point t1 of the next frame cycle may be the transmission end point of the transmission period EPN.

[0104] Fig.12 is a diagram for explaining an exemplary embodiment of the magnitude of the second power supply voltage according to the present invention.

[0105] Reference Fig.12 , the voltage level ELVSSha of the second power voltage ELVSS in the period from the time point t1 to the time point t10 may be lower than the voltage level ELVDDh of the first power voltage ELVDD in the emission period EPN.

[0106] Because conventional technology uses a single voltage source of high level, the high level of the first power voltage ELVDD is equal to the high level of the second power voltage ELVSS. According to the exemplary embodiment shown, the high level of the first power voltage ELVDD and the high level of the second power voltage ELVSS can be supplied separately and can be different from each other.

[0107] Since the voltage level ELVDDh of the first power supply voltage ELVDD in the emission period EPN is set in consideration of the voltage ("IR") drop, the voltage level ELVDDh is very high. Therefore, when the high level ELVSSh of the second power supply voltage ELVSS is set equal to the voltage level, an excessive reverse voltage is applied to the light emitting diode LD, whereby an undesirable reverse current flows, or the light emitting diode LD may be easily degraded. Fig.12 In the exemplary embodiments of the present invention, these problems can be solved.

[0108] Fig.13 and Fig.14 is a diagram illustrating an exemplary embodiment of a method of driving a pixel in a third period according to the present invention.

[0109] Reference Fig.13 and Fig.14 , in a period from the time point t1.5 to the time point t2 between the third period P3 ′ and the first period from the time point t2 to the time point t3 , the initialization voltage VINT may have a high level VINTh.

[0110] exist Fig.13 and Fig.14 In the exemplary embodiment of FIG. 1 , the third period P3′ may be defined as a period between time point t1 and time point t1.5. According to the exemplary embodiment shown, the on-bias period from time point t1 to time point t1.5 may be clearly distinguished from the initialization period from time point t2 to time point t3.

[0111] The display device and the method for driving the display device according to the present invention can solve the IR drop problem and the reliability problem of the control circuit at the same time.

[0112] The drawings and detailed description of the present invention are examples of the present invention and are provided for illustrative purposes rather than to limit the scope of the present invention described in the claims. Therefore, it will be appreciated by those skilled in the art that various modifications may be made and other exemplary embodiments may be used. Therefore, the scope of the present invention should be determined by the spirit and scope of the present disclosure.

Claims

1. A method for driving a display device, the display device comprising pixels, the pixels comprising different light emitting diodes, the pixels being commonly coupled to an initialization line, a control line, a first power line, and a second power line, and the pixels being coupled to different scan lines, wherein: The method comprises: During a third period before the first period within the frame period, supplying a scan signal having an off level, supplying a control voltage having an off level, and supplying an initialization voltage having a low level; After the third period and during the first period as an initialization period, supplying the scan signal having an on level to the scan line, supplying the control voltage having an on level to the control line, and supplying the initialization voltage having the low level to the initialization line; and causing the light emitting diode to emit light during an emission period, The first power supply voltage applied to the first power supply line in the first period is higher than the second power supply voltage applied to the second power supply line in the emission period.

2. The method according to claim 1, wherein: The method further comprises: During a second period, supplying the scan signal having the off level, supplying the control voltage having the off level, and supplying the initialization voltage having the low level, The first power supply voltage in the second period is lower than the first power supply voltage in the first period.

3. The method according to claim 2, wherein: The first power supply voltage in the second period is equal to the second power supply voltage in the transmission period.

4. The method according to claim 2, wherein: The frame period sequentially includes the first period, the second period, and the transmission period.

5. The method according to claim 2, wherein: The pixels are coupled to the same data line.

6. The method according to claim 1, wherein: The second power supply voltage in the first period is lower than the first power supply voltage in the transmission period.

7. The method according to claim 1, wherein: The method further comprises: In a period between the third period and the first period, the initialization voltage having a high level is supplied.

8. The method according to claim 1, wherein: In the frame period, the first power supply voltage in a fourth period between the first period and the second period is higher than the first power supply voltage in the first period and the second period.

9. The method according to claim 8, wherein: The method further comprises: In a fifth period between the fourth period and the second period within the frame period, data voltages are sequentially supplied to the data lines.

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