Semiconductor Devices

Abstract

The semiconductor device includes: standard cells, which are arranged in a first direction parallel to the upper surface of the substrate and in a second direction intersecting the first direction, each standard cell including an active area, a gate structure arranged to intersect the active area, a source / drain region on the active area on both sides of the gate structure, and a first interconnection line electrically connected to the active area and the gate structure; filling cells, which are arranged between at least parts of the standard cells, each filling cell including a filled active area and a filled gate structure arranged to intersect the filled active area; and a wiring structure, which is arranged on the standard cells and the filling cells and includes a second interconnection line, which electrically connects the first interconnections of different standard cells to each other, wherein the second interconnection line includes a first line having a first width and a second line having a second width greater than the first width.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. Background Art

[0002] As the demand for high-performance, high-speed semiconductor devices and / or multifunctional semiconductor devices increases, the integration of semiconductor devices increases. With the higher integration of semiconductor devices, research on layout design, especially research on efficient wiring of interconnects for connecting semiconductor elements to each other, has been actively conducted. Summary of the invention

[0003] According to an aspect of the present disclosure, a semiconductor device may have improved reliability and integration.

[0004] According to one aspect of the present disclosure, a semiconductor device includes: a plurality of standard cells arranged in a first direction parallel to an upper surface of a substrate and in a second direction intersecting the first direction, each of the plurality of standard cells including an active region, a gate structure arranged to intersect the active region, a source region and a drain region arranged on both sides of the gate structure on the active region, and a plurality of first interconnection lines electrically connected to the active region and the gate structure; a plurality of filling cells arranged between parts of the plurality of standard cells, each of the plurality of filling cells including a filled active region and a filled gate structure arranged to intersect the filled active region; and a wiring structure arranged on the plurality of standard cells and the plurality of filling cells, the wiring structure including a plurality of second interconnection lines, the plurality of second interconnection lines electrically connecting corresponding plurality of first interconnection lines of different standard cells among the plurality of standard cells to each other, wherein the plurality of second interconnection lines include a first line having a first width and a second line having a second width greater than the first width.

[0005] According to one aspect of the present disclosure, a semiconductor device includes: a first standard cell and a second standard cell arranged on a substrate, each of the first standard cell and the second standard cell including a semiconductor element and a first interconnection line electrically connected to the semiconductor element; and a wiring structure including a plurality of second interconnections, the plurality of second interconnections extending in a direction across the first standard cell and the second standard cell and on the first standard cell and the second standard cell, each of the plurality of second interconnections electrically connecting a first interconnection line of the first standard cell to a first interconnection line of the second standard cell, wherein the plurality of second interconnections include a first line and a second line having different widths from each other, and wherein the first line and the second line include signal transmission lines that transmit signals to corresponding semiconductor elements of the first standard cell and the second standard cell.

[0006] According to one aspect of the present disclosure, a semiconductor device includes: a plurality of standard cells arranged on a substrate, each of the plurality of standard cells including an active region, a gate structure arranged to intersect the active region, a source region and a drain region on the active region on both sides of the gate structure, and a plurality of first interconnects electrically connected to the active region and the gate structure; and a wiring structure electrically connecting the plurality of standard cells to each other, wherein the wiring structure includes a plurality of vias, each of the plurality of vias being arranged on a corresponding first interconnect among the plurality of first interconnects; and a plurality of second interconnects arranged on the plurality of vias to have a constant distance between corresponding centers of the plurality of second interconnects, and wherein a first line among the plurality of second interconnects has a width different from a width of a second line among the plurality of second interconnects. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent through the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a flowchart illustrating a method for designing and manufacturing a semiconductor device according to an embodiment;

[0009] Figure 2 is a flowchart partially illustrating a method for designing a semiconductor device according to an embodiment;

[0010] Figure 3A and Figure 3B is a schematic plan view showing a semiconductor device according to an embodiment.

[0011] FIG. 4A to FIG. 4C is a circuit diagram showing a unit circuit provided by a standard cell included in a semiconductor device according to an embodiment and a layout diagram showing a standard cell and a padding cell corresponding to the unit circuit;

[0012] FIG. 5A to FIG. 5D is a layout diagram showing a semiconductor device according to an embodiment;

[0013] Figure 6 and Figure 7 is a layout diagram showing a semiconductor device according to an embodiment;

[0014] FIG. 8A to FIG. 8C is a cross-sectional view of a semiconductor device according to an embodiment;

[0015] Fig. 9 is a cross-sectional view of a semiconductor device according to an embodiment; and

[0016] Fig.10 and Fig.11is a layout diagram showing a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0017] Hereinafter, preferred exemplary embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

[0018] Figure 1 is a flowchart illustrating a method for designing and manufacturing a semiconductor device according to example embodiments.

[0019] refer to Figure 1 , a method for manufacturing a semiconductor device may include a semiconductor device design process (S10) and a semiconductor device manufacturing process (S20). The semiconductor device design process (S10) is a process for designing a layout of a circuit, and may be performed using a tool for circuit design. The tool may be a program including a plurality of commands executed by a processor. Therefore, the semiconductor device design process (S10) may be a computer-implemented process for designing a circuit. The semiconductor device manufacturing process (S20) is a process for manufacturing a semiconductor device based on a designed layout, and may be performed in a semiconductor process module.

[0020] The semiconductor device design process (S10) may include a layout planning process (S110), a power planning process (S120), a layout process (S130), a clock tree synthesis (CTS) process (S140), a routing process (S150), and a what-if analysis process (S160).

[0021] The layout planning process (S110) may be a physical design process, including cutting and moving the schematic circuit of the logic design. The memory or functional block may be arranged in the layout planning process (S110). In this process, for example, functional blocks that should be placed adjacently may be identified, and space may be allocated for the functional blocks in consideration of available space, required performance, etc. For example, the layout planning process (S110) may include a process for generating a site row and a process for forming a metal wiring track in the generated site row. The site row is a framework for accommodating standard cells stored in a cell library according to design rules. The metal wiring track is a virtual line along which wiring will be formed later. Specifically, in an example embodiment, the metal wiring track may include two or more non-uniform tracks having different default width values. In the track, interconnects having different widths may be arranged in a subsequent wiring process (S150).

[0022] The power planning process (S120) may be a process of setting a pattern of interconnection lines that connect local power (e.g., driving voltage or ground) to the functional blocks arranged in the layout planning process (S110). For example, a layout pattern of interconnection lines connecting power or ground may be generated in the form of a mesh so that power may be uniformly supplied to the entire chip. In this process, a pattern may be formed in the form of a mesh based on various rules.

[0023] The layout process (S130) is a process for arranging the pattern of the elements constituting the functional block, and may include a process for arranging the standard cell. Specifically, in an example embodiment, each standard cell may include a semiconductor element and a first interconnection line connected thereto. The first interconnection line may include a power transmission line connecting power or grounding and a signal transmission line for transmitting a control signal, an input signal or an output signal. Empty areas may be generated between standard cells arranged in this process and may be filled with filler cells. Compared with standard cells including operable semiconductor elements, unit circuits implemented by semiconductor elements (such as inverter circuits, NAND circuits, NOR circuits, etc.), etc., a filler cell may be a dummy area that does not include any operable semiconductor element. This process defines the shape or size of the pattern for constituting transistors and interconnects that will actually be formed on a silicon substrate. For example, in order to form an inverter circuit (an example of a unit circuit included in a standard cell) on an actual silicon substrate, a layout pattern to be arranged thereon, such as PMOS, NMOS, N-WELL, a gate electrode, and an interconnection line, may be appropriately set.

[0024] The CTS process ( S140 ) may be a process of generating a pattern of a signal line of a central clock related to a response time for determining performance of a semiconductor device.

[0025] The wiring process (S150) may be a process for generating an upper wiring structure including a second interconnection line connecting the arranged standard cells. The second interconnection line is electrically connected to the first interconnection line in the standard cell, and the standard cell is electrically connected to other standard cells. The second interconnection line may be configured to be physically formed above the first interconnection line. In an example embodiment, when the metal wiring track is formed to include two or more non-uniform tracks having different width values ​​in the layout planning process (S110), two second interconnections having different widths may be placed in the track in this process.

[0026] The hypothetical analysis process (S160) may be a virtual analysis process that verifies and modifies the resulting layout generated by the above processes S110 to S150. Verification items may include: a design rule check (DRC) for verifying whether the layout complies with given design rules; an electrical rule check (ERC) for verifying whether there is an electrical disconnection in the layout; a layout and schematic comparison (LVS) for verifying whether the layout is consistent with the gate-level netlist, and the like. Specifically, in an example embodiment, in this process, verification and modification may be performed on the electrical path according to the second interconnect generated by the wiring process (S150). This will refer to Figure 2 Describe in more detail.

[0027] The semiconductor device manufacturing process ( S20 ) may include a mask generating process ( S170 ) and a semiconductor device manufacturing process ( S180 ).

[0028] The mask generation process (S170) may include performing optical proximity correction (OPC) or the like on the layout data generated during the semiconductor device design process (S10) to generate mask data for forming various patterns on a plurality of layers and manufacturing a mask using the mask data. OPC may correct deformation that may occur during the photolithography process. The mask may be manufactured by drawing a layout pattern using a chrome layer deposited on a glass or quartz substrate.

[0029] Various exposure and etching processes may be repeatedly performed during the semiconductor device manufacturing process (S180). Through such processes as described above, the shape of the pattern defined in the layout design process may be sequentially formed on the silicon substrate. Specifically, various semiconductor processes are performed on a semiconductor substrate such as a wafer using a plurality of masks to form a semiconductor device implemented with an integrated circuit. The semiconductor process may include a deposition process, an etching process, an ion implantation process, a cleaning process, and the like. In addition, the semiconductor process may include a packaging process, which includes mounting the semiconductor device on a printed circuit board (PCB) and packaging it with a sealant, and the semiconductor process may include a test process for the semiconductor device or the package.

[0030] Figure 2 is a flowchart partially illustrating a method for designing a semiconductor device according to example embodiments. Figure 2 Specifically shows Figure 1 The hypothesis analysis process (S160) is performed.

[0031] based on Figure 2 , the hypothesis analysis process ( S160 ) may include a critical path extraction process ( S162 ), a process of finding a candidate network ( S164 ), and a process of widening the second interconnection line ( S166 ).

[0032] The critical path extraction process ( S162 ) may be a process of verifying the timing criticality in the second interconnection line under the operating condition of the semiconductor element according to the generated layout to find a critical path.

[0033] The process of finding a candidate network (S164) may be a process of finding a candidate network in the extracted critical path to adjust the width of the second interconnection line. In this process, the candidate network may be determined by considering DRCs related to other adjacent interconnections, etc.

[0034] The process of widening the second interconnection line (S166) may be a process of modifying the layout by expanding the width of the second interconnection line of the candidate network. In an example embodiment, such modification of the width of the second interconnection line may be performed only in this process (S166) alone, or may be performed in conjunction with the previously described process. Figure 1 Alternatively, in example embodiments, the what-if analysis process (S160) may be omitted, in which case the width modification of the second interconnect line may be performed by utilizing the aforementioned width modification of the non-uniform metal wiring track.

[0035] Figure 3A and Figure 3B is a schematic plan view illustrating a semiconductor device according to example embodiments. Figure 3B is Figure 3A A plan view of power transmission lines M1 (VDD) and M1 (VSS) and a gate line GL are additionally shown in the plan view of FIG.

[0036] refer to Figure 3A and Figure 3B , the semiconductor device may include a standard cell region SC and a filling cell region FC. The first to eighth standard cells SC1, SC2, SC3, SC4, SC5, SC6, SC7 and SC8 are arranged in the standard cell region SC to implement a circuit therein. The first to sixth filling cells FC1, FC2, FC3, FC4, FC5 and FC6 are arranged in the filling cell region FC to form a dummy region. Figure 3A and Figure 3B The shapes and numbers of the first to eighth standard cells SC1 to SC8 and the first to sixth filling cells FC1 to FC6 shown are provided as examples, and thus various modifications may be made in the example embodiments. Figure 3B As shown, the semiconductor device may include power transmission lines M1 (VDD) and M1 (VSS) and a gate line GL.

[0037] The power transmission lines M1(VDD) and M1(VSS) may be connected in a first direction (eg, Figure 3BThe power transmission lines M1 (VDD) and M1 (VSS) may extend in a second direction (e.g., the Y direction) that intersects the first direction. For example, the power transmission lines M1 (VDD) and M1 (VSS) may extend along a boundary between the standard cell region SC and the filling cell region FC. The power transmission lines M1 (VDD) and M1 (VSS) may include a first power transmission line M1 (VDD) and a second power transmission line M1 (VSS). According to example embodiments, at least one of the power transmission lines M1 (VDD) and M1 (VSS) may be disposed to intersect at least one of the standard cell region SC and the filling cell region FC. Figure 3B In the example shown, one of the power transmission lines M1 (VDD) crosses the standard cell SC6.

[0038] The gate patterns GL may extend in the second direction and may be spaced apart from each other in the first direction. The gate patterns GL may include gate electrodes providing semiconductor elements and dummy gate electrodes. For example, the gate lines GL disposed on the boundary between the standard cell region SC and the filling cell region FC may be dummy gate electrodes.

[0039] FIG. 4A to FIG. 4C is a circuit diagram illustrating a unit circuit provided by a standard cell included in a semiconductor device according to example embodiments and a layout diagram illustrating a standard cell and a filling cell corresponding to the unit circuit.

[0040] refer to Figure 4A , the unit circuit may be, for example, an inverter circuit. The inverter circuit may include a pull-up element TR1 receiving a first power supply VDD and a pull-down element TR2 receiving a second power supply VSS. The gates of the pull-up element TR1 and the pull-down element TR2 may be connected to each other to provide an input terminal IN. At the same time, one of the source / drain regions of the pull-up element TR1 and one of the source / drain regions of the pull-down element TR2 may be connected to each other to provide an output terminal OUT. However, such an inverter circuit is merely an example of a unit circuit provided by a standard cell. In addition to the inverter circuit, the standard cell may also provide various other unit circuits, such as a NAND standard cell and a NOR standard cell.

[0041] refer to Figure 4B , the standard cell 100S may include a pair of active regions ACT extending in the X direction, a gate line GL extending in the Y direction, a contact CNT connected to the active region ACT and the gate line GL, a lower via V0 connected to the contact CNT, and a first interconnection line M1 connected to the lower via V0. According to example embodiments, the standard cell 100S may further include a well region. Figure 4B, a single standard cell 100S region is indicated by a thick dotted line, and for better understanding, some components arranged across the boundary of the standard cell 100S are also shown.

[0042] The active region ACT may include, for example, one or more active fins extending in the X direction. The active region ACT may be placed in a well region of a different conductivity type and may be connected to the upper source / drain contact CNT_SD. Figure 4A In the inverter circuit, the source / drain contact CNT_SD connected to one of the pair of active regions ACT can be connected to the first power transmission line M1_VDD and the signal transmission line M1_S among the first interconnection line M1 via the lower via V0, and the source / drain contact CNT_SD connected to the other of the active regions ACT can be connected to the second power transmission line M1_VSS and the signal transmission line M1_S among the first interconnection line M1 via the lower via V0. In other words, one of the active regions ACT can be connected to the first power transmission line M1_VDD and the signal transmission line M1_S, and the other of the active regions ACT can be connected to the second power transmission line M1_VSS and the signal transmission line M1_S.

[0043] The gate line GL includes a gate electrode GL_G and a dummy gate electrode GL_D. The gate electrode GL_G may cross the active area ACT. The gate electrode GL_G may provide a pull-up element TR1 and a pull-down element TR2 of the inverter circuit together with the active area ACT. Figure 4A The gates of the pull-up element TR1 and the pull-down element TR2 in the inverter circuit can be connected to each other, so the gate electrode GL_G can be shared between a pair of active regions ACT. The gate electrode GL_G can be connected to the signal transmission line M1_S among the first interconnection line M1 through the gate contact CNT_G. The dummy gate electrode GL_D can be set at both ends of the single standard cell 100S in the X direction.

[0044] The first interconnection line M1 as an interconnection disposed above the gate line GL and the active area ACT may extend in the X direction. The first interconnection line M1 may include a first power transmission line M1_VDD, a second power transmission line M1_VSS, and a signal transmission line M1_S. The first and second power transmission lines M1_VDD and M1_VSS may be power transmission lines that provide different power supply voltages VDD and VSS to the semiconductor device, respectively, and may be electrically connected to the source / drain region on the active area ACT. The signal transmission line M1_S may be a signal transmission line that provides a signal to the semiconductor device, and may be electrically connected to the gate electrode GL_G and the source / drain region on the active area ACT.

[0045] The first power transmission line M1_VDD and the second power transmission line M1_VSS are positioned across the boundary of the standard cell 100S, for example, only half thereof may be disposed inside the standard cell 100S. The regions of all first interconnection lines M1 disposed inside a single standard cell 100S may each have the same width in the Y direction, but may be as follows: Figure 6 In example embodiments, without considering the boundary of the standard cell 100S, the total width of each of the first transmission line M1_VDD and the second transmission line M1_VSS may be the same as the width of the signal transmission line M1_S.

[0046] refer to Figure 4C The filling unit 100F may include a pair of active regions ACT extending in the X direction, a gate line GL extending in the Y direction, a contact CNT connected to the active region ACT and the gate line GL, and a first interconnection line M1. The filling unit 100F may be a region in which a dummy component or a dummy semiconductor element is arranged. Figure 4C , a single filling unit 100F is indicated by a thick dotted line, and for better understanding, some components arranged across the boundary of the filling unit 100F are shown.

[0047] The active area ACT in the filling cell 100F may be formed as a pattern extending continuously from the active area ACT of the standard cell 100S in the X direction. For example, the active area ACT may be on an extension line of the active area ACT of the standard cell 100S. In an example embodiment of the semiconductor device, the active area ACT of the filling cell 100F may be formed by an active isolation layer 135 (see Figure 8C ) is spaced apart from the active region ACT of the standard cell 100S and implemented in the form of a dummy active region, but is not limited thereto. The active region ACT may be connected to the contact CNT_D.

[0048] The gate line GL in the filling cell 100F includes a gate electrode GL_G and a dummy gate electrode GL_D, and the gate electrode GL_G may be formed as a pattern extending continuously from the gate electrode GL_G of the standard cell 100S in the Y direction. For example, the gate line GL_G may be disposed on an extension line of the gate electrode GL_G of the standard cell 100S. In example embodiments, the gate line GL in the filling cell 100F may include only a dummy gate electrode GL_D substantially separated from the gate electrode GL_G of the standard cell 100S.

[0049] The contact CNT includes a dummy contact CNT_D, and the dummy contact CNT_D may not be connected to an upper interconnect such as the first interconnect M1. The first interconnect M1 may include first and second power transmission lines M1_VDD and M1_VSS. The first and second power transmission lines M1_VDD and M1_VSS may be formed as a pattern extending continuously from the first and second power transmission lines M1_VDD and M1_VSS of the standard cell 100S in the X direction, respectively. However, according to example embodiments, the filling unit 100F may further include a signal transmission line M1_S. In this case, the contact CNT may also be connected to the signal transmission line M1_S. In this case, the signal transmission line M1_S may be a dummy interconnect to which no electrical signal is applied. Alternatively, in example embodiments, the filling unit 100F may include a signal transmission line M1_S connected to the standard cell 100S instead of a dummy interconnect. In this case, the contact CNT may be omitted in the filling unit 100F.

[0050] FIG. 5A to FIG. 5D is a layout diagram illustrating a semiconductor device according to example embodiments. Figure 5A Shown includes Figure 4B The standard cells 100S are identical or similar to the standard cells SC1 and SC2 and Figure 4C The layout of a region of the filling unit 100F is similar to that of the filling unit FC. FIG. 5B to FIG. 5D Shows the ratio Figure 5A The area of ​​the second interconnection line M2 is large.

[0051] refer to Figure 5A , the semiconductor device 100 may include a first standard cell SC1 and a second standard cell SC2 arranged in the X direction and a filling cell FC arranged therebetween. Figure 4B The second standard cell SC2 is the same as the standard cell 100S. Figure 4B The standard cell 100S is inverted left and right. The filling cell FC has the same Figure 4C The form corresponding to the half area in the X direction of the filling unit 100F (ie, Figure 4C Such an arrangement of the first and second standard cells SC1 and SC2 and the filling cell FC is merely an example and may be variously modified in example embodiments.

[0052] The semiconductor device 100 may further include a wiring structure disposed on the first standard cell SC1, the second standard cell SC2 and the filling cell FC. The wiring structure may include Figure 1Specifically, the wiring structure may include a first via V1 connected to a first interconnection line M1 inside the first standard cell SC1 and the second standard cell SC2 and the filling cell FC, a second via V2 connected to a second interconnection line M2, and a third interconnection line M3 connected to the second via V2. However, in the accompanying drawings, for better understanding, some of the above components of the wiring structure are shown.

[0053] The first via V1 may be connected to at least a portion of the signal transmission line M1_S in the first interconnection line M1. However, the first via V1 may be provided in all first interconnection lines M1 including the first power transmission line M1_VDD and the second power transmission line M1_VSS.

[0054] The second interconnect line M2 may include a region extending in the Y direction perpendicular to the extension direction of the first interconnect line M1. According to example embodiments, the second interconnect line M2 may include a region extending in the X direction in an unillustrated region of the semiconductor device 100. The second interconnect line M2 may extend across the corresponding first standard cell SC1 and second standard cell SC2 to be longer than the first and second standard cells SC1 and SC2. The second interconnect line M2 may include a first line M2_F and a second line M2_S having a first width W1 and a second width W2, respectively, in the X direction, wherein the first width and the second width are different from each other, as shown in FIG. Figures 5A-5D As shown. The second width W2 may be greater than the first width W1. For example, the second width W2 may be in a range of about 101% to about 125% of the first width W1. The difference between the first width and the second width falls within a range of about 0.5 nm to about 6 nm. For example, the first width W1 may be in a range of about 15 nm to about 40 nm.

[0055] Considering the circuit function of the semiconductor device 100, the first line M2_F and the second line M2_S may be formed to have different widths. Figure 1 As described above, the first wire M2_F and the second wire M2_S may be formed such that the metal wiring track in the layout planning process (S110) includes an uneven track having different default width values, and then the first wire M2_F and the second wire M2_S are generated on the uneven track in the wiring process (S150). Alternatively, as previously described with reference to Figure 2 As described above, the first interconnection line M2_F and the second interconnection line M2_S may be formed to have the same width, and then the width of the second interconnection line M2_S may be selectively expanded through critical path extraction during the what-if analysis process ( S160 ). Figure 5A The positions and shapes of the first line M2_F and the second line M2_S are merely examples, and various modifications may be made in the example embodiments. Figure 5DAs in the example embodiment, the second interconnection line M2 may include three or more lines having different widths.

[0056] As previously described, the semiconductor device 100 includes different first and second lines M2_F and M2_S, so that timing criticality can be considered while controlling parasitic capacitance of a routing network, thereby improving timing quality of results (QoR) and turnaround time (TAT).

[0057] The second via V2 may be disposed on the second interconnection line M2 to overlap therewith.

[0058] The third interconnection line M3 may be disposed on the second via V2 to be connected to the second via V2. The third interconnection line M3 may include an area extending in the X direction perpendicular to the extension direction of the second interconnection line M2. The third interconnection line M3 may extend across both the first and second standard cells SC1 and SC2 and the filling cell FC to be longer than the first standard cell SC1 and the second standard cell SC2. The third interconnection line M3 may be disposed to electrically connect the first line M2_F and the second line M2_S having different widths to each other. The first line M2_F and the second line M2_S may be electrically connected to each other through the third interconnection line M3. However, in example embodiments, the first line M2_F and the second line M2_S may each be connected to a different third interconnection line M3.

[0059] refer to Figure 5B , the second interconnection line M2 may include a first line M2_F, a second line M2_S, and a first line M2_F (ie, another first line M2_F) sequentially arranged in one direction (eg, X direction). The first line M2_F and the second line M2_S may have a first width W1 and a second width W2, respectively, as previously described with reference to Figure 5A As described. The first line M2_F and the second line M2_S may have a constant pitch P, that is, the distance between their centers. For example, this is a structure formed by generating a fixed non-uniform track with different default width values ​​in the layout planning process (S110) and then generating the first line M2_F and the second line M2_S with different widths on the non-uniform track in the wiring process (S150). In an example embodiment, the distance between adjacent first lines M2_F and second lines M2_S may also be constant.

[0060] refer to Figure 5C , the second interconnection line M2 may include a first line M2_F, another first line M2_F, and a second line M2_S sequentially arranged in the X direction. The first line M2_F and the second line M2_S may have a first width W1 and a second width W2, respectively, as previously described with reference to Figure 5AAs described. The first line M2_F and the second line M2_S may have a constant pitch P, that is, the distance between their centers. Therefore, the first separation distance between the first line M2_F and another first line M2_F adjacent to each other may be greater than the second separation distance between the first line M2_F and the second line M2_S adjacent to each other.

[0061] refer to Figure 5D , the second interconnect line M2 may include a first line M2_F, a second line M2_F, and a third line M2_T sequentially arranged in the X direction. The first to third lines M2_F, M2_S, and M2_T may have a first width W1, a second width W2a, and a third width W2b, respectively. The second width W2a may be greater than the first width W1, and the third width W2b may be greater than the second width W2a. Also in this case, the first to third lines M2_F, M2_S, and M2_T may have a constant pitch P, that is, the distance between the centers of the first to third lines M2_F, M2_S, and M2_T. Therefore, the third separation distance between the first line M2_F and the second line M2_S may be greater than the fourth separation distance between the second line M2_S and the third line M2_T.

[0062] Figure 6 and Figure 7 is a layout diagram illustrating a semiconductor device according to example embodiments.

[0063] Reference Figure 6 ,and Figure 5A In contrast to the example embodiment of the present invention, the semiconductor device 100a may have regions of the first interconnect line M1 located in the first standard cell SC1 and the second standard cell SC2 having different widths. Specifically, portions of the first power transmission line M1_VDD and the second power transmission line M1_VSS located in the first standard cell SC1 and the second standard cell SC2 may have a third width W3 in the Y direction perpendicular to the extension direction, and the signal transmission line M1_S may have a fourth width W4 in the Y direction that is smaller than the third width W3. As described above, the regions of the first interconnect line M1 in the first standard cell SC1 and the second standard cell SC2 may be as shown in FIG. Figure 4B and Figure 5A However, the first line M2_F and the second line M2_S of the second interconnection line M2 may be set to have different widths in the upper wiring structure regardless of the shapes of the first interconnection line M1 in the first standard cell SC1 and the second standard cell SC2.

[0064] refer to Figure 7 , the semiconductor device 100b may include Figure 5AThe first vias V1 and the second interconnection lines M2 are arranged differently in the first vias V1 and the second interconnection lines M2. Specifically, the first vias V1 may be connected to the first power transmission line M1_VDD among the first interconnection lines M1. However, the first vias V1 may be provided in all the first interconnection lines M1 including the second power transmission line M1_VSS and the signal transmission line M1_S.

[0065] The second interconnection line M2 may be connected to the first via V1 to be electrically connected to the first power transmission line M1_VDD. The second interconnection line M2 may include a first line M2_Fb and a second line M2_Sb having first widths W1′ and second widths W2′ different from each other in the X direction, respectively. As for the first and second widths W1′ and W2′, Figure 5A The relationship between the first and second widths W1 and W2 described above may be equally applicable. Thus, in example embodiments, the first line M2_Fb and the second line M2_Sb having different widths among the second interconnection lines M2 may be lines electrically connected to at least one of the first power transmission line M1_VDD, the second power transmission line M1_VSS, and the signal transmission line M1_S.

[0066] Figure 5A , Figure 6 and Figure 7 The example embodiments may be combined with each other. For example, the lines among the second interconnection lines M2 electrically connected to the first power transmission line M1_VDD and the signal transmission line M1_S may have different widths. Alternatively, in each case, the first interconnection lines M1 in the first standard cell SC1 and the second standard cell SC2 may be set to have the same width or different widths.

[0067] FIG. 8A to FIG. 8C is a cross-sectional view of a semiconductor device according to example embodiments. FIG. 8A to FIG. 8C The diagrams taken along lines II′, II-II′ and III-III′ are shown. Figure 5A For ease of description, FIG. 8A to FIG. 8C The main components of a semiconductor device are shown.

[0068] refer to FIG. 8A to FIG. 8C, the semiconductor device 200 may include a substrate 101, an active region ACT including an active fin 105, an element isolation layer 110, a source / drain region 120, a gate structure 140 including a gate electrode GL_G, a lower interlayer insulating layer 130, a source / drain contact CNT_SD, an upper interlayer insulating layer 150, a lower via V0, a ​​first interconnect M1, and a wiring structure. The first interconnect M1 may be disposed in the first layer, and the second interconnect M2 may be disposed in the second layer. The wiring structure may include a first via V1 disposed above the first interconnect M1. The wiring structure may further include a second via V2 and a third interconnect M3. The semiconductor device 200 may further include: an active isolation layer 135 isolating the active region ACT; an etching stop layer 160 disposed on the lower surface of the upper interlayer insulating layer 150; and a barrier layer 170 disposed along the lower surfaces of the interconnects M1 to M3 and vias V0 to V2. The semiconductor device 200 may include a FinFET device, for example, a transistor in which the active region ACT includes an active fin 105 having a fin structure.

[0069] The substrate 101 may have an upper surface extending in the X direction and the Y direction. The substrate 101 may include a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, a semiconductor on insulator (SeOI) layer, etc.

[0070] The element isolation layer 110 may define an active region ACT. The element isolation layer 110 may be formed by, for example, a shallow trench isolation (STI) process. Fig. 8A As shown, the element isolation layer 110 may include a region further extending downward into the substrate 101 between adjacent active regions ACT, but is not limited thereto. According to example embodiments, the element isolation layer 110 may have a curved upper surface having a level that increases toward the active fin 105. The element isolation layer 110 may be formed of an insulating material such as oxide, nitride, or a combination thereof.

[0071] The active region ACT is defined by the element isolation layer 110 in the substrate 101 and may be arranged to extend in a first direction (eg, X direction), such as Fig. 8AAs shown. The active fin 105 may be arranged to protrude a predetermined height from the upper surface of the element isolation layer 110. The active fin 105 may be formed by a portion of the substrate 101, or may include an epitaxial layer grown from the substrate 101. The active fin 105 may be partially recessed on both sides of the gate structure 140, and the source / drain region 120 may be disposed on the recessed active fin 105. According to example embodiments, the active region ACT may have a doped region including impurities. For example, the active fin may include impurities diffused from the source / drain region 120 in a region in contact with the source / drain region 120. In example embodiments, the active fin 105 may be omitted; in this case, the active region ACT may have a structure including a flat upper surface.

[0072] The source / drain regions 120 may be disposed in recessed regions on both sides of the gate structure 140, in which the active fins 105 are recessed, such as Fig. 8A As shown. The source / drain region 120 may be provided as a source region or a drain region of a transistor. In a cross section in the X direction, the upper surface of the source / drain region 120 may be placed at the same or similar level as the lower surface of the gate structure 140, as shown in FIG. Figure 8B However, according to example embodiments, the relative heights of the source / drain regions 120 and the gate structure 140 may be variously modified.

[0073] like Fig. 8A As shown, the source / drain regions 120 may be connected to each other in the Y direction between the active fins 105, that is, in a merged form, but are not limited thereto. The source / drain regions 120 may have a side surface having a curved shape in a cross section along the Y direction. In example embodiments, the source / drain regions 120 may have various shapes, for example, any one of a polygonal shape, a circular shape, an elliptical shape, or a rectangular shape.

[0074] The source / drain region 120 may be formed of an epitaxial layer and may include, for example, silicon (Si), silicon germanium (SiGe), or silicon carbide (SiC). The source / drain region 120 may include impurities such as arsenic (As) and / or phosphorus (P). In example embodiments, the source / drain region 120 may include a plurality of regions including elements and / or doping elements of different concentrations.

[0075] The gate structure 140 may be disposed on the active region ACT to extend across the active region ACT in one direction (eg, the Y direction). The gate structure 140 may be disposed to correspond to Figure 5AA channel region of the transistor may be provided in the active fin 105 intersecting the gate structure 140. The gate structure 140 may include a gate dielectric layer 142, a gate electrode layer 145, a gate spacer layer 146, and a gate cap layer 148.

[0076] The gate insulating layer 142 may be disposed between the active fin 105 and the gate electrode layer 145. Figure 8B As shown. In example embodiments, the gate insulating layer 142 may be configured as a multilayer or disposed to extend toward the side surface of the gate electrode layer 145. The gate insulating layer 142 may include oxide, nitride, or a high dielectric (high-k) material. The high dielectric material may refer to a material having a dielectric strength higher than that of silicon oxide (SiO 2 ) has a dielectric constant of a material with a high dielectric constant.

[0077] The gate electrode layer 145 may include a conductive material, and may include, for example, a metal nitride (such as a titanium nitride film (TiN), a tantalum nitride film (TaN), or a tungsten nitride film (WN)) and / or a metal material (such as aluminum (Al), tungsten (W), molybdenum (Mo), etc.) or a semiconductor material (such as doped polysilicon). The gate electrode layer 145 may be configured as a multilayer structure having two or more layers. Depending on the configuration of the semiconductor device 200, the gate electrode layer 145 may be arranged to be separated between at least some adjacent transistors in the Y direction.

[0078] The gate spacer layer 146 may be disposed on both side surfaces of the gate electrode layer 145, such as Figure 8B and Figure 8C As shown. The gate spacer layer 146 may allow the source / drain region 120 to be isolated from the gate electrode layer 145. The gate spacer layer 146 may have a multilayer structure according to an example embodiment. The gate spacer layer 146 may be formed of oxide, nitride, and oxynitride, particularly a low-k film. The gate spacer layer 146 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0079] The gate capping layer 148 may be disposed on the gate electrode layer 145. The lower surface and the side surface thereof may be respectively surrounded by the gate electrode layer 145 and the gate spacer layer 146. The gate capping layer 148 may be formed of, for example, oxide, nitride, or oxynitride.

[0080] In contrast to the gate structure 140, the active isolation layer 135 may be provided corresponding to Figure 5AThe active isolation layer 135 is configured to extend in the Y direction, and may be configured to extend further into the substrate 101 than the source / drain region 120. The active isolation layer 135 may be formed by removing a portion of the gate structure 140 and extending downward. Therefore, components of the gate structure 140 including the gate spacer 146 may be partially retained as a portion of the dummy gate structure on both sides of the active isolation layer 135. The specific shape of the active isolation layer 135 may be variously modified in the example embodiment. The active isolation layer 135 may include an insulating material, and thus may electrically isolate the active region ACT and the source / drain region 120 adjacent in the X direction.

[0081] The lower interlayer insulating layer 130 may be disposed to cover the source / drain regions 120 and the gate structure 140. The lower interlayer insulating layer 130 may include, for example, at least one of oxide, nitride, and oxynitride, and may include a low-k material.

[0082] The source / drain contact CNT_SD may penetrate the lower interlayer insulating layer 130 to be connected to the source / drain region 120, and may apply an electrical signal to the source / drain region 120. The source / drain contact CNT_SD may be provided to extend into a recess of the source / drain region 120 at a predetermined depth, such as Figure 8B As shown, but not limited thereto. The source / drain contact CNT_SD may include, for example, a metal material (such as W, Al, Cu, etc.) or a semiconductor material (such as doped polysilicon). According to example embodiments, the source / drain contact CNT_SD may further include a barrier metal layer disposed along the outer surface. Alternatively, according to example embodiments, the source / drain contact CNT_SD may further include a metal semiconductor layer, such as a silicide layer, disposed at an interface in contact with the source / drain region 120.

[0083] The upper interlayer insulating layer 150 covers the source / drain contact CNT_SD and may be disposed at the same level as the corresponding levels of the interconnect structure including the lower via V0, the first interconnect M1, the first via V1, the second interconnect M2, the second via V2, and the third interconnect M3. The upper interlayer insulating layer 150 may include first to fourth insulating layers 152, 154, 156, and 158, and each may be disposed at the same level as the lower via V0, the first interconnect M1, the first via V1, the second interconnect M2, the second via V2, and the third interconnect M3, respectively. The upper interlayer insulating layer 150 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0084] The etch stop layer 160 may be disposed on a lower surface of each of the first to fourth insulating layers 152, 154, 156, and 158. The etch stop layer 160 may be used as an etch stop layer during an etching process for forming the lower via V0, the first interconnection line M1, the first via V1, the second interconnection line M2, and the second via V2. The etch stop layer 160 may include a high-k material, for example, silicon nitride or aluminum oxide.

[0085] The lower via V0, the first interconnection line M1, the first via V1, the second interconnection line M2, the second via V2, and the third interconnection line M3 forming the interconnection structure may be sequentially stacked from below. Figure 8C As shown, the second interconnection line M2 may each have different widths on the first standard cell SC1 and the second standard cell SC2, for example, a first width W1 and a second width W2, and may be connected to the third interconnection line M3 through a second via V2. The first to third interconnection lines M1 to M3 stacked from below may have a relatively large thickness upward, but are not limited thereto. The interconnection structure may include a conductive material; for example, at least one of Al, Cu, and W.

[0086] A barrier layer 170 may be disposed in the interconnect structure along the lower surfaces of the interconnect lines M1 to M3 and the vias V0 to V2, as shown in FIG. Figure 8C Specifically, the barrier layer 170 may be disposed on the lower surface and side surface of the lower via V0, on the lower surface and side surface of the first interconnection line M1, on the lower surface and side surface of the first via V1, on the lower surface and side surface of the second interconnection line M2, on the lower surface and side surface of the second via V2, and on the lower surface and side surface of the third interconnection line M3, as shown in FIG. Fig. 8A and 8C As shown. In particular, the barrier layer 170 may continue to extend from the lower surface and side surface of the second interconnection line M2 along the side surface of the first via V1 toward the lower surface of the first via V1. Such an arrangement of the barrier layer 170 may be obtained by forming the lower via V0 and the first interconnection line M1 by a single damascene process, and forming the first via V1 and the second interconnection line M2 and the second via V2 and the third interconnection line M3 by a dual damascene process. The barrier layer 170 may include at least one of titanium (Ti), tantalum (Ta), cobalt (Co), titanium nitride (TiN), and tantalum nitride (TaN).

[0087] Fig. 9 is a cross-sectional view of a semiconductor device according to example embodiments. Fig. 9 The diagram taken along line II-II′ is shown. Figure 5A An example cross section of a semiconductor device.

[0088] refer to Fig. 9, the semiconductor device 200a may further include a plurality of channel layers 115 and an inner spacer layer 118, the inner spacer layer 118 being disposed between the plurality of channel layers 115 and parallel to the gate electrode layer 145. The semiconductor device 200a may include a transistor having a full-surround gate structure, wherein the gate structure 140a is disposed between the active fin 105 and the channel layer 115 and between the plurality of channel layers 115 having a nanosheet shape. For example, through the channel layer 115, the source / drain region 120, and the gate structure 140a, the semiconductor device 200a may include a multi-bridge channel FET (MBCFET) TM ) transistor.

[0089] A plurality of channel layers 115 may be disposed in two or more layers spaced apart in a direction perpendicular to the upper surface of the active fin 105 (e.g., the Z direction). The channel layer 115 may be spaced apart from the upper surface of the active fin 105 while being connected to the source / drain region 120. The channel layer 115 may have a width that is the same as or similar to that of the active fin 105 in the Y direction and a width that is the same as or similar to that of the gate structure 140a in the X direction. However, according to example embodiments, the channel layer 115 may have a reduced width so that a side surface thereof may be located below the gate structure 140a in the Z direction.

[0090] The plurality of channel layers 115 may be formed of a semiconductor material. For example, the channel layer 115 may include at least one of Si, SiGe, and Ge. The channel layer 115 may be formed of, for example, the same material as the substrate 101. In example embodiments, the number and shape of the channel layers 115 forming a single channel structure may be variously modified. For example, according to example embodiments, the channel layer may be further disposed in a region where the active fin 105 contacts the gate electrode layer 145.

[0091] The gate structure 140a may be arranged to cross the active fin 105 and the plurality of channel layers 115 and extend thereon. A channel region of a transistor may be formed on the active fin 105 and the plurality of channel layers 115 intersecting the gate structure 140a. In this example embodiment, a gate insulating layer 142 may be arranged not only between the active fin 105 and the gate electrode layer 145, but also between the gate electrode layer 145 and the plurality of channel layers 115. The gate electrode layer 145 may be arranged to extend upward from the plurality of channel layers 115 while filling the space between the plurality of channel layers 115 upward from the active fin 105. The gate electrode layer 145 may be spaced apart from the plurality of channel layers 115 by the gate insulating layer 142.

[0092] The inner spacer layer 118 may be disposed in parallel with the gate electrode layer 145 between the plurality of channel layers 115. The gate electrode layer 145 is spaced apart from the source / drain region 120 by the inner spacer layer 118 and may be electrically isolated therefrom. The inner spacer layer 118 may have a flat side surface facing the gate electrode layer 145 or a side surface convexly rounded toward the inside of the gate electrode layer 145. The inner spacer layer 118 may be formed of one or more of an oxide, a nitride, and an oxynitride, and may be particularly formed of a low-k film.

[0093] In an example embodiment, a MBCFET having TM The semiconductor device 200a of the structure can be compared with the reference FIG. 8A to FIG. 8C The semiconductor device 200 described herein is also provided with reference to FIG. 5A to FIG. 7 In one region of the semiconductor device described. In addition, in example embodiments, the semiconductor device may include a vertical FET in which an active region extending vertically to the upper surface of the substrate 101 and a gate structure surrounding the active region are arranged.

[0094] Fig.10 and Fig.11 is a layout diagram illustrating a semiconductor device according to example embodiments. Fig.10 and Fig.11 A layout is shown including an area including Figure 5A The standard cells SC1 and SC2 and the filling cells FC are arranged symmetrically and repeatedly in the Y direction. For better understanding, Fig.10 and Fig.11 Omitted Figure 5A The active area ACT and the contact CNT, and Fig.10 The second via V2 and the third interconnection line M3 are also omitted.

[0095] refer to Fig.10 , the semiconductor device 100c may be configured such that the second interconnect line M2 has an extended width in the critical path region CP. The critical path region CP may be the region described in the previous reference. Figure 2 The regions extracted during the what-if analysis process (S160) are described.

[0096] Specifically, the first line M2_Fc and the second line M2_Sc of the second interconnect line M2 have a fifth width W5 and may have an area extending in the Y direction. However, the first line M2_Fc among the second interconnect lines M2 may have a sixth width W6 locally in the critical path area CP, and the sixth width W6 is greater than the fifth width W5. Therefore, the first line M2_Fc may have a curved portion according to a width change at the boundary of the critical path area CP. As for the fifth width W5 and the sixth width W6, the same as for Figure 5A The relationship between the first width W1 and the second width W2 is described. In particular, the sixth width W6 may be determined within a range that does not violate the design rule regarding the adjacent second interconnection line M2.

[0097] refer to Fig.11 , the third interconnect line M3 in the semiconductor device 100d may include a first line M3_F and a second line M3_S having different widths. Specifically, the third interconnect line M3 may include a first line M3_F and a second line M3_S having seventh widths W7 and eighth widths W8, respectively, different from each other in a direction perpendicular to the extension direction (e.g., the X direction), for example, in the Y direction. The eighth width W8 may be greater than the seventh width W7. For example, the eighth width W8 may be in the range of about 101% to about 125% of the seventh width W7. The difference between the seventh width W7 and the eighth width W8 may fall within the range of about 0.5nm to about 20nm.

[0098] Considering the circuit function of the semiconductor device 100d, the first line M3_F and the second line M3_S of the third interconnection line M3 may be formed to have different widths. Each of the first line M3_F and the second line M3_S may electrically connect the first standard cell SC1 and the second standard cell SC2 to each other. The first standard cell SC1 and the second standard cell SC2 electrically connected to each of the first line M3_F and the second line M3_S may be different first standard cells SC1 and second standard cells SC2.

[0099] Can be done through Figure 1 The first and second wires M3_F and M3_S are formed by generating the first and second wires M3_F and M3_S on non-uniform tracks in the layout planning process (S110) and the routing process (S150). Alternatively, the first and second wires M3_F and M3_S may be formed by generating the first and second wires M3_F and M3_S on non-uniform tracks in the layout planning process (S110) and the routing process (S150). Figure 2 The width of the second line M3_S is selectively extended by critical path extraction during the what-if analysis process ( S160 ) to form the first and second lines M3_F and M3_S. Fig.11 The positions and shapes of the arrangement of the first and second lines M3_F and M3_S, the lower circuit structure, etc. are examples and may be variously modified in example embodiments.

[0100] In this example embodiment, the second interconnection line M2 disposed below the third interconnection line M3 in the Z direction may have a FIG. 5A to FIG. 7 As such, in example embodiments, not only the second interconnection line M2 but also an upper interconnection line disposed on the second interconnection line M2 may be disposed to have different widths.

[0101] According to the aforementioned example embodiments, a semiconductor device having improved integration and reliability may be provided by allowing a wiring structure disposed on a standard cell to include interconnection lines having different widths.

[0102] Various advantages and beneficial effects of the present disclosure are not limited to the above description and can be easily understood in the process of describing specific embodiments.

[0103] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

[0104] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2019-0140136 filed in the Korean Intellectual Property Office on November 5, 2019 and Korean Patent Application No. 10-2020-0035680 filed in the Korean Intellectual Property Office on March 24, 2020, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A semiconductor device, comprising: A plurality of standard cells are arranged in a first direction parallel to an upper surface of a substrate and in a second direction intersecting the first direction, each of the plurality of standard cells comprising an active region, a gate structure arranged to intersect the active region, a source region and a drain region arranged on both sides of the gate structure on the active region, and a plurality of first interconnect lines electrically connected to the active region and the gate structure; A plurality of filling cells disposed between portions of the plurality of standard cells, each of the plurality of filling cells comprising a filling active region and a filling gate structure disposed to intersect the filling active region; as well as a wiring structure disposed on the plurality of standard cells and the plurality of filling cells, the wiring structure comprising a plurality of second interconnection lines, the plurality of second interconnection lines electrically connecting the corresponding plurality of first interconnection lines of different standard cells among the plurality of standard cells to each other, The plurality of second interconnection lines include first lines having a first width and second lines having a second width greater than the first width.

2. The semiconductor device according to claim 1, wherein A distance between centers of adjacent second interconnection lines among the plurality of second interconnection lines is constant in a direction perpendicular to an extending direction of the plurality of second interconnection lines.

3. The semiconductor device according to claim 2, in, the plurality of second interconnection lines include another first line having the first width, wherein each of the plurality of second interconnection lines includes a region extending in the second direction, the first line, the another first line and the second line of the second interconnection lines are sequentially arranged in the first direction, and In the first direction, a first distance between centers of the first line and the another first line adjacent to each other is equal to a second distance between centers of the another first line and the second line adjacent to each other.

4. The semiconductor device according to claim 1, wherein: The first line and the second line include signal transmission lines electrically connected to the source region and the drain region of a corresponding standard cell among the plurality of standard cells.

5. The semiconductor device according to claim 1, wherein The first line and the second line include power transmission lines electrically connected to the source region and the drain region of a corresponding standard cell among the plurality of standard cells.

6. The semiconductor device according to claim 1, wherein The second width is in a range of 101% to 125% of the first width.

7. The semiconductor device according to claim 6, wherein: A difference between the first width and the second width is in a range of 0.5 nm to 6 nm.

8. The semiconductor device according to claim 1, wherein The second line includes a first region having the first width and a second region having the second width.

9. The semiconductor device according to claim 1, wherein: Each standard cell among the plurality of standard cells further includes dummy gate structures disposed at both ends of the standard cell in the first direction.

10. The semiconductor device according to claim 1, wherein In each of the plurality of standard cells, the plurality of first interconnection lines include a third line having a third width and a fourth line having a fourth width greater than the third width.

11. The semiconductor device according to claim 1, wherein Each of the plurality of standard cells further comprises a first contact and a second contact connecting the plurality of first interconnect lines to the source region, the drain region and the gate structure, respectively, and The wiring structure further includes a plurality of vias connecting the plurality of first interconnect lines with the plurality of second interconnect lines.

12. The semiconductor device according to claim 11, wherein The wiring structure further includes a barrier layer disposed in contact with the plurality of second interconnection lines and the plurality of vias, The barrier layer extends from side surfaces and lower surfaces of the plurality of second interconnection lines along side surfaces of the plurality of vias toward lower surfaces of the plurality of vias.

13. The semiconductor device according to claim 1, wherein The wiring structure further includes a plurality of third interconnection lines disposed on the plurality of second interconnection lines and electrically connected to the plurality of second interconnection lines, The plurality of third interconnection lines include a fifth line having a fifth width and a sixth line having a sixth width greater than the fifth width.

14. The semiconductor device according to claim 1, wherein Each of the plurality of standard cells further includes a plurality of channel layers spaced apart from each other in a direction perpendicular to an upper surface of a corresponding active region, and Wherein, the gate structure is configured to surround the plurality of channel layers.

15. A semiconductor device comprising: A first standard cell and a second standard cell are disposed on a substrate, each of the first standard cell and the second standard cell comprising a semiconductor element and a first interconnection line electrically connected to the semiconductor element; as well as a wiring structure comprising a plurality of second interconnection lines extending in a direction crossing the first standard cell and the second standard cell and on the first standard cell and the second standard cell, each second interconnection line among the plurality of second interconnection lines electrically connecting the first interconnection line of the first standard cell to the first interconnection line of the second standard cell, wherein the plurality of second interconnection lines include first lines and second lines having different widths from each other, and The first line and the second line include signal transmission lines that transmit signals to corresponding semiconductor elements of the first standard cell and the second standard cell.

16. The semiconductor device according to claim 15, in, The plurality of second interconnection lines extend longer than each of the first standard cell and the second standard cell.

17. The semiconductor device according to claim 15, wherein: The first interconnection line of each of the first standard cell and the second standard cell includes a power transmission line that supplies power to the semiconductor element.

18. The semiconductor device according to claim 17, wherein: The plurality of second interconnection lines extend in a direction perpendicular to extension lines of the corresponding power transmission lines.

19. A semiconductor device comprising: A plurality of standard cells are arranged on a substrate, each of the plurality of standard cells comprising an active region, a gate structure arranged to intersect the active region, a source region and a drain region on both sides of the gate structure on the active region, and a plurality of first interconnect lines electrically connected to the active region and the gate structure; as well as a wiring structure electrically connecting the plurality of standard cells to each other, Wherein, the wiring structure comprises: a plurality of vias, each via of the plurality of vias being disposed on a corresponding first interconnection line of the plurality of first interconnections; and a plurality of second interconnection lines disposed on the plurality of vias to have a constant distance between respective centers of the plurality of second interconnection lines, and Wherein, a first line among the plurality of second interconnection lines has a width different from a width of a second line among the plurality of second interconnection lines.

20. The semiconductor device according to claim 19, wherein The plurality of second interconnection lines are spaced apart from each other at different distances.

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