Sensor device

Abstract

A sensor device comprising: a mediator comprising a first via and a lower pad on a bottom surface of the mediator; an image sensor chip on a top surface of the mediator, the image sensor chip comprising a logic chip and a sensing chip on the logic chip, the logic chip comprising a first wiring pattern and a second via, and the sensing chip comprising a second wiring pattern; a conductive structure penetrating a portion of the logic chip and the sensing chip, the conductive structure connected to at least one of the first wiring pattern and at least one of the second wiring pattern; and a passivation layer on an inner surface of the conductive structure, wherein a side surface of the mediator is coplanar with a side surface of the image sensor chip.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a sensor device. BACKGROUND

[0002] An image sensor is an electronic device configured to convert optical data containing one-dimensional or multi-dimensional image information into an electrical signal. The image sensor can be a complementary metal-oxide semiconductor (CMOS) image sensor or a charge-coupled device (CCD) image sensor. The image sensor can be used, for example, in a camera, a camcorder, a multimedia personal computer, or a security camera, and the demand for the image sensor is rapidly increasing.

[0003] In the semiconductor industry, various packaging technologies have been developed to meet the growing demand for semiconductor devices and electronic products having large capacity, thin thickness, and small size. SUMMARY

[0004] Embodiments can be implemented by providing a sensor device including an interposer including a first via and a lower pad, the lower pad being on a bottom surface of the interposer, an image sensor chip on a top surface of the interposer, the image sensor chip including a logic chip and a sensing chip on the logic chip, the logic chip including a first wiring pattern and a second via, the sensing chip including a second wiring pattern, a conductive structure penetrating a portion of the logic chip and the sensing chip, the conductive structure being connected to at least one of the first wiring pattern and at least one of the second wiring pattern, and a passivation layer on an inner surface of the conductive structure, wherein a side surface of the interposer is coplanar with a side surface of the image sensor chip.

[0005] Embodiments can be implemented by providing a sensor device including an interposer including a lower pad and a first via connected to the lower pad, the lower pad being on a bottom surface of the interposer, a redistribution layer on a top surface of the interposer, the redistribution layer including a redistribution pattern, an image sensor chip stacked on a top surface of the redistribution layer, the image sensor chip including a logic chip and a sensing chip stacked on the logic chip, the logic chip including a first circuit layer, the sensing chip including a second circuit layer, a conductive structure penetrating a portion of the logic chip and the sensing chip, the conductive structure having a recess, and a passivation layer in the recess and covering an inner surface of the conductive structure, wherein the first circuit layer includes a first wiring pattern, the second circuit layer includes a second wiring pattern, the conductive structure is in direct contact with at least one of the first wiring pattern in the first circuit layer and at least one of the second wiring pattern in the second circuit layer, and a side surface of the interposer is vertically aligned to a side surface of the image sensor chip.

[0006] Implementations can be realized by providing a sensor device including: a mediator including a lower pad on a bottom surface of the mediator and a first via connected to the lower pad, the first via extending in a first direction; a redistribution layer on a top surface of the mediator, the redistribution layer including a redistribution pattern; an image sensor chip stacked on a top surface of the redistribution layer, the image sensor chip including a logic chip and a sensing chip stacked on the logic chip, the logic chip including a first circuit layer and a second via, the sensing chip including a second circuit layer; a color filter and a microlens on a top surface of the image sensor chip; a conductive structure penetrating a portion of the logic chip and the sensing chip and having a recess; and a passivation layer in the recess and covering an inner surface of the conductive structure, wherein the first circuit layer includes a first wiring pattern, the second circuit layer includes a second wiring pattern, the conductive structure is in direct contact with at least one of the first wiring pattern in the first circuit layer and at least one of the second wiring pattern in the second circuit layer, a first connection pad in an upper portion of the first circuit layer is electrically connected to a second connection pad in a lower portion of the second circuit layer, the first via is electrically connected to the redistribution pattern, the second via is electrically connected to the first wiring pattern and the redistribution pattern, a side surface of the mediator is vertically aligned to a side surface of the image sensor chip. BRIEF DESCRIPTION OF DRAWINGS

[0007] Features will become apparent to those of ordinary skill in the art upon examination of the following details description of example implementations in conjunction with the accompanying drawings, of which:

[0008] Figure 1 A top view of a sensor device according to some implementations is shown.

[0009] Figure 2 A cross-sectional view taken along line I-I' of Figure 1 is shown.

[0010] Figure 3 An enlarged cross-sectional view of portion 'A' of Figure 2 is shown.

[0011] Figure 4 A cross-sectional view of a sensor device according to some implementations is shown.

[0012] Figure 5 A cross-sectional view of a sensor device according to some implementations is shown.

[0013] Figures 6A to 6D Cross-sectional views of stages in a method of manufacturing a sensor device according to some implementations are shown.

[0014] Figures 7A to 7D Cross-sectional views of stages in a method of manufacturing a sensor device according to some implementations are shown. DETAILED DESCRIPTION

[0015] Figure 1 is a top view of a sensor device according to some embodiments. Figure 2 is a cross-sectional view taken along line I-I' of Figure 1 Figure 3 is an enlarged cross-sectional view of portion 'A' of Figure 2

[0016] Referring to Figure 1 , Figure 2 and Figure 3 , the sensor device 1 can include an image sensor chip 400, a redistribution layer 150, an interposer 100, a conductive structure 322 (e.g., as part of a sensing chip 300 of the image sensor chip 400), a color filter 510, and a microlens 520.

[0017] The image sensor chip 400 can be on a top surface of the interposer 100. The image sensor chip 400 can include a logic chip 200 and a sensing chip 300 on the logic chip 200. The sensing chip 300 can be on the logic chip 200, and a size of the image sensor chip 400 can be reduced. The image sensor chip 400 can have a first surface 400a and a second surface 400b opposite to each other. In an embodiment, the first surface 400a can be a front surface of the image sensor chip 400, and the second surface 400b can be a back surface of the image sensor chip 400. Hereinafter, a first direction D1 will be used to indicate a direction perpendicular to the second surface 400b of the image sensor chip 400. A second direction D2 will be used to indicate a direction parallel to the second surface 400b of the image sensor chip 400 and perpendicular to the first direction D1. A third direction D3 will be used to indicate a direction perpendicular to both the first direction D1 and the second direction D2. In this specification, a size of an element can be represented by a width of the element. The width can be a length of the element measured in the second direction D2. When viewed in a top view (e.g., along the first direction D1), a size of the image sensor chip 400 can be substantially equal to a size of the interposer 100. In an embodiment, a width W1 of the interposer 100 can be substantially equal to a width W2 of the image sensor chip 400. A planar area of the interposer 100 can be substantially equal to a planar area of the image sensor chip 400. In this specification, "substantially" the same of the width can mean that a difference between the widths concerned is within an error range allowed by a related process. As used herein, the width of the image sensor chip 400 can be a width of the sensing chip 300. The width of the image sensor chip 400 can be a width of the logic chip 200. The width of the image sensor chip 400 can be a width of the image sensor chip 400 excluding the conductive structure 322. Figure 2 ​​As shown, the side surface 400c of the image sensor chip 400 can be vertically aligned to the side surface 100c of the interposer 100. In an embodiment, the side surface 400c of the image sensor chip 400 can be coplanar with the side surface 100c of the interposer 100. Further, the side surface 400c of the image sensor chip 400 can be coplanar with the side surface 150c of the redistribution layer 150. The side surface 400c of the image sensor chip 400 can be defined by the side surface 200c of the logic chip 200 and the side surface 300c of the sensing chip 300. In an embodiment, the side surface 200c of the logic chip 200 and the side surface 300c of the sensing chip 300 can be vertically aligned to each other.

[0018] The image sensor chip 400 can be disposed such that the first surface 400a faces the interposer 100. Light can be incident on the second surface 400b of the image sensor chip 400. The image sensor chip 400 can include a pixel P. When viewed in a top view, the pixel P can be in a central area CA of the image sensor chip 400. The image sensor chip 400 can be configured to sense an object and output a sensed result as an electrical signal. A color filter 510 and a microlens 520 can be on the second surface 400b of the image sensor chip 400. In an embodiment, each color filter 510 and a corresponding microlens 520 can be sequentially disposed on a corresponding one of the pixels P.

[0019] The redistribution layer 150 can be between the interposer 100 and the image sensor chip 400 (e.g., in the first direction Dl). In an embodiment, the redistribution layer 150 can be on the first surface 400a of the image sensor chip 400. The logic chip 200 can include a top surface 200b and an opposite surface facing away from the top surface 200b (e.g., facing in a direction opposite to the top surface 200b). The top surface 200b of the logic chip 200 can be in direct contact with the bottom surface 300a of the sensing chip 300. The opposite surface of the logic chip 200 can correspond to the first surface 400a of the image sensor chip 400. The redistribution layer 150 can include a plurality of insulating layers 156 and a redistribution pattern 155. The first pads 151 can be in a lower portion (e.g., a portion facing the interposer 100) of the redistribution layer 150. The second pads 152 can be in an upper portion (e.g., a portion facing the image sensor chip 400) of the redistribution layer 150. The insulating layers 156 can be on the first surface 400a of the image sensor chip 400. Each insulating layer 156 can be formed of or include an insulating material. The redistribution pattern 155 can include at least one electrically conductive layer and at least one electrically conductive via. The electrically conductive layer can be between adjacent insulating layers 156. The electrically conductive via can penetrate at least one of the plurality of insulating layers 156 and can be coupled to the electrically conductive layer. The first pads 151 can be electrically connected to the second pads 152 through the redistribution pattern 155. When viewed in a top view, the first pads 151 can not overlap the second pads 152. In an embodiment, the redistribution pattern 155 can be provided and the second pads 152 can be freely disposed regardless of the position of the first vias 102 of the interposer 100. In an embodiment, the degree of freedom in disposing circuitry in the image sensor chip 400 can be improved.

[0020] The interposer 100 can be on the first surface 400a of the image sensor chip 400. In an embodiment, the interposer 100 can be on a bottom surface of the redistribution layer 150 (e.g., such that the redistribution layer 150 is between the interposer 100 and the image sensor chip 400). The interposer 100 can be formed of or include, for example, a curable polymer, an epoxy polymer, or silicon (Si). As used herein, the term "or" is not an exclusive term, for example, "A or B" will include A, B, or both A and B. The interposer 100 can include a lower pad 101 and a first via 102. The lower pad 101 and the first via 102 can be formed of or include a conductive material. The lower pad 101 can be on a bottom surface of the interposer 100. The first via 102 can be on the lower pad 101. In an embodiment, the first via 102 can be between the lower pad 101 and the first pad 151, and can extend in a first direction D1 (e.g., longitudinally). The first via 102 can penetrate the interposer 100 perpendicularly, and can be in direct contact with both the lower pad 101 and the first pad 151. In an embodiment, the redistribution pattern 155 of the redistribution layer 150 and the lower pad 101 can be electrically connected or coupled to each other through the first via 102. The redistribution pattern 155 of the redistribution layer 150 can receive an electrical signal input through the lower pad 101 and the first via 102, or send an electrical signal to the lower pad 101. In this specification, the expression "electrically connected or coupled" can mean that a plurality of elements are directly connected or coupled to each other, or indirectly connected or coupled to each other through another conductive element. In an embodiment, a thickness of the interposer 100 in the first direction D1 can be in a range of, for example, 50 μm to 300 μm. Maintaining the thickness of the interposer 100 to be 50 μm or more can facilitate handling of the sensing substrate and the logic substrate in a manufacturing process of the sensor device, which will be described below. Maintaining the thickness of the interposer 100 to be 300 μm or less can facilitate reducing a thickness of the sensor device or can help achieve a small sensor device. The sensor device according to an embodiment can include the interposer 100, and can improve durability of the sensor device. In an embodiment, due to the interposer 100 on the first surface 400a of the image sensor chip 400, a warpage problem (e.g., reducing warpage) in the image sensor chip 400 can be improved and the sensor device can be easily handled in a manufacturing process. The interposer 100 can include the lower pad 101 on a bottom surface thereof, and mounting the sensor device on a substrate can not require bonding wires. In an embodiment, a volume of the sensor device in an electronic product can be reduced and a small electronic product can be achieved.

[0021] As described above, the image sensor chip 400 can include the logic chip 200 and the sensing chip 300 on the logic chip 200. The logic chip 200 can include the first circuit layer 210, the first base layer 220, the second via 222, and the first bonding pad 218. The first base layer 220 can include a silicon substrate. The second via 222 can penetrate a portion of the first circuit layer 210 and the first base layer 220. The second via 222 can be on the second pad 152 and can be connected to at least one of the first wiring pattern 216 and the second pad 152. When viewed in a top view, the second via 222 can be aligned to or overlap the second pad 152. The second via 222 can be electrically connected to the lower pad 101 through the redistribution pattern 155 and the first via 102.

[0022] In conjunction with Figure 2 Referring to Figure 3 , the first circuit layer 210 can include a plurality of first insulating layers 214, a first integrated circuit 225, and a first wiring pattern 216. The first integrated circuit 225 can be on the first base layer 220. The first integrated circuit 225 can include a transistor. The first wiring pattern 216 can be in the plurality of first insulating layers 214 and can be coupled to the first integrated circuit 225. The first bonding pad 218 can be in an upper portion of the first circuit layer 210 of the logic chip 200 and can be coupled to the first wiring pattern 216. The first wiring pattern 216 can include at least one first metal pattern and at least one first metal via. The first metal pattern can be between adjacent first insulating layers 214, and the first metal via can penetrate at least one of the plurality of first insulating layers 214 and can be coupled to the first metal pattern. The first wiring pattern 216 can electrically connect the second via 222 and the first integrated circuit 225 to each other.

[0023] The sensing chip 300 can include a second circuit layer 310, a second base layer 320, and a second bonding pad 318. The pixels P can be provided on the sensing chip 300. The second base layer 320 can include a silicon substrate. The second circuit layer 310 can be closer to the logic chip 200 (e.g., in the first direction D1) than the second base layer 320 to the logic chip 200. The second circuit layer 310 can include a plurality of second insulating layers 314, a second integrated circuit 325, and a second wiring pattern 316. The second integrated circuit 325 can include a sensing transistor. The second integrated circuit 325 can be electrically connected to the second wiring pattern 316. The second bonding pad 318 can be in a lower portion of the second circuit layer 310 of the sensing chip 300 and can be coupled to the second wiring pattern 316. The second wiring pattern 316 can include at least one second metal pattern and at least one second metal via. The second metal pattern can be between adjacent second insulating layers 314, and the second metal via can penetrate at least one of the plurality of second insulating layers 314 and can be coupled to the second metal pattern. The second integrated circuit 325 can be electrically connected to the first integrated circuit 225 through the first bonding pad 218 and the second bonding pad 318.

[0024] The conductive structure 322 can be in the image sensor chip 400. In an embodiment, the conductive structure 322 can penetrate at least a portion of the logic chip 200 and the sensing chip 300. In an embodiment, the conductive structure 322 can penetrate a portion of the first circuit layer 210, the second circuit layer 310, and the second base layer 320. The conductive structure 322 can be in direct contact with at least one of the second wiring pattern 316 and at least one of the first wiring pattern 216. The second integrated circuit 325 can be electrically connected to the conductive structure 322 through the first wiring pattern 216 and the second wiring pattern 316. The conductive structure 322 can serve as an electrical connection path between the sensing chip 300 and the logic chip 200. When viewed in a top view, the conductive structure 322 can be in the edge area EA of the image sensor chip 400. In an embodiment, the conductive structure 322 can be between the side surface 400c of the image sensor chip 400 and the pixel P (e.g., in the second direction D2). The conductive structure 322 can be spaced apart from the pixel P (e.g., in the second direction D2). The conductive structure 322 can have a recess 322a. A passivation layer 323 can be provided in the recess 322a. The passivation layer 323 can cover an inner surface of the conductive structure 322. In an embodiment, the passivation layer 323 can extend to partially cover a top surface of the sensing chip 300 or a second surface 400b of the image sensor chip 400.

[0025] Figure 4is a cross-sectional view of a sensor device according to some embodiments. For a concise description, previously described elements can be identified by the same reference numerals without repeating overlapping descriptions thereof.

[0026] Referring to Figure 4 , in addition to the image sensor chip 400, the redistribution layer 150, the interposer 100, the conductive structure 322, the color filter 510, and the microlens 520, the sensor device 2 can include a memory chip 600. The image sensor chip 400, the redistribution layer 150, the conductive structure 322, the color filter 510, and the microlens 520 can be substantially the same as those described with reference to Figures 1 to 3 .

[0027] The memory chip 600 can be in the interposer 100. The interposer 100 can cover side surfaces of the memory chip 600, and can not cover a bottom surface of the memory chip 600. In an embodiment, the memory chip 600 can be at least one of a DRAM, an SRAM, an MRAM, and a FLASH memory chip. The memory chip 600 can include silicon. A top surface of the memory chip 600 can be used as an active surface. The memory chip 600 can include a circuit pattern layer and a chip pad 601. The chip pad 601 is disposed in an insulating layer 603. In an embodiment, the circuit pattern layer can include a plurality of layers. The chip pad 601 can be on the memory chip 600, and can be electrically connected to integrated devices in the circuit pattern layer. Hereinafter, in the present specification, the expression “an element is electrically connected to a circuit pattern layer or a circuit layer” means that the element is electrically connected to integrated devices or integrated circuits provided in the circuit pattern layer or the circuit layer. In addition, the expression “an element is electrically connected to the memory chip 600” means that the element is electrically connected to integrated devices provided in the memory chip 600. In an embodiment, the chip pad 601 can be formed of or include a metallic material, such as aluminum.

[0028] In addition to the lower pad 101 and the first via 102, the interposer 100 can include a connection terminal CT, a connection pad 602, and a third via 103. The first via 102 and the lower pad 101 can be substantially the same as those described with reference to Figure 2 . The first via 102 can be spaced apart from the memory chip 600. In an embodiment, when viewed in a top view, the first via 102 can be between the memory chip 600 and a side surface 100c of the interposer 100.

[0029] The connection terminal CT can be on a top surface of the storage chip 600. In an embodiment, the connection terminal CT can be between the chip pad 601 and the connection pad 602. The connection terminal CT can be coupled to the chip pad 601 and the connection pad 602. The connection terminal CT can be in the form of a bump, a solder ball, or a pillar. The connection terminal CT can be formed of or include a metallic material. In an embodiment, the connection terminal CT can be formed of or include, for example, silver (Ag), tin (Sn), bismuth (Bi), or an alloy thereof. The connection terminal CT can electrically connect an integrated device provided as a part of the circuit pattern layer of the storage chip 600 to the connection pad 602. Accordingly, the storage chip 600 can be electrically connected to the image sensor chip 400 through the connection terminal CT and the third via 103. This makes it possible to reduce the length of a connection path between the storage chip 600 and the image sensor chip 400 and to increase the speed of a signal to be transmitted between the storage chip 600 and the image sensor chip 400. The connection pad 602 can be between the connection terminal CT and the third via 103. The connection pad 602 can electrically connect the connection terminal CT to the third via 103.

[0030] The third via 103 can be between the first pad 151 and the connection pad 602. The third via 103 can extend in parallel with the first direction Dl to penetrate a portion of the interposer 100. When viewed in a top view, the third via 103 can overlap the storage chip 600. The third via 103 can be a signal transmission path between the storage chip 600 and the redistribution layer 150. The third via 103 can be formed of or include a conductive material. Through the chip pad 601, the connection terminal CT, the connection pad 602, the third via 103, the first pad 151, the redistribution pattern 155, the first via 102, and the lower pad 101, the storage chip 600 can output an electrical signal generated by an integrated device in the circuit pattern layer to the outside or can receive an electrical signal from the outside.

[0031] Figure 5 is a cross-sectional view of a sensor device according to some embodiments. For a concise description, previously described elements can be identified by the same reference numerals without repeating the overlapping description thereof.

[0032] Referring to Figure 5 In addition to the image sensor chip 400, the redistribution layer 150, the interposer 100, the conductive structure 322, the color filter 510, and the microlens 520, the sensor device 3 can include a substrate 1000, a connector 1005, a bracket 2000, and a transparent cover 1500. The image sensor chip 400, the redistribution layer 150, the interposer 100, the conductive structure 322, the color filter 510, and the microlens 520 can be the same as those described with reference to Figures 1 to 3Those described are substantially the same.

[0033] The substrate 1000 can be, for example, a printed circuit board (PCB). The substrate 1000 can be flexible. The upper substrate pad 1003 can be in an upper portion of the substrate 1000. The lower substrate pad 1001 can be below the substrate 1000. The external terminal 1002 can be on a bottom surface of the lower substrate pad 1001. The external terminal 1002 can be in the form of a solder ball. The external terminal 1002, the upper substrate pad 1003, and the lower substrate pad 1001 can be formed of or include a conductive material. As depicted by the dashed line, the external terminal 1002 can be electrically connected to the upper substrate pad 1003 through the substrate 1000.

[0034] The connector 1005 can be between the lower pad 101 and the upper substrate pad 1003. The connector 1005 can electrically connect the lower pad 101 to the upper substrate pad 1003. In an embodiment, the connector 1005 can be used to transmit an electrical signal input from the outside through the substrate 1000 to the image sensor chip 400, or output an electrical signal generated by the image sensor chip 400 to the outside.

[0035] The bracket 2000 can be on the substrate 1000 to support the transparent cover 1500. The bracket 2000 can be spaced apart horizontally (e.g., in the second direction D2) from the image sensor chip 400. When viewed in a top view, the bracket 2000 can overlap a portion of the edge area EA of the image sensor chip 400. When viewed in a top view, the bracket 2000 can not overlap the pixels P. The bracket 2000 can include an engineering plastic. The transparent cover 1500 can be on the bracket 2000 to face the image sensor chip 400 and can be spaced apart from the image sensor chip 400 (e.g., in the first direction D1). The transparent cover 1500 can be formed of or include a transparent material (e.g., glass) to allow light to pass through.

[0036] Figures 6A to 6D is a cross-sectional view of a stage in a method of manufacturing a sensor device according to some embodiments. For a succinct description, previously described elements can be identified by the same reference numerals without repeating their overlapping descriptions. In the following drawings, wiring patterns and integrated devices provided in circuit layers can be omitted or simplified.

[0037] In conjunction Figure 2 Referring to Figure 6AThe sensing substrate 1300 can be fabricated. In an embodiment, the sensing substrate 1300 can be fabricated by forming the color filter 510, the microlens 520, the second circuit layer 310, and the second bonding pad 318 on the second base layer 320. The sensing substrate 1300 can be, for example, a wafer. The second bonding pad 318 can be formed of or include a metallic material (e.g., copper).

[0038] The logic substrate 1200 can be fabricated. In an embodiment, the logic substrate 1200 can be fabricated by forming the first circuit layer 210, the first bonding pad 218, and the second via 222 on the first base layer 220. The logic substrate 1200 can be, for example, a wafer. The first integrated circuit 225 (e.g., see Figure 3 ) of the first circuit layer 210 and the second via 222 can be formed by a via-middle process. The second via 222 can be formed to penetrate at least a portion of the first base layer 220 from a surface of the first base layer 220. Thereafter, the first circuit layer 210 can be formed by forming the first insulating layer 214 and the first wiring pattern 216 on the surface of the first base layer 220. The first bonding pad 218 can be formed on the first circuit layer 210. In an embodiment, the first bonding pad 218 can be formed of or include a metallic material (e.g., copper).

[0039] The logic substrate 1200 can be electrically connected to the sensing substrate 1300. In an embodiment, the electrical connection can be achieved by a direct bonding process. In an embodiment, the logic substrate 1200 can be placed on the sensing substrate 1300 such that the first bonding pad 218 is aligned to or aligned with the second bonding pad 318. A heat treatment process can be performed on the logic substrate 1200 and the sensing substrate 1300 to bond the second bonding pad 318 to the first bonding pad 218. The bonding process (e.g., heat treatment process) on the logic substrate 1200 and the sensing substrate 1300 can be performed at a temperature of about 350 °C to about 400 °C.

[0040] After the bonding process of the logic substrate 1200 and the sensing substrate 1300, a conductive structure can be formed. A portion of the logic substrate 1200 and the sensing substrate 1300 can be etched to form a first recess. The first recess can expose a portion of the second wiring pattern 316 and a portion of the first wiring pattern 216. The conductive structure can be formed by conformally covering the inner surface of the first recess with a metallic material. In an embodiment, the conductive structure can be formed to have a second recess. A passivation layer can be formed in the second recess. The passivation layer can fill the interior space of the second recess of the conductive structure. In an embodiment, the top surface of the passivation layer can be coplanar with the adjacent surface of the sensing substrate 1300. The top surface of the passivation layer can be coplanar with the second surface 400b of the image sensor chip 400 (e.g., in the resulting structure). The second surface 400b can be the top surface of the image sensor chip 400. The passivation layer can be formed of or include at least one of an insulating material. In an embodiment, the passivation layer can extend to cover at least a portion of the top surface of the sensing substrate 1300.

[0041] Referring to Figure 6A and Figure 6B The sensing substrate 1300 can be provided on the carrier substrate 900. The carrier adhesive layer 910 can be between the carrier substrate 900 and the sensing substrate 1300. Thereafter, a process of thinning the logic substrate 1200 can be performed to expose the second via 222. In an embodiment, a grinding process can be performed on the opposite surface of the logic substrate 1200 to expose the second via 222. The opposite surface of the logic substrate 1200 can correspond to the first surface 400a of the image sensor chip 400 (e.g., in the resulting structure). Figure 2

[0042] Referring to Figure 6C A redistribution layer 1150 can be formed on the logic substrate 1200. In an embodiment, the insulating layer 156, the first pad 151 and the second pad 152, and the redistribution pattern 155 constituting the redistribution layer 1150 can be formed on the logic substrate 1200. The redistribution pattern 155 can be electrically connected to the second via 222.

[0043] Referring to Figure 6D The interposer layer 1100 can be prepared. The interposer layer 1100 can be a silicon wafer. The interposer layer 1100 can be fabricated by forming the first via 102 in the silicon wafer and forming the lower pad 101 on the surface of the silicon wafer. The interposer layer 1100 can be provided on the redistribution layer 1150 such that the lower pad 101 is exposed to the outside. The interposer layer 1100 can be electrically connected to the redistribution layer 1150. In an embodiment, the electrical connection can be achieved by a direct bonding process. The interposer layer 1100 can be prepared in a manner similar to the preparation of the sensing substrate 1300 with reference to Figure 6A ​The direct bonding process is performed in substantially the same manner as described. Thus, the first via 102 can be bonded to the first pad 151.

[0044] The through-holes T can be formed along Figure 6D The sensing substrate 1300, the logic substrate 1200, the redistribution layer 1150, and the interposer layer 1100 can be sawn along the dotted line S illustrated in FIG. 13B. Next, the carrier substrate 900 and the carrier adhesive layer 910 can be removed to expose the microlens 520. The sensor device 1 can be manufactured by the aforementioned processes. The sensor devices 1 can be separated from each other by a sawing process, and the sensing chip 300, the logic chip 200, and the redistribution layer 1150 in each of the sensor devices 1 can be manufactured to have the same width.

[0045] Figures 7A to 7D is a cross-sectional view of a stage in a method of manufacturing a sensor device according to some embodiments. For a brief description, the previously described elements can be identified by the same reference numerals without repeating the overlapping description thereof. In the following drawings, the wiring patterns and integrated devices provided in the circuit layers can be omitted or simplified.

[0046] Referring to Figure 7A The logic substrate 1200, the sensing substrate 1300, and the redistribution layer 1150 can be formed on the carrier substrate 900. The logic substrate 1200, the sensing substrate 1300, and the redistribution layer 1150 can be formed by substantially the same method as described with reference to Figure 6A and Figure 6C Referring to

[0047] Referring to Figure 7B The polymer layer 1100' can be formed on the redistribution layer 1150. The polymer layer 1100' can be formed of or include a curable polymer material. A process of applying heat or light to the polymer layer 1100' can be performed. Thus, the polymer layer 1100' can be firmly cured.

[0048] Referring to Figure 7C The through-hole T can be formed to penetrate the polymer layer 1100'. The through-hole T can vertically (e.g., in the first direction D1) penetrate the polymer layer 1100' and can expose the first pad 151. The through-hole T can be formed by a laser drilling process.

[0049] Referring to Figure 7D The first via 102 can be formed by filling the through-hole T with a metallic material. After the formation of the first via 102, the lower pad 101 can be formed. Thus, the interposer layer 1100 can be formed.

[0050] The through-holes T can be formed along Figure 7DThe sensing substrate 1300, the logic substrate 1200, the redistribution layer 1150, and the interposer layer 1100 are sawn along the dotted line S drawn in the middle. Next, the carrier substrate 900 and the carrier adhesive layer 910 can be removed to expose the microlens 520. The sensor device 1 can be manufactured by the aforementioned processes. The sensor devices 1 can be separated from each other by a sawing process, and the sensing chip 300, the logic chip 200, and the redistribution layer 1150 in each sensor device 1 can be manufactured to have the same width.

[0051] According to an embodiment, an interposer can be provided on a bottom surface of an image sensor chip. A via can be provided in the interposer, and can electrically connect the image sensor chip to a lower pad provided on the bottom surface of the interposer. A sensor device can be mounted on a substrate through the lower pad. Accordingly, the footprint of the sensor device on the substrate can be reduced and a small electronic product can be implemented.

[0052] One or more embodiments can provide a stacked image sensor.

[0053] One or more embodiments can provide a highly integrated sensor device.

[0054] Example embodiments have been disclosed herein and, although the use of particular nomenclature and / or specific terms has been presented herein for the purpose of knowledge, they are only used in a generic and descriptive sense and not for limitation purposes. In some instances, it will be apparent to those having ordinary skill in the art in light of the present disclosure that features, characteristics, and / or elements described in connection with a particular embodiment can be used singly or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless explicitly stated otherwise. Accordingly, those having ordinary skill in the art will recognize that there are a number of ways of implementing the present application as claimed in the appended claims which have been drawn up in all substantial and relative aspects.

[0055] Korean Patent Application No. 10-2019-0138739, entitled "Sensor Device," filed on November 1, 2019, in the Korean Intellectual Property Office, is hereby incorporated by reference.

Claims

1. A sensor device, comprising: An intermediary comprising a first channel and a lower pad, the lower pad being on the bottom surface of the intermediary; An image sensor chip on the top surface of the intermediary, the image sensor chip including a logic chip and a sensing chip on the logic chip, the logic chip including a first wiring pattern and a second path, the sensing chip including a second wiring pattern; A conductive structure that penetrates a portion of the logic chip and the sensing chip, the conductive structure being connected to at least one of the first wiring patterns and at least one of the second wiring patterns; as well as Passivation layer on the inner surface of the conductive structure The thickness of the intermediary in the first direction is in the range of 50 μm to 300 μm, and the first direction is perpendicular to the bottom surface of the intermediary. The logic chip is disposed between the intermediary and the sensing chip along the first direction. The second path is in contact with the first wiring pattern to which the conductive structure in the first wiring pattern is connected. The conductive structure is interposed between the first wiring pattern and the passivation layer. The conductive structure has a recess defined by the inner surface of the conductive structure. The recess is filled with the passivation layer provided on the inner surface of the conductive structure.

2. The sensor device of claim 1, wherein the side surface of the image sensor chip includes the side surface of the sensing chip and the side surface of the logic chip.

3. The sensor device as described in claim 1, wherein, When viewed from above, the conductive structure is located in the edge region of the image sensor chip.

4. The sensor device of claim 1, further comprising a microlens on the top surface of the sensing chip. in, When viewed from above, the conductive structure is laterally spaced from the microlens.

5. The sensor device of claim 1, further comprising a redistribution layer between the logic chip and the intermediary. in: The redistribution layer includes a first pad in the lower portion of the redistribution layer, and The first path is located between the first pad and the lower pad, and is in direct contact with both the first pad and the lower pad.

6. The sensor device as described in claim 5, wherein: The redistribution layer further includes a second pad in the upper portion of the redistribution layer, and The second path is between the second pad and the first wiring pattern, and connects the second pad to at least one of the first wiring patterns.

7. The sensor device of claim 1, wherein the intermediate comprises a curable polymer, an epoxy polymer, or silicon.

8. The sensor device of claim 1, wherein the width of the intermediary is equal to the width of the image sensor chip.

9. The sensor device of claim 1, wherein the planar area of ​​the intermediate is equal to the planar area of ​​the image sensor chip.

10. A sensor device, comprising: An intermediary component includes a lower pad and a first passage connected to the lower pad, the lower pad being located on the bottom surface of the intermediary component; A redistribution layer on the top surface of the intermediary, the redistribution layer comprising a redistribution pattern; An image sensor chip stacked on the top surface of the redistribution layer, the image sensor chip including a logic chip and a sensing chip stacked on the logic chip, the logic chip including a first circuit layer, and the sensing chip including a second circuit layer; A conductive structure that penetrates a portion of the logic chip and the sensing chip, and has a recess defined by the inner surface of the conductive structure; as well as A passivation layer is formed in the recess and covers the inner surface of the conductive structure. in: The first circuit layer includes a first wiring pattern, and the second circuit layer includes a second wiring pattern. The conductive structure is in direct contact with at least one of the first wiring patterns in the first circuit layer and in direct contact with at least one of the second wiring patterns in the second circuit layer. The thickness of the intermediary component is in the range of 50 μm to 300 μm in a first direction, which is perpendicular to the bottom surface of the intermediary component. The logic chip is disposed between the intermediary and the sensing chip along the first direction. The second path contacts the first wiring pattern to which the conductive structure in the first wiring pattern is connected. The conductive structure is interposed between the first wiring pattern and the passivation layer, and The recess is filled with the passivation layer provided on the inner surface of the conductive structure.

11. The sensor device of claim 10, wherein: The logic chip includes a second path, which is connected to and penetrates the first wiring pattern. The first path electrically connects the lower pad to the redistribution pattern, and The second path electrically connects the first wiring pattern to the redistribution pattern.

12. The sensor device of claim 10, further comprising a microlens on the top surface of the image sensor chip. in, When viewed from above, the conductive structure is located between the side surface of the image sensor chip and the microlens.

13. The sensor device of claim 10, wherein, When viewed from above, the conductive structure is located in the edge region of the image sensor chip.

14. The sensor device of claim 10, wherein the width of the intermediary is equal to the width of the image sensor chip.

15. The sensor device of claim 10, further comprising: The substrate electrically connected to the lower pad; A support, which is on the substrate and, when viewed from above, is spaced apart from the pixels of the image sensor chip; as well as A transparent cover on the bracket.

16. The sensor device of claim 10, further comprising a memory chip in the intermediary, in: The intermediary also includes a third path electrically connecting the memory chip to the redistribution pattern, and The first path is spaced apart from the memory chip.

17. A sensor device, comprising: An intermediary component includes a lower pad and a first passage connected to the lower pad, the lower pad being on the bottom surface of the intermediary component, and the first passage extending in a first direction. A redistribution layer on the top surface of the intermediary, the redistribution layer comprising a redistribution pattern; An image sensor chip stacked on the top surface of the redistribution layer, the image sensor chip including a logic chip and a sensing chip stacked on the logic chip, the logic chip including a first circuit layer and a second path, and the sensing chip including a second circuit layer; Color filters and microlenses on the top surface of the image sensor chip; A conductive structure that penetrates a portion of the logic chip and the sensing chip and has a recess defined by the inner surface of the conductive structure; as well as A passivation layer is formed in the recess and covers the inner surface of the conductive structure. in: The first circuit layer includes a first wiring pattern, and the second circuit layer includes a second wiring pattern. The conductive structure is in direct contact with at least one of the first wiring patterns in the first circuit layer and at least one of the second wiring patterns in the second circuit layer. The first connection pad in the upper portion of the first circuit layer is electrically connected to the second connection pad in the lower portion of the second circuit layer. The first path is electrically connected to the redistribution pattern. The second path is electrically connected to the first wiring pattern and the redistribution pattern. The thickness of the intermediary in the first direction is in the range of 50 μm to 300 μm. The logic chip is disposed between the intermediary and the sensing chip along the first direction. The second path contacts the first wiring pattern that directly contacts the conductive structure in the first wiring pattern. The conductive structure is interposed between the first wiring pattern and the passivation layer, and The recess is filled with the passivation layer provided on the inner surface of the conductive structure.

18. The sensor device of claim 17, further comprising: The substrate electrically connected to the lower pad; The support is on the substrate and, when viewed from above, is spaced apart from the pixels of the image sensor chip; as well as A transparent cover on the bracket.

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