Display device and method of manufacturing a display device

Abstract

A display device and a method of manufacturing a display device are disclosed. The display device includes a substrate; a first active layer on the substrate; a first insulating layer on the first active layer; a first gate electrode on the first insulating layer, the first gate electrode overlapping the first active layer; a second insulating layer on the first gate electrode; a second active layer on the second insulating layer; a first capacitor electrode on the second insulating layer, the first capacitor electrode overlapping the first gate electrode; a third insulating layer on the second active layer and the first capacitor electrode; a second gate electrode on the third insulating layer, the second gate electrode overlapping the second active layer; and a second capacitor electrode on the third insulating layer, the second capacitor electrode overlapping the first gate electrode and electrically connected to the first capacitor electrode.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a display apparatus including a display substrate including a transistor and a capacitor, and a method of manufacturing a display apparatus. BACKGROUND

[0002] A display apparatus is an apparatus that displays an image for providing visual information to a user. Recently, an organic light emitting display apparatus has attracted attention in display apparatuses.

[0003] An organic light emitting display apparatus has a self-light emitting characteristic, and unlike a liquid crystal display apparatus, the organic light emitting display apparatus does not require a separate light source, thereby reducing thickness and weight. The organic light emitting display apparatus exhibits high quality characteristics such as low power consumption, high brightness, and high response speed.

[0004] Generally, an organic light emitting display apparatus can include a plurality of pixels. Each of the pixels can include a pixel circuit electrically connected to a gate line and a data line, and an organic light emitting element electrically connected to the pixel circuit. Recently, as high resolution display apparatuses are developed, a space for arranging the pixel circuit has become narrow.

[0005] It is to be understood that the background technique section partially aims to provide a useful background of the technology. However, the background technique section can also include ideas, concepts or recognitions that are not part of the prior art known or understood by those skilled in the art before the respective effective filing date of the subject matter disclosed herein. SUMMARY

[0006] Embodiments can provide a display apparatus in which characteristics of a transistor and a capacitor can be improved.

[0007] Embodiments can provide a method of manufacturing a display apparatus to reduce manufacturing costs and time.

[0008] A display apparatus according to an embodiment can include a substrate, a first active layer disposed on the substrate, a first insulating layer disposed on the first active layer, and a first gate electrode disposed on the first insulating layer, the first gate electrode overlapping the first active layer. The display apparatus can include a second insulating layer disposed on the first gate electrode, a second active layer disposed on the second insulating layer, and a first capacitor electrode disposed on the second insulating layer, the first capacitor electrode overlapping the first gate electrode. The display apparatus can include a third insulating layer disposed on the second active layer and the first capacitor electrode, a second gate electrode disposed on the third insulating layer, the second gate electrode overlapping the second active layer, and a second capacitor electrode disposed on the third insulating layer, the second capacitor electrode overlapping the first gate electrode and electrically connected to the first capacitor electrode.

[0009] In an embodiment, the first capacitor electrode and the second active layer can include the same material.

[0010] In an embodiment, the first active layer can include polysilicon.

[0011] In an embodiment, the second insulating layer can include silicon nitride.

[0012] In an embodiment, a dielectric constant of the second insulating layer can be greater than a dielectric constant of the third insulating layer.

[0013] In an embodiment, the second active layer and the first capacitor electrode can each include an oxide semiconductor.

[0014] In an embodiment, the third insulating layer can include silicon oxide.

[0015] In an embodiment, a hydrogen content of the third insulating layer can be less than a hydrogen content of the second insulating layer.

[0016] In an embodiment, the second capacitor electrode can not overlap the first capacitor electrode.

[0017] In an embodiment, the second capacitor electrode can overlap the first capacitor electrode.

[0018] In an embodiment, the display device can further include a fourth insulating layer provided over the second gate electrode and the second capacitor electrode, and a connection electrode provided over the fourth insulating layer, the connection electrode electrically connecting the second capacitor electrode and the first capacitor electrode.

[0019] In an embodiment, a constant voltage can be applied to the connection electrode.

[0020] In an embodiment, the display device can further include a first source electrode and a first drain electrode provided over the fourth insulating layer and electrically connected to the first active layer, and a second source electrode and a second drain electrode provided over the fourth insulating layer and electrically connected to the second active layer. The connection electrode, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode can be provided over the same layer.

[0021] In an embodiment, the display device can further include a pixel electrode electrically connected to the first source electrode or the first drain electrode, an emission layer provided over the pixel electrode, and a counter electrode provided over the emission layer.

[0022] In an embodiment, the display device can further include a lower electrode provided between the first insulating layer and the second insulating layer, the lower electrode overlapping the second active layer.

[0023] In an embodiment, the lower electrode can be electrically connected to the second gate electrode.

[0024] A method of manufacturing a display device according to an embodiment can include forming a first active layer over a substrate; forming a first insulating layer over the first active layer; forming a first gate electrode over the first insulating layer, the first gate electrode overlapping the first active layer; and forming a second insulating layer over the first gate electrode. The method can include forming a second active layer over the second insulating layer; forming a first capacitor electrode over the second insulating layer, the first capacitor electrode overlapping the first gate electrode; and forming a third insulating layer over the second active layer and the first capacitor electrode. The method can include forming a second gate electrode over the third insulating layer, the second gate electrode overlapping the second active layer; and forming a second capacitor electrode over the third insulating layer, the second capacitor electrode overlapping the first gate electrode and electrically connected to the first capacitor electrode.

[0025] In an embodiment, the forming of the second active layer and the forming of the first capacitor electrode can be performed simultaneously. The forming of the second gate electrode and the forming of the second capacitor electrode can be performed simultaneously.

[0026] In an embodiment, the forming of the second active layer and the forming of the first capacitor electrode can include forming an oxide semiconductor layer over the second insulating layer; etching the oxide semiconductor layer to form the second active layer and the first capacitor electrode; and implanting impurities into the second active layer and the first capacitor electrode using the second gate electrode and the second capacitor electrode as a mask.

[0027] In an embodiment, the forming of the second gate electrode and the forming of the second capacitor electrode can include forming a conductive layer over the third insulating layer; and etching the conductive layer to form the second gate electrode and the second capacitor electrode.

[0028] In an embodiment, the method can further include forming a fourth insulating layer over the second gate electrode and the second capacitor electrode; forming a first contact hole in the third insulating layer and the fourth insulating layer, the first contact hole exposing the first capacitor electrode; forming a second contact hole in the fourth insulating layer, the second contact hole exposing the second capacitor electrode; and forming a connection electrode over the fourth insulating layer, the connection electrode filling the first contact hole and the second contact hole.

[0029] In an embodiment, the forming of the first contact hole and the forming of the second contact hole are performed simultaneously.

[0030] In an embodiment, the method can further include forming a lower electrode between the first insulating layer and the second insulating layer, the lower electrode overlapping the second active layer.

[0031] In an embodiment, the forming of the first gate electrode and the forming of the lower electrode are performed simultaneously.

[0032] A display device according to an embodiment can include a substrate and a first transistor including: a first active layer disposed on the substrate; a first insulating layer disposed on the first active layer; and a first gate electrode disposed on the first insulating layer, the first gate electrode overlapping the first active layer. The display device can include a capacitor including: the first gate electrode; a second insulating layer disposed on the first gate electrode; a first capacitor electrode disposed on the second insulating layer, the first capacitor electrode overlapping the first gate electrode; a third insulating layer disposed on the first capacitor electrode; and a second capacitor electrode disposed on the third insulating layer, the second capacitor electrode overlapping the first gate electrode and electrically connected to the first capacitor electrode. The display device can include a second transistor including: a second active layer disposed between the second insulating layer and the third insulating layer, the second active layer and the first capacitor electrode including the same material; the third insulating layer; and a second gate electrode disposed on the third insulating layer, the second gate electrode overlapping the second active layer.

[0033] In an embodiment, the first active layer can include polycrystalline silicon.

[0034] In an embodiment, the second active layer and the first capacitor electrode can each include an oxide semiconductor.

[0035] In an embodiment, the second transistor can further include a lower electrode disposed between the first insulating layer and the second insulating layer, the lower electrode overlapping the second active layer.

[0036] In an embodiment, the lower electrode can be electrically connected to the second gate electrode.

[0037] A display device according to an embodiment can include: a first active layer; a first gate electrode overlapping the first active layer, the first gate electrode being insulated from the first active layer; and a first capacitor electrode overlapping a first portion of the first gate electrode, the first capacitor electrode being insulated from the first gate electrode. The display device can include: a second active layer not overlapping the first gate electrode, the second active layer and the first capacitor electrode including the same material; a second gate electrode overlapping the second active layer, the second gate electrode being insulated from the second active layer; and a second capacitor electrode overlapping a second portion of the first gate electrode, the second capacitor electrode being insulated from the first gate electrode and electrically connected to the first capacitor electrode.

[0038] In an embodiment, the second capacitor electrode can not overlap the first capacitor electrode.

[0039] In an embodiment, the second capacitor electrode can overlap the first capacitor electrode.

[0040] In an embodiment, the display apparatus can further include a connection electrode overlapping the first and second capacitor electrodes, the connection electrode electrically connecting the second capacitor electrode and the first capacitor electrode.

[0041] The display apparatus according to an embodiment can include a second transistor including a second active layer and a second gate electrode, a third insulating layer disposed between the second active layer and the second gate electrode, and a capacitor including a first gate electrode and a first capacitor electrode, a second insulating layer disposed between the first gate electrode and the first capacitor electrode. Thus, a threshold voltage of the second transistor can be reduced, and a capacitance of the capacitor can be increased.

[0042] In a method of manufacturing a display apparatus according to an embodiment, the second active layer of the second transistor and the first capacitor electrode of the capacitor can be disposed on the second insulating layer substantially simultaneously, so that the number of photolithography processes for forming the second transistor and the capacitor can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0043] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0044] Figure 1 FIG. 1 is a schematic plan view illustrating a display apparatus according to an embodiment of the present application.

[0045] Figure 2 FIG. 2 is a schematic circuit diagram illustrating a pixel according to an embodiment of the present application.

[0046] Figure 3 FIG. 3 is a schematic cross-sectional view illustrating a display substrate according to an embodiment of the present application.

[0047] Figure 4 FIG. 4 is a schematic plan view illustrating a portion of the display substrate in FIG. 1. Figure 3

[0048] Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 FIG. 6 is a schematic view illustrating a method of manufacturing a display substrate according to an embodiment of the present application.

[0049] Figure 13 FIG. 7 is a schematic cross-sectional view illustrating a display substrate according to an embodiment of the present application.

[0050] Figure 14 FIG. 8 is a schematic cross-sectional view illustrating a method of manufacturing a display substrate according to an embodiment of the present application.

[0051] ​​​​​​​​Figure 15 is a schematic cross-sectional view illustrating a display substrate according to an embodiment of the present application.

[0052] Figure 16 is a schematic cross-sectional view illustrating a display substrate according to an embodiment of the present application.

[0053] Figure 17 is a schematic cross-sectional view illustrating a display apparatus according to an embodiment of the present application.

[0054] Figure 18 is a schematic circuit diagram illustrating a pixel according to an embodiment of the present application. DETAILED DESCRIPTION

[0055] Hereinafter, a display apparatus according to an embodiment and a method of manufacturing the display apparatus will be described in detail with reference to the accompanying drawings.

[0056] In the drawings, the size of some components can be exaggerated, omitted, or simplified for illustration purposes.

[0057] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term "and / or" is intended to include both the term "and" and the term "or," such that "A and / or B" means "A, B, or A and B." The terms "and" and "or" can be used in either a conjunctive or a disjunctive sense and can be understood to be equivalent to "and / or," depending on the context.

[0058] The term "overlapped" can include layers, stacks, faces or facing, extending above, extending below, covering or partially covering, or any other suitable term that would be recognized and understood by one of ordinary skill in the art. The phrase "not overlapped" can include "separated from" or "placed outside of" or "offset from" and any other suitable equivalent that would be recognized and understood by one of ordinary skill in the art.

[0059] For purposes of meaning and interpretation, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0060] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in the specification.

[0061] Figure 1This is a schematic plan view illustrating a display device according to an embodiment of the present invention.

[0062] See Figure 1 The display device 200 according to an embodiment of the present invention may include a plurality of pixels PX. The pixels PX may be arranged in a generally matrix form along the row and column directions. The display device 200 may display an image as a combination of light emitted from each of the pixels PX.

[0063] Figure 2 This is a schematic circuit diagram illustrating pixels according to an embodiment of the present invention. For example, Figure 2 It can be shown Figure 1 An example of a pixel PX is shown.

[0064] See Figure 2 According to embodiments of the present invention, a pixel PX may include a pixel circuit PC and a light-emitting element LE electrically connected to the pixel circuit PC. The pixel circuit PC may provide a drive current to the light-emitting element LE. The light-emitting element LE may emit light based on the drive current provided from the pixel circuit PC. The pixel circuit PC may include at least one transistor and at least one capacitor to generate the drive current.

[0065] In an embodiment, the pixel circuit PC may include a first transistor TR1, a second transistor TR2, and a capacitor CAP.

[0066] The gate electrode of the first transistor TR1 can be electrically connected to the first node N1. A first power supply voltage VDD can be applied to the source electrode of the first transistor TR1, and the drain electrode of the first transistor TR1 can be electrically connected to the light-emitting element LE. The first transistor TR1 can generate a drive current based on the voltage between the gate electrode and the source electrode, and can transmit the drive current to the light-emitting element LE.

[0067] A gate signal GS can be applied to the gate electrode of the second transistor TR2. A data signal DS can be applied to the source electrode of the second transistor TR2, and the drain electrode of the second transistor TR2 can be electrically connected to the first node N1. The second transistor TR2 can transmit the data signal DS to the first node N1 based on the gate signal GS.

[0068] A first power supply voltage VDD can be applied to the first electrode of capacitor CAP, and the second electrode of capacitor CAP can be electrically connected to the first node N1. When the second transistor TR2 is off, capacitor CAP can maintain the voltage between the gate electrode and the source electrode of the first transistor TR1, so that the light-emitting element LE can emit light.

[0069] The first electrode of the light emitting element LE can be electrically connected to the pixel circuit PC, and a second power supply voltage VSS can be applied to the second electrode of the light emitting element LE. In an embodiment, the second power supply voltage VSS can be less than the first power supply voltage VDD. The light emitting element LE can emit light based on a driving current transmitted from the pixel circuit PC.

[0070] Figure 3 is a schematic cross-sectional view illustrating a display substrate according to an embodiment of the present application. For example, Figure 3 The display substrate illustrated in Figure 2 The pixel circuit PC illustrated in Figure 4 is a schematic plan view illustrating a portion of the display substrate in Figure 3 For example, Figure 4 may illustrate Figure 3 The first transistor TR1 and the capacitor CAP illustrated in

[0071] Referring to Figure 3 and Figure 4 The display substrate 100 according to an embodiment of the present application can include a first transistor TR1, a second transistor TR2, and a capacitor CAP which can be disposed on a substrate SUB.

[0072] The substrate SUB can be an insulating substrate including glass, quartz, plastic, or the like, or a combination thereof. In an embodiment, the substrate SUB can include a first flexible layer, a first barrier layer disposed on the first flexible layer, a second flexible layer disposed on the first barrier layer, and a second barrier layer disposed on the second flexible layer. The first flexible layer and the second flexible layer can include an organic insulating material, such as polyimide (PI), or the like, and the first barrier layer and the second barrier layer can include an inorganic insulating material, such as silicon oxide, silicon nitride, amorphous silicon, or the like, or a combination thereof.

[0073] A buffer layer BUF can be disposed on the substrate SUB. The buffer layer BUF can block impurities, such as oxygen, moisture, or the like, from permeating above the substrate SUB through the substrate SUB. The buffer layer BUF can provide a planarized upper surface above the substrate SUB. The buffer layer BUF can include an inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination thereof.

[0074] A first active layer 110 can be disposed on the buffer layer BUF. In an embodiment, the first active layer 110 can include polysilicon.

[0075] The first active layer 110 can include a first source region, a first drain region, and a first channel region provided between the first source region and the first drain region. The first source region and the first drain region can be doped with a P-type or N-type impurity. In a plan view, the first channel region can have a curved shape such as an "S", a "U", or the like. Thus, the first active layer 110 can have the first channel region having a relatively large length in a limited space. Accordingly, a driving range of the first transistor TR1 including the first active layer 110 can be increased.

[0076] The first insulating layer 120 can be provided on the first active layer 110. The first insulating layer 120 can be provided on the buffer layer BUF and can cover the first active layer 110. The first insulating layer 120 can insulate the first gate electrode 131 provided on the first active layer 110 from the first active layer 110. The first insulating layer 120 can include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination thereof.

[0077] The first gate electrode 131 can be provided on the first insulating layer 120. The first gate electrode 131 can overlap the first channel region of the first active layer 110. The first gate electrode 131 can include a conductive material such as molybdenum (Mo), copper (Cu), or the like, or a combination thereof. The first active layer 110 including the first source region, the first drain region, and the first channel region, the first insulating layer 120, and the first gate electrode 131 can form the first transistor TR1.

[0078] The second insulating layer 140 can be provided on the first gate electrode 131. The second insulating layer 140 can be provided on the first insulating layer 120 and can cover the first gate electrode 131. The second insulating layer 140 can insulate the first capacitor electrode 152 provided on the first gate electrode 131 from the first gate electrode 131. In an embodiment, the second insulating layer 140 can include silicon nitride.

[0079] The second active layer 151 and the first capacitor electrode 152 can be provided on the second insulating layer 140. The second active layer 151 can not overlap the first gate electrode 131. The first capacitor electrode 152 can be spaced apart from the second active layer 151 and can overlap the first gate electrode 131. Specifically, the first capacitor electrode 152 can overlap a first portion of the first gate electrode 131. The second active layer 151 and the first capacitor electrode 152 can include substantially the same material. In an embodiment, the second active layer 151 and the first capacitor electrode 152 can include an oxide semiconductor. For example, the oxide semiconductor can include indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), or the like, or a combination thereof.

[0080] The second active layer 151 can include a second source region, a second drain region, and a second channel region disposed between the second source region and the second drain region. The second source region and the second drain region can be doped with a P-type or N-type impurity. Also, the first capacitor electrode 152 can be doped with a P-type or N-type impurity. For example, the first capacitor electrode 152 can be doped with an impurity of the same type as the impurities of the second source region and the second drain region of the second active layer 151. Since the first capacitor electrode 152 can be doped with an impurity, the first capacitor electrode 152 can be electrically conductive.

[0081] The third insulating layer 160 can be disposed on the second active layer 151 and the first capacitor electrode 152. The third insulating layer 160 can be disposed on the second insulating layer 140 and can cover the second active layer 151 and the first capacitor electrode 152. The third insulating layer 160 can insulate the second gate electrode 171 disposed on the second active layer 151 from the second active layer 151 and can insulate the second capacitor electrode 172 disposed on the first gate electrode 131 from the first gate electrode 131. In an embodiment, the third insulating layer 160 can include silicon oxide.

[0082] The second insulating layer 140 can have a relatively large dielectric constant. In an embodiment, the dielectric constant of the second insulating layer 140 can be greater than the dielectric constant of the third insulating layer 160. The dielectric constant of silicon nitride can be greater than the dielectric constant of silicon oxide, and in the case where the second insulating layer 140 and the third insulating layer 160 include silicon nitride and silicon oxide, respectively, the dielectric constant of the second insulating layer 140 can be greater than the dielectric constant of the third insulating layer 160.

[0083] The third insulating layer 160 can have a relatively small hydrogen content. In an embodiment, the hydrogen content of the third insulating layer 160 can be less than the hydrogen content of the second insulating layer 140. The hydrogen content of silicon oxide can be less than the hydrogen content of silicon nitride, and in the case where the second insulating layer 140 and the third insulating layer 160 include silicon nitride and silicon oxide, respectively, the hydrogen content of the third insulating layer 160 can be less than the hydrogen content of the second insulating layer 140.

[0084] The second insulating layer 140 can have a relatively small thickness, and the third insulating layer 160 can have a relatively large thickness. In an embodiment, the thickness of the second insulating layer 140 can be less than the thickness of the third insulating layer 160.

[0085] The second gate electrode 171 and the second capacitor electrode 172 can be disposed on the third insulating layer 160. The second gate electrode 171 can overlap the second channel region of the second active layer 151. The second capacitor electrode 172 can be spaced apart from the second gate electrode 171 and can overlap the first gate electrode 131. Specifically, the second capacitor electrode 172 can overlap a second portion of the first gate electrode 131, which can be different from a first portion of the first gate electrode 131. The second capacitor electrode 172 can be electrically connected to the first capacitor electrode 152. The second gate electrode 171 and the second capacitor electrode 172 can include a conductive material, such as molybdenum (Mo), copper (Cu), or the like, or a combination thereof.

[0086] The second active layer 151 including the second source region, the second drain region, and the second channel region, the third insulating layer 160, and the second gate electrode 171 can form the second transistor TR2. The third insulating layer 160 disposed between the second active layer 151 and the second gate electrode 171 can include silicon oxide having a relatively small hydrogen content and can have a relatively large thickness, so that a threshold voltage of the second transistor TR2 can be reduced. Accordingly, characteristics of the second transistor TR2 can be improved.

[0087] In an embodiment, the second capacitor electrode 172 can not overlap the first capacitor electrode 152. In a case where impurities can be injected into the first capacitor electrode 152, the second capacitor electrode 172 can serve as a mask, and the impurities can not be injected into a portion of the first capacitor electrode 152 overlapping the second capacitor electrode 172. However, since the second capacitor electrode 172 does not overlap the first capacitor electrode 152, the impurities can be injected into the entire first capacitor electrode 152. Accordingly, the conductivity of the first capacitor electrode 152 can increase, and the first capacitor electrode 152 can serve as an electrode of the capacitor CAP.

[0088] The first gate electrode 131, the second insulating layer 140, and the first capacitor electrode 152, the third insulating layer 160, and the second capacitor electrode 172 can form the capacitor CAP. The first gate electrode 131 can serve as a lower capacitor electrode, and the first capacitor electrode 152 and the second capacitor electrode 172 electrically connected to each other can serve as an upper capacitor electrode. Further, the second insulating layer 140 can serve as a first dielectric layer between the first gate electrode 131 and the first capacitor electrode 152, and the second insulating layer 140 and the third insulating layer 160 can serve as a second dielectric layer between the first gate electrode 131 and the second capacitor electrode 172. The second insulating layer 140 disposed between the first gate electrode 131 and the first capacitor electrode 152 can include silicon nitride having a relatively large dielectric constant and can have a relatively small thickness, so that a capacitance of the capacitor CAP can increase. Accordingly, characteristics of the capacitor CAP can be improved.

[0089] The fourth insulating layer 180 can be disposed on the second gate electrode 171 and the second capacitor electrode 172. The fourth insulating layer 180 can be disposed on the third insulating layer 160 and can cover the second gate electrode 171 and the second capacitor electrode 172. The fourth insulating layer 180 can include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like or a combination thereof and / or an organic insulating material such as polyimide (PI) or the like.

[0090] The first source electrode 191, the first drain electrode 192, the second source electrode 193, the second drain electrode 194, and the connection electrode 195 can be disposed on the fourth insulating layer 180. The first source electrode 191 and the first drain electrode 192 can be electrically connected to a source region and a drain region of the first active layer 110, respectively. The second source electrode 193 and the second drain electrode 194 can be electrically connected to a source region and a drain region of the second active layer 151, respectively. The connection electrode 195 can overlap the first capacitor electrode 152 and the second capacitor electrode 172 and can connect the second capacitor electrode 172 to the first capacitor electrode 152. The connection electrode 195 can contact the first capacitor electrode 152 through a first contact hole CH1 disposed (e.g., formed) in the third insulating layer 160 and the fourth insulating layer 180 and can contact the second capacitor electrode 172 through a second contact hole CH2 disposed in the fourth insulating layer 180. The first source electrode 191, the first drain electrode 192, the second source electrode 193, the second drain electrode 194, and the connection electrode 195 can include a conductive material such as aluminum (Al), titanium (Ti), copper (Cu), or the like or a combination thereof.

[0091] In an embodiment, a constant voltage can be applied to the connection electrode 195. For example, Figure 2 The first power supply voltage VDD shown in FIG. 1B can be applied to the connection electrode 195. Thereby, the first power supply voltage VDD can be applied to the first capacitor electrode 152 and the second capacitor electrode 172 of the capacitor CAP which can be electrically connected to the connection electrode 195.

[0092] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 are schematic diagrams illustrating a method of manufacturing a display substrate according to an embodiment of the present application. For example, Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12A method of manufacturing a display substrate 100 in Figure 3 and Figure 4 may be shown.

[0093] Referring to Figure 5 and Figure 6 , a first active layer 110 can be disposed (e.g., formed) on a substrate SUB.

[0094] A buffer layer BUF can be disposed on the substrate SUB. For example, an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, or a combination thereof can be deposited on the substrate SUB using chemical vapor deposition such as PECVD to form the buffer layer BUF.

[0095] The first active layer 110 can be disposed on the buffer layer BUF. For example, amorphous silicon can be deposited on the buffer layer BUF using chemical vapor deposition such as PECVD to form an amorphous silicon layer, and the amorphous silicon layer can be crystallized by an excimer layer or the like to form a polysilicon layer. The polysilicon layer can be etched to form the first active layer 110.

[0096] Referring to Figure 7 and Figure 8 , a first insulating layer 120 can be disposed on the first active layer 110, and a first gate electrode 131 can be disposed on the first insulating layer 120.

[0097] The first insulating layer 120 can be disposed on the first active layer 110. For example, an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, or a combination thereof can be deposited on the first active layer 110 using chemical vapor deposition such as PECVD to form the first insulating layer 120.

[0098] The first gate electrode 131 can be disposed on the first insulating layer 120. For example, a conductive material such as molybdenum (Mo), copper (Cu), or the like, or a combination thereof can be deposited on the first insulating layer 120 using physical vapor deposition such as sputtering to form a conductive layer, and the conductive layer can be etched to form the first gate electrode 131. The first gate electrode 131 can overlap (e.g., overlap with a portion of) the first active layer 110.

[0099] Impurities can be implanted into the first active layer 110. The first gate electrode 131 overlapping a portion of the first active layer 110 can be used as a mask to implant impurities into the first active layer 110. Thereby, impurities can be implanted into a portion of the first active layer 110 that does not overlap the first gate electrode 131 to form a first source region and a first drain region, and impurities can not be implanted into a portion of the first active layer 110 that overlaps the first gate electrode 131 to form a first channel region.

[0100] Referring toFigure 9 and Figure 10 The second insulating layer 140 can be disposed on the first gate electrode 131, and the second active layer 151 and the first capacitor electrode 152 can be disposed (e.g., substantially simultaneously) on the second insulating layer 140.

[0101] The second insulating layer 140 can be disposed on the first gate electrode 131. For example, silicon nitride can be deposited on the first gate electrode 131 using chemical vapor deposition, such as PECVD, to form the second insulating layer 140.

[0102] The second active layer 151 and the first capacitor electrode 152 can be disposed on the second insulating layer 140. For example, an oxide semiconductor, such as indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), or the like, can be deposited on the second insulating layer 140 using chemical vapor deposition, such as PECVD, to form an oxide semiconductor layer, and the oxide semiconductor layer can be etched to form the second active layer 151 and the first capacitor electrode 152. The first capacitor electrode 152 can overlap the first gate electrode 131.

[0103] Since the second active layer 151 and the first capacitor electrode 152 can be substantially simultaneously disposed on the second insulating layer 140, an additional process for forming the first capacitor electrode 152 can not be needed. Thus, the number of photolithography processes for forming the second transistor TR2 and the capacitor CAP can be reduced.

[0104] Referring to Figure 11 and Figure 12 The third insulating layer 160 can be disposed on the second active layer 151 and the first capacitor electrode 152, and the second gate electrode 171 and the second capacitor electrode 172 can be disposed (e.g., substantially simultaneously) on the third insulating layer 160.

[0105] The third insulating layer 160 can be disposed on the second active layer 151 and the first capacitor electrode 152. For example, silicon oxide can be deposited on the second active layer 151 and the first capacitor electrode 152 using chemical vapor deposition, such as PECVD, to form the third insulating layer 160.

[0106] The second gate electrode 171 and the second capacitor electrode 172 can be disposed on the third insulating layer 160. For example, a conductive material such as molybdenum (Mo), copper (Cu), or the like, or a combination thereof can be deposited on the third insulating layer 160 using physical vapor deposition such as sputtering to form a conductive layer, and the conductive layer can be etched to form the second gate electrode 171 and the second capacitor electrode 172. The second gate electrode 171 can overlap (e.g., overlap with a portion of) the second active layer 151. The second capacitor electrode 172 can overlap with the first gate electrode 131 and can not overlap with the first capacitor electrode 152.

[0107] Impurities can be implanted into the second active layer 151 and the first capacitor electrode 152. The second gate electrode 171 overlapping with a portion of the second active layer 151 and the second capacitor electrode 172 not overlapping with the first capacitor electrode 152 can be used as a mask to implant impurities into the second active layer 151 and the first capacitor electrode 152. Thereby, impurities can be implanted into a portion of the second active layer 151 not overlapping with the second gate electrode 171 to form a second source region and a second drain region, and impurities can not be implanted into a portion of the second active layer 151 overlapping with the second gate electrode 171 to form a second channel region. In addition, impurities can be implanted into the entire first capacitor electrode 152 not overlapping with the second capacitor electrode 172, such that the first capacitor electrode 152 can become conductive.

[0108] Since the second gate electrode 171 and the second capacitor electrode 172 can be substantially simultaneously disposed on the third insulating layer 160, an additional process for forming the second gate electrode 171 can not be needed. Thereby, the number of photolithography processes for forming the second transistor TR2 and the capacitor CAP can be reduced.

[0109] Referring to Figure 3 and Figure 4 , the fourth insulating layer 180 can be disposed on the second gate electrode 171 and the second capacitor electrode 172, and the first source electrode 191, the first drain electrode 192, the second source electrode 193, the second drain electrode 194, and the connection electrode 195 can be disposed (e.g., substantially simultaneously disposed) on the fourth insulating layer 180.

[0110] The fourth insulating layer 180 can be disposed on the second gate electrode 171 and the second capacitor electrode 172. For example, an inorganic insulating material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, or a combination thereof can be deposited on the second gate electrode 171 and the second capacitor electrode 172, or an organic insulating material such as polyimide or the like can be coated on the second gate electrode 171 and the second capacitor electrode 172 to form the fourth insulating layer 180.

[0111] A contact hole that passes through the fourth insulating layer 180 can be disposed (e.g., formed). For example, the first insulating layer 120, the second insulating layer 140, the third insulating layer 160, and the fourth insulating layer 180 can be etched using a first mask to form contact holes that overlap with source and drain regions of the first active layer 110, respectively. In addition, the third insulating layer 160 and the fourth insulating layer 180 can be etched using a second mask to form contact holes that overlap with source and drain regions of the second active layer 151, respectively. A first contact hole CH1 that overlaps with the first capacitor electrode 152 can be disposed by etching the third insulating layer 160 and the fourth insulating layer 180 using the second mask, and a second contact hole CH2 that overlaps with the second capacitor electrode 172 can be disposed by etching the fourth insulating layer 180 using the second mask. In other words, the first contact hole CH1 and the second contact hole CH2 can be disposed substantially simultaneously with the contact holes that overlap with the source and drain regions of the second active layer 151, respectively.

[0112] The first source electrode 191, the first drain electrode 192, the second source electrode 193, the second drain electrode 194, and the connection electrode 195 can be disposed on the fourth insulating layer 180. For example, a conductive material such as aluminum (Al), titanium (Ti), copper (Cu), or the like, or a combination thereof can be deposited on the fourth insulating layer 180 using physical vapor deposition such as sputtering to form a conductive layer, and the conductive layer can be etched to form the first source electrode 191, the first drain electrode 192, the second source electrode 193, the second drain electrode 194, and the connection electrode 195. The first source electrode 191 and the first drain electrode 192 can fill the contact holes that pass through the first insulating layer 120, the second insulating layer 140, the third insulating layer 160, and the fourth insulating layer 180, and can be electrically connected to the source and drain regions of the first active layer 110, respectively. The second source electrode 193 and the second drain electrode 194 can fill the contact holes that pass through the third insulating layer 160 and the fourth insulating layer 180, and can be electrically connected to the source and drain regions of the second active layer 151, respectively. The connection electrode 195 can fill the first contact hole CH1 that passes through the third insulating layer 160 and the fourth insulating layer 180 and the second contact hole CH2 that passes through the fourth insulating layer 180, and can be electrically connected to the first capacitor electrode 152 and the second capacitor electrode 172. The connection electrode 195 can contact the first capacitor electrode 152 and the second capacitor electrode 172 through the first contact hole CH1 and the second contact hole CH2, respectively, such that the second capacitor electrode 172 can be electrically connected to the first capacitor electrode 152.

[0113] Figure 13 is a schematic cross-sectional view illustrating a display substrate according to an embodiment of the present application. For example, Figure 13 The display substrate illustrated in FIG. 1A can include Figure 2 The pixel circuit PC illustrated in FIG. 1A.

[0114] Referring to Figure 13 , the display substrate 101 according to an embodiment of the present application can include the first transistor TR1, the second transistor TR2, and the capacitor CAP which can be disposed on the substrate SUB. The display substrate 101 described with reference to Figure 13 may be substantially the same as or similar to the display substrate 100 described with reference to Figure 3 . Thus, a description of elements which can be substantially the same as or similar to those of the display substrate 101 described with reference to Figure 13 may be omitted. Figure 3

[0115] The lower electrode 132 can be disposed between the first insulating layer 120 and the second insulating layer 140. The lower electrode 132 can overlap the second active layer 151. The lower electrode 132 and the first gate electrode 131 can include substantially the same material.

[0116] In an embodiment, the lower electrode 132 can be electrically connected to the second gate electrode 171. In such an embodiment, the lower electrode 132 can serve as a lower gate electrode of the second transistor TR2, and the second gate electrode 171 can serve as an upper gate electrode of the second transistor TR2. In other words, the second transistor TR2 can have a dual-gate structure.

[0117] In an embodiment, no electrical signal can be applied to the lower electrode 132, and the lower electrode 132 can serve as a light-shielding layer for blocking light incident from below the display substrate 101 toward the second active layer 151. In the case where the second active layer 151 is irradiated with light, a leakage current can occur, so that reliability of the second transistor TR2 can be reduced. In the case where the lower electrode 132 overlapping the second active layer 151 is disposed between the first insulating layer 120 and the second insulating layer 140, light incident toward the second active layer 151 can be blocked, so that the leakage current can be reduced.

[0118] Figure 14 is a schematic cross-sectional view illustrating a method of manufacturing a display substrate according to an embodiment of the present application. For example, Figure 14 may illustrate a method of manufacturing the display substrate 101 in Figure 13 .

[0119] The method of manufacturing the display substrate 101 described with reference to Figure 14 may be substantially the same as or similar to the method of manufacturing the display substrate 100 described with reference to Figures 5 to 12 . Thus, a description of elements which can be substantially the same as or similar to those of the method of manufacturing the display substrate 101 described with reference to Figure 14 may be omitted. Figures 5 to 12 ​The description of those elements of the method of manufacturing the display substrate 100 that are substantially the same or similar to the elements described above will be omitted.

[0120] Referring to Figure 14 , the first insulating layer 120 can be provided on the first active layer 110, and the first gate electrode 131 and the lower electrode 132 can be provided (e.g., substantially simultaneously provided) on the first insulating layer 120.

[0121] The first insulating layer 120 can be provided on the first active layer 110. The first gate electrode 131 and the lower electrode 132 can be provided on the first insulating layer 120. For example, a conductive material such as molybdenum (Mo), copper (Cu), or the like, or a combination thereof can be deposited on the first insulating layer 120 using physical vapor deposition such as sputtering to form a conductive layer, and the conductive layer can be etched to form the first gate electrode 131 and the lower electrode 132. The first gate electrode 131 can overlap (e.g., overlap with a portion of) the first active layer 110. Impurities can be implanted into the first active layer 110.

[0122] Figure 15 is a schematic cross-sectional view illustrating a display substrate according to an embodiment of the present application. For example, Figure 15 The display substrate illustrated in Figure 2 may include the pixel circuit PC illustrated in

[0123] Referring to Figure 15 , the display substrate 102 according to an embodiment of the present application can include a first transistor TR1, a second transistor TR2, and a capacitor CAP that can be provided on a substrate SUB. Except for the second capacitor electrode 172, referring to Figure 15 The display substrate 102 described can be substantially the same as or similar to the display substrate 100 described with reference to Figure 3 Thereby, the description of those elements of the display substrate 102 that are substantially the same as or similar to the elements described with reference to Figure 15 the display substrate 100 will be omitted. The description of those elements of the display substrate 102 that are substantially the same as or similar to the elements described with reference to Figure 3 the display substrate 100 will be omitted. The description of those elements of the display substrate 102 that are substantially the same as or similar to the elements described with reference to

[0124] In an embodiment, the second capacitor electrode 172 can overlap the first capacitor electrode 152. For example, the second capacitor electrode 172 can partially overlap the first capacitor electrode 152. In a case where impurities are implanted into the first capacitor electrode 152, impurities can not be implanted into a portion of the first capacitor electrode 152 that overlaps the second capacitor electrode 172. However, since the second capacitor electrode 172 overlaps the first capacitor electrode 152, a planar area of the capacitor CAP can be reduced and a resolution of the display substrate 102 can be increased.

[0125] Figure 16is a schematic cross-sectional view illustrating a display substrate according to an embodiment of the present application. For example, Figure 16 The display substrate illustrated in FIG. 1A can include Figure 2 The pixel circuit PC illustrated in FIG. 1A.

[0126] Referring to Figure 16 The display substrate 103 according to an embodiment of the present application can include a first transistor TR1, a second transistor TR2, and a capacitor CAP which can be disposed on a substrate SUB. The display substrate 103 described with reference to Figure 16 may be substantially the same as or similar to the display substrate 100 described with reference to Figure 3 Thus, a description of elements which can be substantially the same as or similar to those of the display substrate 100 described with reference to Figure 16 may be substantially the same as or similar to the display substrate 100 described with reference to Figure 3 Thus, a description of elements which can be substantially the same as or similar to those of the display substrate 100 described with reference to

[0127] The lower electrode BML can be disposed between the substrate SUB and the buffer layer BUF. The lower electrode BML can overlap the first active layer 110. The lower electrode BML can include a conductive material, such as molybdenum (Mo), copper (Cu), or the like, or a combination thereof.

[0128] In an embodiment, the lower electrode BML can be electrically connected to the first gate electrode 131. In such an embodiment, the lower electrode BML can function as a lower gate electrode of the first transistor TR1, and the first gate electrode 131 can function as an upper gate electrode of the first transistor TR1. In other words, the first transistor TR1 can have a dual-gate structure.

[0129] In an embodiment, no electrical signal can be applied to the lower electrode BML, and the lower electrode BML can function as a light-blocking layer for blocking light incident from below the display substrate 103 toward the first active layer 110. In the case where the first active layer 110 is irradiated with light, a leakage current can occur, such that reliability of the first transistor TR1 can be reduced. In the case where the lower electrode BML overlapping the first active layer 110 is disposed between the substrate SUB and the buffer layer BUF, light incident toward the first active layer 110 can be blocked, such that the leakage current can be reduced.

[0130] Figure 17 is a schematic cross-sectional view illustrating a display apparatus according to an embodiment of the present application. For example, Figure 17 The display apparatus illustrated in FIG. 2A can be Figure 1 the display apparatus 200 of FIG. 1A, and can include Figure 2 the pixel circuit PC and the light emitting element LE illustrated in FIG. 1A.

[0131] Referring to Figure 17The display apparatus 200 according to an embodiment of the present application can include a first transistor TR1, a second transistor TR2, a capacitor CAP, and a light emitting element LE which can be disposed on a substrate SUB. Figure 17 The display apparatus 200 including the display substrate 100 shown in FIG. 1 is illustrated, but the present application is not limited thereto, and the display apparatus 200 can include a display substrate 101 shown in FIG. 2, Figure 3 The display apparatus 200 including the display substrate 102 shown in FIG. 3, Figure 13 The display apparatus 200 including the display substrate 101 shown in FIG. 2, Figure 15 The display apparatus 200 including the display substrate 102 shown in FIG. 3, Figure 16 The display apparatus 200 including the display substrate 103 shown in FIG. 4.

[0132] A planarization layer PLA can be disposed on the first source electrode 191, the first drain electrode 192, the second source electrode 193, the second drain electrode 194, and the connection electrode 195. The planarization layer PLA can be disposed on the fourth insulating layer 180 and can cover the first source electrode 191, the first drain electrode 192, the second source electrode 193, the second drain electrode 194, and the connection electrode 195. The planarization layer PLA can provide a planarized upper surface over the display substrate. The planarization layer PLA can include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination thereof, and / or an organic insulating material such as polyimide (PI), or the like.

[0133] A pixel electrode 210 can be disposed on the planarization layer PLA. The pixel electrode 210 can be electrically connected to the first source electrode 191 or the first drain electrode 192. The pixel electrode 210 can contact the first source electrode 191 or the first drain electrode 192 through a contact hole disposed in the planarization layer PLA. The pixel electrode 210 can include a conductive material such as a metal, an alloy, a transparent conductive oxide, or the like, or a combination thereof. For example, the pixel electrode 210 can include silver (Ag), indium tin oxide (ITO), or the like, or a combination thereof.

[0134] A pixel definition layer PDL can be disposed on the pixel electrode 210. The pixel definition layer PDL can be disposed on the planarization layer PLA and can cover the pixel electrode 210. The pixel definition layer PDL can have a pixel opening that exposes at least a portion of the pixel electrode 210. In an embodiment, the pixel opening can expose a central portion of the pixel electrode 210 and the pixel definition layer PDL can cover a peripheral portion of the pixel electrode 210. The pixel definition layer PDL can include an organic insulating material such as polyimide (PI), or the like.

[0135] An emission layer 220 can be disposed on the pixel electrode 210. The emission layer 220 can be disposed on the pixel electrode 210 exposed by the pixel opening. The emission layer 220 can include at least one of an organic light emitting material and a quantum dot.

[0136] In an embodiment, the organic light emitting material can include a low molecular organic compound or a high molecular organic compound. For example, the low molecular organic compound can include copper phthalocyanine, diphenyl benzidine (N,N'-diphenyl benzidine), aluminum trihydroxyquinoline (tris-(8-hydroxyquinoline) aluminum), or the like or a combination thereof. The high molecular organic compound can include polyethylenedioxythiophene (poly(3,4-ethylenedioxythiophene)), polyaniline, polyphenylacetylene, polyfluorene, or the like or a combination thereof.

[0137] In an embodiment, the quantum dot can include a core including a Group II-VI compound, a Group III-V compound, a Group IV-VI compound, a Group IV element, a Group IV compound, or a combination thereof. In one embodiment, the quantum dot can have a core-shell structure including a core and a shell surrounding the core. The shell can prevent chemical degeneration of the core, thereby functioning as a protective layer for maintaining a semiconductor property and a charging layer for imparting an electrophoretic property to the quantum dot.

[0138] The counter electrode 230 can be disposed on the emission layer 220. In an embodiment, the counter electrode 230 can also be disposed on the pixel definition layer PDL. The counter electrode 230 can include a conductive material, such as a metal, an alloy, a transparent conductive oxide, or the like or a combination thereof. For example, the counter electrode 230 can include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), titanium (Ti), or the like or a combination thereof. The pixel electrode 210, the emission layer 220, and the counter electrode 230 can form a light emitting element LE.

[0139] The encapsulation layer 240 can be disposed on the counter electrode 230. The encapsulation layer 240 can cover the light emitting element LE to protect the light emitting element LE from impurities such as oxygen, moisture, or the like. The encapsulation layer 240 can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, the encapsulation layer 240 can include a first inorganic encapsulation layer disposed on the counter electrode 230, an organic encapsulation layer disposed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer. The inorganic encapsulation layer can include silicon nitride, silicon oxynitride, or the like or a combination thereof, and the organic encapsulation layer can include an epoxy-based resin, an acrylic-based resin, a polyimide-based resin, or the like or a combination thereof.

[0140] Figure 18 is a schematic circuit diagram illustrating a pixel according to an embodiment of the present application. For example, Figure 18 An example of the pixel PX shown in Figure 1 may be illustrated.

[0141] Referring to Figure 18According to an embodiment of the present invention, a pixel PX can include a pixel circuit PC and a light emitting element LE electrically connected to the pixel circuit PC. The pixel circuit PC can provide a driving current to the light emitting element LE. The light emitting element LE can emit light based on the driving current provided from the pixel circuit PC. The pixel circuit PC can include at least one transistor and at least one capacitor to generate the driving current.

[0142] In an embodiment, the pixel circuit PC can include a first transistor TR1, a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, a sixth transistor TR6, a seventh transistor TR7, and a capacitor CAP.

[0143] A gate electrode of the first transistor TR1 can be electrically connected to a first node N1. A source electrode of the first transistor TR1 can be electrically connected to a second node N2, and a drain electrode of the first transistor TR1 can be electrically connected to a third node N3. The first transistor TR1 can generate a driving current based on a voltage between the gate electrode and the source electrode.

[0144] A first gate signal GS1 can be applied to a gate electrode of the second transistor TR2. A data signal DS can be applied to a source electrode of the second transistor TR2, and a drain electrode of the second transistor TR2 can be electrically connected to the second node N2. The second transistor TR2 can transmit the data signal DS to the second node N2 based on the first gate signal GS1.

[0145] The first gate signal GS1 can be applied to a gate electrode of the third transistor TR3. A source electrode of the third transistor TR3 can be electrically connected to the first node N1, and a drain electrode of the third transistor TR3 can be electrically connected to the third node N3. The third transistor TR3 can connect the gate electrode and the drain electrode of the first transistor TR1 based on the first gate signal GS1 to compensate for a threshold voltage of the first transistor TR1.

[0146] A second gate signal GS2 can be applied to a gate electrode of the fourth transistor TR4. In an embodiment, in a case where the pixel PX is included in an Nth pixel row, the second gate signal GS2 can be a first gate signal applied to an (N-1)th pixel row. An initialization voltage VINT can be applied to a source electrode of the fourth transistor TR4, and a drain electrode of the fourth transistor TR4 can be electrically connected to the first node N1. The fourth transistor TR4 can transmit the initialization voltage VINT to the first node N1 based on the second gate signal GS2 to initialize the gate electrode of the first transistor TR1.

[0147] The emission control signal EM can be applied to the gate electrode of the fifth transistor TR5. The first power supply voltage VDD can be applied to the source electrode of the fifth transistor TR5, and the drain electrode of the fifth transistor TR5 can be electrically connected to the second node N2.

[0148] The emission control signal EM can be applied to the gate electrode of the sixth transistor TR6. The source electrode of the sixth transistor TR6 can be electrically connected to the third node N3, and the drain electrode of the sixth transistor TR6 can be electrically connected to the light emitting element LE. The fifth transistor TR5 and the sixth transistor TR6 can transmit the generated drive current from the first transistor TR1 to the light emitting element LE based on the emission control signal EM.

[0149] The third gate signal GS3 can be applied to the gate electrode of the seventh transistor TR7. In an embodiment, in a case where the pixel PX is included in the Nth pixel row, the third gate signal GS3 can be the first gate signal applied to the (N+1)th pixel row. The initialization voltage VINT can be applied to the source electrode of the seventh transistor TR7, and the drain electrode of the seventh transistor TR7 can be electrically connected to the light emitting element LE. The seventh transistor TR7 can transmit the initialization voltage VINT to the light emitting element LE based on the third gate signal GS3 to initialize the light emitting element LE.

[0150] The first power supply voltage VDD can be applied to the first electrode of the capacitor CAP, and the second electrode of the capacitor CAP can be electrically connected to the first node N1. In a case where the second transistor TR2 is cut off, the capacitor CAP can maintain the voltage between the gate electrode and the source electrode of the first transistor TR1, so that the light emitting element LE can emit light.

[0151] The first electrode of the light emitting element LE can be electrically connected to the pixel circuit PC, and the second power supply voltage VSS can be applied to the second electrode of the light emitting element LE. In an embodiment, the second power supply voltage VSS can be less than the first power supply voltage VDD. The light emitting element LE can emit light based on the drive current transmitted from the pixel circuit PC.

[0152] Figure 18 The first transistor TR1 and the capacitor CAP illustrated in FIG. 1A can respectively have the structure of the first transistor TR1 and the structure of the capacitor CAP illustrated in FIG. 1B. Figure 3 , Figure 13 , Figure 15 or Figure 16 The first transistor TR1 and the capacitor CAP illustrated in FIG. 1A can respectively have the structure of the first transistor TR1 and the structure of the capacitor CAP illustrated in FIG. 1B. Figure 18 Each of the second transistor TR2, the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5, the sixth transistor TR6, and the seventh transistor TR7 illustrated in FIG. 1A can have the structure of the second transistor TR2, the structure of the third transistor TR3, the structure of the fourth transistor TR4, the structure of the fifth transistor TR5, the structure of the sixth transistor TR6, and the structure of the seventh transistor TR7 illustrated in FIG. 1B. Figure 3 , Figure 13 , Figure 15or Figure 16 The second transistor TR2 has the same structure as the first transistor TR1.

[0153] The display apparatus according to an embodiment can be applied to a display apparatus included in a computer, a notebook, a mobile phone, a smart phone, a smart pad, a PMP, a PDA, an MP3 player, etc.

[0154] Although the display apparatus and the method of manufacturing the display apparatus according to an embodiment have been described with reference to the accompanying drawings, the illustrated embodiments are examples, and can be modified and changed by those skilled in the relevant art without departing from the technical spirit described in the appended claims including equivalents thereof.

Claims

1. A display device comprising: a substrate; a first active layer provided over the substrate; a first insulating layer provided over the first active layer; a first gate electrode provided over the first insulating layer, the first gate electrode overlapping the first active layer; a second insulating layer provided over the first gate electrode; a second active layer provided over the second insulating layer; a first capacitor electrode provided over the second insulating layer, the first capacitor electrode overlapping the first gate electrode; a third insulating layer provided over the second active layer and the first capacitor electrode; a second gate electrode provided over the third insulating layer, the second gate electrode overlapping the second active layer; and a second capacitor electrode provided over the third insulating layer, the second capacitor electrode overlapping the first gate electrode and electrically connected to the first capacitor electrode, wherein a thickness of the second insulating layer is less than a thickness of the third insulating layer. The first capacitor electrode and the second active layer comprise a same material.

2. The display device of claim 1, wherein, The first active layer comprises polysilicon.

3. The display device of claim 1, wherein, The second insulating layer comprises silicon nitride.

4. The display device of claim 1, wherein, A dielectric constant of the second insulating layer is greater than a dielectric constant of the third insulating layer.

5. The display device of claim 1, wherein, The second active layer and the first capacitor electrode each comprise an oxide semiconductor.

6. The display device of claim 1, wherein, The third insulating layer comprises silicon oxide.

7. The display device of claim 1, wherein, A hydrogen content of the third insulating layer is less than a hydrogen content of the second insulating layer.

8. The display device of claim 1, wherein, The second capacitor electrode does not overlap the first capacitor electrode.

9. The display device of claim 1, wherein, The second capacitor electrode overlaps the first capacitor electrode.

10. The display device of claim 1, wherein, 11. The display device according to claim 1, further comprising: a fourth insulating layer provided over the second gate electrode and the second capacitor electrode; and a connection electrode provided over the fourth insulating layer, the connection electrode electrically connecting the second capacitor electrode and the first capacitor electrode. A constant voltage is applied to the connection electrode.

13. The display device according to claim 11, further comprising:

12. The display device of claim 11, wherein, a first source electrode and a first drain electrode provided over the fourth insulating layer and electrically connected to the first active layer; and a second source electrode and a second drain electrode provided over the fourth insulating layer and electrically connected to the second active layer, wherein the connection electrode, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are provided on a same layer.

14. The display device according to claim 13, further comprising: a pixel electrode electrically connected to the first source electrode or the first drain electrode; an emission layer provided over the pixel electrode; and a counter electrode provided over the emission layer.

15. The display device according to claim 1, further comprising: a lower electrode provided between the first insulating layer and the second insulating layer, the lower electrode overlapping the second active layer. The lower electrode is electrically connected to the second gate electrode.

17. A method of manufacturing a display device, the method comprising: forming a first active layer over a substrate; forming a first insulating layer over the first active layer; 16. The display device of claim 15, wherein, ​ ​ ​ ​ forming a first gate electrode over the first insulating layer, the first gate electrode overlapping with the first active layer; forming a second insulating layer over the first gate electrode; forming a second active layer over the second insulating layer; forming a first capacitor electrode over the second insulating layer, the first capacitor electrode overlapping with the first gate electrode; forming a third insulating layer over the second active layer and the first capacitor electrode; forming a second gate electrode over the third insulating layer, the second gate electrode overlapping with the second active layer; and forming a second capacitor electrode over the third insulating layer, the second capacitor electrode overlapping with the first gate electrode and electrically connected to the first capacitor electrode, wherein a thickness of the second insulating layer is smaller than a thickness of the third insulating layer.

18. The method according to claim 17, wherein, the forming of the second active layer and the forming of the first capacitor electrode are performed simultaneously, and the forming of the second gate electrode and the forming of the second capacitor electrode are performed simultaneously. the forming of the second active layer and the first capacitor electrode includes:

19. The method of claim 18, wherein, forming an oxide semiconductor layer over the second insulating layer; etching the oxide semiconductor layer to form the second active layer and the first capacitor electrode; and implanting impurities into the second active layer and the first capacitor electrode using the second gate electrode and the second capacitor electrode as masks. the forming of the second gate electrode and the second capacitor electrode includes:

20. The method of claim 18, wherein, forming a conductive layer over the third insulating layer; and etching the conductive layer to form the second gate electrode and the second capacitor electrode.

21. The method according to claim 18, further comprising: forming a fourth insulating layer over the second gate electrode and the second capacitor electrode; forming a first contact hole in the third insulating layer and the fourth insulating layer, the first contact hole exposing the first capacitor electrode; forming a second contact hole in the fourth insulating layer, the second contact hole exposing the second capacitor electrode; and forming a connection electrode over the fourth insulating layer, the connection electrode filling the first contact hole and the second contact hole. the forming of the first contact hole and the forming of the second contact hole are performed simultaneously.

23. The method according to claim 18, further comprising:

22. The method of claim 21, wherein, forming a lower electrode between the first insulating layer and the second insulating layer, the lower electrode overlapping with the second active layer. the forming of the first gate electrode and the forming of the lower electrode are performed simultaneously.

25. A display device comprising:

24. The method of claim 23, wherein, a substrate; a first transistor including: a first active layer provided over the substrate; a first insulating layer provided over the first active layer; and a first gate electrode provided over the first insulating layer, the first gate electrode overlapping with the first active layer; a capacitor including: the first gate electrode; a second insulating layer provided over the first gate electrode; a first capacitor electrode provided over the second insulating layer, the first capacitor electrode overlapping with the first gate electrode; ​ ​ a third insulating layer provided over the first capacitor electrode; and a second capacitor electrode provided over the third insulating layer, which overlaps with the first gate electrode and is electrically connected to the first capacitor electrode; and a second transistor including: a second active layer provided between the second insulating layer and the third insulating layer, the second active layer and the first capacitor electrode including the same material; the third insulating layer; and a second gate electrode provided over the third insulating layer, which overlaps with the second active layer, wherein a thickness of the second insulating layer is smaller than a thickness of the third insulating layer.

26. The display device of claim 25, wherein, The first active layer includes polycrystalline silicon.

27. The display device of claim 25, wherein, The second active layer and the first capacitor electrode each include an oxide semiconductor.

28. The display device of claim 25, wherein, The second transistor further includes a lower electrode provided between the first insulating layer and the second insulating layer, which overlaps with the second active layer.

29. The display device of claim 28, wherein, The lower electrode is electrically connected to the second gate electrode.

30. A display device comprising: a first active layer; a first insulating layer provided over the first active layer; a first gate electrode provided over the first insulating layer and overlapping with the first active layer, which is insulated from the first active layer; a second insulating layer provided over the first gate electrode; a first capacitor electrode provided over the second insulating layer and overlapping with a first portion of the first gate electrode, which is insulated from the first gate electrode; a second active layer provided over the second insulating layer and not overlapping with the first gate electrode, the second active layer and the first capacitor electrode including the same material; a third insulating layer provided over the second active layer and the first capacitor electrode; a second gate electrode provided over the third insulating layer and overlapping with the second active layer, which is insulated from the second active layer; and a second capacitor electrode provided over the third insulating layer and overlapping with a second portion of the first gate electrode, which is insulated from the first gate electrode and electrically connected to the first capacitor electrode, wherein a thickness of the second insulating layer is smaller than a thickness of the third insulating layer. The second capacitor electrode does not overlap with the first capacitor electrode.

31. The display device of claim 30, wherein, The second capacitor electrode overlaps with the first capacitor electrode.

32. The display device of claim 30, wherein, 33. The display device according to claim 30, further comprising: a connection electrode overlapping with the first capacitor electrode and the second capacitor electrode, which electrically connects the second capacitor electrode and the first capacitor electrode. ​

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