Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The method includes: providing a layer to be etched; forming an initial sacrificial layer on the layer to be etched; performing a modification process on the sidewalls of the initial sacrificial layer to form a transition layer on the sidewalls of the initial sacrificial layer; and removing the transition layer to form a sacrificial layer. The forming method reduces the sidewall roughness of the sacrificial layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] With the progress of semiconductor manufacturing technology, in order for semiconductor devices to achieve faster computing speeds, larger data storage capacities, and more functions, many different methods have been adopted in the prior art to reduce the feature size (CD) and achieve the purpose of increasing the integration density of semiconductor chips, including using Self-Aligned-Double-Patterning (SADP) and Self-Aligned-Quadra Patterning (SAQP).

[0003] Both the Self-Aligned-Double-Patterning technology and the Self-Aligned-Quadra Patterning technology have achieved a doubling of the spatial pattern density. However, due to the manufacturing process limitations of the Self-Aligned-Double-Patterning technology and the Self-Aligned-Quadra Patterning technology, the yield of semiconductor devices has been reduced. Summary of the Invention

[0004] The technical problem solved by the present invention is to reduce the roughness of the sidewalls of the sacrificial layer in the Self-Aligned-Double-Patterning technology and the Self-Aligned-Quadra Patterning technology.

[0005] To solve the above technical problem, one aspect of the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a layer to be etched; forming an initial sacrificial layer on the layer to be etched; performing a modification treatment process on the sidewalls of the initial sacrificial layer to form a transition layer on the sidewalls of the initial sacrificial layer; removing the transition layer to form a sacrificial layer.

[0006] Optionally, the material of the transition layer is different from that of the initial sacrificial layer.

[0007] Optionally, the material of the transition layer has a hydrogen-oxygen bond.

[0008] Optionally, the material of the initial sacrificial layer is one of amorphous silicon or silicon nitride.

[0009] Optionally, the material of the transition layer includes Si-OH groups.

[0010] Optionally, the transition layer is a hydrophilic material.

[0011] Optionally, the modification treatment process is a plasma treatment process.

[0012] Optionally, the parameters of the plasma processing technology include: the gas includes process gas, the gas pressure range is 5 mTorr to 35 mTorr, the process gas is H2 and O2, the bias pressure range is 700V to 1300V, the duration of the gas continuously bombarding the initial sacrificial layer ranges from 10s to 30s, and the temperature range of the semiconductor structure is 20°C to 70°C.

[0013] Optionally, the gas pressure range is 5 mTorr to 25 mTorr; the temperature range of the semiconductor structure is 30°C to 60°C.

[0014] Optionally, the percentage content range of O2 in the process gas in the gas volume is 1% to 3%.

[0015] Optionally, the bias voltage range is 800V to 1200V.

[0016] Optionally, the duration of the gas continuously bombarding the initial sacrificial layer ranges from 10s to 20s; the gas also includes carrier gas, and the carrier gas is one or more of helium or argon.

[0017] Optionally, the process for removing the transition layer is a wet cleaning process; the material of the transition layer has hydrogen-oxygen bonds, and the solution used in the wet cleaning process is an acidic solution.

[0018] Optionally, the parameters of the acidic solution include: the type is hydrofluoric acid, the temperature is room temperature, and the concentration of the hydrofluoric acid is proportional to the duration of cleaning the transition layer.

[0019] Optionally, the mass percentage concentration range of the hydrofluoric acid is 5% - 10%.

[0020] Optionally, the method for forming the initial sacrificial layer on the layer to be etched includes: forming a sacrificial material layer to be etched on the surface of the layer to be etched, and etching the sacrificial material layer to be etched to form the initial sacrificial layer.

[0021] Optionally, the method for forming the initial sacrificial layer on the layer to be etched includes: forming a sacrificial material layer to be etched on the surface of the layer to be etched; forming a number of discrete first sacrificial layers on the surface of the sacrificial material layer to be etched; forming a first sidewall on the sidewall of the first sacrificial layer; after forming the first sidewall, removing the first sacrificial layer; after removing the first sacrificial layer, etching the sacrificial material layer to be etched with the first sidewall as a mask to form the initial sacrificial layer.

[0022] Optionally, it further includes: after removing the transition layer, forming a sidewall on the sidewall of the sacrificial layer; after forming the sidewall, removing the sacrificial layer.

[0023] Optionally, when the initial sacrificial layer formed on the layer to be etched is a plurality of mutually discrete initial sacrificial layers, before the modification treatment process, the ratio range of the height of the initial sacrificial layer to the spacing between the discrete initial sacrificial layers is 1.6 to 3.

[0024] Correspondingly, the technical solution of the present invention further provides a semiconductor structure formed by using any one of the above forming methods.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] In the forming method of the technical solution of the present invention, since the side wall of the initial sacrificial layer is modified to form the transition layer, and then the transition layer including the rough part of the side wall surface is removed, the side wall surface of the formed sacrificial layer becomes smooth, thereby reducing the roughness of the side wall of the initial sacrificial layer, which helps to improve the pattern accuracy of the sacrificial layer, so as to achieve the purpose of improving the yield of semiconductor devices, reducing the manufacturing cost of semiconductor devices, reducing the feature size in the semiconductor manufacturing process, and increasing the integration density of semiconductor chips.

[0027] Furthermore, since the transition layer is modified to a material different from the initial sacrificial layer, when removing the transition layer, according to the different material properties of the transition layer and the initial sacrificial layer, a suitable process for removing the transition layer can be selected, and while removing the transition layer, the influence on the sacrificial layer can be weakened specifically, further improving the pattern accuracy of the sacrificial layer.

[0028] Furthermore, since the parameters of the plasma treatment process are limited, during the plasma treatment process, the initial sacrificial layer can be processed better and more safely.

[0029] Furthermore, since the solution of the wet cleaning process is an acidic solution, the acidic solution can corrode the transition layer with hydrogen-oxygen bonds in the material, thereby removing the transition layer and reducing the roughness of the side wall of the initial sacrificial layer.

[0030] Furthermore, since the acidic solution is a hydrofluoric acid solution, the transition layer material with hydrogen-oxygen bonds is easily corroded by the hydrofluoric acid solution, while the sacrificial layer without hydrogen-oxygen bonds is not easily corroded by the hydrofluoric acid, weakening the influence of the wet cleaning process on the pattern accuracy of the sacrificial layer.

[0031] Furthermore, since a low-concentration hydrofluoric acid solution is used, while removing the transition layer in the wet treatment process, the corrosion of the sacrificial layer by the hydrofluoric acid solution can be further weakened, improving the pattern accuracy of the sacrificial layer.

[0032] Furthermore, due to the selection of an appropriate aspect ratio, the gap size between the discrete initial sacrificial layers is within a suitable range, avoiding the formation of narrow and deep gaps. Therefore, the gases H2 and O2 can more easily bombard the sidewall portion of the initial sacrificial layer deep in the gap, improving the roughness of the entire sidewall of the initial sacrificial layer.

[0033] Correspondingly, in the semiconductor structure of the technical solution of the present invention, due to the use of the above formation method, a semiconductor device with more precise patterns, smaller feature sizes, and higher integration density of semiconductor chips is obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figures 1 to 5 is a schematic cross-sectional structure diagram of the pattern formation process of a self-aligned dual imaging technique;

[0035] Figures 6 to 16 is a schematic cross-sectional structure diagram of the formation process of the semiconductor structure in the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] As described in the background art, it is necessary to further improve the manufacturing process of the self-aligned multiple imaging technique.

[0037] Figures 1 to 5 is a schematic cross-sectional structure diagram of the pattern formation process of a self-aligned dual imaging technique;

[0038] Please refer to Figure 1 , a layer to be etched 20 is formed on a semiconductor substrate 10;

[0039] Please refer to Figure 2 , a sacrificial material layer to be etched (not shown) is formed on the surface of the layer to be etched 20, and the sacrificial material layer to be etched is etched to form a patterned sacrificial layer 30, exposing a part of the surface of the layer to be etched 20;

[0040] Please refer to Figure 3 , a sidewall material layer (not shown) with a relatively uniform thickness is deposited on the surface of the patterned sacrificial layer 30 and the surface of the layer to be etched 20, and the sidewall material layer is etched to form a first sidewall 40 on the sidewall surface of the patterned sacrificial layer 30;

[0041] Please refer to Figure 4 , the patterned sacrificial layer 30 is removed;

[0042] Please refer to Figure 5 , using the first sidewall 40 as a mask, the layer to be etched 20 is etched to form a pattern 21 on the layer to be etched 20.

[0043] Compared with the self-aligned dual imaging technique, the self-aligned quadruple imaging technique requires the formation of two sacrificial layers and two sidewalls twice.

[0044] It can be seen therefrom that since the sidewall needs to be formed on the sidewall surface of the sacrificial layer, the roughness of the sidewall of the sacrificial layer will directly affect the accuracy of the sidewall pattern as a mask, and then affect the accuracy of the pattern formed on the layer 20 to be etched.

[0045] However, due to reasons such as the exposure limit of the lithography process and the loss during the etching process, when the sacrificial layer is formed, the roughness of its sidewall is relatively large.

[0046] To solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, which can reduce the roughness of the sidewall of the sacrificial layer, make its sidewall surface smoother, and further improve the pattern accuracy of the layer to be etched after etching. Therefore, it can improve the yield of semiconductor devices, reduce the manufacturing cost of semiconductor devices, and at the same time reduce the feature size in the semiconductor manufacturing process to increase the integration density of semiconductor chips.

[0047] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0048] Figures 6 to 16 It is a schematic cross-sectional structure diagram of the process of forming a semiconductor structure in an embodiment of the present invention.

[0049] Please refer to Figure 6 , and provide a layer 200 to be etched.

[0050] In this embodiment, the layer 200 to be etched includes a substrate (not shown) and a buffer layer (not shown) located on the substrate; the material of the substrate includes silicon, and the material of the buffer layer is silicon dioxide; the method for forming the buffer layer is chemical vapor deposition, physical vapor deposition, or oxidation process.

[0051] In another embodiment, the layer to be etched includes a substrate, a buffer layer, a metal structure (not shown), and a dielectric layer (not shown); the metal structure is located on the surface of the substrate, and the dielectric layer is located between the metal structures, on the surface of the metal structures, or on a partial surface of the substrate. The buffer layer is located on the surface of the dielectric layer. The material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP. The material of the metal structure includes one or more combinations of aluminum, copper, tungsten, nickel, chromium, titanium, and tantalum. The material of the dielectric layer includes silicon oxycarbide, fluorinated silica glass, or silicon nitride. The material of the buffer layer includes silicon oxide.

[0052] In this embodiment, an initial sacrificial layer is formed on the layer 200 to be etched subsequently. The number of the initial sacrificial layers is multiple, and the multiple initial sacrificial layers are discrete from each other. For the specific method of forming the initial sacrificial layer, please refer to Figures 7 to 10 . In another embodiment, the number of the formed initial sacrificial layers is one.

[0053] Please refer to Figure 7 , a sacrificial material layer 302 to be etched is formed on the surface of the layer 200 to be etched; a first sacrificial material layer (not shown) is formed on the surface of the sacrificial material layer 302 to be etched; the first sacrificial material layer is etched until the sacrificial material layer 302 to be etched is exposed, and a plurality of first sacrificial layers 500 discrete from each other are formed on the surface of the sacrificial material layer 302 to be etched.

[0054] In this embodiment, the methods of forming the sacrificial material layer 302 to be etched and the first sacrificial material layer include a deposition process or a spin coating process.

[0055] In this embodiment, the method of etching the first sacrificial material layer includes: a dry etching process or a wet etching process.

[0056] Please refer to Figure 8 , after the first sacrificial layer 500 is formed, a first sidewall material layer (not shown) covering the surfaces of the first sacrificial layer 500 and the sacrificial material layer 302 to be etched and having a uniform thickness is formed; the first sidewall material layer is etched until the top surface of the first sacrificial layer 500 is exposed, and a first sidewall 600 is formed on the sidewall surface of the first sacrificial layer 500.

[0057] In this embodiment, the method for forming the first sidewall material layer is deposition. For example, an atomic layer deposition process (ALD) is used to form a first sidewall material layer that covers the surfaces of the first sacrificial layer 500 and the sacrificial material layer to be etched 302 and has a uniform thickness.

[0058] In this embodiment, the process of etching the first sidewall material layer includes: a dry etching process or a wet etching process. Preferably, an anisotropic dry etchback process is used to selectively remove the first sidewall material layer in the horizontal direction while retaining the first sidewall material layer in the vertical direction to form the first sidewall 600.

[0059] Please refer to Figure 9 and Figure 10 , Figure 10 is Figure 9 a partial schematic view of region A in

[0060] After forming the first sidewall 600, the first sacrificial layer 500 is removed; after removing the first sacrificial layer 500, the sacrificial material layer to be etched 302 is etched using the first sidewall 600 as a mask to form the initial sacrificial layer 300 on the layer to be etched 200; after forming the initial sacrificial layer 300, the first sidewall 600 is etched and removed.

[0061] In another embodiment, the material of the initial sacrificial layer 300 is amorphous silicon.

[0062] In this embodiment, the processes of removing the first sacrificial layer 500, etching the sacrificial material layer to be etched 302, and etching the first sidewall 600 include: a dry etching process or a wet etching process.

[0063] In this embodiment, the dimension of the top surface of the initial sacrificial layer 300 to the surface of the layer to be etched 200 in the direction perpendicular to the surface of the layer to be etched 200 is the depth D, and the minimum spacing dimension between several discrete initial sacrificial layers 300 parallel to the surface of the layer to be etched 200 is the spacing width W. The ratio D / W of the depth D to the spacing width W ranges from 1.6 to 3.

[0064] Since a suitable aspect ratio is selected, the gap size between the discrete initial sacrificial layers is within a suitable range, avoiding the formation of narrow and deep gaps. Therefore, when performing the modification process on the sidewalls of the initial sacrificial layer subsequently, whether it is the gas in the dry process or the solution in the wet process can easily contact the sidewall portion of the initial sacrificial layer deep in the gap, improving the roughness of the entire sidewall of the initial sacrificial layer.

[0065] In another embodiment, the method for forming the initial sacrificial layer 300 includes: forming a sacrificial material layer to be etched (not shown) on the surface of the layer 200 to be etched, and etching the sacrificial material layer to be etched using a photoresist (not shown) formed by lithographic patterning as a mask to form the initial sacrificial layer 300. The method for forming the sacrificial material layer to be etched includes deposition or spin coating. The method for etching the sacrificial material layer to be etched includes: a dry etching process or a wet etching process.

[0066] In this embodiment, the initial sacrificial layer 300 is etched using the first sidewall 600 as a mask. Since the line width dimension of the pattern of the first sidewall 600 is smaller than the line width dimension of the photoresist pattern, therefore, compared with another embodiment, the line width dimension of the initial sacrificial layer 300 formed in this embodiment can be smaller, and thus a semiconductor device with a higher integration degree can be manufactured subsequently.

[0067] In Figure 10 On this basis, please refer to Figure 11 , after forming the initial sacrificial layer 300, a modification process is performed on the sidewall 301 of the initial sacrificial layer 300 to form a transition layer 400 on the sidewall 301 of the initial sacrificial layer 300.

[0068] In this embodiment, the modification process is a plasma treatment process.

[0069] In this embodiment, the parameters of the plasma process include: the gas includes a process gas, the process gas includes H2 and O2; the pressure of the gas is 5 mTorr to 35 mTorr; the bias pressure range of the gas is 700V to 1300V; the duration of the gas continuously bombarding the initial sacrificial layer 300 ranges from 10s to 30s, and the temperature range of the semiconductor structure is 20°C to 70°C.

[0070] In this embodiment, the material of the transition layer 400 includes Si-OH groups.

[0071] The H2 and O2 become hydrogen ions and oxygen ions after ionization and are bombarded onto the sidewall 301 of the initial sacrificial layer 300. During the bombardment process, by using a higher bias voltage, the hydrogen ions and oxygen ions not only obtain higher energy, but also the bombardment angle distribution range is reduced to be more concentrated and bombarded onto the sidewall 301 of the initial sacrificial layer 300. Therefore, the Si-Si material in the sidewall 301 material of the initial sacrificial layer 300 is more effectively broken and combined with the hydrogen-oxygen bond formed by the hydrogen ions and oxygen ions to form a transition layer 400 whose material includes Si-OH groups.

[0072] Meanwhile, since the gas is controlled to be within a lower pressure range, the gas molecular density of the gas is small. When the gas is ionized, a plasma with a small density can be formed. At the same time, as H2 and O2 are part of the gas, the densities of the hydrogen ions and oxygen ions formed after ionization are also small. By bombarding the sidewall 301 of the initial sacrificial layer 300 with the hydrogen ions and oxygen ions with small densities, the penetration rate of the hydrogen ions and oxygen ions into the initial sacrificial layer 300 can be slowed down, so that the hydrogen ions and oxygen ions mainly perform a modification process on the sidewall 301 of the initial sacrificial layer 300. After the modification process, a relatively thin transition layer 400 is formed, so as to reduce the damage to the pattern of the initial sacrificial layer 300 by the plasma treatment process after the step of removing the transition layer 400.

[0073] Moreover, the longer the time for the hydrogen ions and oxygen ions to bombard the sidewall 301 of the initial sacrificial layer 300, the thicker the formed transition layer 400; the higher the temperature of the semiconductor structure, the easier it is for the initial sacrificial layer 300 to break the Si-Si bonds by the hydrogen ions and oxygen ions during the bombardment process, and then form a transition layer 400 whose material includes Si-OH groups.

[0074] Therefore, by cooperating with the slower penetration rate, controlling the duration of the continuous bombardment of the sidewall 301 of the initial sacrificial layer 300 by the hydrogen ions and oxygen ions and the temperature of the semiconductor structure, the degree of the modification process of the sidewall 301 of the initial sacrificial layer 300 can be accurately controlled, and a relatively thin transition layer 400 is formed, so as to reduce the damage to the pattern of the initial sacrificial layer 300 by the plasma treatment process after the step of removing the transition layer 400.

[0075] Not only that, since the rougher part of the sidewall 301 of the initial sacrificial layer 300 has a larger contact area with the hydrogen ions and oxygen ions, therefore, the rougher part of the sidewall 301 of the initial sacrificial layer 300 is more likely to form the transition layer 400 after being treated by the plasma treatment process, and is removed in the subsequent process of removing the transition layer 400, so as to improve the roughness of the sidewall 301 of the initial sacrificial layer 300 and increase the smoothness of the sidewall 301 of the initial sacrificial layer 300.

[0076] In another embodiment, the pressure range of the gas is 5 mTorr to 25 mTorr. Since the pressure range is controlled within a lower and smaller range, the thickness of the transition layer 400 can be further controlled to reduce the influence of the plasma treatment process on the initial sacrificial layer 300.

[0077] In another embodiment, the percentage content of O2 in the process gas ranges from 1% to 3% of the gas volume, ensuring that during the plasma treatment process, the concentration of O2 is less than the explosion limit, thus ensuring the safety during the formation of the semiconductor structure. Preferably, the concentration of O2 is 2%. By narrowing the concentration range of O2, the fluctuation of the O2 concentration is reduced, facilitating further control of the O2 concentration within a safe range to improve the safety during the formation of the semiconductor structure.

[0078] In another embodiment, the bias voltage ranges from 800V to 1200V. Since the bias voltage range is controlled within a smaller range, it can effectively enable the hydrogen ions and oxygen ions to break the Si-Si material in the sidewall 301 material of the initial sacrificial layer 300 and form Si-OH groups with the Si ions in the sidewall 301 of the initial sacrificial layer 300 while reducing energy consumption.

[0079] In another embodiment, the duration for which the gas continuously bombards the initial sacrificial layer 300 ranges from 10s to 20s. Since the duration range is controlled within a smaller range, it can further reduce the thickness of the transition layer 400 to reduce the impact of the plasma treatment process on the initial sacrificial layer 300.

[0080] In another embodiment, the temperature of the semiconductor structure ranges from 30°C to 60°C. Since the temperature range is controlled within a smaller range, it can further reduce the thickness of the transition layer 400 to reduce the damage to the pattern of the initial sacrificial layer 300 caused by the plasma treatment process.

[0081] In another embodiment, the gas further includes a carrier gas, and the carrier gas is one or more of helium or argon.

[0082] In another embodiment, when the material of the initial sacrificial layer does not include Si element, the material of the transition layer has hydrogen-oxygen bonds. For example, the material of the initial sacrificial layer includes aluminum element or germanium element.

[0083] Please refer to Figure 12 , after forming the transition layer 400 (as Figure 11 shown), the transition layer 400 is removed to form a sacrificial layer 310. The sacrificial layer 310 has a smoother sidewall with lower roughness compared to the initial sacrificial layer 300 (as Figure 10 shown).

[0084] In this embodiment, the method for removing the transition layer 400 includes a wet cleaning process, and the parameters of the wet cleaning process include: the solution used is a hydrofluoric acid solution, the temperature of the hydrofluoric acid solution is room temperature, and the concentration of the hydrofluoric acid is proportional to the duration of cleaning the transition layer 400.

[0085] In this embodiment, since the Si-OH groups are hydrophilic, the material of the transition layer 400 is also hydrophilic. Furthermore, the transition layer 400 is more soluble in the hydrofluoric acid solution and is removed.

[0086] Since the hydrofluoric acid solution has excellent selectivity for the transition layer 400 whose material includes Si-OH groups compared to the material of the initial sacrificial layer 300, the pattern of the sacrificial layer 310 can be effectively removed without being damaged while removing the transition layer 400.

[0087] Moreover, the temperature of the hydrofluoric acid solution is relatively low, so that the temperature of the semiconductor structure after heat transfer with the hydrofluoric acid solution is also relatively low. Since the reaction rate between the material of the semiconductor structure and the hydrofluoric acid solution will be slowed down at a lower temperature, the wet cleaning process can be more precisely controlled, so that while removing the transition layer 400, the damage to the pattern of the sacrificial layer 310 is reduced.

[0088] At the same time, when the concentration of the hydrofluoric acid is relatively high, the duration of cleaning the transition layer 400 is controlled to be shorter; when the concentration of the hydrofluoric acid is relatively low, the duration of cleaning the transition layer 400 is controlled to be longer. Therefore, even when the concentration of the hydrofluoric acid is not very stable, the duration of cleaning the transition layer 400 can be flexibly controlled, that is, the reaction between the hydrofluoric acid solution and the transition layer 400 can be controlled to start or stop, so that when cleaning the transition layer 400, the transition layer 400 can be accurately removed without damaging the pattern of the sacrificial layer 310.

[0089] In this embodiment, the mass percentage concentration range of the hydrofluoric acid is 5%-10%.

[0090] Since a low-concentration hydrofluoric acid solution is used, while removing the transition layer 400 in the wet processing technology, the corrosion of the sacrificial layer 310 by the hydrofluoric acid solution can be further weakened, and the pattern accuracy of the sacrificial layer 310 is improved. Moreover, since a low-concentration hydrofluoric acid solution is used, the corrosion of the hydrofluoric acid solution on the layer 200 to be etched is also further reduced.

[0091] In other embodiments, when the material of the transition layer 400 has a hydrogen-oxygen bond, the solution of the wet cleaning process is an acidic solution.

[0092] Since the material of the transition layer 400 has hydrogen-oxygen bonds, the material 400 of the transition layer is alkaline and can undergo an acid-base neutralization reaction with the acidic solution, and thus is removed.

[0093] Please refer to Figure 13 , and a sidewall 700 is formed on the sidewall of the sacrificial layer 310.

[0094] In this embodiment, the method for forming the sidewall 700 includes: depositing a sidewall material layer (not shown) that covers the surfaces of the sacrificial layer 310 and the layer to be etched 200 and has a uniform thickness, and etching the sidewall material layer to form the sidewall 700.

[0095] In this embodiment, the process of etching the sidewall material layer includes: a dry etching process or a wet etching process.

[0096] In this embodiment, an anisotropic dry etchback process is used to selectively remove the sidewall material layer in the horizontal direction while retaining the sidewall material layer in the vertical direction to form the sidewall 700.

[0097] Since the sacrificial layer 310 has a sidewall with lower roughness and is smoother compared to the initial sacrificial layer 300, when depositing the sidewall material layer, the roughness of the portion of the sidewall material layer in contact with the sidewall of the sacrificial layer 310 will also be smaller, thereby improving the pattern accuracy of the subsequent formed sidewall 700.

[0098] Please refer to Figure 14 , after forming the sidewall 700, the sacrificial layer 310 is removed.

[0099] The process of removing the sacrificial layer 310 includes: a dry etching process or a wet etching process.

[0100] Please refer to Figure 15 and Figure 16 , after removing the sacrificial layer 310, using the sidewall 700 as a mask, etching the layer to be etched 200 to form a pattern of the etched layer 210 with grooves; after forming the pattern of the etched layer 210, the sidewall 700 is removed.

[0101] Since the accuracy of the sidewall 700 is higher, when transferring the pattern of the sidewall to the layer to be etched 200, the roughness of the sidewall of the groove can be reduced, thereby making the pattern accuracy of the etched layer 210 higher.

[0102] An embodiment of the present invention further provides a semiconductor device, including: a semiconductor structure formed by the above forming method.

[0103] In this embodiment, due to the adoption of the above formation method, the roughness of the sidewalls of the sacrificial layer is greatly reduced. Therefore, the subsequent formed semiconductor structure can have a higher integration degree and better reliability at the same time.

[0104] For example, in the lithography process, the roughness of the edge of the photoresist pattern is called the line edge roughness (LER); while the line width roughness (LWR) describes the deviation of the photoresist line width from the target value due to the line edge roughness. For the self-aligned double imaging technology or the self-aligned quadruple imaging technology, when etching the sacrificial material layer to be etched to form the sacrificial layer, the line width roughness of the photoresist will be directly or indirectly transferred to the sacrificial layer, increasing the line width roughness of the sacrificial layer. When the line width roughness of the sacrificial layer is in the range of 2.0 nm to 3.5 nm, after adopting the above formation method, the line width roughness of the sacrificial layer can be reduced by 10% to 20%, thereby making the pattern accuracy of the etching layer 210 higher, and thus a semiconductor device with a higher integration density and higher reliability can be obtained.

[0105] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a layer to be etched; Forming an initial sacrificial layer on the layer to be etched; Performing a modification process on the sidewalls of the initial sacrificial layer to form a transition layer on the sidewalls of the initial sacrificial layer. The modification process is bombarding the sidewalls of the initial sacrificial layer with plasma to form the transition layer, and the material of the transition layer has a hydrogen-oxygen bond; Removing the transition layer including the rough part of the sidewall surface to form a sacrificial layer. The process of removing the transition layer is a wet cleaning process, and the solution used in the wet cleaning process is an acidic solution; 2. The method for forming a semiconductor structure according to claim 1, wherein The material of the transition layer is different from that of the initial sacrificial layer; 3. The method for forming a semiconductor structure according to claim 1, wherein The material of the initial sacrificial layer is one of amorphous silicon or silicon nitride; 4. The method for forming a semiconductor structure according to claim 3, wherein, The material of the transition layer includes Si-OH groups; 5. The method for forming a semiconductor structure according to claim 1, wherein The transition layer is a hydrophilic material; 6. The method for forming a semiconductor structure according to claim 1, wherein, The parameters of the plasma treatment process include: the gas includes process gas, the gas pressure range is 5 mTorr to 35 mTorr, the process gas is H2 and O2, the bias voltage range is 700V to 1300V, the duration of the gas continuously bombarding the initial sacrificial layer is in the range of 10s to 30s, and the temperature range of the semiconductor structure is 20°C to 70°C; 7. The method for forming a semiconductor structure according to claim 6, wherein, The gas pressure range is 5 mTorr to 25 mTorr; the temperature range of the semiconductor structure is 30°C to 60°C; 8. The method for forming a semiconductor structure according to claim 6, wherein, The percentage content of O2 in the process gas by volume ranges from 1% to 3%; 9. The method for forming a semiconductor structure according to claim 6, wherein, The bias voltage range is 800V to 1200V; 10. The method for forming a semiconductor structure according to claim 6, wherein The duration of the gas continuously bombarding the initial sacrificial layer is in the range of 10s to 20s; the gas also includes a carrier gas, and the carrier gas is one or more of helium or argon; 11. The method for forming a semiconductor structure according to claim 1, wherein The parameters of the acidic solution include: the type is hydrofluoric acid, the temperature is room temperature, and the concentration of the hydrofluoric acid is proportional to the duration of cleaning the transition layer; 12. The method for forming a semiconductor structure according to claim 11, wherein The mass percentage concentration range of the hydrofluoric acid is 5% - 10%; 13. The method for forming a semiconductor structure according to claim 1, wherein The method of forming the initial sacrificial layer on the layer to be etched includes: forming a sacrificial material layer to be etched on the surface of the layer to be etched, and etching the sacrificial material layer to be etched to form the initial sacrificial layer; 14. The method for forming a semiconductor structure according to claim 1, wherein The method of forming the initial sacrificial layer on the layer to be etched includes: forming a sacrificial material layer to be etched on the surface of the layer to be etched; forming a number of discrete first sacrificial layers on the surface of the sacrificial material layer to be etched; forming a first sidewall on the sidewall of the first sacrificial layer; after forming the first sidewall, removing the first sacrificial layer; after removing the first sacrificial layer, etching the sacrificial material layer to be etched using the first sidewall as a mask to form the initial sacrificial layer; 15. The method for forming a semiconductor structure according to claim 1, wherein, Also comprising: After removing the transition layer, forming a sidewall on the sidewall of the sacrificial layer; After forming the sidewall, removing the sacrificial layer; 16. The method for forming a semiconductor structure according to claim 6, wherein When the initial sacrificial layer formed on the layer to be etched is a number of discrete initial sacrificial layers, before performing the modification process, the ratio of the height of the initial sacrificial layer to the spacing between the discrete initial sacrificial layers ranges from 1.6 to 3; 17. A semiconductor structure formed by using the method according to any one of claims 1 to 16.

Images