Integrated circuit including an avalanche diode array and method for manufacturing the same

Abstract

Embodiments of the present disclosure relate to an integrated circuit including an avalanche diode array and a method of manufacturing the same. The integrated circuit is formed in a semiconductor substrate. An array of single-photon avalanche diodes is formed on a front side of the semiconductor substrate. The array includes a first diode and a second diode, and the first diode and the second diode are adjacent to each other. A Bragg reflector is positioned between the first diode and the second diode. The Bragg reflector is configured to prevent light from propagating between the first diode and the second diode.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of French Patent Application No. 1912072, filed on October 28, 2019, which is hereby incorporated herein by reference. Technical Field

[0003] Embodiments relate to arrays of single-photon avalanche diodes and their manufacturing processes. Background Art

[0004] Single-photon avalanche diodes are commonly referred to by those skilled in the art as SPADs. A SPAD is capable of detecting low-intensity signals (such as single photons) and is capable of emitting a signal of the arrival time of the photon with high time resolution.

[0005] In particular, a SPAD utilizes the avalanche current of a p-n junction, which is triggered by incident light. More particularly, the SPAD is reverse-biased to exceed its breakdown voltage.

[0006] The high reverse-bias voltage generates a high enough electric field so that a single charge carrier introduced into the depletion region of the SPAD can cause an avalanche, which self-sustains via one ionization per impact.

[0007] Then, the avalanche is actively or passively suppressed, allowing the SPAD to be reset to detect other photons.

[0008] Initial charge carriers can be generated photoelectrically by a single incident photon hitting a high-field region. This operating mode for detecting single photons is commonly referred to as Geiger mode.

[0009] During the avalanche in a SPAD, a high number of hot carriers are generated. These hot carriers relax by emitting parasitic light in the red or near-infrared in all directions.

[0010] In a conventional SPAD array, the light emitted by the hot carriers generated in the SPADs of the array can propagate through the relatively large thickness of the silicon separating the SPADs and be absorbed by adjacent SPADs.

[0011] Then, this absorption of parasitic light by adjacent SPADs generates an unwanted avalanche in that SPAD. This effect is called electro-optical crosstalk.

[0012] The avalanche in adjacent SPADs caused by this crosstalk can cause the voltage to drop below the breakdown voltage. Thus, the adjacent SPAD can no longer detect photons. Then, the adjacent SPAD needs to be recharged in order to increase the bias voltage above the breakdown voltage so that the SPAD can detect photons again.

[0013] This recharge takes a relatively long time (a few nanoseconds), during which the SPAD cannot detect photons.

[0014] This recharge caused by the transmission of unwanted light emitted by hot carriers generated by adjacent SPADs thus degrades the performance of the SPAD array.

[0015] To attenuate this crosstalk, the excess bias voltage of the SPAD is typically reduced. Specifically, reducing the excess bias voltage allows reducing the number of hot carriers generated during the avalanche. However, this solution results in a degradation of the performance of the SPADs of the SPAD array. SUMMARY OF THE INVENTION

[0016] Embodiments and examples of the present invention relate to integrated circuits, and in particular examples, to integrated circuits including an array of single-photon avalanche diodes.

[0017] Embodiments may provide an integrated circuit including a high-performance SPAD array, which allows reducing or even eliminating crosstalk.

[0018] According to one aspect, there is provided an integrated circuit. The integrated circuit includes a semiconductor substrate including an array of single-photon avalanche diodes, the single-photon avalanche diodes including at least two diodes adjacent to each other. Accordingly, at least one Bragg reflector is positioned between at least two adjacent diodes. The Bragg reflector is adapted to prevent the propagation of light between the two diodes.

[0019] Hereinafter, the SPAD array is also referred to as a light detector array. Thus, the light detector array includes a plurality of SPADs.

[0020] The integrated circuit according to this aspect may include one or more Bragg reflectors. Each Bragg reflector thus has a first lateral side and a second lateral side, the first lateral side being in contact with a first SPAD of the light detector array, the second lateral side being opposite to the first lateral side and in contact with a second SPAD of the light detector array, the second SPAD being adjacent to the first SPAD.

[0021] Thus, in the integrated circuit according to this aspect, the crosstalk between two adjacent SPADs between which the Bragg reflector is positioned can be eliminated. Specifically, when a SPAD placed on one side of the Bragg reflector receives photons, the Bragg reflector allows the incident parasitic light emitted by hot carriers to be reflected and / or absorbed, the hot carriers being generated during the avalanche in the receiving SPAD.

[0022] Accordingly, the parasitic light is not transmitted to an adjacent SPAD placed on the other side of the Bragg mirror. Thus, these two SPADs can operate simultaneously without the risk of being activated by the parasitic light generated by one of these SPADs.

[0023] In addition, positioning the Bragg mirror between the SPADs allows for the continued use of a high excess bias voltage. Specifically, the number of hot carriers generated during avalanche no longer has any effect on adjacent SPADs. Thus, high-performance photodetector arrays can be designed and manufactured.

[0024] According to one embodiment, each Bragg mirror is configured to prevent the propagation of light having a wavelength among the wavelengths that can be generated by the energy relaxation of hot carriers, the hot carriers being generated by the avalanche effect triggered in one of the two corresponding diodes.

[0025] Indicatively, for example, such a wavelength can be between 500 nm and 2 μm.

[0026] Preferably, the integrated circuit includes Bragg mirrors positioned between each adjacent diode of the photodetector array.

[0027] Thus, such an integrated circuit is suitable for eliminating crosstalk throughout the photodetector array. Thus, all SPADs of the array can operate simultaneously without the risk of being activated by parasitic light originating from adjacent SPADs.

[0028] Preferably, according to one embodiment, each Bragg mirror includes multiple layers and is adapted to reflect light having an incident angle on the Bragg mirror that, with respect to an axis orthogonal to each layer of the material of the Bragg mirror, has an incident angle between 0° and 90°.

[0029] Such a Bragg mirror is thus suitable for preventing the diffusion of the most harmful photons. Specifically, for photons with an incident angle between 0° and 90°, the risk of crosstalk is the highest.

[0030] According to one embodiment, the semiconductor substrate has a front side, and each Bragg mirror includes at least three alternating layers of at least two materials with different refractive indices, at least two of the layers extending into the substrate in depth from the front side down to a bottom insulating region that defines the bottom of each diode and electrically insulates each diode from the rest of the substrate.

[0031] Thus, each diode has a height defined between the front side and the back side of the substrate, the front side being intended to be exposed to the optical signal to be detected and the back side being in contact with the insulating region.

[0032] According to one embodiment, at least one of the layers extends in depth from the front side down to a distal end, which is located between the front side and the bottom insulating region.

[0033] In particular, each of these layers extends in depth for a sufficient length to be able to reflect light having an incident angle less than the Brewster angle.

[0034] Advantageously, according to one embodiment, at least two materials with different refractive indices include silicon and silicon dioxide.

[0035] The refractive indices of these materials allow the use of layers with a smaller thickness while facilitating the reflection of light that can be generated by the energy relaxation of hot carriers, which are generated by the avalanche effect triggered in one of two corresponding diodes. In addition, silicon and silicon dioxide are materials already mastered by those skilled in the art, and these materials are not expensive. Therefore, it is advantageous to manufacture a Bragg reflector with such materials.

[0036] According to one embodiment, the integrated circuit further includes a lateral deep trench isolation, and the layer of silicon dioxide and the lateral deep trench isolation have the same depth and the same structure.

[0037] According to another aspect, there is provided an electronic device, which includes an integrated circuit as defined above.

[0038] According to another aspect, there is provided a process for manufacturing an integrated circuit. An array including at least two diodes adjacent to each other is formed in a semiconductor substrate. The diodes are single-photon avalanche diodes. At least one Bragg reflector is formed between at least two diodes adjacent to each other in the array. The Bragg reflector is adapted to prevent the propagation of light between these two diodes.

[0039] According to one implementation, at least one Bragg reflector is formed such that it can reflect light having a wavelength among the wavelengths that can be generated by the energy relaxation of hot carriers, which are generated by the avalanche effect triggered in one of two corresponding diodes.

[0040] According to one implementation, at least one Bragg reflector is formed such that it is adapted to reflect light having an incident angle on the Bragg reflector with an incident angle between 0° and 90°.

[0041] According to one implementation, the formation of the diodes in the array includes: forming a bottom insulating region, which defines the bottom of each diode and electrically insulates each diode from the rest of the substrate.

[0042] Furthermore, according to one embodiment, the formation of each Bragg mirror includes: forming at least three alternating layers of at least two materials with different refractive indices between two adjacent diodes such that at least two of the layers extend into the substrate in depth as follows: from the front side of the substrate down to the bottom insulating region.

[0043] According to one embodiment, the formation of at least one Bragg mirror includes: forming an initial volume of a first material between two adjacent diodes. The first material has a first refractive index. A plurality of trenches are etched into the volume of the first material. Each trench is filled with a second material having a second refractive index different from the first refractive index so as to form a layer of the second material. Each volume of the first material is located between two layers of the second material, thereby forming a layer of the first material.

[0044] Thus, the Bragg mirror includes layers alternating between: a layer of the first material, and a layer formed by filling trenches with at least one other material.

[0045] This process for manufacturing a Bragg mirror allows the single crystal of the first material to be maintained. Specifically, each layer of the first material is obtained from the initial volume of the first material.

[0046] According to the latter embodiment, at least one of the trenches filled with the second material extends in depth from the front side down to a distal end located between the front side and the bottom insulating region.

[0047] Since it is not necessary to etch the volume of the first material over the entire height of the diode, such trenches can be formed easily and quickly.

[0048] As a variant, according to another embodiment, the formation of at least one Bragg mirror includes: forming an initial volume of a first material between two adjacent diodes, the first material having a first refractive index, etching a trench into the first material, the trench having two lateral edges defined by the first material, and then successively forming at least one alternation of a layer of the second material and a layer of the first material from the lateral edges of the trench until the trench is filled, the second material having a second refractive index different from the first refractive index.

[0049] This process for manufacturing a Bragg mirror has the advantage of etching one and only one trench into the first material.

[0050] According to one embodiment, the first material and the second material are selected from silicon and silicon dioxide.

[0051] According to one embodiment, the manufacturing process further includes forming a lateral deep trench isolation including silicon dioxide, and the formation of the layer of silicon dioxide is carried out simultaneously with the formation of the lateral deep trench isolation. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Other advantages and features of the present invention will become apparent from the following non - limiting and detailed description of embodiments and examples and the drawings, in which:

[0053] Figure 1 is a schematic representation of a top view of an integrated circuit according to an embodiment of the present invention;

[0054] Figure 2 is a schematic representation of a partial cross - section of an integrated circuit according to a first embodiment of the present invention;

[0055] Figure 3 is a schematic representation of a partial cross - section of an integrated circuit according to a second embodiment of the present invention;

[0056] Figure 4 is a schematic representation of an electronic device according to an embodiment of the present invention;

[0057] Figure 5 illustrates the results of the steps of a process for manufacturing an integrated circuit according to a first embodiment of the present invention; and

[0058] Figure 6 illustrates the results of the steps of a process for manufacturing an integrated circuit according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0059] Figure 1 Shows an embodiment of an integrated circuit CI according to the present invention. The integrated circuit CI includes an array RES of photodetectors. The photodetector array RES includes a plurality of single - photon - avalanche diodes, so - called SPADs. In Figure 2 and Figure 3 In the embodiment shown, only two diodes SPAD1, SPAD2 are shown. Preferably, all the SPADs in the photodetector array RES are the same. In particular, each SPAD has a parallelogram shape. Preferably, the photodetector array RES is located in a plane.

[0060] The SPAD allows light to be detected. In particular, the SPAD uses the avalanche current of a p - n junction triggered by an incident photon to detect the photon.

[0061] In particular, in Figure 2 and Figure 3In the embodiment shown, each SPAD is formed in a semiconductor substrate SBT. Each SPAD includes a first region REG1 of the SPAD. This first region REG1 is of a first conductivity type, for example n+-type. This first region REG1 is designed to capture photons incident on a portion (referred to as the front side FAV) of one side of the semiconductor substrate SBT. The front side FAV delimits the first region REG1 in particular.

[0062] The front side FAV of the semiconductor substrate SBT bears the components of the integrated circuit. In particular, the front side FAV is the side on which the regions of the integrated circuit containing electronic components (such as transistors and diodes) of the integrated circuit are fabricated. This region is also referred to by the conventional acronym "FEOL" for "Front End Of Line". The optical signal to be detected by the array can be received via the following: via the front side FAV of the substrate SBT, or via the rear side FAR, which is opposite to the front side FAV.

[0063] The first region REG1 is connected to the cathode contact.

[0064] Each SPAD also includes a second region REG2 of a second conductivity type (for example, p-type). This second region REG2 laterally frames the first region REG1.

[0065] Each SPAD also includes a third region REG3 of a third conductivity type (for example, p-type), which is connected to the anode contact. In particular, this third region REG3 extends below the first region REG1 and the second region REG2.

[0066] Each SPAD also includes a deep region REG4 of a second conductivity type (for example, p-type). This deep region REG4 is surrounded by the third region REG3.

[0067] This deep region REG4 rests on a bottom insulating region ISO, which extends below all of the SPADs in the SPADs of the photodetector array RES. Thus, each diode has a height suitable for capturing photons, which is defined between the front side FAV of the substrate SBT and the rear side FAR of the substrate SBT, and the rear side FAR is in contact with the bottom insulating region ISO.

[0068] Each SPAD is reverse-biased. For example, the first region of REG1 of n+-type is raised to 20V, and the third region REG3 of p-type is held at 0V. In particular, each SPAD is reverse-biased to exceed its breakdown voltage.

[0069] A high reverse bias voltage generates an electric field high enough to enable a single charge carrier introduced into the depletion region of the SPAD to cause an avalanche that sustains itself via one ionization per impact.

[0070] During the avalanche in the SPAD, a high number of hot carriers are generated. These hot carriers relax by emitting parasitic light in the red or near-infrared in all directions.

[0071] To avoid electro-optical crosstalk between the SPADs of the array, the photodetector array RES also includes a Bragg mirror MB between each SPAD of the photodetector array RES. Specifically, each Bragg mirror MB allows the parasitic light generated by the receiver SPAD to be reflected and / or absorbed in order to prevent this parasitic light from being transmitted to the SPAD adjacent to the receiver SPAD.

[0072] Figure 2 and Figure 3 Two embodiments are shown that include a Bragg mirror MB between two diodes SPAD1 and SPAD2. In these two embodiments, the Bragg mirror MB includes at least two layers CO of materials MAT1, MAT2 with successive, different refractive indices. The successive layers CO allow the light incident on the Bragg mirror MB to be reflected and / or absorbed.

[0073] In particular, the layers CO are oriented so as to extend perpendicularly (i.e., orthogonally) with respect to the front side FAV of the substrate SBT. In addition, the refractive index of a layer CO of the Bragg mirror MB is different from the refractive index of an adjacent layer CO.

[0074] Each Bragg mirror MB thus has a first lateral side CL1 and a second lateral side CL2, the first lateral side CL1 being in contact with the first diode SPAD1 of the photodetector array RES, and the second lateral side CL2 being in contact with the second diode SPAD2 of the photodetector array RES, the second lateral side CL2 being opposite the first lateral side CL1, the second diode SPAD2 being adjacent to the first diode SPAD1.

[0075] More particularly, the Bragg mirror MB can then include alternating, successive layers CO of silicon and layers CO of silicon dioxide, silicon and silicon dioxide having different refractive indices. These materials have such refractive indices as to allow the use of layers CO of small thickness while favoring the reflection of light that can be generated by the energy relaxation of hot carriers generated by the avalanche effect triggered in one of the two corresponding diodes. In addition, silicon and silicon dioxide are materials that are mastered and commonly used in semiconductor devices. Thus, manufacturing the Bragg mirror MB with this material is relatively easy to implement and is particularly advantageous in terms of cost savings.

[0076] The greater the number of layers CO included in the Bragg mirror MB, the higher its performance in terms of preventing the diffusion of photons between the two diodes SPAD1 and SPAD2, where the Bragg mirror is positioned between the two diodes SPAD1 and SPAD2. In Figure 2 and Figure 3 the embodiment shown in, the Bragg mirror MB includes five layers CO of silicon dioxide and four layers CO of silicon.

[0077] The thickness of each layer can be selected using the following Bragg relation:

[0078] L = λ0 / 4n,

[0079] where λ0 is the wavelength of interest and n is the refractive index of the layer.

[0080] In particular, the wavelength of interest can be calculated using the following formula:

[0081] Equation 1

[0082]

[0083] To reflect the parasitic light that can cause avalanches in the SPAD adjacent to the SPAD receiving the photons, λmin can be selected to be between 500 nm and 600 nm (red), and λmax can be selected to be between 1.1 μm and 1.2 μm (near infrared). Thus, λ0 can be equal to 824 nm. The thickness of the silicon dioxide layer can then be equal to 142 nm, and the thickness of the silicon layer can be 56 nm.

[0084] Each Bragg mirror MB of the optical detector array RES is at least adapted to reflect light having an incident angle between 0° and 60° on the Bragg mirror MB. Subsequently, each Bragg mirror MB is adapted to prevent the diffusion of the most harmful photons. Specifically, for photons having an incident angle between 0° and 60°, the risk of crosstalk is the highest.

[0085] In the embodiment described above with reference to Figure 2 each layer CO in the layers CO extends over the height of the diode, and the Bragg mirror MB is positioned between the diodes. Thus, each layer CO extends from the front side FAV of the substrate SBT to the bottom insulation region ISO.

[0086] As a variant, as shown in Figure 3 certain layers CO' of the Bragg mirror MB may extend only over a fraction of the height of the diode, where the Bragg mirror MB is positioned between the diodes. In particular, in Figure 3In the embodiment shown, the two layers CO' of silicon dioxide extend only over a fraction of the height of the diode. In particular, each layer CO' that extends only over a part of the height of the diode extends in depth from the front side FAV down to a distal end located between the front side FAV and the bottom insulation region ISO.

[0087] Each layer CO' that extends only over a part of the height of the SPAD is adapted to prevent the diffusion of light between the diodes: light with a small angle of incidence, in particular, light with an angle of incidence between 0° and the Brewster angle.

[0088] Thus, the integrated circuit CI according to the invention is adapted to eliminate crosstalk between two adjacent SPADs between which the Bragg mirror MB is positioned.

[0089] When a SPAD placed on one side of the CL1, CL2 of the Bragg mirror MB receives photons, the Bragg mirror MB allows the incident parasitic light emitted by hot carriers, generated during the avalanche in the receiving SPAD, to be reflected and / or absorbed.

[0090] Thus, the parasitic light does not penetrate to the adjacent SPAD placed on the other side of the CL1, CL2 of the Bragg mirror MB. Thus, these two SPADs can operate simultaneously without the risk of being deactivated by the parasitic light generated by one of these SPADs.

[0091] Furthermore, positioning the Bragg mirror MB between the SPADs makes it possible to continue to use a high excess bias voltage. Specifically, the number of hot carriers generated during the avalanche no longer has any effect on the adjacent SPADs. Thus, a high-performance optical detector array RES can be designed.

[0092] Furthermore, the integrated circuit may include a lateral deep trench isolation DTI as shown in Figure 2 and Figure 3 Deep trench isolation is well known to those skilled in the art, and those skilled in the art refer to deep trench isolation by the abbreviation "DTI".

[0093] Figure 4 An electronic device AE including the integrated circuit CI according to the invention is shown. The electronic device AE can be a time-of-flight sensor, or a device equipped with a time-of-flight sensor.

[0094] Figure 5 Illustrates the result of the steps of a process for manufacturing an integrated circuit according to a first embodiment.

[0095] Figure 6Illustrates the result of the steps of a process for manufacturing an integrated circuit according to a second embodiment.

[0096] These two embodiments first include forming a plurality of SPADs adjacent to each other to form a photodetector array. In particular, an initial volume of a first material MAT1, such as silicon for example, is also formed between each adjacent diode of the array.

[0097] Each initial volume of the first material MAT1 extends against the SPAD adjacent to that initial volume at a height equal to the height of the adjacent SPAD. Each Bragg mirror is then formed from this volume of silicon.

[0098] Thus, Figure 5 and Figure 6 Illustrates two embodiments for manufacturing a Bragg mirror from the volume of the first material MAT1 between two adjacent diodes of the photodetector array.

[0099] Figure 5 The embodiment shown in includes step A, in which a plurality of trenches TR are etched into the first material MAT1. In this embodiment, the first material MAT1 is silicon. In particular, in Figure 5 only two trenches TR are illustrated. However, more than two trenches TR can be etched in step A.

[0100] In step B, a layer CO of a second material MAT2 is then formed in the resulting trenches TR. This second material MAT2 has a refractive index different from that of the first material MAT1. In particular, the second material MAT2 can be silicon dioxide. These layers of the second material MAT2 are formed to fill each of these trenches TR.

[0101] In step C, another trench TR is then etched into the volume of the first material MAT1 between the layers of the second material MAT2. Next, in step D, another layer of the second material MAT2 is formed in the trench TR resulting from step C. This layer of the second material MAT2 is formed to fill the trench TR resulting from step C.

[0102] Thus, each trench TR etch is used to form a layer of the second material MAT2. Layers of the first material MAT1 are formed between the layers of the second material MAT2 from the initial volume of the first material MAT1.

[0103] Thus, depending on the desired thickness of the layer of the second material MAT2, the width of the trench TR is selected. In particular, when the second material MAT2 is silicon dioxide, the width of each trench TR is 142 nm. The arrangement of the trenches TR is selected such that when the first material MAT1 is silicon, a layer of the first material MAT1 with a thickness of 56 nm is formed.

[0104] The trenches TR are created in two different steps (step A and step C) in order to avoid forming a fragile layer CO of the first material MAT1 with a small thickness between the trenches TR before these trenches TR are filled with the second material MAT2. In this embodiment, the layer of the first material MAT1 is entirely formed from the initial volume of the first material MAT1.

[0105] Thus, this process for manufacturing a Bragg mirror can allow a single-crystalline layer of the first material MAT1, and in particular, a single-crystalline layer of silicon to be maintained. Furthermore, in this embodiment, the formation of the layer of silicon dioxide can be implemented simultaneously with the formation of the lateral deep trench isolation. Specifically, the layer of silicon dioxide and the lateral deep trench isolation have the same structure and can thus be formed in the same manufacturing step.

[0106] As a variant, Figure 6 the embodiment shown in includes: in step A', trenches TR with a sufficient width are formed by etching to contain a plurality of layers CO of the Bragg mirror, and in particular all the layers in the layer. In particular, the layers CO of the materials MAT1, MAT2 of the Bragg mirror are successively formed in the trench TR from the lateral edges of the trench TR until the trench TR is filled. For example, layers of silicon MAT1 and layers of silicon dioxide MAT2 are successively formed in the trench TR.

[0107] More particularly, in Figure 6 the example shown in, a trench TR of 538 nm is etched into the initial volume of silicon. This width allows for receiving three layers of 142 nm of silicon dioxide MAT2 and two layers of 56 nm of silicon MAT1. In particular, in step B', two layers of 142 nm of silicon dioxide MAT2 are formed on each lateral edge of the trench TR to contact the silicon in the initial volume of silicon.

[0108] Next, in step C', two layers of 56 nm of silicon MAT1 are formed against the layers of silicon dioxide formed in step B'. Finally, in step D', a layer of 142 nm of silicon dioxide MAT2 is formed between the layers of silicon formed in step C'.

[0109] This process for manufacturing a Bragg mirror has the advantage of etching one and only one trench TR in a first material MAT1. Specifically, etching multiple trenches TR in the first material MAT1 weakens the first material MAT1.

[0110] In Figure 5 and Figure 6 In the two embodiments shown, the depth of the etched feature can be selected depending on the desired height of the layer of the Bragg mirror (e.g., a layer of silicon dioxide). Thus, the etched feature can be formed at the height of the SPAD, or on a portion of the height of the SPAD.

[0111] Specifically, a layer CO' of silicon dioxide that extends only over a portion of the height of the SPAD can be formed easily and quickly. Specifically, for such a layer of silicon dioxide, it is not necessary to etch the volume of the first material MAT1 over the entire height of the diode, and due to the smaller height of the layer, the formation of each layer of silicon dioxide is faster.

[0112] Of course, various variations and modifications of the present invention will be apparent to those skilled in the art. For example, nothing prevents the use of a Bragg mirror including an alternation of a layer of silicon nitride and a layer of germanium, instead of a mirror including an alternation of a layer of silicon and a layer of silicon dioxide.

Claims

1. An integrated circuit, comprising: A semiconductor substrate; An array of single-photon avalanche diodes formed on a front side of the semiconductor substrate, the array including a first diode and a second diode, the first diode and the second diode being adjacent to each other; And A Bragg reflector positioned between the first diode and the second diode, the Bragg reflector being configured to prevent light from propagating between the first diode and the second diode, Wherein each Bragg reflector (MB) includes at least three alternating layers of at least two materials having different refractive indices, at least two of the at least three alternating layers extending into the semiconductor substrate in depth as follows: from the front side downward to a bottom insulating region, the bottom insulating region defining a bottom of each diode, the bottom insulating region electrically insulating each diode from the rest of the semiconductor substrate, wherein at least one of the at least three alternating layers extends in depth from the front side downward to a distal end, the distal end being located between the front side and the bottom insulating region.

2. The integrated circuit according to claim 1, wherein each Bragg reflector is configured to: prevent the propagation of light having a wavelength among the wavelengths that can be generated by the energy relaxation of hot carriers, the hot carriers being generated by an avalanche effect triggered in the first diode or the second diode.

3. The integrated circuit according to claim 1, wherein each Bragg reflector (MB) is configured to reflect light having an incident angle that, on the Bragg reflector, with respect to an axis orthogonal to each layer of the material of the Bragg reflector, has an incident angle between 0° and 90°.

4. The integrated circuit according to claim 1, wherein the at least two materials having different refractive indices include silicon and silicon dioxide.

5. The integrated circuit according to claim 4, further comprising a lateral deep trench isolation region, wherein a layer including silicon dioxide among the at least three alternating layers and the lateral deep trench isolation region have the same depth and the same structure.

6. A method for manufacturing an integrated circuit, the method comprising: Forming an array of single-photon avalanche diodes in a semiconductor substrate, the array including a first diode and a second diode, wherein forming the array of single-photon avalanche diodes includes: forming a bottom insulating region in the semiconductor substrate, the bottom insulating region defining a bottom of each diode and electrically insulating each diode from the rest of the semiconductor substrate; and A Bragg reflector is formed between the first diode and the second diode, and the Bragg reflector is configured to prevent light from propagating between the first diode and the second diode. Each Bragg reflector (MB) includes at least three alternating layers of at least two materials with different refractive indices, and at least two of the at least three alternating layers extend into the semiconductor substrate in depth as follows: from the front side of the semiconductor substrate downward to the bottom insulating region, wherein at least one of the at least three alternating layers extends downward from the front side to a distal end, and the distal end is located between the front side and the bottom insulating region.

7. The method according to claim 6, wherein the Bragg reflector is formed to reflect light having a wavelength among the wavelengths that can be generated by the energy relaxation of hot carriers, and the hot carriers are generated by the avalanche effect triggered in the first diode or the second diode.

8. The method according to claim 6, wherein the Bragg reflector is formed to reflect light having an incident angle such that, on the Bragg reflector, with respect to an axis orthogonal to the main surface of the Bragg reflector, the incident angle is between 0° and 90°.

9. The method according to claim 6, wherein forming the Bragg reflector comprises: Between the first diode and the second diode, at least three alternating layers of at least two materials with different refractive indices are formed.

10. The method according to claim 6, wherein forming the Bragg reflector includes: forming an initial volume of a first material having a first refractive index between the first diode and the second diode; etching trenches into the first material, the trenches having lateral edges defined by the first material; and successively forming alternating layers of a second material and the first material from the lateral edges of the trenches until the trenches are filled, the second material having a second refractive index different from the first refractive index.

11. The method according to claim 10, wherein the first material is one of silicon or silicon dioxide, and the second material is the other of silicon or silicon dioxide.

12. The method according to claim 6, wherein forming the Bragg reflector includes: forming an initial volume of a first material having a first refractive index between the first diode and the second diode; etching a plurality of trenches into the volume of the first material; and filling each trench with a second material having a second refractive index different from the first refractive index, thereby forming a layer of the second material, and each volume of the first material is located between two layers of the second material, thereby forming a layer of the first material.

13. The method according to claim 12, wherein at least one of the trenches filled with the second material extends downward from the front side to the distal end, and the distal end is located between the front side and the bottom insulating region.

14. The method according to claim 13, wherein the first material is one of silicon or silicon dioxide, and the second material is the other of silicon or silicon dioxide, and the method further comprises: Form a lateral deep trench isolation region including silicon dioxide, wherein a layer of silicon dioxide is formed simultaneously with the formation of the lateral deep trench isolation region.

15. A method for manufacturing an integrated circuit, the method comprising: Forming an array of single photon avalanche diodes in a semiconductor substrate; And Forming a plurality of structures, each structure including alternating layers of silicon and silicon dioxide, the alternating layers of silicon and silicon dioxide extending into the semiconductor substrate between pairs of adjacent ones of the diodes, wherein forming the plurality of structures includes: Forming a plurality of first trenches in the semiconductor substrate, each first trench being disposed between a respective pair of adjacent ones of the diodes; Filling the plurality of first trenches with a first material, the first material being one of silicon or silicon dioxide; Etching respective second trenches into the first material of each of the plurality of first trenches such that each respective second trench has lateral edges defined by the first material; and Successively forming alternating layers of a second material and the first material from the lateral edges of each respective second trench, the second material being the other of silicon or silicon dioxide.

16. The method according to claim 15, further comprising forming a lateral deep trench isolation region around each pair of single photon avalanche diodes of the array of single photon avalanche diodes.

17. The method according to claim 15, wherein forming the array of single photon avalanche diodes includes forming a bottom insulation region in the semiconductor substrate, the bottom insulation region defining the bottom of each diode and electrically insulating each diode from the remainder of the semiconductor substrate.

18. A method for manufacturing an integrated circuit, the method comprising: Forming an array of single photon avalanche diodes in a semiconductor substrate; And Forming a plurality of structures, each structure including alternating layers of silicon and silicon dioxide, the alternating layers of silicon and silicon dioxide extending into the semiconductor substrate between pairs of adjacent ones of the diodes, wherein forming the plurality of structures includes: Forming a plurality of trenches in the semiconductor substrate, each trench being disposed between a respective pair of adjacent ones of the diodes; Filling each trench with a first material, the first material being one of silicon or silicon dioxide; For each of the trenches, etching a plurality of smaller trenches into the first material; and For each of the trenches, filling each smaller trench with a second material, the second material being the other of silicon or silicon dioxide.

19. The method according to claim 18, further comprising forming a lateral deep trench isolation region around each pair of single photon avalanche diodes of the array of single photon avalanche diodes.

20. The method according to claim 18, wherein forming the array of single photon avalanche diodes includes forming a bottom insulation region in the semiconductor substrate, the bottom insulation region defining the bottom of each diode and electrically insulating each diode from the remainder of the semiconductor substrate.

Images