Hybrid EFJ-type power amplifier based on branch-parallel dual-fan-shaped microstrip line and its design method

Abstract

The present invention provides a hybrid EFJ type power amplifier based on a branch parallel double fan-shaped microstrip line and a design method, comprising an input matching circuit, a gate bias circuit, a transistor, a drain bias circuit, and an output matching circuit. The input end of the input matching network is connected to the power input end, the output end is connected to the gate of the transistor, the gate bias circuit is connected in parallel with the gate, the drain of the transistor is connected to the output matching circuit, the drain bias circuit is connected in parallel with the drain, and the output end of the output matching circuit is used as the power output.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency communication technology, and in particular to a hybrid EFJ-type power amplifier based on branch-parallel dual-sector microstrip lines and a design method thereof. Background Art

[0002] With the rapid development of wireless communication technology, future high-performance wireless communication systems require faster speeds and wider bandwidths. Therefore, people have paid a lot of attention to the research of power amplifiers, which are an important part of the RF front end of the communication system. In order to meet multiple communication frequency band standards, the entire RF communication system will need to achieve ultra-wideband transmission.

[0003] In order to improve power utilization and save costs, a broadband high-efficiency power amplifier should be configured at the front end of the multi-band transmitter. This power amplifier will seriously affect the performance of the entire wireless communication system. Therefore, how to realize a broadband high-efficiency power amplifier has become an active research field. In 2020, Zhang Zhiwei of Hangzhou Dianzi University first proposed a hybrid EFJ-class power amplifier, which successfully combined the high efficiency of the EF-class power amplifier and the broadband of the J-class power amplifier to realize a broadband high-efficiency RF power amplifier. However, the design process is complicated, difficult to implement, has limited bandwidth, is large in size, and has a high cost.

[0004] Therefore, it is necessary to conduct research to provide a solution to solve the defects in the prior art. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a hybrid EFJ-type power amplifier and a design method based on a branch-parallel dual-fan-shaped microstrip line, thereby simplifying the design complexity of the EFJ-type power amplifier; under the same technical requirements, the circuit substrate area designed using the fan-shaped microstrip line is smaller, and at the same time, the bandwidth of the EFJ type is further expanded, which has a good application prospect in the field of wireless communications.

[0006] In order to overcome the defects of the prior art, the present invention adopts the following technical solutions:

[0007] A hybrid EFJ-type power amplifier based on a branch-parallel dual-fan-shaped microstrip line includes at least an input matching network, a gate bias circuit, a transistor, an output matching network and a drain bias circuit, wherein:

[0008] The input end of the input matching network serves as a power input end, and the output end thereof is connected to the gate of the transistor;

[0009] The transistor drain is connected to the input end of the output matching network, and the output end of the output matching network serves as the power output end;

[0010] The input matching network includes a first microstrip line TL1, a second microstrip line TL2, and a third microstrip line TL3, wherein one end of the first microstrip line TL1 is connected to the power input end, and the other end is connected to the second microstrip line TL2, the other end of the second microstrip line TL2 is connected to the third microstrip line TL3, and the other end of the third microstrip line TL3 is connected to the transistor gate;

[0011] The gate bias circuit includes a fourth microstrip line TL4, one end of the fourth microstrip line TL4 is connected between the second microstrip line TL2 and the third microstrip line TL3, and the other end is connected to the gate power supply;

[0012] The output matching network includes a fifth microstrip line TL5, a sixth microstrip line TL6, a seventh microstrip line TL7, a first fan-shaped microstrip line Rad stub1, and a second fan-shaped microstrip line Rad stub2, wherein one end of the fifth microstrip line TL5 is connected to the transistor drain, and the other end is connected to the sixth microstrip line, and the other end of the sixth microstrip line is connected to the power output end, and one end of the seventh microstrip line is connected between the fifth microstrip line and the sixth microstrip line, and the other end is connected to the first fan-shaped microstrip line Rad stub1 and the second fan-shaped microstrip line Rad stub2, and the first fan-shaped microstrip line Rad stub1 and the second fan-shaped microstrip line Rad stub2 are connected in parallel;

[0013] The drain bias circuit includes an eighth microstrip line TL8 , one end of the eighth microstrip line TL8 is connected between the fifth microstrip line TL5 and the sixth microstrip line TL6 , and the other end of the eighth microstrip line TL8 is connected to the drain power supply.

[0014] As a further improvement, a gate bias circuit is provided between the input matching circuit and the transistor, and the bias voltage thereof is -2.8V.

[0015] As a further improvement, a bias circuit is provided at the drain of the transistor, and its bias voltage is 28V.

[0016] The present invention also discloses a design method of a hybrid EFJ-type power amplifier based on a branch-parallel dual-fan-shaped microstrip line, comprising the following steps:

[0017] Step S1: design a standard EFJ class power amplifier;

[0018] Step S2: Designing an output matching network that meets the fundamental impedance of the hybrid EFJ class power amplifier, specifically comprising the following steps:

[0019] According to the output matching network structure of the traditional hybrid EFJ power amplifier, the input impedance expression of the output matching network structure is obtained as follows:

[0020]

[0021] Let the characteristic impedance of the fifth microstrip line TL5 and the sixth microstrip line TL6 be Z5 = 80Ω and Z6 = 30Ω, then we can deduce Z in The value range is greater than or equal to 20.91Ω;

[0022] Then according to the formula Design the required branch parallel dual fan-shaped microstrip line;

[0023] Step S3: Designing a harmonic control network, including the following steps:

[0024] For harmonic control, the microstrip lines TL5 and TL8 are tuned so that TL5+TL8=λ / 4, and the second harmonic is short-circuited. The microstrip lines TL5 and TL7, and the fan-shaped microstrip lines Rad stub1 and Rad stub2 are tuned so that TL5+TL7+Rad stub1 / Radstub2=λ / 12, and the third harmonic is open-circuited.

[0025] Step S4: designing a bias circuit;

[0026] Step S5: designing an input matching circuit, using a short-section variable resistor design method to further expand bandwidth and improve efficiency;

[0027] Step S6: construct an overall circuit and optimize the overall circuit to further improve the efficiency and output power of the designed circuit.

[0028] As a further improvement, in step S5, the input matching circuit adopts the same design method as the output matching circuit.

[0029] As a further improvement, the input end of the input matching network serves as the power input end, and the output end thereof is connected to the gate of the transistor;

[0030] The drain of the transistor is connected to the input end of the output matching network, and the output end of the output matching network serves as a power output end;

[0031] The input matching network includes a first microstrip line TL1, a second microstrip line TL2, and a third microstrip line TL3; one end of the first microstrip line TL1 is connected to the power input end, and the other end is connected to the second microstrip line TL2, the other end of the second microstrip line TL2 is connected to the third microstrip line TL3, and the other end of the third microstrip line TL3 is connected to the transistor gate;

[0032] The gate bias circuit includes a λ / 4 microstrip line TL4; one end of the fourth microstrip line TL4 is connected between the second microstrip line TL2 and the third microstrip line TL3, and the other end is connected to the gate power supply;

[0033] The output matching network includes a fifth microstrip line TL5, a sixth microstrip line TL6, a seventh microstrip line TL7, a first fan-shaped microstrip line Rad stub1, and a second fan-shaped microstrip line Rad stub2. One end of the fifth microstrip line TL5 is connected to the drain of the transistor, and the other end is connected to the sixth microstrip line. The other end of the sixth microstrip line is connected to the power output end. One end of the seventh microstrip line is connected between the fifth microstrip line and the sixth microstrip line, and the other end is connected to the fan-shaped microstrip lines Rad stub1 and Rad stub2. The fan-shaped microstrip line Radstub1 and the fan-shaped microstrip line Rad stub2 are connected in parallel.

[0034] The drain bias circuit includes an eighth microstrip line TL8 , one end of the eighth microstrip line TL8 is connected between the fifth microstrip line TL5 and the sixth microstrip line TL6 , and the other end is connected to the drain power supply.

[0035] As a further improvement, a gate bias circuit is provided between the input matching circuit and the transistor, and the bias voltage of the gate bias circuit is -2.8V.

[0036] As a further improvement, a bias circuit is provided at the drain of the transistor, and its bias voltage is 28V.

[0037] Compared with the prior art, the present invention provides a hybrid EFJ-type power amplifier based on a branch-parallel dual-fan-shaped microstrip line and a design method. For the previous EFJ-type power amplifier, it is proposed to use a branch-parallel dual-fan-shaped microstrip line to realize an output matching circuit, and the impedance expression of the branch-parallel dual-fan-shaped microstrip line output matching network based on a T-type network is theoretically derived. Then, according to the load impedance value range of the EFJ class, the impedance value range of the branch-parallel dual-fan-shaped microstrip line that meets the EFJ class is inverted, thereby simplifying the design complexity of the EFJ-type power amplifier. The physical length of the fan-shaped microstrip line is about 1 / 2 of the physical length of the traditional straight microstrip line. Therefore, under the same technical requirements, the circuit substrate area designed using the fan-shaped microstrip line is smaller. Under the condition of the same input impedance, after ADS simulation, the reflection coefficient S of the fan-shaped microstrip line is obtained compared with the straight microstrip line. 11 Smoother, transmission coefficient S 21 Smaller and wider bandwidth, this is because the reactance of the fan-shaped microstrip line near the resonance point changes slowly with frequency, which makes it have a wider bandwidth. Therefore, the use of branch parallel double fan-shaped microstrip lines further expands the bandwidth of the EFJ class. The output matching network is designed based on a T-type two-port network. The design method is simple. At the same time, the output matching circuit has a compact structure and has good application prospects in the field of wireless communications. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a structural block diagram of a hybrid EFJ-type power amplifier based on a branch-parallel dual-fan-shaped microstrip line of the present invention;

[0039] Figure 2 It is a schematic diagram of the output circuit structure of the present invention based on the branch parallel double fan-shaped microstrip line;

[0040] Figure 3 is a schematic diagram of the optimal fundamental impedance trajectory of the present invention;

[0041] Figure 4 It is a simulation result diagram of the output power and drain efficiency of the hybrid EFJ-type power amplifier based on the branch parallel dual fan-shaped microstrip line of the present invention. DETAILED DESCRIPTION

[0042] The following are specific embodiments of the present invention and the accompanying drawings to further describe the technical solution of the present invention, but the present invention is not limited to these embodiments.

[0043] In view of the defects of the prior art, the applicant has conducted an in-depth study on the structure of the traditional hybrid EFJ type power amplifier in the prior art. The applicant found that the traditional hybrid EFJ type power amplifier in the prior art has a complex structure, a complex design process, limited bandwidth, a large size and a high cost.

[0044] In order to overcome the defects of the prior art, the present application provides a hybrid EFJ-type power amplifier and design method based on a branch-parallel dual-fan-shaped microstrip line. For the previous EFJ-type power amplifier, it is proposed to use a branch-parallel dual-fan-shaped microstrip line to realize the output matching circuit, and theoretically derive the impedance expression of the branch-parallel dual-fan-shaped microstrip line output matching network based on the T-type network. Then, according to the load impedance value range of the EFJ class, the impedance value range of the branch-parallel dual-fan-shaped microstrip line that meets the EFJ class is inverted, thereby simplifying the design complexity of the EFJ-type power amplifier. The physical length of the fan-shaped microstrip line is about 1 / 2 of the physical length of the traditional straight microstrip line. Therefore, under the same technical requirements, the circuit substrate area designed using the fan-shaped microstrip line is smaller. Under the condition of the same input impedance, after ADS simulation, the reflection coefficient S of the fan-shaped microstrip line is obtained compared with the straight microstrip line. 11 Smoother, transmission coefficient S 21 Smaller and wider bandwidth, this is because the reactance of the fan-shaped microstrip line near the resonance point changes slowly with frequency, which makes it have a wider bandwidth. Therefore, the use of branch parallel double fan-shaped microstrip lines further expands the bandwidth of the EFJ class. The output matching network is designed based on a T-type two-port network. The design method is simple. At the same time, the output matching circuit has a compact structure and has good application prospects in the field of wireless communications.

[0045] See also Figure 1, shown is a hybrid EFJ-type power amplifier based on a branch parallel dual-fan-shaped microstrip line of the present invention, characterized in that it includes an input matching network, a gate bias circuit, a transistor, an output matching network, and a drain bias circuit, wherein the input end of the input matching network serves as a power input end, and its output end is connected to the gate of the transistor, the gate bias circuit is connected in parallel with the gate of the transistor to provide a voltage required for the gate, the drain of the transistor is connected in parallel with the drain bias circuit to provide a voltage required for the drain, the drain of the transistor is connected to the input end of the output matching network, and the output end of the output matching network serves as a power output end to match to the required final impedance value;

[0046] See also Figure 2 , which shows an output matching structure based on a branch-parallel dual-fan-shaped microstrip line in the present invention, wherein the output matching circuit includes three conventional microstrip lines and two fan-shaped microstrip lines.

[0047] The input impedance expression of the fan-shaped microstrip line is:

[0048]

[0049] in, and N i(x) are Bessel functions of the first and second kind. α, r1 and r2 represent the angle, inner radius and outer radius of the fan-shaped microstrip line respectively. λ0 is the wavelength of free space. ε re is the equivalent dielectric constant and h is the thickness of the dielectric substrate.

[0050] Therefore, the impedance expression of the branch parallel double fan-shaped microstrip line can be obtained as:

[0051]

[0052] Wherein, Z7 represents the characteristic impedance of the seventh microstrip line TL7, Z rad represents the impedance of the fan-shaped microstrip line, β represents the phase constant, and l represents the length of the microstrip line.

[0053] In the output matching network, a T-type network is used. Therefore, the impedance expression of the output matching network is obtained as follows:

[0054]

[0055] Wherein, Z5 represents the characteristic impedance of the fifth microstrip line TL5, Z6 represents the characteristic impedance of the sixth microstrip line TL6, and Z in represents the impedance of the branch parallel fan-shaped microstrip line, and Z0 represents the characteristic impedance.

[0056] See also Figure 3, which shows the optimal fundamental impedance trajectory of the output matching circuit, and the trajectory shows the fundamental impedance of the designed EFJ class power amplifier, indicating that the fundamental impedance value meets the optimal fundamental impedance value range of the EFJ class, and at the same time achieves a certain control over the second and third harmonics;

[0057] See also Figure 4 , which is a simulation result diagram of the output power and efficiency of the hybrid EFJ-type power amplifier based on the branch-parallel dual-fan-shaped microstrip line of the present invention. The designed power amplifier has an output power of 40.1-42.2dBm and a drain efficiency of 62.8%-71.4% in the frequency band of 1.2-4GHz, showing good performance indicators.

[0058] In a preferred embodiment, the power amplifier is implemented using a GaN HEMT CGH40010F transistor from Cree;

[0059] In a preferred embodiment, a gate bias circuit is provided between the input matching circuit and the transistor, and its bias voltage is -2.8V;

[0060] In a preferred embodiment, a bias circuit is provided at the drain of the transistor, and the bias voltage thereof is 28V.

[0061] The present invention is based on a hybrid EFJ-type power amplifier with dual fan-shaped microstrip lines connected in parallel with branches, and is implemented by the following steps:

[0062] Step S1: design a standard EFJ class power amplifier;

[0063] Step S2: Designing an output matching network that meets the fundamental impedance of the hybrid EFJ class power amplifier, specifically comprising the following steps:

[0064] The fundamental impedance of a conventional hybrid EFJ class power amplifier is expressed as:

[0065] R * represents the optimal load impedance, ranging from 15.89-46.29Ω. γ is a coefficient ranging from -1 to 1.

[0066] According to the above output matching network structure, the input impedance expression of the output matching network structure can be obtained as follows:

[0067]

[0068] Assuming that the characteristic impedances of the fifth microstrip line TL5 and the sixth microstrip line TL6 are Z5=80Ω and Z6=30Ω, it can be deduced that Z in The value range is greater than or equal to 20.91Ω.

[0069] Then according to the formula The required branch parallel double fan-shaped microstrip line can be designed.

[0070] Step S3: Designing a harmonic control network, including the following steps:

[0071] For harmonic control, the microstrip lines TL5 and TL8 are tuned so that TL5+TL8=λ / 4, and the second harmonic is short-circuited. The microstrip lines TL5 and TL7, and the fan-shaped microstrip lines Rad stub1 and Rad stub2 are tuned so that TL5+TL7+Rad stub1 / Radstub2=λ / 12, and the third harmonic is open-circuited.

[0072] Step S4: designing a bias circuit;

[0073] Step S5: designing an input matching circuit, using a short-section variable resistor design method to further expand bandwidth and improve efficiency;

[0074] Step S6: construct an overall circuit and optimize the overall circuit to further improve the efficiency and output power of the designed circuit.

[0075] The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention. It is obvious to those skilled in the art that various modifications to these embodiments can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown in the present application, but will conform to the widest range consistent with the principles and novel features disclosed in the present application.

Claims

1. A hybrid EFJ-type power amplifier based on a branch-parallel dual-fan-shaped microstrip line, characterized in that: At least includes an input matching network, a gate bias circuit, a transistor, an output matching network and a drain bias circuit, wherein, The input end of the input matching network serves as a power input end, and the output end thereof is connected to the gate of the transistor; The transistor drain is connected to the input end of the output matching network, and the output end of the output matching network serves as the power output end; The input matching network includes a first microstrip line TL1, a second microstrip line TL2, and a third microstrip line TL3, wherein one end of the first microstrip line TL1 is connected to the power input end, and the other end is connected to the second microstrip line TL2, the other end of the second microstrip line TL2 is connected to the third microstrip line TL3, and the other end of the third microstrip line TL3 is connected to the transistor gate; The gate bias circuit includes a fourth microstrip line TL4, one end of the fourth microstrip line TL4 is connected between the second microstrip line TL2 and the third microstrip line TL3, and the other end is connected to the gate power supply; The output matching network includes a fifth microstrip line TL5, a sixth microstrip line TL6, a seventh microstrip line TL7, a first fan-shaped microstrip line Rad stub1, and a second fan-shaped microstrip line Rad stub2, wherein one end of the fifth microstrip line TL5 is connected to the transistor drain, and the other end is connected to the sixth microstrip line, and the other end of the sixth microstrip line is connected to the power output end, and one end of the seventh microstrip line is connected between the fifth microstrip line and the sixth microstrip line, and the other end is connected to the first fan-shaped microstrip line Rad stub1 and the second fan-shaped microstrip line Rad stub2, and the first fan-shaped microstrip line Rad stub1 and the second fan-shaped microstrip line Rad stub2 are connected in parallel; The drain bias circuit includes an eighth microstrip line TL8, one end of the eighth microstrip line TL8 is connected between the fifth microstrip line TL5 and the sixth microstrip line TL6, and the other end is connected to the drain power supply; A gate bias circuit is provided between the input matching circuit and the transistor, and its bias voltage is -2.8V; A bias circuit is provided at the drain of the transistor, and its bias voltage is 28V.

2. The design method of a hybrid EFJ-type power amplifier based on a branch-parallel dual-sector microstrip line as claimed in claim 1, characterized in that: The following steps are involved: Step S1: design a standard EFJ class power amplifier; Step S2: Designing an output matching network that meets the fundamental impedance of the hybrid EFJ class power amplifier, specifically comprising the following steps: According to the output matching network structure of the traditional hybrid EFJ power amplifier, the input impedance expression of the output matching network structure is obtained as follows: Let the characteristic impedance of the fifth microstrip line TL5 and the sixth microstrip line TL6 be Z5 = 80Ω, Z6 = 30Ω, then we can deduce Z in The value range is greater than or equal to 20.91Ω; Then according to the formula Design the required branch parallel dual fan-shaped microstrip line; Step S3: Designing a harmonic control network, including the following steps: For harmonic control, tune the microstrip lines TL5 and TL8 so that TL5+TL8=λ / 4, short-circuit the second harmonic, tune the microstrip lines TL5 and TL7, fan-shaped microstrip lines Rad stub1 and Rad stub2 so that TL5+TL7+Rad stub1 / Rad stub2=λ / 12, open-circuit the third harmonic; Step S4: designing a bias circuit; Step S5: designing an input matching circuit, using a short-section variable resistor design method to further expand bandwidth and improve efficiency; Step S6: construct the overall circuit and optimize the overall circuit to further improve the efficiency and output power of the designed circuit.

3. The design method of a hybrid EFJ-type power amplifier based on branch-parallel dual-sector microstrip lines according to claim 2, characterized in that: In step S5, the input matching circuit is designed using the same method as the output matching circuit.

4. The design method of a hybrid EFJ-type power amplifier based on branch-parallel dual-sector microstrip lines according to claim 2, characterized in that: The input end of the input matching network serves as the power input end, and its output end is connected to the gate of the transistor; The drain of the transistor is connected to the input end of the output matching network, and the output end of the output matching network serves as a power output end; The input matching network includes a first microstrip line TL1, a second microstrip line TL2, and a third microstrip line TL3; One end of the first microstrip line TL1 is connected to the power input end, and the other end is connected to the second microstrip line TL2, the other end of the second microstrip line TL2 is connected to the third microstrip line TL3, and the other end of the third microstrip line TL3 is connected to the transistor gate; The gate bias circuit includes a section of λ / 4 microstrip line TL4; One end of the fourth microstrip line TL4 is connected between the second microstrip line TL2 and the third microstrip line TL3, and the other end is connected to the gate power supply; The output matching network includes a fifth microstrip line TL5, a sixth microstrip line TL6, a seventh microstrip line TL7, a first fan-shaped microstrip line Rad stub1, and a second fan-shaped microstrip line Rad stub2. One end of the fifth microstrip line TL5 is connected to the drain of the transistor, and the other end is connected to the sixth microstrip line. The other end of the sixth microstrip line is connected to the power output end. One end of the seventh microstrip line is connected between the fifth microstrip line and the sixth microstrip line, and the other end is connected to the fan-shaped microstrip lines Rad stub1 and Rad stub2. The fan-shaped microstrip line Rad stub1 and the fan-shaped microstrip line Rad stub2 are connected in parallel. The drain bias circuit includes an eighth microstrip line TL8 , one end of the eighth microstrip line TL8 is connected between the fifth microstrip line TL5 and the sixth microstrip line TL6 , and the other end is connected to the drain power supply.

5. The design method of a hybrid EFJ-type power amplifier based on branch-parallel dual-sector microstrip lines according to claim 4, characterized in that: A gate bias circuit is provided between the input matching circuit and the transistor, and its bias voltage is -2.8V.

6. The design method of a hybrid EFJ-type power amplifier based on branch-parallel dual-sector microstrip lines according to claim 4, characterized in that: A bias circuit is provided at the drain of the transistor, and its bias voltage is 28V.

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