Device and method for encoding column-plane compressed data

Abstract

The present application relates to an apparatus and method for encoding column-plane compressed data. An exemplary memory includes: a memory cell array configured to store a plurality of data bits, each data bit associated with a corresponding column plane; and input / output circuitry including a compression circuit configured to provide error data based on a comparison between a plurality of data bits received from the memory cell array and an expected value and based on the corresponding column plane of the memory cell array associated with the bit. The compression circuit is further configured to encode column-plane bit errors based on the error data for provision to a data terminal.

Description

Technical Field

[0001] The present application relates to semiconductor devices, and more particularly to an apparatus and method for encoding column-plane compressed data. Background Art

[0002] During production and before being put into use, semiconductor devices (e.g., devices under test) may undergo testing operations to detect errors in the semiconductor devices. In some instances, the testing operations may include performing a write-read test, which includes writing data to a memory cell, reading the data out, and verifying that the read data matches the written data. However, for high-density memories, reading all the data from the semiconductor device may consume a significant amount of time and resources of the test equipment to transmit and process the large amount of memory during the read-out period. Summary of the Invention

[0003] One aspect of the present disclosure provides a device, wherein the device includes: a comparison circuit configured to receive a plurality of column plane read data bits during a test operation, each column plane read data bit being associated with a corresponding column plane of a memory cell array, wherein the comparison circuit is further configured to detect whether a value of a bit of the plurality of column plane read data bits is different from an expected value, and provide error data based on the detection and based on the corresponding column plane of the memory cell array associated with the bit; and an encoder circuit configured to encode a column plane bit error based on the error data to provide to a data terminal.

[0004] Another aspect of the present disclosure provides a memory, wherein the memory includes: a memory cell array configured to store multiple data bits, each data bit associated with a corresponding column plane; and an input / output circuit, the input / output circuit including a compression circuit configured to provide error data based on a comparison between bits of the multiple data bits received from the memory cell array and expected values ​​and based on the corresponding column planes of the memory cell array associated with the bits, wherein the compression circuit is further configured to encode column plane errors based on the error data to provide to data terminals.

[0005] Another aspect of the present disclosure provides a method, wherein the method includes: receiving a plurality of column plane read data bits during a test operation of a compression circuit of a semiconductor device, each column plane read data bit being associated with a corresponding column plane of a memory cell array of the semiconductor device; detecting whether values ​​of bits of the plurality of column plane read data bits are different from expected values; encoding column plane errors based on detecting whether the values ​​of the bits of the plurality of column plane read data bits have values ​​different from the expected values ​​and based on the corresponding column planes associated with the bits; and storing the column plane errors at the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of a semiconductor device according to a disclosed embodiment.

[0007] Figure 2 is a schematic block diagram of a portion of an input / output circuit according to an embodiment of the present disclosure.

[0008] Figure 3 An exemplary timing diagram of a serial transmission containing column plane errors according to an embodiment of the present disclosure.

[0009] According to an embodiment of the present disclosure, Figure 4A Tables C through C contain exemplary encodings of column-plane errors by encoder circuits.

[0010] Figure 5 is a flow chart of an exemplary method of generating column-plane bit errors according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] The following begins to set forth certain details to provide a full understanding of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure can be implemented without these specific details. In addition, the specific embodiments of the present disclosure described herein are provided by way of example and should not be used to limit the scope of the present disclosure to these specific embodiments. In other cases, well-known circuits, control signals, timing protocols, and software operations are not shown in detail to avoid unnecessarily obscuring the present disclosure.

[0012] Some materials described in this disclosure include circuit systems for semiconductor devices that include compression circuit systems configured to compress output data during test operations. For example, during test operations, data can be written to a memory cell array and then read out to verify whether the read data matches the written data. A mismatch between the read data and the written data can indicate a defect in the corresponding cell of the memory cell array. The semiconductor device can include a column plane compression circuit system that is configured to perform a logical comparison between column plane read data bits or between column plane read data bits and expected data to detect errors. The expected data can be provided externally (e.g., via a tester) or can be stored internally in a register. Based on the comparison, the column plane compression circuit system can encode a column plane error indicating the location of the error in the column plane data. The column plane error can indicate whether there is no error in the column plane data, which column plane has an error, whether there are errors on several column planes, error patterns, etc. The column plane error can be provided to the tester via one or more input / output data terminals of the semiconductor device. In some examples, column plane bit errors can be provided to a tester via one or more test input / output data terminals dedicated to the semiconductor device during testing operations. Providing column plane bit errors that provide information about detected errors can improve the ability to determine the cause of the error, compared to test circuitry that provides single-bit pass / fail flags for all column plane error data.

[0013] Figure 1 1 is a schematic block diagram of a semiconductor device 100 according to an embodiment of the present disclosure. For example, the semiconductor device 100 may include a chip 135 and a ZQ resistor (RZQ) 155. The chip 135 may include a clock input circuit 105, an internal clock generator 107, a timing generator 109, an address command input circuit 115, an address decoder 120, a command decoder 125, a mode register data mask generator 126, a plurality of row decoders 130, a memory cell array 145 including a sense amplifier 150 and a transmission gate 195, a plurality of column decoders 140, a plurality of read / write amplifiers 165, an input / output (I / O) circuit 170, a column plane compression circuit 172, a ZQ resistor (RZQ) 155, a ZQ calibration circuit 175, and a voltage generator 190. The semiconductor device 100 may include a plurality of external terminals, including address and command terminals coupled to a command / address bus 110, clock terminals CK and / CK, data terminals DQ, DQS, and DM, power supply terminals VDD, VSS, VDDQ, and VSSQ, and a calibration terminal ZQ. The chip 135 may be mounted on a substrate, such as a memory module substrate, a motherboard, or the like.

[0014] Memory cell array 145 includes multiple banks BANK0-N, each of which includes multiple word lines WL, multiple bit lines BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL. The number of banks BANK0-N can include 2, 4, 8, 16, or any other number of banks. Each of banks BANK0-N can be divided into two or more memory planes (e.g., column planes). In some examples, each of banks BANK0-N can include 2, 4, 8, 16, 32, or other column planes. The word lines WL of each bank are selected by a corresponding row decoder 130, and the bit lines BL are selected by a corresponding column decoder 140. Multiple sense amplifiers 150 are positioned for their corresponding bit lines BL and are coupled to at least one corresponding local I / O line via a transmission gate TG 195 acting as a switch. The local I / O line is further coupled to a corresponding one of at least two main I / O line pairs.

[0015] The address / command input circuit 115 may receive an address signal and a bank address signal from the outside at a command / address terminal via the command / address bus 110, and transmit the address signal and the bank address signal to the address decoder 120. The address decoder 120 may decode the address signal received from the address / command input circuit 115, and provide a row address signal XADD to the row decoder 130, and provide a column address signal YADD to the column decoder 140. The address decoder 120 may also receive a bank address signal and provide a bank address signal BADD to the row decoder 130 and the column decoder 140.

[0016] The address / command input circuit 115 may receive a command signal from the outside (e.g., the memory controller 105) at a command / address terminal via the command / address bus 110 and provide the command signal to the command decoder 125. The command decoder 125 may decode the command signal and provide various internal command signals. For example, the internal command signal may include a row command signal for selecting a word line, a column command signal for selecting a bit line (such as a read command or a write command), a mode register set command MRS that may cause the mode register to be set to the value stored in the mode register data mask generator 126, and a ZQ calibration command ZQ_com that may activate the ZQ calibration circuit 175.

[0017] Therefore, when a read command is issued and the read command is provided in time with the row address and column address, read data is read from the memory cell specified by the row address and column address in the memory cell array 145. The read / write amplifier 165 can receive the read data DQ and provide the read data DQ to the IO circuit 170. The IO circuit 170 can provide the read data DQ, as well as the data strobe signal at DQS and / or the data mask signal at DM to the outside via the data terminal DQ. Similarly, when a write command is issued and the row address and column address are provided in time with the write command, the input / output circuit 170 can receive the write data at the data terminal DQ, receive the data strobe signal at DQS and / or receive the data mask signal at DM, and provide the write data to the memory cell array 145 via the read / write amplifier 165. Therefore, the write data can be written to the memory cell specified by the row address and column address.

[0018] In some examples, the IO circuitry 170 may include a column plane compression circuit 172 configured to compress output data during a test operation. For example, during a test operation, data may be written to the memory cell array 145 and then read back out to verify that the read data matches the written data. A mismatch between the read data and the written data may indicate a defect in the corresponding cell of the memory cell array 145. To detect errors, the column plane compression circuit 172 may be configured to perform a logical comparison between bits of column plane read data read from the memory cell array 145, or between bits of column plane read data read from the memory cell array 145 and expected data. The expected data may be provided externally (e.g., via a tester) or may be stored internally in a register. Based on the comparison, the column plane compression circuit 172 may encode a column plane error code that indicates the location of an error in the column plane data. The column plane error code may indicate whether there are no errors in the column plane data, which column plane has an error, whether there are errors in several column planes, the error pattern, etc. The column plane compression circuit 172 and / or the IO circuit 170 can provide column plane bit errors to one or more data terminals DQ for access by a tester. In some examples, the column plane compression circuit 172 and / or the IO circuit 170 can provide column plane bit errors to one or more test input / output data terminals TDQ of the semiconductor device 100 that are dedicated to testing operations. Providing column plane bit errors that provide information about detected errors can improve the ability to determine the cause of the error, compared to test circuit systems that provide single-bit pass / fail flags for all column plane error data and involve performing several separate column plane read operations to determine which column plane(s) failed.

[0019] Turning to the description of the external terminals included in semiconductor device 100, clock terminals CK and / CK can receive an external clock signal and a complementary external clock signal, respectively. The external clock signal (including the complementary external clock signal) can be provided to clock input circuit 105. Clock input circuit 105 can receive the external clock signal and generate an internal clock signal ICLK. Clock input circuit 105 can provide internal clock signal ICLK to internal clock generator 107. Internal clock generator 107 can generate a phase-controlled internal clock signal LCLK based on internal clock signal ICLK and clock enable signal CKE received from address / command input circuit 115. Although not limited to this, a DLL circuit can be used as internal clock generator 107. Internal clock generator 107 can provide the phase-controlled internal clock signal LCLK to IO circuit 170 and timing generator 109. IO circuit 170 can use phase-controlled internal clock signal LCLK as a timing signal to determine the output timing of read data. Timing generator 109 can receive internal clock signal ICLK and generate various internal clock signals.

[0020] The power supply terminals can receive power supply voltages VDD and VSS. These power supply voltages VDD and VSS can be provided to voltage generator circuit 190. Voltage generator circuit 190 can generate various internal voltages based on power supply voltages VDD and VSS: VPP, VOD, VARY, VPERI, etc. Internal voltage VPP is primarily used by row decoder 130, internal voltages VOD and VARY are primarily used by sense amplifier 150 included in memory cell array 145, and internal voltage VPERI is used by many other circuit blocks. The power supply terminals can also receive power supply voltages VDDQ and VSSQ. IO circuit 170 can receive power supply voltages VDDQ and VSSQ. For example, power supply voltages VDDQ and VSSQ can be the same voltages as power supply voltages VDD and VSS, respectively. However, dedicated power supply voltages VDDQ and VSSQ can be used for IO circuit 170 and ZQ calibration circuit 175.

[0021] The calibration terminal ZQ of the semiconductor memory device 100 can be coupled to the ZQ calibration circuit 175. The ZQ calibration circuit 175 can perform a calibration operation with reference to the impedance of the ZQ resistor (RZQ) 155. In some examples, the ZQ resistor (RZQ) 155 can be mounted on a substrate coupled to the calibration terminal ZQ. For example, the ZQ resistor (RZQ) 155 can be coupled to the power supply voltage (VDDQ). The impedance code ZQCODE obtained by the calibration operation can be provided to the IO circuit 170, and thus the impedance of the output buffer (not shown) included in the IO circuit 170 is specified.

[0022] Figure 22 is a schematic block diagram of a portion of an IO circuit 270 according to an embodiment of the present disclosure. For example, the IO circuit 270 may include a column plane compression circuit 272, a serializer circuit 274, and a data terminal DQ 276. Figure 1 The semiconductor device 100 may implement a portion of the IO circuit 270 .

[0023] The column plane compression circuit 272 can be configured to receive column plane data CP0-CPN and ECC bits. In some instances, the CP0-CPN and ECC data can include multiple bits of data for each column plane. In some instances, the semiconductor device can be implemented without an ECC plane. Therefore, although the foregoing description contemplates including ECC data in the column plane data CP0-CPN, it should be understood that an implementation in which the column plane compression circuit 272 only receives column plane data CP0-CPN is within the scope of the present disclosure. For example, for column plane 0, CP0 can include multiple bits (e.g., 4, 8, 16, etc.); for column plane 1, CP1 can include multiple bits (e.g., 4, 8, 16, etc.), and so on. Therefore, in a specific non-limiting example, if each of the column planes and ECC circuits provides corresponding 8 bits of data, and there are 16 column planes in CP0-CPN, the CP0-CPN and ECC data can include 136 bits of data.

[0024] The column plane compression circuit 272 may include a comparison circuit 222 and an encoder circuit 224. The comparison circuit 222 may be configured to perform a comparison of the CPO-CPN and ECC data to detect errors. The comparison circuit 222 may determine whether the CPO-CPN and ECC data contain errors by detecting which bits of the CPO-CPN and error correction code (ECC) data are different from the expected value, and provide a corresponding CPO-CPN and ECC pass / fail flag (e.g., bit) for each of the column plane and the ECC plane. In some instances, the expected value may be determined based on the logical value of the majority of the bits of the CPO-CPN and ECC data. In other instances, the expected value may be provided to the comparison circuit 222 by a tester and / or may be stored or provided internally. The comparison circuit 222 may set the CPO-CPN and ECC pass / fail flag for each column plane and ECC based on the detected error.

[0025] The encoder circuit 224 can receive the CPO-CPN and / or ECC pass / fail flags and can encode the CP error (e.g., CP ERR0-CP ERRM) based on the values ​​of the CPO-CPN and ECC pass / fail flags. A CP error with M+1 bits (e.g., CP ERR0-CP ERRM) contains fewer bits than the count of the column plane and ECC (e.g., N+2). The encoded value of the CP error can indicate a pattern of no column plane failure, a single column plane failure, multiple column plane failures, or any combination thereof. For example, in the case of a single CP or ECC failure, the encoder circuit 224 can encode the CP error with a value that identifies a specific column plane or ECC. In instances where more than one column plane fails, the encoder circuit 224 can encode a value indicating multiple column plane failures. In some instances, failures of multiple column planes may have some logical relationship within the semiconductor device that indicates a failure mode (e.g., sharing a common control signal / line, etc.), and similarly, encoder circuit 224 may encode the CP error as a value indicating the failure mode. Encoder circuit 224 may provide the CP error to serializer circuit 274.

[0026] In some examples, the serializer circuit 274 can receive CP error bits (e.g., CP ERR0-CP ERRM) in parallel and can serialize the CP errors to provide to the data terminal DQ 276. In other examples, the CP error bits can be provided in parallel to multiple data terminals DQ 276 to be output in parallel. In some examples, in addition to or as an alternative to providing the CP errors to the data terminal DQ 276, the CP errors can be stored and / or used internally.

[0027] In operation, the column plane compression circuit 272 can be configured to compress the CPO-CPN data during a test operation. For example, during a test operation, data can be written to the memory cell array and then read out to verify whether the read data matches the written data. In some instances, a mismatch between the read data and the written data can be used to indicate a defect in the corresponding cell of the memory cell array (for example, when the mismatch is an unexpected or unintended result). In some instances, the mismatch can indicate the correct operation of various other functions and logic within the semiconductor device (for example, when the mismatch is an expected or expected result). The column plane compression circuit 272 can be configured to perform a logical comparison between the CPO-CPN and ECC data bits read from the memory cell array to detect errors, and encode the CP bit error to provide an indication of the location of the error in the column plane data.

[0028] Comparison circuit 222 can determine whether the CPO-CPN and ECC data contain errors by determining that the bits of the CPO-CPN and ECC data are different from the expected values. When a bit is detected to have a value different from the expected value, comparison circuit 222 can be configured to set one of the corresponding CPO-CPN and ECC pass / fail flags (e.g., bits) associated with the column plane or ECC plane containing the unexpected data. In some instances, errors can be detected based on a logical bit-by-bit comparison between bits. In some instances, the expected value can be determined based on the logical values ​​of the majority of the bits of the CPO-CPN and ECC data. Therefore, if two bits do not pass the logical bit-by-bit comparison (e.g., XOR or NAND bit-by-bit comparison), the bit considered to have failed can be based on which of the two bits has a common logical value with the majority of the selected group or all bits of the CPO-CPN and ECC data. In other instances, the expected value can be provided to comparison circuit 222 from the outside (e.g., via a tester) and / or can be set or stored from the inside.

[0029] Encoder circuit 224 can receive CPO-CPN and ECC pass / fail flags and can encode CP errors based on the values ​​of the CPO-CPN and ECC pass / fail flags. In some instances, encoder circuit 224 includes logic to determine the encoded value of the CP error. In other instances, encoder circuit 224 can look up the encoded value in a table based on the CPO-CPN and ECC pass / fail flags. The encoded value of the CP error can indicate a pattern of no column plane or ECC failure, a single column plane failure, multiple column plane failures, or any combination thereof. For example, in the case of a single CP or ECC failure, encoder circuit 224 can encode the CP error using a value identifying the specific column plane or ECC. In instances where more than one column plane fails, encoder circuit 224 can encode a value indicating multiple column plane failures. In some instances, the failures of multiple column planes may have some logical relationship within the semiconductor device that indicates a failure mode (e.g., sharing a common control signal / line, etc.), and similarly, encoder circuit 224 can encode the CP error as a value indicating the failure mode. Encoder circuit 224 may provide the CP error to serializer circuit 274 .

[0030] According to an embodiment of the present disclosure, Figure 4A Tables 400 through C contain tables 401 and 402 of exemplary encodings of CP errors by encoder circuit 224 . Figures 4A to 4C The examples provided in are intended to cover one specific implementation. It should be understood that the encoding of CP errors can be applied to different implementations with more or fewer column planes, with or without ECC planes, with more or fewer CP error bits, etc., or any combination thereof, without departing from the scope of this disclosure. Figure 4ATable 400 in Figure 4 depicts an exemplary CP error coding for a semiconductor device comprising eight column planes and one ECC plane. The implementation of table 400 includes four bits for a total of 16 different coding options. In the example of a semiconductor device comprising eight column planes and one ECC plane, ten codes would be used (e.g., no errors, one code for each individual column plane, and one code for ECC), and six codes would remain available to encode other failure modes, such as multiple column plane failures, multiple column plane failure modes, a combination of ECC and column plane failures, etc., or any combination thereof.

[0031] Figure 4B Table 401 in Figure 4 depicts an exemplary CP error coding for a semiconductor device including 16 column planes and an ECC. The implementation of Table 401 includes five bits for a total of 32 different coding options. In the example of a semiconductor device including 16 column planes and an ECC, 18 codes will be used (e.g., no errors, one code for each individual column plane, and one code for ECC), and 14 codes will remain available to encode other failure modes, such as multiple column plane failures, multiple column plane failure modes, a combination of ECC and column plane failures, etc., or any combination thereof.

[0032] Figure 4C Table 402 in FIG. 4 depicts an exemplary multi-column plane CP error coding for a semiconductor device including eight column planes and one ECC. Assume that the first ten codes (e.g., b0000 to b1010) are assigned to error-free, eight column planes, and ECC (e.g., Figure 4A 400 ), an eleventh code (eg, b1011 ) may indicate a failure of both column planes 0 and 1 , a twelfth code may indicate a failure of both column planes 2 and 3 , and so on.

[0033] It should be noted that Figures 4A to 4C The coding examples provided in Tables 400, 401, and 402 are exemplary. Different codings may be implemented without departing from the scope of this disclosure. Furthermore, more or fewer bits than described may be included in the CP error to allow for more or fewer coding options.

[0034] Back to Figure 2 In some examples, serializer circuit 274 may receive CP error bits (eg, CP ERR0-CP ERRM) in parallel and may serialize the CP error bits to provide to data terminal DQ 276. Figure 3An exemplary timing diagram 300 of serial transmission including CP error according to an embodiment of the present disclosure. At time T0, the semiconductor device receives an activation command ACT to prepare the semiconductor device for a read operation. At times T1 and T2, the semiconductor device receives consecutive first read commands RD0 and second read commands RD1, respectively. At time T3 after a delay of a read latency RL, the IO circuit 270 (e.g., or Figure 1 The IO circuit 170 of the embodiment of the present invention begins to serially transmit a first CP error associated with the first read command RD0 at the serializer circuit 274. The serialized first CP error may be generated by the serializer circuit 274. Immediately after transmitting the last bit of the first CP error at time T4, the IO circuit 270 begins to serially transmit a second CP error associated with the second read command RD1 at the serializer circuit 274. The serialized second CP error may be generated by the serializer circuit 274.

[0035] In other examples, bits of CP errors may be sent in parallel or partially in parallel via multiple data terminals DQ 276. Providing column plane errors that provide information about detected errors may improve the ability to determine the cause of the error compared to test circuitry that provides single-bit pass / fail flags for all column plane error data and involves performing several separate column plane read operations to determine which column plane(s) failed.

[0036] Figure 5 is a flow chart of an exemplary method 500 for generating column-plane bit errors according to an embodiment of the present disclosure. The method 500 may be performed by Figure 1 IO circuit 170 and / or Figure 2 The IO circuit 270 is used to perform.

[0037] The method 500 may include receiving a plurality of column plane read data bits, each column plane read data bit associated with a corresponding column plane of a memory cell array of the memory device, during a test operation of a compression circuit of the memory device (at 510). The compression circuit may include Figure 1 The column plane compression circuit 172 and / or Figure 2 In some examples, the plurality of column plane read data bits may include Figure 2 In some examples, method 500 may include writing desired data to a memory cell array of a semiconductor device before receiving a plurality of column plane read data bits during a test operation.

[0038] The method 500 may further include detecting whether the values ​​of the bits of the plurality of column plane read data bits are different from the expected values ​​(at 520). The detection may be performed by Figure 2In some examples, the comparison circuit 222 may provide error data based on a comparison between a plurality of column plane read data bits received from the memory cell array and an expected value and based on the corresponding column plane of the memory cell array associated with the bit. The error data may include Figure 2 CP0-CPN and ECC pass / fail flags. In some instances, method 500 may include receiving an expected value for a bit from a tester. In some instances, method 500 may include determining the expected value based on a logical bit-by-bit comparison between a plurality of column-plane read data bits. In some instances, the logical bit-by-bit comparison may include a bit-by-bit XOR, a comparison, a bit-by-bit NAND comparison, or a combination thereof between at least two bits of the plurality of column-plane read data bits. In some instances, method 500 may include selecting one of the first logic value or the second logic value as the expected value based on whether more than half of a group of the plurality of column-plane read data bits has the first logic value or the second logic value.

[0039] The method 500 may further include encoding (at 530) a column plane bit error based on detecting whether a value of a bit of the plurality of column plane read data bits has a value different from an expected value and based on the corresponding column plane associated with the bit. The encoding may be performed by Figure 2 The encoder circuit 224 performs the above. The column plane bit errors may include Figure 2 In some instances, the CP error rate can be calculated based on Figures 4A to 4C The encoding may be performed using tables 400, 401, and / or 402 of the present disclosure. Other encoding schemes may be implemented without departing from the scope of the present disclosure. In some examples, method 500 may include encoding a column-plane bit error with a first value in response to a value of a bit of the plurality of column-plane read data bits being different from an expected value when the bit is associated with a first column plane, and encoding the column-plane bit error with a second value in response to a value of a bit of the plurality of column-plane read data bits being different from an expected value when the bit is associated with a second column plane.

[0040] In some instances, method 500 may include, in response to a value of a bit of the plurality of column plane read data bits being different from an expected value: encoding a column plane error with a first value based on a corresponding column plane associated with the bit when all other bits of the plurality of column plane read data bits match the expected value, and encoding the column plane error with a second value in response to a value of a second bit of the plurality of column plane read data bits being different from the expected value when the second bit is associated with a corresponding column plane different from the bit.

[0041] The method 500 may further include storing the column plane errors at the semiconductor device (at 540). In some examples, the method 500 may further include providing the column plane errors to an output of the semiconductor device and / or internal logic of the semiconductor device (e.g., error correction circuitry, row or column replacement logic, etc.). The output of the semiconductor device may include one or more Figure 1 Data terminal DQ or test data terminal TDQ and / or Figure 2 In some embodiments, the output of the semiconductor device is a test data terminal or a data terminal. In some embodiments, the method 500 may include serializing the bits of the column plane error to provide to the output of the semiconductor device, for use in the internal logic of the semiconductor device, or any combination thereof. In some embodiments, the serialization of the bits of the column plane error may be performed by Figure 2 The serializer circuit 274 is used to perform.

[0042] Although the detailed description describes certain preferred embodiments and examples, it will be understood by those skilled in the art that the scope of this disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of embodiments and their obvious modifications and equivalents. In addition, other modifications within the scope of this disclosure will be apparent to those skilled in the art. It is also conceivable that various combinations or sub-combinations may be made to the specific features and aspects of the embodiments, and that the various combinations or sub-combinations still fall within the scope of this disclosure. It should be understood that the various features and aspects of the disclosed embodiments may be combined or substituted with each other to form different modes of the disclosed embodiments. Therefore, the specifically disclosed embodiments described above should not limit the scope of at least some of the disclosure.

Claims

1. A device comprising: a comparison circuit configured to receive a plurality of column plane read data bits during a test operation, each of the column plane read data bits being associated with a corresponding column plane of a memory cell array, wherein the comparison circuit is further configured to detect whether a value of each of the plurality of column plane read data bits is different from an expected value, and to provide error data based on a detection result of a corresponding bit of the plurality of column plane read data bits and the corresponding column plane associated with the corresponding bit, wherein the comparison circuit is configured to determine the expected value based on a logical bit-by-bit comparison between the plurality of column plane read data bits; and An encoder circuit is configured to encode column-plane bit errors based on the error data to provide to a data terminal. 2 . The apparatus of claim 1 , wherein the comparison circuit is configured to receive the expected value of the bit from a tester. 3 . The apparatus of claim 1 , wherein the logical bit-by-bit comparison comprises a bit-by-bit XOR, a comparison, a bit-by-bit NAND comparison, or a combination thereof between at least two bits of the plurality of column-plane read data bits.

4. The apparatus of claim 1 , wherein the comparison circuit is configured to select one of the first logic value or the second logic value as the expected value based on whether more than half of the plurality of column-plane read data bits have the first logic value or the second logic value.

5. The device according to claim 1 further includes a serializer, which is configured to convert the bits of the column plane error represented in the form of parallel data into the bits of the column plane error represented in the form of serial data, and provide the bits of the column plane error represented in the form of serial data to the data terminal, and the data terminal is configured as a test data terminal.

6. A device comprising: a comparison circuit configured to receive a plurality of column plane read data bits during a test operation, each of the column plane read data bits being associated with a corresponding column plane of a memory cell array, wherein the comparison circuit is further configured to detect whether a value of each of the plurality of column plane read data bits is different from an expected value, and to provide error data based on a detection result of a corresponding bit of the plurality of column plane read data bits and the corresponding column plane associated with the corresponding bit; and an encoder circuit configured to encode column plane errors based on the error data for provision to a data terminal, wherein the encoder circuit is configured, in response to the error data indicating that the value of the bit of the plurality of column plane read data bits is different from the expected value and is associated with a first column plane: encoding the column plane bit error with a first value based on the first column plane, wherein the error data indicates that all other bits of the plurality of column plane read data bits match the expected value; and In response to the error data indicating that the value of a second bit associated with a second column plane of the plurality of column-plane read data bits is different than the expected value, the column-plane bit error is encoded with a second value.

7. A memory comprising: a memory cell array configured to store a plurality of data bits, each of the data bits being associated with a respective column plane; and an input / output circuit comprising a compression circuit configured to provide error data based on a comparison between bits of the plurality of data bits received from the memory cell array and expected values ​​and based on corresponding column planes of the memory cell array associated with the bits, wherein the compression circuit is further configured to encode column plane errors based on the error data for provision to data terminals, wherein the compression circuit is configured to select one of the first logic value or the second logic value as the expected value based on whether more than half of the plurality of data bits have the first logic value or the second logic value.

8. The memory according to claim 7, wherein the compression circuit is configured to: responsive to the error data indicating that the value of the bit of the plurality of data bits is different from the expected value and is associated with a first column plane, encoding the column plane bit error with a first value; and In response to the error data indicating that the value of the bit of the plurality of data bits is different from the expected value and is associated with a second column plane, encoding the column plane bit error with a second value.

9. A method comprising: receiving, during a test operation of a compression circuit of a semiconductor device, a plurality of column plane read data bits, each of the column plane read data bits being associated with a respective column plane of a memory cell array of the semiconductor device; determining an expected value based on a logical bit-by-bit comparison between the plurality of column plane read data bits; detecting whether a value of each of the plurality of column plane read data bits is different from the expected value; encoding a column plane error based on detecting whether the value of the bit of the plurality of column plane read data bits has the value different from the expected value and based on the corresponding column plane associated with the bit; as well as The column plane errors are stored at the semiconductor device.

10. The method of claim 9, further comprising receiving the expected value of the bit from a tester.

11. The method of claim 9, wherein the logical bit-by-bit comparison comprises a bit-by-bit XOR, a comparison, a bit-by-bit NAND comparison, or a combination thereof between at least two bits of the plurality of column-plane read data bits.

12. The method of claim 9, further comprising selecting one of the first logic value or the second logic value as the expected value based on whether more than half of the plurality of column-plane read data bits have the first logic value or the second logic value.

13. The method according to claim 9, further comprising: encoding the column plane bit error with a first value in response to the value of the bit of the plurality of column plane read data bits being different than the expected value when the bit is associated with a first column plane; as well as When the bit is associated with a second column plane, the column plane bit error is encoded with a second value in response to the value of the bit of the plurality of column plane read data bits being different than the expected value.

14. The method of claim 9 , further comprising: in response to the value of the bit of the plurality of column plane read data bits being different from the expected value: encoding the column plane bit error with a first value based on the corresponding column plane associated with the bit when all other bits of the plurality of column plane read data bits match the expected value; and The column plane error is encoded with a second value in response to a value of the second bit of the plurality of column plane read data bits being different from the expected value when the second bit is associated with a corresponding column plane different from the bit.

15. A method comprising: receiving, during a test operation of a compression circuit of a semiconductor device, a plurality of column plane read data bits, each of the column plane read data bits being associated with a respective column plane of a memory cell array of the semiconductor device; detecting whether a value of each of the plurality of column plane read data bits is different from an expected value; encoding a column plane error based on detecting whether the value of the bit of the plurality of column plane read data bits has the value different from the expected value and based on the corresponding column plane associated with the bit; storing the column plane errors at the semiconductor device; and The bits of the column plane error represented in the form of parallel data are converted into bits of the column plane error represented in the form of serial data, and the bits of the column plane error represented in the form of serial data are provided to the output of the semiconductor device, the internal logic of the semiconductor device, or the output of the semiconductor device and the internal logic of the semiconductor device.

16. The method according to claim 15, wherein the output of the semiconductor device is a test data terminal.

17. The method according to claim 15, further comprising: During a test operation, data is written to the memory cell array of the semiconductor device before receiving the plurality of column-plane read data bits.

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