Semiconductor package with reinforcement structure

Abstract

A semiconductor package with a reinforcement structure is disclosed. The semiconductor package includes a substrate, an interposer located on the substrate, and a first logic chip, a second logic chip, a memory stack, and a reinforcement chip, all of which are located on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding logic chip in the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each reinforcement chip is arranged between corresponding memory stacks to align with and overlap a boundary area between the first logic chip and the second logic chip.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0146833 filed in the Korean Intellectual Property Office on November 15, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Some exemplary embodiments of the present disclosure relate to a semiconductor package including a logic chip, a memory chip, and a stiffening structure mounted on an interposer of a substrate. Background Art

[0004] For the next generation of high-performance communication equipment, semiconductor packages including logic devices and high-bandwidth memory (HBM) devices are being studied. Such semiconductor packages may include an interposer mounted on a substrate, and a logic chip and a plurality of memory stacks mounted on the interposer. In particular, semiconductor packages designed to be suitable for mobile communications are made very thin, so the resistance to external physical stress (e.g., warping) may be very weak. In addition, warping of the chip may easily occur in the extension direction of the boundary area (or boundary line) of the chip. In this case, the resulting semiconductor package may be physically damaged or electrically damaged. Summary of the invention

[0005] Some example embodiments of the present disclosure provide a package having a reinforcement structure capable of avoiding or limiting warping.

[0006] Some example embodiments of the present disclosure also provide a reinforcement structure capable of protecting constituent elements from physical impact.

[0007] Various problems to be solved by some exemplary embodiments of the present disclosure will be described in detail in the specification.

[0008] A semiconductor package according to an embodiment of the present disclosure may include: a substrate; an interposer located on the substrate; a first logic chip and a second logic chip located on the interposer, the first logic chip and the second logic chip being arranged side by side and adjacent to each other; memory stacks located on the interposer, each of the memory stacks including a plurality of stacked memory chips and being adjacent to a corresponding logic chip in the first logic chip and the second logic chip; and a reinforcement chip located on the interposer, the reinforcement chip being located between corresponding memory stacks in the memory stacks and being aligned with and overlapping a boundary area between the first logic chip and the second logic chip.

[0009] A semiconductor package according to some example embodiments of the present disclosure may include: a substrate; an interposer located on the substrate; a first logic chip and a second logic chip located adjacent to each other on the interposer; a first memory stack and a second memory stack, the first memory stack being located at opposite side surfaces of the first logic chip, the second memory stack being located at opposite side surfaces of the second logic chip; and a reinforcement chip located between the first memory stack and the second memory stack. The first logic chip and the second logic chip may be electrically connected through wiring inside the interposer. The minimum distance between the first logic chip and the second logic chip may be less than the minimum distance between the first memory stack and the second memory stack. The reinforcement chip may be adjacent to a boundary region between the first logic chip and the second logic chip and aligned with an extension line of the boundary region. The width of the reinforcement chip may be greater than the width of the boundary region.

[0010] A semiconductor package according to some example embodiments of the present disclosure may include: a substrate; an interposer located on the substrate; a plurality of logic chips located on the interposer, the plurality of logic chips being adjacent to each other within 100 mm and being electrically connected through the interposer; a plurality of memory stacks located on the interposer, each of the memory stacks comprising a plurality of stacked memory chips and a through-via extending vertically through the memory chips; a plurality of reinforcement chips located on the interposer, the long sides of the reinforcement chips being parallel to the short sides of the memory stacks, the short sides of the reinforcement chips corresponding to 1 / 2 or less of the length of the long sides of the memory stacks, and the width of each of the reinforcement chips being greater than the width of a boundary region between corresponding logic chips among the plurality of logic chips, so that the plurality of reinforcement chips horizontally overlap with a portion of the corresponding logic chips, and a molding compound surrounding side surfaces of the interposer, side surfaces of the logic chips, side surfaces of the memory stacks, and side surfaces of the reinforcement chips.

[0011] Various effects according to the exemplary embodiments of the present disclosure will be described in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A is a projection top view schematically illustrating a semiconductor package according to some example embodiments of the present disclosure.

[0013] Figure 1B is along Figure 1A The line I-I' in Figure 1A A cross-sectional view or projected side view of a semiconductor package is shown.

[0014] Figure 1C and Figure 1D It is along Figure 1A The line II-II' in Figure 1A A cross-sectional view or projected side view of a semiconductor package is shown.

[0015] Figure 1E is an enlarged side view of the memory stack.

[0016] Figure 2A is a projection top view schematically illustrating a semiconductor package according to some example embodiments of the present disclosure.

[0017] Figure 2B It is along Figure 2A The line III-III' in Figure 2A A cross-sectional view or projected side view of a semiconductor package is shown.

[0018] Figure 2C and Figure 2D It is along Figure 2A The line IV-IV' in Figure 2A A cross-sectional view or projected side view of a semiconductor package is shown.

[0019] Figures 2E to 2H are projection top views schematically illustrating semiconductor packages according to various example embodiments of the present disclosure, respectively.

[0020] Figure 3A and Figure 3B are cross-sectional views schematically illustrating semiconductor packages according to example embodiments of the present disclosure, respectively.

[0021] Figure 4A is a projection top view or a projection layout view of a semiconductor package according to some example embodiments of the present disclosure.

[0022] Figure 4B and Figure 4C is along Figure 4A The line V-V' in Figure 4A A cross-sectional view or projected side view of a semiconductor package is shown.

[0023] Figure 5A and Figure 5B are cross-sectional views schematically illustrating semiconductor packages according to example embodiments of the present disclosure, respectively.

[0024] 6A to 6F They are respectively projected top views of semiconductor packages according to example embodiments of the present disclosure. DETAILED DESCRIPTION

[0025] Figure 1Ais a projection top view schematically illustrating a semiconductor package 100A according to some example embodiments of the present disclosure.

[0026] refer to Figure 1A , a semiconductor package 100A according to some exemplary embodiments of the present disclosure may include an interposer 20 disposed on a substrate 10 , upper and lower logic chips 31 and 32 , a plurality of memory stacks 41 a to 41 d and 42 a to 42 d , and reinforcement chips 51 a and 51 b .

[0027] The interposer 20 may be mounted on the substrate 10. The substrate 10 and the interposer 20 may each include one of a printed circuit board (PCB), a flexible PCB (FPCB), a silicon-based substrate, a ceramic substrate, a glass substrate, and / or an insulating circuit board. In some example embodiments, the substrate 10 may include a PCB or an FPCB. The interposer 20 may include a silicon-based substrate or a redistribution structure.

[0028] The upper logic chip 31 and the lower logic chip 32 may be arranged side by side in the column direction so that the upper logic chip 31 and the lower logic chip 32 are arranged adjacent to each other. The upper logic chip 31 and the lower logic chip 32 may each include a core processor, an application specific integrated circuit (ASIC), a mobile application processor (AP), and / or one of other processing chips. The terms "upper" and "lower" are used to distinguish the logic chips 31 and 32 in the drawings. The upper logic chip 31 and the lower logic chip 32 may be arranged horizontally at the same level.

[0029] The memory stacks 41a to 41d and 42a to 42d may include first to fourth upper memory stacks 41a to 41d arranged side by side in the row direction relative to the upper logic chip 31, and first to fourth lower memory stacks 42a to 42d arranged side by side in the row direction relative to the lower logic chip 32. The row direction and the column direction are opposite to each other and may be interchanged with each other.

[0030] The first to fourth upper memory stacks 41a to 41d may be arranged in parallel and symmetrically on opposite sides of the upper logic chip 31 along the row direction. In detail, the first upper memory stack 41a and the second upper memory stack 41b may be arranged on the first side surface of the upper logic chip 31 (e.g., the left side of the upper logic chip 31), and the third memory stack 41c and the fourth memory stack 41d may be arranged on the second side surface of the upper logic chip 31 (e.g., the right side of the upper logic chip 31). The first upper memory stack 41a and the second upper memory stack 41b may be aligned with each other in the column direction while being arranged side by side in the column direction. Similarly, the third upper memory stack 41c and the fourth upper memory stack 41d may be aligned with each other in the column direction while being arranged side by side in the column direction. Therefore, the first upper memory stack 41a and the third upper memory stack 41c may be arranged at a higher level than the second upper memory stack 41b and the fourth upper memory stack 41d.

[0031] The first to fourth lower memory stacks 42a to 42d may be arranged in parallel and symmetrically on opposite sides of the lower logic chip 32 along the row direction. Specifically, the first lower memory stack 42a and the second lower memory stack 42b may be arranged on the first side surface of the lower logic chip 32 (e.g., the left side of the lower logic chip 32), and the third memory stack 42c and the fourth memory stack 42d may be arranged on the second side surface of the lower logic chip 32 (e.g., the right side of the lower logic chip 32). The first lower memory stack 42a and the second lower memory stack 42b may be aligned with each other in the column direction while being arranged side by side in the column direction. Similarly, the third lower memory stack 42c and the fourth lower memory stack 42d may be aligned with each other in the column direction while being arranged side by side in the column direction. Therefore, the first lower memory stack 42a and the third lower memory stack 42c may be arranged at a higher level than the second lower memory stack 42b and the fourth lower memory stack 42d.

[0032] The reinforcing chips 51a and 52b may be arranged to be aligned with the boundary region (border line) between the upper logic chip 31 and the lower logic chip 32 in the row direction, while overlapping the boundary region (border line) in the row direction. The width of the reinforcing chips 51a and 51b may be greater than the width of the boundary region (border line) between the upper logic chip 31 and the lower logic chip 32. Therefore, the reinforcing chips 51a and 51b may overlap a portion of the upper logic chip 31 and a portion of the lower logic chip 32 in the row direction.

[0033] The reinforcing chips 51a and 51b may include: a first reinforcing chip 51a disposed on the left side of the boundary area (border line) between the upper logic chip 31 and the lower logic chip 32, and a second reinforcing chip 51b disposed on the right side of the boundary area (border line) between the upper logic chip 31 and the lower logic chip 32. The first reinforcing chip 51a may be aligned with the first upper memory stack 41a and the second upper memory stack 41b and the first lower memory stack 42a and the second lower memory stack 42b in the column direction. The second reinforcing chip 51b may be aligned with the third upper memory stack 41c and the fourth upper memory stack 41d and the third lower memory stack 42c and the fourth lower memory stack 42d in the column direction. For example, the first reinforcing chip 51a may be disposed between the second upper memory stack 41b and the first lower memory stack 42a, and the second reinforcing chip 51b may be disposed between the fourth upper memory stack 41d and the third lower memory stack 42c. The size of the reinforcing chips 51a and 51b may be smaller than the size of the memory stacks 41a to 41d and 42a to 42d. The length of the short side of the reinforcing chips 51a and 51b is less than the length of the long side of the memory stacks 41a to 41d and 42a to 42d, so that the length of the short side is 1 / 2 of the length of the long side or less. The length of the long side of the reinforcing chips 51a and 51b may be less than the length of the short side of the memory stacks 41a to 41d and 42a to 42d. The long sides of the reinforcing chips 51a and 51b may be parallel to the short sides of the memory stacks 41a to 41d and 42a to 42d. Some of the short sides of the reinforcing chips 51a and 51b may be aligned with some of the long sides of the long sides of the memory stacks 41a to 41d and 42a to 42d.

[0034] The upper logic chip 31 and the lower logic chip 32 may be arranged to be spaced apart from each other or adjacent to each other at a distance of about 0.04mm to 0.08mm. In some example embodiments, the upper logic chip 31 and the lower logic chip 32 may be arranged to be spaced apart from each other or adjacent to each other at a distance of about 0.06mm. That is, the logic chips 31 and 32 may be arranged to be very close to each other. The logic chips 31 and 32 and the memory stacks 41a to 41d and 42a to 42d may be arranged to be spaced apart from each other or adjacent to each other at a distance of about 0.5mm to 0.9mm. In some example embodiments, the logic chips 31 and 32 and the memory stacks 41a to 41d and 42a to 42d may be arranged to be spaced apart from each other or adjacent to each other at a distance of about 0.7mm.

[0035] When the term "approximately" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value includes a manufacturing or operating tolerance (e.g., 10%) around the numerical value. In addition, when the words "usually" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the tolerance of the shape is required to be within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified to "approximately" or "substantially", it should be understood that these numerical values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., 10%) around the numerical value or shape. Although the terms "same" or "same" are used in the description of the example embodiments, it should be understood that there may be some inaccuracies. Therefore, when an element or value is referred to as being the same as another element or value, it should be understood that the element or value is the same as the other element or value within the desired manufacturing or operating tolerance range (e.g., 10%).

[0036] For example, the first gap (e.g., the first minimum distance) between the logic chips 31 and 32 may be smaller than the second gap (the second minimum distance) between one of the logic chips 31 and 32 and the adjacent memory stacks in the memory stacks 41a to 41d and 42a to 42d. The third gap (the third minimum distance) between one of the logic chips 31 and 32 and the adjacent reinforcement chips in the reinforcement chips 51a and 51b may be larger than the second gap (the second minimum distance). For example, the memory stacks 41a to 41d and 42a to 42d may be arranged closer to the logic chips 31 and 32 than the reinforcement chips 51a and 51b, respectively. The fourth gap (the fourth minimum distance) between one of the reinforcement chips 51a and 51b and the adjacent memory stacks in the memory stacks 41a to 41d and 42a to 42d may be smaller than the fifth gap (the fifth minimum distance) between two adjacent memory stacks in the memory stacks 41a to 41d and 42a to 42d. In some example embodiments, a first gap (eg, a first minimum distance) between the logic chips 31 and 32 may be smaller than a fifth gap (a fifth minimum distance) between adjacent memory stacks of the memory stacks 41 a to 41 d and 42 a to 42 d.

[0037] Figure 1B is along Figure 1A The line I-I' in Figure 1A A cross-sectional view or projected side view of a semiconductor package 100A is shown. Figure 1C and Figure 1D It is along Figure 1A The line II-II' in Figure 1A A cross-sectional view or projected side view of a semiconductor package 100A is shown.

[0038] refer to Figures 1A to 1D, the semiconductor package 100A, 100Aa or 100Ab according to some example embodiments of the present disclosure may include an interposer 20, logic chips 31 and 32, memory stacks 41a to 41d and 42a to 42d, reinforcing chips 51a and 51b, and a molding compound 80 disposed on a substrate 10. The semiconductor package 100A, 100Aa or 100Ab may also include a substrate bump 61, an interposer bump 62, a chip bump 63, and bottom fillers 71 and 72. The substrate bump 61 may be disposed at a lower portion of the substrate 10. The interposer bump 62 may be disposed between the substrate 10 and the interposer 20. The chip bump 63 may be disposed between the interposer 20 and the logic chips 31 and 32 and between the interposer 20 and the memory stacks 41a to 41d and 42a to 42d. The substrate bump 61, the interposer bump 62, and the chip bump 63 may each include a solder ball or a metal. The reinforcing chips 51a and 51b may have a hexahedral or solid shape. In some example embodiments, the reinforcing chips 51a and 52a may each include a solid dummy chip and a plurality of stacked dummy chips. That is, each reinforcing chip 51a and 51b may include a chip stack. The reinforcing chips 51a and 51b may include a portion of a silicon wafer (silicon die), a portion of a printed circuit board, a metal or ceramic die, an epoxy compound, a cured polymer resin, an inorganic material such as glass, and / or other hard materials.

[0039] The thickness of the substrate 10 may be about 1.5 mm to 2 mm. In some example embodiments, the thickness of the substrate 10 may be about 1.722 mm. The interposer 20 may be thinner than the substrate 10, or the interposer 20 and the substrate 10 may have the same thickness. For example, the thickness of the interposer 20 may be about 0.05 mm to 0.15 mm. In some example embodiments, the thickness of the interposer 20 may be about 0.11 mm. That is, the substrate 10 and the interposer 20 are very thin, and therefore, the electrical connection of the logic chip 31, the memory stacks 41a to 41d and 42a to 42d, the interposer 20 and the substrate 10 cannot be provided with much protection from physical stress such as warping. The diameter or vertical height of the substrate bump 61 may be about 0.2 mm to 0.8 mm. In some example embodiments, the diameter or vertical height of the substrate bump 61 may be about 0.46 mm. The diameter or vertical height of the interposer bump 62 may be approximately 0.05 mm to 0.1 mm smaller than the diameter or vertical height of the substrate bump 61. In some example embodiments, the diameter or vertical height of the interposer bump 62 may be approximately 0.07 mm. The diameter or vertical height of the chip bump 63 may be approximately 0.02 mm to 0.05 mm. In some example embodiments, the diameter or vertical height of the chip bump 63 may be approximately 0.0356 mm smaller than the diameter or vertical height of the interposer bump 62. The total height of the semiconductor package 100A may be approximately 2.7 mm to 3.3 mm. In some example embodiments, the total height of the semiconductor package 100A may be 3.082 mm. The vertical height of each of the logic chips 31 and 32 may be approximately 0.65 mm to 0.72 mm. In some example embodiments, the vertical height of each of the logic chips 31 and 32 may be approximately 0.685 mm. Therefore, the total vertical height of the interposer bump 62, the interposer 20, the chip bump 63, and one of the logic chips 31 and 32 may be about 0.8 mm to 1.0 mm. In some example embodiments, the total vertical height of the interposer bump 62, the interposer 20, the chip bump 63, and one of the logic chips 31 and 32 may be about 0.9 mm.

[0040] The semiconductor package 100A, 100Aa or 100Ab may include: a substrate bump pad 11 disposed at the lower portion of the substrate 10, and an interposer bump pad 12 disposed at the upper portion of the substrate 10. The substrate bump pad 11 and the interposer bump pad 12 may be electrically connected through a substrate wiring 15 and a substrate via 16. The substrate bump pads 11 may contact the substrate bumps 61, respectively, and thus may be electrically connected to an external circuit board. The interposer bump pads 12 may contact the corresponding interposer bumps 62, and thus may be electrically connected to the interposer 20.

[0041] The interposer 20 may include an interposer wiring 25 and an interposer path 26 inside. The interposer wiring 25 and the interposer path 26 may contain a conductor such as a metal. The interposer wiring 25 and the interposer path 26 may electrically connect the interposer bump 62 to the chip bump 63. The chip bump 63 may electrically connect the interposer 20 to the logic chips 31 and 32, while electrically connecting the interposer 20 to the memory stacks 41a to 41d and 42a to 42d. For example, the upper logic chip 31 and the lower logic chip 32 may be electrically connected by the chip bump 63, the interposer wiring 25 and the interposer path 26 to perform dual processing. The first to fourth upper memory stacks 41a to 41d may be electrically connected to the upper logic chip 31 by the chip bump 63, the interposer wiring 25 and the interposer path 26. The first to fourth lower memory stacks 42a to 42d may be electrically connected to the lower logic chip 32 by the chip bump 63, the interposer wiring 25 and the interposer path 26.

[0042] The bottom fillers 71 and 72 may include an interposer bottom filler 71 and a chip bottom filler 72. The interposer bottom filler 71 may be formed between the substrate 10 and the interposer 20 to surround the interposer bump 62. The interposer bottom filler 71 may provide a bonding force between the substrate 10 and the interposer 20. The chip bottom filler 72 is formed between the interposer 20 and the logic chips 31 and 32 and between the interposer 20 and the memory stacks 41a to 41d and 42a to 42d to surround the chip bump 63. The chip bottom filler 72 may provide a bonding force between the interposer 20 and the logic chips 31 and 32 and between the interposer 20 and the memory stacks 41a to 41d and 42a to 42d. The bottom fillers 71 and 72 may contain a thermosetting resin.

[0043] The molding compound 80 may surround the upper surface of the substrate 10, the side surface and the upper surface of the interposer 20, the side surfaces of the logic chips 31 and 32, and the side surfaces of the memory stacks 41a to 41d and 42a to 42d. The molding compound 80 may be filled between the logic chips 31 and 32 and the memory stacks 41a to 41d and 42a to 42d. The upper surfaces of the logic chips 31 and 32 and the upper surfaces of the memory stacks 41a to 41d and 42a to 42d may be exposed without being covered by the molding compound 80. In some example embodiments, the upper surfaces of the logic chips 31 and 32 and the upper surfaces of the memory stacks 41a to 41d and 42a to 42d may be covered by the molding compound 80. The molding compound 80 may include an epoxy molding compound (EMC).

[0044] Reference Figure 1C, the interposer 20 and the reinforcing chip 51a may be connected and fixed by an adhesive structure (e.g., chip bumps 63). The chip bumps 63 between the interposer 20 and the reinforcing chip 51a may also be surrounded by a chip bottom filler 72. For example, when the reinforcing chip 51a includes an under bumped metal (UBM), a metal pad, etc., the reinforcing chip 51a, the chip bumps 63, and the interposer 20 may have a physical bonding force. As described above, the chip bottom filler 72 may enhance the bonding force between the interposer 20 and the reinforcing chip 51a.

[0045] refer to Figure 1D , the interposer 20 and the reinforcing chip 51a may be connected and fixed by an adhesive structure (e.g., an adhesive layer 75). The adhesive layer 75 may include a curable resin having adhesive properties, for example, a die attach film (DAF) or a non-conductive film (NCF). When the reinforcing chip 51a does not include a UBM or a metal pad, the interposer 20 and the reinforcing chip 51a may be physically bonded and fixed by the adhesive layer 75. In some example embodiments, when the reinforcing chip 51a includes a dummy chip, no electrical connection may be formed between the interposer 20 and the reinforcing chip 51a.

[0046] Figure 1E is an enlarged side view of memory stacks 41a to 41d and 42a to 42d. Figure 1E , memory stacks 41x and 42x may each include a plurality of stacked memory chips 40a to 40d, a through-path 65, and an adhesive film 73. The memory chips 40a to 40d in each of the memory stacks 41a to 41d and 42a to 42d may include non-volatile memory chips such as dynamic random access memory (DRAM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), phase variable random access memory (PRAM) and / or flash memory, or various other memory chips. In some example embodiments, the bottommost memory chip (i.e., memory chip 40a) may include a substrate die. The substrate die may include test logic circuits such as design for test (DFT), joint test action group (JTAG) or memory built-in self-test (MBIST), signal interface circuits (e.g., PHY), etc.

[0047] When the lowermost memory chip 40a is a base die, the number of stacked memory chips may be 4 or more. Figure 1E, only four memory chips 40x are shown, but the concept of the present invention is not limited thereto. Through passage 65 can be connected to corresponding chip bump 63, while vertically extending through memory chip 40a to 40d. Through passage 65 can be vertically aligned with corresponding chip bump 63. Each adhesive film 73 can be between adjacent memory chips in stacked memory chips 40a to 40d. Each adhesive film 73 can include die attach film (DAF). In some example embodiments, each adhesive film 73 can include bottom filling material.

[0048] Figure 2A is a projection top view schematically illustrating a semiconductor package 100B according to some example embodiments of the present disclosure. Figure 2B It is along Figure 2A The line III-III' in Figure 2A A cross-sectional view or projected side view of a semiconductor package 100B is shown. Figure 2C and Figure 2D It is along Figure 2A The line IV-IV' in Figure 2A A cross-sectional view or projected side view of a semiconductor package 100B is shown.

[0049] refer to FIG. 2A to FIG. 2D , a semiconductor package 100B according to some example embodiments of the present disclosure may include an interposer 20, logic chips 31 and 32, memory stacks 41a to 41d and 42a to 42d, and a stiffening dam 55 disposed on a substrate 10. Figures 1A to 1E The substrate 10, the interposer 20, the logic chips 31 and 32, and the memory stacks 41a to 41d and 42a to 42d are described, and therefore, no additional description thereof will be given. The reinforcing dam 55 may be provided on the substrate 10 in the form of a frame and surround the interposer 20, but the reinforcing dam 55 may be in other forms, for example, having a circular cross section. The reinforcing dam 55 may include a portion of a silicon wafer, a portion of a printed circuit board, a metal or ceramic rod, an epoxy compound, a cured polymer resin, an inorganic material such as glass, or other hard materials.

[0050] The upper end of the reinforcing dam 55 may be lower than the upper ends of the logic chips 31 and 32 and the upper ends of the memory stacks 41a to 41d and 42a to 42d, so that the mold compound 80 may uniformly fill the inside of the reinforcing dam 55 and the outside of the reinforcing dam 55. The reinforcing dam 55 may be bonded and fixed to the upper surface of the substrate 10 by an adhesive material. The vertical height of the reinforcing dam 55 may be approximately 0.64 mm to 0.75 mm. In some example embodiments, the vertical height of the reinforcing dam 55 including the adhesive material may be approximately 0.71 mm. The vertical height (thickness) of the adhesive material may be approximately 0.08 mm to 0.12 mm. In some example embodiments, the vertical height (thickness) of the adhesive material may be approximately 0.1 mm. Reference Figure 2C , the reinforcing chip 51a can be connected and fixed to the interposer 20 through the chip bumps 63 and the chip underfill 72. Figure 2D , the reinforcement chip 51 a may be bonded and fixed to the interposer 20 via the adhesive layer 75 .

[0051] Figures 2E to 2H 1 is a projection top view schematically showing semiconductor packages 100Bc to 100Bf according to respective example embodiments of the present disclosure. A description of repeated constituent elements will not be given.

[0052] refer to Figure 2E , the semiconductor package 100Bc according to some example embodiments of the present disclosure may include reinforcement dams 56 surrounding the upper side, lower side, and opposite lateral sides of the logic chips 31 and 32 and the memory stacks 41a to 41d and 42a to 42d. Each reinforcement dam 56 may have a bar shape, but other shapes, such as a crescent shape, may also be used. For example, the reinforcement dam 56 may not be provided at the corners of the interposer 20.

[0053] refer to Figure 2F , the semiconductor package 100Bd according to some example embodiments of the present disclosure may include the opposite lateral sides surrounding the logic chips 31 and 32 and the memory stacks 41a to 41d and 42a to 42d while having the reinforcing dam 56 in a strip shape. For example, the reinforcing dam 56 provided at the bottom of the semiconductor package 100Bd may be omitted. Figure 2E The reinforcing dams 56 on the upper and lower sides of the structure are provided.

[0054] refer to Figure 2G, the semiconductor package 100 according to some example embodiments of the present disclosure may include a plurality of reinforcing dams 57, each of which has a segment form. The segment-type reinforcing dam 57 may be arranged so that a portion of the reinforcing dam 57 is aligned with and overlaps with an extension line of a boundary region (boundary line) between the logic chips 31 and 32 in a row direction, and the remaining portion of the reinforcing dam 57 is aligned with and overlaps with an extension line of a boundary region (boundary line) between the logic chips 31 and 32 and the memory stacks 41a to 41d and 42a to 42d in a column direction, respectively.

[0055] refer to Figure 2H , the semiconductor package 100Bf according to some example embodiments of the present disclosure may include a segment-type reinforcement dam 57 that is aligned with and overlaps an extension line of a boundary region (boundary line) between the logic chips 31 and 32 in a row direction. Figure 2G Compared with the case of FIG. 5 , the reinforcing dam 57 that is aligned with and overlaps with the extension lines of the boundary areas (boundary lines) between the logic chips 31 and 32 and the memory stacks 41 a to 41 d and 42 a to 42 d in the column direction, respectively, can be omitted.

[0056] Figure 3A and Figure 3B 1 and 2 are cross-sectional views schematically illustrating semiconductor packages 100Ca and 100Cb according to example embodiments of the present disclosure, respectively.

[0057] refer to Figure 1A , Figure 3A and Figure 3B , semiconductor packages 100Ca and 100Cb according to some example embodiments of the present disclosure may each include an interposer 20, logic chips 31 and 32, memory stacks 41a to 41d and 42a to 42d, reinforcement chips 51a and 51b, a mold compound 80, and a reinforcement cover 95 disposed on a substrate 10. The reinforcement cover 95 may cover the interposer 20, the logic chips 31 and 32, the memory stacks 41a to 41d and 42a to 42d, the reinforcement chips 51a and 51b, and the mold compound 80. The reinforcement cover 95 may completely cover the upper surfaces of the logic chips 31 and 32, the upper surfaces of the memory stacks 41a to 41d and 42a to 42d, the upper surfaces of the reinforcement chips 51a and 51b, and the upper surface of the mold compound 80, as well as the side surfaces of the mold compound 80. Reference Figure 3A , the reinforcing chip 51a can be connected and fixed to the interposer 20 through the chip bumps 63 and the chip underfill 72. Figure 3B , the reinforcement chip 51 a may be bonded and fixed to the interposer 20 via the adhesive layer 75 .

[0058] Figure 4Ais a projection top view or a projection layout view of a semiconductor package 100D according to some example embodiments of the present disclosure. Figure 4B and Figure 4C is along Figure 4A The line V-V' in Figure 4A A cross-sectional view or projected side view of a semiconductor package 100D is shown.

[0059] refer to FIG. 4A to FIG. 4C , the semiconductor package 100D, 100Da or 100Db according to some example embodiments of the present disclosure may include an interposer 20, logic chips 31 and 32, memory stacks 41a to 41d and 42a to 42d, and reinforcement structures 51a, 55 and 91 disposed on a substrate 10. The reinforcement structures 51a, 55 and 91 may include a reinforcement chip 51a, a reinforcement dam 55 and a reinforcement plate 91. The reinforcement plate 91 may be disposed on the logic chips 31 and 32. The reinforcement plate 91 may have a strip or segment extending to align or overlap with the boundary area (boundary line) between the logic chips 31 and 32 in the vertical direction. The reinforcement plate 91 may include a material (e.g., metal) that is hard and exhibits excellent thermal conductivity. Therefore, the reinforcement plate 91 may additionally perform a heat dissipation function. In some example embodiments, the upper surface of the reinforcement plate 91 may have a heat dissipation structure (e.g., a groove and a protrusion).

[0060] refer to Figure 4B , the reinforcing chip 51a may be connected and fixed to the interposer 20 by an adhesive structure such as a chip bump 63. Figure 4C , the reinforcing chip 51a may be bonded and fixed to the interposer 20 by an adhesive structure such as the adhesive layer 75. Constituent elements not described may be understood by referring to other drawings.

[0061] Figure 5A and Figure 5B 1 and 2 are cross-sectional views schematically illustrating semiconductor packages 100Ea and 100Eb according to example embodiments of the present disclosure, respectively. Figure 5A and Figure 5B , the semiconductor packages 100Ea and 100Eb according to some example embodiments of the present disclosure may each include an interposer 20, logic chips 31 and 32, memory stacks 41a to 41d and 42a to 42d, a reinforcing chip 51a, a reinforcing dam 55, a mold compound 80, and a reinforcing cap 95 disposed on a substrate 10. The reinforcing cap 95 may cover the interposer 20, the logic chips 31 and 32, the memory stacks 41a to 41d and 42a to 42d, the reinforcing chip 51a, and the mold compound 80. The reinforcing cap 95 may completely cover the upper and side surfaces of the logic chips 31 and 32, the memory stacks 41a to 41d and 42a to 42d, the reinforcing dam 55, and the mold compound 80. Reference Figure 5A , the reinforcing chip 51a can be connected and fixed to the interposer 20 through the chip bumps 63. Figure 5B , the reinforcing chip 51a may be bonded and fixed to the interposer 20 by the adhesive layer 75. In some example embodiments, the reinforcing dam 55 may be omitted.

[0062] 6A to 6F 1 and 2 are projected top views of semiconductor packages 100Fa to 100Ff according to example embodiments of the present disclosure, respectively.

[0063] refer to Fig. 6A , a semiconductor package 100Fa according to an example embodiment of the present disclosure may include an interposer 20, a plurality of logic chips 31 to 33, memory stacks 41a to 41d, 42a to 42d, and 43a to 43d, and reinforcement chips 51a, 51b, 52a, and 52b disposed on a substrate 10. The logic chips 31 to 33 may be disposed side by side and aligned along a column direction. The memory stacks 41a to 41d, 42a to 42d, and 43a to 43d may be disposed along a row direction so that each group of memory stacks 41a to 41d, 42a to 42d, and 43a to 43d is disposed adjacent to two side surfaces of a corresponding logic chip among the logic chips 31 to 33. For example, the memory stacks 41a to 41d, 42a to 42d and 43a to 43d may include: a first upper memory stack 41a and a second upper memory stack 41b arranged adjacent to the first side surface of the upper logic chip 31, a third upper memory stack 41c and a fourth upper memory stack 41d arranged adjacent to the second side surface of the upper logic chip 31, a first intermediate memory stack 42a and a second intermediate memory stack 42b arranged adjacent to the first side surface of the intermediate logic chip 32, a third intermediate memory stack 42c and a fourth intermediate memory stack 42d arranged adjacent to the second side surface of the intermediate logic chip 32, a first lower memory stack 43a and a second lower memory stack 43b arranged adjacent to the first side surface of the lower logic chip 33, and a third lower memory stack 43c and a fourth lower memory stack 43d arranged adjacent to the second side surface of the lower logic chip 33.

[0064] The first upper reinforcement chip 51a can be arranged between the second upper memory stack 41b and the first intermediate memory stack 42a. The second upper reinforcement chip 51b can be arranged between the fourth upper memory stack 41d and the third intermediate memory stack 42c. The first lower reinforcement chip 52a can be arranged between the second intermediate memory stack 42b and the first lower memory stack 43a. The second lower reinforcement chip 52b can be arranged between the fourth intermediate memory stack 42d and the third lower memory stack 43c. The first upper memory stack 41a and the second upper memory stack 41b, the first upper reinforcement chip 51a, the first intermediate memory stack 42a and the second intermediate memory stack 42b, the first lower reinforcement chip 52a, and the first lower memory stack 43a and the second lower memory stack 43b can be aligned in the column direction. The third upper memory stack 41c and the fourth upper memory stack 41d, the second upper reinforcement chip 51b, the third intermediate memory stack 42c and the fourth intermediate memory stack 42d, the second lower reinforcement chip 52b, and the third lower memory stack 43c and the fourth lower memory stack 43d can be aligned in the column direction. Reference Figure 6B The semiconductor package 100Fb according to some example embodiments of the present disclosure may further include a reinforcement dam 55 .

[0065] refer to Figure 6C, the semiconductor package 100Fc according to some example embodiments of the present disclosure may include an interposer 20, a plurality of logic chips 31 to 34, memory stacks 41a to 41d, 42a to 42d, 43a to 43d, and 44a to 44d, and reinforcement chips 51a, 51b, 52a, 52b, 53a, and 53b disposed on a substrate 10. The logic chips 31 to 34 may be disposed side by side and aligned in a column direction. Each group of memory stacks 41a to 41d, 42a to 42d, 43a to 43d, and 44a to 44d may be disposed at opposite side surfaces of corresponding logic chips in the logic chips 31 to 34 in a separated state. For example, the memory stacks 41a to 41d, 42a to 42d, 43a to 43d, and 44a to 44d may include a first upper memory stack 41a and a second upper memory stack 41b disposed adjacent to a first side surface of the upper logic chip 31, a third upper memory stack 41c and a fourth upper memory stack 41d disposed adjacent to a second side surface of the upper logic chip 31, a first middle upper memory stack 42a and a second middle upper memory stack 42b disposed adjacent to a first side surface of the middle upper logic chip 32, and a third middle upper memory stack 41c and a fourth upper memory stack 41d disposed adjacent to a second side surface of the middle upper logic chip 32. The memory stack 42c and the fourth upper intermediate memory stack 42d, the first lower intermediate memory stack 43a and the second lower intermediate memory stack 43b arranged adjacent to the first side surface of the middle lower logic chip 33, the third lower intermediate memory stack 43c and the fourth lower intermediate memory stack 43d arranged adjacent to the second side surface of the middle lower logic chip 33, the first lower memory stack 44a and the second lower memory stack 44b arranged adjacent to the first side surface of the lower logic chip 34, and the third lower memory stack 44c and the fourth lower memory stack 44d arranged adjacent to the second side surface of the lower logic chip 34.

[0066] The first upper reinforcement chip 51a may be arranged between the second upper memory stack 41b and the first middle upper memory stack 42a. The second upper reinforcement chip 51b may be arranged between the fourth upper memory stack 41d and the third middle upper memory stack 42c. The first middle reinforcement chip 52a may be arranged between the second middle upper memory stack 42b and the first middle lower memory stack 43a. The second middle reinforcement chip 52b may be arranged between the fourth middle upper memory stack 42d and the third middle lower memory stack 43c. The first lower reinforcement chip 53a may be arranged between the second middle lower memory stack 43b and the first lower memory stack 44a. The second lower reinforcement chip 53b may be arranged between the fourth middle lower memory stack 43d and the third lower memory stack 44c. The first upper memory stack 41a and the second upper memory stack 41b, the first upper reinforcement chip 51a, the first middle upper memory stack 42a and the second middle upper memory stack 42b, the first middle reinforcement chip 52a, the first middle lower memory stack 43a and the second middle lower memory stack 43b, the first lower reinforcement chip 53a, and the first lower memory stack 44a and the second lower memory stack 44b can be aligned in the column direction. The third upper memory stack 41c and the fourth upper memory stack 41d, the second upper reinforcement chip 51b, the third middle upper memory stack 42c and the fourth middle upper memory stack 42d, the second middle reinforcement chip 52b, the third middle lower memory stack 43c and the fourth middle lower memory stack 43d, the second lower reinforcement chip 53b, and the third lower memory stack 44a and the fourth lower memory stack 44b can be aligned in the column direction. Reference Fig.6D The semiconductor package 100Fd according to some example embodiments of the present disclosure may further include a reinforcement dam 55 .

[0067] refer to Fig. 6E , a semiconductor package 100Fe according to some example embodiments of the present disclosure may include an interposer 20, a plurality of logic chips 31 to 34, memory stacks 41 to 44, and a reinforcement chip 51 disposed on a substrate 10. For example, the logic chips 31 to 34 may be arranged in the form of a grid or a window. The memory stacks 41 to 44 may be disposed around the logic chips 31 to 34. For example, the memory stacks 41 to 44 may be disposed around the logic chips 31 to 34, thereby allocating four memory stacks to each logic chip. The reinforcement chip 51 may be disposed to be aligned with and overlap with extension lines (boundary lines) of boundary areas of the logic chips 31 to 34, respectively. For example, each reinforcement chip 51 may be disposed between corresponding memory stacks in the memory stacks 41 to 44, while being aligned with another reinforcement chip 51 in one of the row direction and the column direction. Reference Fig. 6F The semiconductor package 100Ff according to some example embodiments of the present disclosure may further include a reinforcement dam 55 .

[0068] The semiconductor package according to example embodiments of the present disclosure may include a reinforcement structure and thus may have excellent resistance to physical stress such as warpage.

[0069] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present disclosure and without changing its basic features. Therefore, the above embodiments should be considered only as illustrative and not for limiting purposes.

Claims

1. A semiconductor package, comprising: substrate; an inner plug-in unit located on the substrate; a first logic chip and a second logic chip located on the interposer, the first logic chip and the second logic chip being arranged side by side and adjacent to each other; memory stacks on the interposer, each of the memory stacks comprising a plurality of stacked memory chips and adjacent to a corresponding logic chip of the first logic chip and the second logic chip; as well as A reinforcement chip located on the interposer, the reinforcement chip being located between corresponding memory stacks in the memory stack and adjacent to a boundary area between the first logic chip and the second logic chip and aligned with an extension line of the boundary area, each of the reinforcement chips having a width greater than a width of the boundary area.

2. The semiconductor package according to claim 1, wherein: Each of the reinforcement chips overlaps a portion of the first logic chip and a portion of the second logic chip in a row direction.

3. The semiconductor package according to claim 1, wherein: When viewed in a top view, the length of the short side of the reinforcement chip corresponds to 1 / 2 or less of the length of the long side of the memory stack.

4. The semiconductor package according to claim 1, wherein: When viewed in a top view, a length of a long side of the reinforcement chip is shorter than a length of a short side of the memory stack.

5. The semiconductor package according to claim 1, wherein: A minimum distance between the first logic chip and the second logic chip is less than a minimum distance between the first logic chip and the second logic chip and the memory stack.

6. The semiconductor package according to claim 1, wherein: A minimum distance between the first logic chip and the second logic chip and the reinforcement chip is greater than a minimum distance between the first logic chip and the second logic chip and the memory stack.

7. The semiconductor package according to claim 1, wherein: A minimum distance between the reinforcement chip and the memory stack is smaller than a minimum distance between the memory stacks.

8. The semiconductor package according to claim 1, further comprising: a chip bump, the chip bump being located between the interposer and the reinforcing chip and physically connecting and fixing the interposer and the reinforcing chip; as well as A chip underfill surrounds the chip bumps.

9. The semiconductor package according to claim 1, further comprising: An adhesive layer is located between the interposer and the reinforcing chip and physically bonds and fixes the interposer and the reinforcing chip.

10. The semiconductor package according to claim 1, further comprising: chip bumps, the chip bumps being located between the interposer and the first and second logic chips and between the interposer and the memory stack; A chip bottom filler, the chip bottom filler surrounds the chip bump; an interposer bump, the interposer bump being located between the substrate and the interposer; an interposer bottom filler, the interposer bottom filler surrounding the interposer bump; as well as a substrate bump, the substrate bump being located on the lower surface of the substrate, Wherein, the chip bump is smaller than the interposer bump, and Wherein, the substrate bump is larger than the interposer bump.

11. The semiconductor package according to claim 1, wherein: Each of the memory stacks includes a through via extending vertically through the plurality of stacked memory chips; and The through via is electrically connected to the interposer through a chip bump between the interposer and the memory stack.

12. The semiconductor package according to claim 11, wherein The interposer includes an interposer wiring and an interposer via; and The first logic chip and the second logic chip are electrically connected through the interposer wiring and the interposer via.

13. The semiconductor package according to claim 1, wherein: The memory stack comprises: two first memory stacks located at a first side surface of the first logic chip, two second memory stacks located at a second side surface of the first logic chip, two third memory stacks located at a first side surface of the second logic chip, and two fourth memory stacks located at a second side surface of the second logic chip; and and The enhanced chip comprises: a first reinforcement chip located between the adjacent first memory stack and the third memory stack, and A second reinforcement chip is located between the adjacent second memory stack and the fourth memory stack.

14. The semiconductor package according to claim 1, further comprising: A reinforcing dam is located on the substrate and surrounds the interposer.

15. The semiconductor package according to claim 14, wherein: The reinforcing dam has a frame shape surrounding the first logic chip, the second logic chip, the memory stack, and the reinforcing chip; and An upper end of the reinforcement dam is lower than an upper end of the first logic chip, an upper end of the second logic chip, and an upper end of the memory stack.

16. The semiconductor package according to claim 1, further comprising: a reinforcing plate, the reinforcing plate being located on the first logic chip and the second logic chip, The reinforcing plate overlaps with a boundary area between the first logic chip and the second logic chip, and Wherein, the reinforcing plate is a horizontally extending section.

17. The semiconductor package according to claim 1, further comprising: A molding compound covers the interposer, the first and second logic chips, the memory stack, and the stiffener chip.

18. The semiconductor package according to claim 17, further comprising: A cover covers the upper and side surfaces of the molding compound.

19. A semiconductor package, comprising: substrate; an inner plug-in unit located on the substrate; a first logic chip and a second logic chip located adjacent to each other on the interposer, the first logic chip and the second logic chip being electrically connected via wiring inside the interposer; a first memory stack and a second memory stack, the first memory stack being located at opposite side surfaces of the first logic chip, and the second memory stack being located at opposite side surfaces of the second logic chip; as well as a reinforcement chip located between the first memory stack and the second memory stack, wherein the minimum distance between the first logic chip and the second logic chip is smaller than the minimum distance between the first memory stack and the second memory stack, The reinforcing chip is adjacent to a boundary region between the first logic chip and the second logic chip and is aligned with an extension line of the boundary region, and Wherein, the width of the reinforcing chip is greater than the width of the boundary area.

20. A semiconductor package, comprising: substrate; an inner plug-in unit located on the substrate; a plurality of logic chips located on the interposer, the logic chips being adjacent to each other and within 100 mm of each other and being electrically connected through the interposer; a plurality of memory stacks on the interposer, each of the memory stacks comprising a plurality of stacked memory chips and a through via extending vertically through the memory chips; a plurality of reinforcing chips located on the interposer, wherein the long sides of the reinforcing chips are parallel to the short sides of the memory stack, the length of the short sides of the reinforcing chips corresponds to 1 / 2 or less of the length of the long sides of the memory stack, and the reinforcing chips are adjacent to a boundary region between corresponding logic chips in the logic chips and aligned with an extension line of the boundary region, and the width of each of the reinforcing chips is greater than the width of the boundary region, so that the reinforcing chips horizontally overlap a portion of the corresponding logic chip; as well as A molding compound surrounds a side surface of the interposer, a side surface of the logic chip, a side surface of the memory stack, and a side surface of the reinforcement chip.

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