Semiconductor device

Abstract

A semiconductor device includes a pair of first and second dummy active regions extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, a pair of first and second circuit active regions extending in the first horizontal direction and spaced apart in the second horizontal direction, and a plurality of line patterns extending in the second horizontal direction and spaced apart in the first horizontal direction. The pair of first and second dummy active regions can be between a pair of line patterns adjacent to each other among the plurality of line patterns. At least one of the first and second dummy active regions can have a width change portion in which a width of the at least one of the first and second dummy active regions changes in the second horizontal direction between the pair of line patterns adjacent to each other.

Description

Technical Field

[0001] The example implementation relates to a semiconductor device. Background Technology

[0002] As the demand for high performance, high speed, and / or multifunctionality in semiconductor devices increases, the integration density of semiconductor devices is also increasing. The dummy regions within a semiconductor device where no integrated circuits are located may limit this increase in integration density. Summary of the Invention

[0003] An embodiment relates to a semiconductor device comprising: a pair of first and second dummy active regions extending in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; a pair of first and second circuit active regions extending in the first horizontal direction and spaced apart from each other in the second horizontal direction; and a plurality of line patterns extending in the second horizontal direction and spaced apart from each other in the first horizontal direction. The pair of first and second dummy active regions may be disposed between adjacent pairs of line patterns in the plurality of line patterns. At least one of the first and second dummy active regions may have a width-changing portion, wherein the width of the at least one of the first and second dummy active regions changes in the second horizontal direction between adjacent pairs of line patterns.

[0004] The embodiment also relates to a semiconductor device, comprising: a semiconductor substrate; a first active line extending in a first horizontal direction on the semiconductor substrate and intersecting a first circuit region, a dummy region, and a second circuit region; a second active line extending in the first horizontal direction on the semiconductor substrate and intersecting the first circuit region, the dummy region, and the second circuit region; and a line pattern extending in a second horizontal direction perpendicular to the first horizontal direction on the semiconductor substrate. The first active line may be disposed in an N-well region of the semiconductor substrate. The second active line may be spaced apart from the N-well region of the semiconductor substrate. The dummy region may be disposed between the first circuit region and the second circuit region. The first active line may include a first circuit active portion in the first circuit region, a first dummy active portion in the dummy region, and a second circuit active portion in the second circuit region. The second active line may include a third circuit active portion in the first circuit region, a second dummy active portion in the dummy region, and a fourth circuit active portion in the second circuit region. At least a portion of the first dummy active portion may have a width different from the width of at least a portion of the second dummy active portion.

[0005] The embodiment also relates to a semiconductor device comprising: a semiconductor substrate; an active line extending in a first horizontal direction on the semiconductor substrate and intersecting a circuit region and a dummy region; a line pattern extending in a second horizontal direction perpendicular to the first horizontal direction on the semiconductor substrate; a circuit source / drain region and a dummy source / drain region above the active line; and a plurality of semiconductor layers disposed on the active line in the circuit region. Each line pattern may include a gate line intersecting the plurality of semiconductor layers and covering an upper surface, a side surface, and a lower surface of each of the plurality of semiconductor layers. The line pattern may include a pair of dummy lines disposed on both sides of the dummy source / drain region and adjacent to each other. The active line below the dummy source / drain region may include a first width portion having a first width, a second width portion having a second width different from the first width, and a first width change portion between the first width portion and the second width portion. The first width portion may be disposed between the pair of dummy lines. Attached Figure Description

[0006] Features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings.

[0007] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device;

[0008] Figure 2 This is a flowchart illustrating a variation of a method for manufacturing a semiconductor device;

[0009] Figure 3A and Figure 3B This is a plan view illustrating a semiconductor device according to an example embodiment;

[0010] Figures 4A to 4C This is a plan view showing standard cells included in a semiconductor device according to an example embodiment;

[0011] Figures 5A to 5J This is a plan view showing the filler cells included in a semiconductor device according to an example embodiment;

[0012] Figure 6 and Figure 7 This is a plan view illustrating a method for laying out a semiconductor device according to an exemplary embodiment;

[0013] Figures 8A to 8C It shows the use Figure 7 A plan view of a semiconductor device manufactured using the layout shown;

[0014] Figure 9 It is shown Figure 8C An enlarged view of a portion of the semiconductor device shown;

[0015] Figures 10A to 10C This is a cross-sectional view showing a semiconductor device according to an example embodiment;

[0016] Figure 11 This is a plan view illustrating a semiconductor device according to an example embodiment;

[0017] Figure 12 It is shown Figure 11 An enlarged view of a portion of the semiconductor device shown;

[0018] Figure 13 This is a cross-sectional view showing a semiconductor device according to an example embodiment;

[0019] Figures 14A to 14C This is a plan view illustrating a variant example of the filler units included in a semiconductor device according to an exemplary embodiment;

[0020] Figures 15A to 15C This is a plan view illustrating another variation of the filler units included in a semiconductor device according to an exemplary embodiment;

[0021] Figure 16A This is a plan view illustrating a variant of a semiconductor device according to an exemplary embodiment;

[0022] Figure 16B It is shown Figure 16A An enlarged view of a portion of the semiconductor device shown;

[0023] Figure 17 This is a cross-sectional view showing a semiconductor device according to an example embodiment;

[0024] Figure 18 This is a cross-sectional view showing a variant example of a semiconductor device according to an exemplary embodiment; and

[0025] Figure 19 This is a cross-sectional view showing another variation of a semiconductor device according to an example embodiment. Detailed Implementation

[0026] Figure 1 This is a flowchart illustrating a method for manufacturing semiconductor devices.

[0027] Reference Figure 1A circuit can be designed (S10). The circuit design can include designing an integrated circuit for a semiconductor device. A layout can be formed (S20a). The layout can be formed using an integrated circuit formed according to the designed circuit. Forming the layout (S20a) can include forming a plurality of standard cells (S25), forming reference fill cells (S30), analyzing the pattern (S35), selecting unsuitable fill cells from the reference fill cells (each unsuitable fill cell has a pattern that is not continuous with the pattern of the adjacent standard cell) (S40), and replacing the unsuitable fill cells with new fill cells that have a pattern that is continuous with the pattern of the adjacent standard cell (S45). A photomask can be formed (S60). The above layout can be used to form a photomask. A semiconductor device can be formed (S80). A semiconductor device can be formed using a photomask.

[0028] Reference Figure 2 A variation of the layout is described. Figure 2 This is a flowchart illustrating a variation of a method for manufacturing a semiconductor device.

[0029] Reference Figure 2 Forming the layout (S20b) may include forming a plurality of standard units (S25), analyzing patterns (S36), and forming filler units (S50). Analyzing patterns (S36) may include extracting information about the width of each pattern of the plurality of standard units. Forming filler units (S50) may include forming filler units in regions adjacent to the plurality of standard units, the filler units comprising patterns that are continuous with the patterns of the plurality of standard units.

[0030] In the following description, reference will be made to Figures 3A to 7 Examples describing the formation of a layout ( Figure 1 S20a and Figure 2 (S20b in the text).

[0031] Reference Figure 3A and Figure 3B Describe the planar shape of the semiconductor device in the example implementation.

[0032] Figure 3A This is a plan view showing the circuit region and dummy region of a semiconductor device according to an example embodiment. Figure 3B It is shown Figure 3A The example plan shown also includes power supply wires M1 (VDD, VSS) and line pattern GL.

[0033] Reference Figure 3A and Figure 3BThe semiconductor device according to this example embodiment may include a plurality of standard cell regions SC and a plurality of filler cell regions FC adjacent to the plurality of standard cell regions SC. The plurality of standard cell regions SC may be defined as circuit regions, and the plurality of filler cell regions FC may be defined as dummy regions.

[0034] Figure 3A and Figure 3B An example is shown in which the plurality of standard cell regions SC include first to eighth standard cell regions SC1, SC2, SC3, SC4, SC5, SC6, SC7 and SC8, but the plurality of standard cell regions SC may include standard cell regions arranged in various other forms and numbers. Figure 3A and Figure 3B An example is shown in which the plurality of filler unit regions FC include first to sixth filler unit regions FC1, FC2, FC3, FC4, FC5 and FC6, but the plurality of filler unit regions FC may include filler unit regions arranged in various other forms and numbers.

[0035] Reference Figure 3B The power supply lines M1 (VDD, VSS) can be configured to extend in a first horizontal direction (X). The power supply lines M1 (VDD, VSS) can be spaced apart from each other in a second horizontal direction (Y) perpendicular to the first horizontal direction (X). The power supply lines M1 (VDD, VSS) can include a first power supply line VDD and a second power supply line VSS. The line pattern GL can be configured to extend in the second horizontal direction (Y). The line pattern GL can include gate lines and dummy lines.

[0036] In the following description, reference will be made to Figures 4A to 4C Examples of standard units described according to exemplary implementation methods.

[0037] Figures 4A to 4C This is a plan view illustrating standard cells included in a semiconductor device according to an example embodiment.

[0038] Reference Figures 4A to 4C The semiconductor device according to this example embodiment may include filling multiple standard cell regions ( Figure 3A and Figure 3B The standard cell (SC) is a standard cell within the standard cell region of an integrated circuit, configured as a unit of the layout included in the integrated circuit. Standard cells can include various types of standard cells, such as inverter standard cells, NAND standard cells, NOR standard cells, etc. For example, Figures 4A to 4C The first to third standard units C1, C2 and C3 shown can be implemented as inverter standard units among the standard units.

[0039] Figures 4A to 4C The first to third standard units C1, C2 and C3 shown may include a pair of active lines ACT extending in the first horizontal direction (X), an N-well region NWELL, multiple line patterns GL extending in the second horizontal direction (Y) perpendicular to the first horizontal direction (X), multiple contact plugs CNT, multiple lower conductors M1 extending in the first horizontal direction (X), multiple lower passages V0, multiple upper passages V1 and an upper conductor M2 extending in the second horizontal direction (Y).

[0040] The plurality of line patterns GL may include dummy lines GL_D spaced apart from each other and gate lines GL_G disposed between the dummy lines GL_D. The gate lines GL_G may cross a pair of active lines ACT.

[0041] The plurality of lower conductors M1 may include a pair of first and second power conductors VDD and VSS, and a plurality of wiring conductors M1_R. The wiring conductors M1_R may have a width smaller than the width of the first power conductor VDD or the second power conductor VSS.

[0042] A pair of active lines ACT may include a first active line (in) Figure 4A In Chinese, it is represented as "ACT_1a". Figure 4B This is represented as "ACT_1b" in Chinese. Figure 4C (represented as "ACT_1c") and the second active line (in) Figure 4A In Chinese, it is represented as "ACT_2a". Figure 4B In Chinese, it is represented as "ACT_2b". Figure 4C (represented as "ACT_2c" in Chinese).

[0043] First active line ( Figure 4A "ACT_1a" in Figure 4B "ACT_1b" and Figure 4C The “ACT_1c” in the N-well region (NWELL) can be set in the N-well region (NWELL). The first active line set in the N-well region (NWELL) Figure 4A "ACT_1a" in Figure 4B "ACT_1b" and Figure 4C The “ACT_1c” in the text can have N-type conductivity and is not located in the N-well region NWELL as a second active line. Figure 4A "ACT_2a" in Figure 4B "ACT_2b" and Figure 4C The “ACT_2c” in the code can have P-type conductivity. Therefore, the first active line (with N-type conductivity) Figure 4A "ACT_1a" in Figure 4B "ACT_1b" and Figure 4CThe “ACT_1c” in the configuration can be configured to house the active region of a PMOS transistor and have a second active line with P-type conductivity. Figure 4A "ACT_2a" in Figure 4B "ACT_2b" and Figure 4C The “ACT_2c” in the configuration can be set as the active region of the NMOS transistor.

[0044] In the example implementation described below, the first active line disposed in the N-well region NWELL may have N-type conductivity, and the second active line (opposite to the first active line and not disposed in the N-well region NWELL) may have P-type conductivity.

[0045] The plurality of contact plugs CNT may include a first contact plug CNT_1a, a second contact plug CNT_1b, a third contact plug CNT_2a, and a fourth contact plug CNT_2b. The first contact plug CNT_1a and the second contact plug CNT_1b are disposed on both sides of the gate line GL_G and are connected to the first active line ( Figure 4A "ACT_1a" in Figure 4B "ACT_1b" and Figure 4C The third contact plug CNT_2a and the fourth contact plug CNT_2b are disposed on both sides of the gate line GL_G and are adjacent to the second active line (ACT_1c). Figure 4A "ACT_2a" in Figure 4B "ACT_2b" and Figure 4C The "ACT_2c" in the diagram overlaps. The plurality of contact plugs CNT may also include a gate contact plug CNT_G that overlaps with the gate line GL_G. The first to fourth contact plugs CNT_1a, CNT_1b, CNT_2a, and CNT_2b may be referred to as "source / drain contact plugs". The first contact plug CNT_1a may be referred to as the first source / drain contact plug.

[0046] The length of the first contact plug CNT_1a in the second horizontal direction (Y) may differ from the length of the second contact plug CNT_1b in the second horizontal direction (Y). For example, the length of the first contact plug CNT_1a in the second horizontal direction (Y) may be greater than the length of the second contact plug CNT_1b in the second horizontal direction (Y). The length of the third contact plug CNT_2a in the second horizontal direction (Y) may be greater than the length of the fourth contact plug CNT_2b in the second horizontal direction (Y).

[0047] A portion of the first contact plug CNT_1a may overlap with the first power lead VDD, and a portion of the third contact plug CNT_2a may overlap with the second power lead VSS. A lower passage V0 provided between the first contact plug CNT_1a and the first power lead VDD electrically connects the first contact plug CNT_1a to the first power lead VDD, and a lower passage V0 provided between the third contact plug CNT_2a and the second power lead VSS electrically connects the third contact plug CNT_2a to the second power lead VSS.

[0048] In an example implementation, the second and fourth contact plugs CNT_1b and CNT_2b can be electrically connected to the wiring conductor M1_R via a lower passage V0 that overlaps with the second contact plug CNT_1b and the fourth contact plug CNT_2b, respectively.

[0049] In an example implementation, the gate contact plug CNT_G can be electrically connected to the wiring wire M1_R via a lower path V0 that overlaps with the gate contact plug CNT_G.

[0050] In an example implementation, the upper conductor M2 may include portions overlapping with the second contact plug CNT_1b and the fourth contact plug CNT_2b. The upper conductor M2 may be electrically connected to the wiring conductor M1_R via an upper passage V1 on the wiring conductor M1_R that overlaps with the second contact plug CNT_1b and the fourth contact plug CNT_2b, respectively.

[0051] In the first standard unit C1 (in Figure 4A In the middle), the first active line ACT_1a (in Figure 4A (in) and the second active line ACT_2a (in Figure 4A Each of the bars in the middle can have a first width in the second horizontal direction (Y).

[0052] In the second standard unit C2 (in Figure 4B In the middle), the first active line ACT_1b (in Figure 4B (in) and the second active line ACT_2b (in Figure 4B Each line in the middle can have a second width in the second horizontal direction (Y). The second width can be greater than the first width.

[0053] In the third standard unit C3 (in Figure 4C In the middle), the first active line ACT_1c (in Figure 4C (in) and the second active line ACT_2c (in Figure 4C The middle element (C3) can have different widths in the second horizontal direction (Y). For example, in the third standard unit C3 (in... Figure 4C In the middle), the first active line ACT_1c (in Figure 4CThe second active line ACT_2c can have a second width in the second horizontal direction (Y). Figure 4C The middle part can have a first width in the second horizontal direction (Y).

[0054] In the following description, reference will be made to Figures 5A to 5G An example describing a filling unit according to an exemplary implementation.

[0055] Figures 5A to 5J This is a plan view illustrating the filler cells included in a semiconductor device according to an example embodiment.

[0056] Reference Figures 5A to 5J The semiconductor device according to this example embodiment may include filler cells configured as cells of a layout included in an integrated circuit. For example, Figures 5A to 5G The first to twenty-eighth filler units F1 to F28 shown may include a pair of first and second active lines ACT (ACT_1, ACT_2), an N-well region NWELL, a pair of first and second line patterns GL (GL_D1, GL_D2), a pair of first and second power supply lines M1 (VDD and VSS), and contact plugs CNT. The first active line ACT_1 may be disposed in the N-well region NWELL.

[0057] In each of the first to twenty-eighth filler units F1 to F28, the contact plug CNT may include a contact plug overlapping with the first active line ACT_1 and a contact plug overlapping with the second active line ACT_2. The contact plug CNT may be disposed in the middle portion between a pair of adjacent first and second line patterns GL_D1 and GL_D2.

[0058] The contact plugs (CNTs) can overlap with the first and second active lines (ACTs, ACT_1, ACT_2). The shape and size of each contact plug (CNT) can be varied relative to the example shown in the figure.

[0059] In another example implementation, the contact plug CNT may be omitted in each of the first to twenty-eighth filler units F1 to F28. Besides the first to twenty-eighth filler units F1 to F28, the different filler units described below may or may not include the contact plug CNT. Therefore, in the following description of the filler units, example implementations may include examples where the filler unit includes a contact plug and examples where the filler unit does not include a contact plug.

[0060] In each of the first to twenty-eighth filler units F1 to F28, a pair of first and second line patterns GL (GL_D1, GL_D2) can be configured as a dummy line GL_D.

[0061] In the filler cells, the active line ACT can be a pattern corresponding to the standard cells. For example, the active lines ACT of the first to third standard cells C1 to C3 (in...) Figures 4A to 4C (middle) can correspond to the active line ACT of the first to twenty-eighth filler units F1 to F28.

[0062] The first to twenty-eighth filler units F1 to F28 can have various shapes to have a pattern that is continuous with the pattern of the standard unit described above. For example, the first to twenty-eighth filler units F1 to F28 may include: first to fourth filler units F1 to F4 having active lines ACT, each active line ACT not having a width-changing portion in a single filler unit; and fifth to twenty-eighth filler units F5 to F28 having active lines ACT, each active line ACT having a width-changing portion in a single filler unit. In the first active line ACT_1 of the first to twenty-eighth filler units F1 to F28, the portion of the first active line having a first width in the second horizontal direction (Y) can be designated as a "first dummy portion" (W_A1a), and the portion of the first active line having a second width in the second horizontal direction (Y) that is less than the first width can be designated as a "second dummy portion" (W_A1b). In the second active line ACT_2 of the first to twenty-eighth filler units F1 to F28, the portion of the second active line with a first width can be designated as the "third dummy portion" (W_A2a), and the portion of the second active line with a second width can be designated as the "fourth dummy portion" (W_A2b).

[0063] Reference Figure 5A In the first to fourth filler units F1 to F4, the first and second active lines ACT_1 and ACT_2 of the first filler unit F1 can have the same width in the second horizontal direction (Y), the first and second active lines ACT_1 and ACT_2 of the second filler unit F2 can have the same width in the second horizontal direction (Y) and this width is less than the width of each of the first active lines ACT_1 and ACT_2 of the first filler unit F1, the first active line ACT_1 of the third filler unit F3 can have a width in the second horizontal direction (Y) that is less than the width of the second active line ACT_2 of the third filler unit F3, and the first active line ACT_1 of the fourth filler unit F4 can have a width in the second horizontal direction (Y) that is greater than the width of the second active line ACT_2 of the fourth filler unit F4.

[0064] Reference Figure 5B and Figure 5CIn the fifth to twelfth filler units F5 to F12, the first active line ACT_1 may include both a first dummy portion W_A1a and a second dummy portion W_A1b with different widths in the second horizontal direction (Y), and the second active line ACT_2 may include both a third dummy portion W_A2a and a fourth dummy portion W_A2b with different widths in the second horizontal direction (Y). Therefore, in the fifth to twelfth filler units F5 to F12, the first active line ACT_1 may have a first width-changing portion VA1 between the first dummy portion W_A1a and the second dummy portion W_A1b, where the first dummy portion W_A1a and the second dummy portion W_A1b have different widths in the second horizontal direction (Y), and the second active line ACT_2 may have a second width-changing portion VA2 between the third dummy portion W_A2a and the fourth dummy portion W_A2b, where the third dummy portion W_A2a and the fourth dummy portion W_A2b have different widths in the second horizontal direction (Y).

[0065] Reference Figure 5B In the fifth to eighth filler units F5 to F8, each of the first width-changing portion VA1 of the first active line ACT_1 and the second width-changing portion VA2 of the second active line ACT_2 can be set in the middle portion between a pair of first and second line patterns GL (GL_D1 and GL_D2).

[0066] Reference Figure 5C Each of the first width-changing portion VA1 of the first active line ACT_1 and the second width-changing portion VA2 of the second active line ACT_2 can be adjacent to one of the first and second line patterns GL (GL_D1 and GL_D2). For example, in the ninth fill unit F9, the first width-changing portion VA1 and the second width-changing portion VA2 can be adjacent to the second line pattern GL_D2. In the tenth fill unit F10, the first width-changing portion VA1 can be adjacent to the second line pattern GL_D2, and the second width-changing portion VA2 can be adjacent to the first line pattern GL_D1. In the eleventh fill unit F11, the first width-changing portion VA1 and the second width-changing portion VA2 can be adjacent to the first line pattern GL_D1. In the twelfth fill unit F12, the first width-changing portion VA1 can be adjacent to the first line pattern GL_D1, and the second width-changing portion VA2 can be adjacent to the second line pattern GL_D2.

[0067] Reference Figures 5D to 5GIn the thirteenth to twenty-eighth filler units F13 to F28, one of the first active line ACT_1 and the second active line ACT_2 can have a constant width in the second horizontal direction (Y), and the other can have a width-changing portion.

[0068] Reference Figure 5D and Figure 5E In the thirteenth to twentieth filler units F13, F14, F15, F16, F17, F18, F19 and F20, one of the first active line ACT_1 and the second active line ACT_2 may have a constant width in the second horizontal direction (Y), and the other may have a width-changing portion in the middle part between the first line pattern GL_D1 and the second line pattern GL_D2. For example, the width of the second active line ACT_2 in the second horizontal direction (Y) may change approximately in the middle of the first horizontal direction (X) between the first line pattern GL_D1 and the second line pattern GL_D2.

[0069] Reference Figure 5F and Figure 5G In the twenty-first to twenty-eighth filler units F21, F22, F23, F24, F25, F26, F27 and F28, one of the first active line ACT_1 and the second active line ACT_2 may have a constant width in the second horizontal direction (Y), and the other may have a width-changing portion VA1 or a width-changing portion VA2 adjacent to one of the first and second line patterns GL_D1 and GL_D2.

[0070] Return to reference Figures 5B to 5G In the fifth to twenty-eighth filler units F5 to F28, at least one of the first active line ACT_1 and the second active line ACT_2 may have different widths in the second horizontal direction (Y). The active lines with different widths in the second horizontal direction (Y) may include relatively wide dummy portions and relatively narrow dummy portions. The former (i.e., the dummy portion with a relatively large width) may be configured to protrude further than the latter (i.e., the dummy portion with a relatively small width) in the direction toward the middle portion between the first and second power conductors M1 (VDD and VSS).

[0071] In another variant (see below) Figure 5H and Figure 5I Describe it. Figure 5H and Figure 5I(A portion of a variant of filler units F5 to F28 is shown). In filler units F5 to F28, at least one of the first active line ACT_1 and the second active line ACT_2 can have different widths in the second horizontal direction (Y), and a dummy portion (having a relatively wide portion and a relatively narrow portion in the second horizontal direction (Y)) can be configured such that the relatively wide portion protrudes away from the middle portion between the first and second power conductors M1 (VDD and VSS) compared to the relatively narrow portion. The variants can be understood based on filler units F5 to F28, but for further understanding of the variants, reference will be made to... Figure 5H and Figure 5I Describe an example implementation method, Figure 5H and Figure 5I A portion of the variant examples of filler units F5 to F28 from the fifth to the twenty-eighth are shown.

[0072] Reference Figure 5H and Figure 5I Filler units F29 to F30, F31, F32, F33, F34, F35, and F36 are variations of filler units F5 to F12, respectively. For example, compared with filler unit F5 (in... Figure 5B Unlike the 29th filler unit F29, the relatively wide dummy portions W_A1a and W_A2a can be configured to protrude further in the direction away from the middle portion between the first and second power supply wires M1 (VDD, VSS) than the relatively narrow dummy portions W_A1b and W_A2b.

[0073] Reference Figures 5A to 5I The described first to thirty-sixth filler units F1 to F36 may include a pair of first and second line patterns GL (GL_D1, GL_D2) adjacent to each other. However, exemplary embodiments may include filler units formed by combining the first to thirty-sixth filler units F1 to F36. For example, exemplary embodiments may include a first combined filler unit formed by combining identical filler units from the first to thirty-sixth filler units F1 to F36, and a second combined filler unit formed by combining different filler units from the first to thirty-sixth filler units F1 to F36. (Refer to...) Figure 5J Examples describing the first and second combined filler units. Figure 5J An example of a combined filler unit is shown, and in Figure 5J Various other combinations of filler units not described herein may be included in the example implementation.

[0074] Reference Figure 5JThe thirty-seventh filler unit F37 can be formed by combining the same first filler unit F1 in the first horizontal direction (X). The thirty-eighth filler unit F38 can be formed by combining the ninth filler unit F9 and the first filler unit F1 in the first horizontal direction (X). The thirty-ninth filler unit F39 can be formed by combining the thirty-third filler unit F33 and the first filler unit F1 in the first horizontal direction (X).

[0075] In the example implementation, Figure 1 In the example embodiment shown, the formation of the reference filler unit (S30) can be configured as one of a first filler unit F1 and a second filler unit F2. For example, the first filler unit F1 can be formed as the reference filler unit.

[0076] In another example, when the width of each filler unit region FC in the first horizontal direction (X) is greater than the width of the first filler unit F1, the thirty-seventh filler unit F37 (formed by combining multiple first filler units F1 in the first horizontal direction (X)) can be formed as a reference filler unit.

[0077] The following description will describe... Figure 1 The formation layout (S20a) is described in the example implementation shown.

[0078] Figure 6 and Figure 7 This is a plan view illustrating a method for laying out a semiconductor device according to an example embodiment.

[0079] In the following description, a method for forming the layout using the first filler unit F1 as a reference filler unit will be described, although, for example, the thirty-seventh filler unit F37 may be used as a reference filler unit depending on the size of the filler unit region.

[0080] Reference Figure 6 This can form multiple standard units C1a, C2a, and C3a. The regions where standard units C1a, C2a, and C3a are set can be defined as standard unit regions SC. The first standard unit region SC1 can be the region where the first standard unit C1a is set, the second standard unit region SC2 can be the region where the second standard unit C2a is set, and the third standard unit region SC3 can be the region where the third standard unit C3a is set. Multiple standard unit regions SC can correspond to... Figure 3A The first to third standard unit regions SC1 to SC3 are described in the text.

[0081] In the example implementation, the first and second standard units C1a and C2a can be configured as inverter standard units, and the third standard unit C3a can be configured as a NAND standard unit.

[0082] Reference filler unit F1 can be formed in the region where the first to third standard units C1a, C2a, and C3a are not formed. The region forming the reference filler unit F1 can be configured as a filler unit region FC. The filler unit region FC can include a first filler unit region FC1 where a single filler unit is set, a second filler unit region FC2 where multiple filler units are set, and a third filler unit region FC3 where a single filler unit is set. The second filler unit region FC2 can include a filler unit region FC2_1 where a single filler unit is set and a filler unit region FC2_2 where a single filler unit is set.

[0083] Depending on the gap or spacing between the first to third standard cells C1a, C2a, and C3a, a single reference filler cell F1 or multiple reference filler cells F1 can be disposed between adjacent standard cells. Multiple reference filler cells F1 can be replaced with a thirty-seventh filler cell F37.

[0084] exist Figure 6 In the layout shown, wiring for the first to third standard cells C1a, C2a, and C3a can be completed. For example, the first to third standard cells C1a, C2a, and C3a can be formed up to the plurality of contact plugs CNTs, the plurality of lower conductors M1, the plurality of lower paths V0, the plurality of upper paths V1, and the upper conductor M2 described in the above example embodiment. Furthermore, the layout in which the first to third standard cells C1a, C2a, and C3a and the reference filler cell F1 are arranged can include the line pattern GL described in the foregoing example embodiment. The line pattern GL can include a gate line GL_G and a dummy line GL_D. The gate line GL_G can be included in the standard cells, and the dummy line GL_D can be included in the reference filler cell F1. Moreover, the dummy line GL_D can be disposed on both sides of each of the first to third standard cells C1a, C2a, and C3a.

[0085] Reference Figure 7 It can be executed Figure 1 The operation of the analysis pattern (S35) and the operation of selecting unsuitable filler cells (S40) in the reference filler cells (where each reference filler cell has a pattern that is continuous with the pattern of the adjacent standard cells). For example, the analysis pattern (S35) (in Figure 1(In the middle) may include obtaining information about the width of each of the active lines ACT_1 and ACT_2 of the first to third standard units C1a, C2a and C3a in the second horizontal direction (Y).

[0086] In selecting unsuitable filler elements (S40) from the reference filler elements (where each reference filler element has a pattern that is continuous with the pattern of the adjacent standard element), the width of each of the active lines ACT_1 and ACT_2 of the first to third standard elements C1a, C2a and C3a in the second horizontal direction (Y) can be the same as that of the reference filler element F1 (in Figure 6 The width of each of the active lines ACT_1 and ACT_2 in the second horizontal direction (Y) is compared with that of the reference filler element F1. When the width of each of the active lines ACT_1 and ACT_2 of the first to third standard elements C1a, C2a, and C3a is compared with that of the reference filler element F1... Figure 6 When the width of each of the active lines ACT_1 and ACT_2 in the first to third standard units C1a, C2a and C3a is the same, the filler unit can be identified as a continuous pattern, and the reference filler unit F1 can be selected as a suitable filler unit. When the width of each of the active lines ACT_1 and ACT_2 in the second horizontal direction (Y) of the first to third standard units C1a, C2a and C3a is different from that of the reference filler unit F1 (in Figure 6 When the width of each of the active lines ACT_1 and ACT_2 in the second horizontal direction (Y) is equal to the width of the reference filler unit F1 (in the middle), Figure 6 (The middle) can be selected as an unsuitable filler unit.

[0087] Replace the unsuitable filler unit with a new filler unit having a pattern that is continuous with the pattern of the adjacent standard unit (S45). Figure 1 (in) can include using Figures 5A to 5I The unsuitable filler unit is replaced by a suitable filler unit from the second to thirty-sixth filler units F2 to F36 shown. For example, in filler unit region FC1, reference filler unit F1 (in Figure 6 The middle) can be replaced by the eighth filler unit F8. In the filler unit region FC2_1, referencing filler unit F1 (in Figure 6 The middle) can be replaced by the ninth filler unit F9. In the filler unit region FC2_2, referencing filler unit F1 (in Figure 6 (in) can be selected as a suitable filler cell and can be retained, and in the filler cell region FC3, referencing filler cell F1 (in Figure 6 (middle) can be replaced by the eighth filler unit F8.

[0088] In another example implementation, in the filler unit region FC2_1, the reference filler unit F1 (in Figure 6 (in) can be filled by the ninth filler unit F9 (in) Figure 7 (in) replacement, while the reference filler unit F1 (in) Figure 6 (In the middle) can be selected as a suitable filler unit and can be retained, including filler unit regions FC2_1 and FC2_2. The filler unit in filler unit region FC2 can be replaced by combined filler unit F38 (in Figure 5J middle).

[0089] In another example implementation, it can be achieved by... Figure 2 The same method described in the example implementation shown forms the layout. For example, forming the reference filler unit F1 (S30) may not be performed (in Figure 1 (in the middle), and can execute the formation of multiple standard units (S25) (in Figure 2 (in the middle). Afterwards, pattern analysis (S36) can be performed (in... Figure 2 The operation (S50) is used to obtain information about the width of each of the active lines ACT_1 and ACT_2 of the first to third standard units C1a, C2a, and C3a, and can perform the formation of filler units (S50) that have active lines continuous with the active lines ACT of the first to third standard units C1a, C2a, and C3a in regions where the first to third standard units C1a, C2a, and C3a are not formed. This can be used... Figures 5A to 5F The first to thirty-ninth filler units F1 to F39 shown form filler units.

[0090] In the following description, the description will use... Figure 7 The semiconductor device formed by the layout shown.

[0091] Figures 8A to 8C It shows the use Figure 7 The layout shown is a plan view of a semiconductor device manufactured using this method. Figure 9 It is shown Figure 8C An enlarged view of a portion of the semiconductor device shown. Figures 10A to 10C This is a cross-sectional view showing a semiconductor device according to an example embodiment. Figures 10A to 10C middle, Figure 10A It is along Figure 8A A cross-sectional view taken from line I-I' in the diagram. Figure 10B It is along Figure 8A Cross-sectional views taken from lines II-II' and III-III' in the diagram. Figure 10C It is along Figure 8A The cross-sectional view taken from line IV-IV' in the diagram.

[0092] exist Figures 8A to 8C middle, Figure 8B It is shown Figure 8A A plan view of a portion of the components shown. Figure 8C It is shown Figure 8B The example floor plan shown further includes Figure 8A A portion of the components shown. Figures 8A to 8C It shows the basis Figure 7 The layout shown is an example plan view of a semiconductor device. Therefore, Figure 7 The elements of the layout shown can be reflected in Figures 8A to 8C The plan view shown. In the following description, in the description of the semiconductor device according to the example embodiment, in Figure 7 Of the components in the layout shown, the main focus will be on components that are modified during the process of manufacturing semiconductor devices, as well as those that... Figure 7 Components not shown in the layout. Therefore, in Figure 7 Among the components shown, those whose planar shape has not changed can be directly referenced without repeating their detailed descriptions, or their descriptions can be briefly described.

[0093] Reference Figures 8A to 8C The first to third standard units C1a, C2a and C3a, as well as the filler units F8, F9 and F1, can be formed by the semiconductor device process (S80) (in Figure 1 and Figure 2 (The middle) is reflected and formed in semiconductor devices. For example, in Figure 7 The filler cells F8, F9, and F1 in the layout shown can be formed using a semiconductor device process (S80) (in Figure 1 and Figure 2 The plurality of contact plugs (CNTs), the plurality of lower conductors (M1), the plurality of lower passages (V0), the plurality of upper passages (V1), and the upper conductor (M2) can be connected to... Figure 7 The layout shown is largely the same. (Reflects...) Figure 7 The layout shown includes an active line ACT' that can be set, and line patterns SP and GATE that reflect line pattern GL can be set. Line patterns SP and GATE can include... Figure 7 The layout shown includes the dummy line SP corresponding to the dummy line GL_D, and the dummy line SP corresponding to the dummy line GL_D. Figure 7 The layout shown includes the gate line GL_G corresponding to the gate line GATE (i.e., the device gate line).

[0094] In an example implementation, the dummy line SP may include a first dummy line SP1 adjacent to the standard cell and a second dummy line SP2 disposed between the adjacent first dummy lines SP1.

[0095] In the filled cell region FC, the dummy source / drain region SD_d can be set on the active line ACT'. In the standard cell region SC, the circuit source / drain region SD_a can be set on the active line ACT'. Each circuit source / drain region SD_a can have a symmetrical structure.

[0096] A portion of the dummy source / drain region SD_d can have an asymmetric structure. For example, the dummy cell F8d (corresponding to...) Figure 7 The eighth filling unit F8 (in the filling unit regions FC1 and FC3 described in the text) is formed in the filling unit region FC1. Figure 7 (in) and dummy unit F9d (corresponding to in) Figure 7 The ninth filling unit F9 (in the filling unit region FC2_1 described in the text) is formed in the filling unit region FC2_1. Figure 7 The source / drain regions SD_d of dummy cells F8d and F9d can have asymmetric structures. For example, each side surface of the source / drain region SD_d of dummy cells F8d and F9d can have an asymmetric structure in the second horizontal direction (Y).

[0097] In semiconductor devices, Figure 7 The plurality of standard cell regions SC in the layout shown can be referred to as circuit regions, and the filler cell region FC can be referred to as dummy regions. The standard cell regions SC may include a first circuit region SC2 and a second circuit region SC3 disposed in a first horizontal direction (X), and the dummy region FC may include a first dummy region FC3 disposed between the first circuit region SC2 and the second circuit region SC3.

[0098] The active line ACT' may include a first active line ACT_1' and a second active line ACT_2' extending in the first horizontal direction (X) and intersecting with the first circuit region SC2, the dummy region FC3, and the second circuit region SC3. The first active line ACT_1' and the second active line ACT_2' may be opposite each other. The first active line ACT_1' may be disposed in the N-well region NWELL. The first active line ACT_1' disposed in the N-well region NWELL may have N-type conductivity, and the second active line ACT_2' not disposed in the N-well region NWELL may have P-type conductivity.

[0099] The first active line ACT_1' may include the first active circuit portion AT1 disposed in the first circuit region SC2 (in Figure 8B (in the middle), the first virtual active part AD1 set in the virtual region FC3 (in Figure 8B (in the middle) and the second circuit active part AT2 located in the second circuit region SC3 (in Figure 8B(Middle). The second active line ACT_2' may include the third active circuit region AT3 located in the first circuit region SC2. Figure 8B (in the middle), the second virtual active part AD2 set in the virtual region FC3 (in Figure 8B (middle) and the fourth active circuit AT4 located in the second circuit region SC3 (middle) and Figure 8B (in the middle). The first dummy source part AD1 (in Figure 8B (in) and the second dummy active part AD2 (in) Figure 8B (In the middle) can be set between a pair of adjacent dummy lines SP1.

[0100] The active portion AT1 of the first circuit can have a first width in the second horizontal direction (Y). The active portion AT2 of the second circuit can have a second width in the second horizontal direction (Y) that is smaller than the first width. The first dummy active portion AD1 (in Figure 8B The first width portion (specified in the image) may have a first width portion, a second width portion, and a first width-changing portion disposed between the first width portion and the second width portion, wherein the first width portion has the same width as the first width, and the second width portion has the same width as the second width. The first width-changing portion may be disposed between a pair of dummy lines SP1. (Refer to...) Figure 9 Describe the portion where the first width changes.

[0101] Reference Figure 9 Describe dummy cells F8d and F9d. Dummy cell F8d, located in the filler cell region FC3, will be referred to as the first dummy cell. Dummy cell F9d, located in the filler cell region FC2_1, will be referred to as the second dummy cell.

[0102] Reference Figure 9 In the active line ACT', the first active line ACT_1' set in the first dummy unit F8d can be defined as the first dummy active region ACT_1d1'. The second active line ACT_2' set in the first dummy unit F8d can be defined as the second dummy active region ACT_2d1'.

[0103] In the example implementation, the first dummy source region ACT_1d1' can also be referred to as the first dummy source portion AD1. The second dummy source region ACT_2d1' can also be referred to as the second dummy source portion AD2.

[0104] In the first dummy unit F8d, the first dummy source region ACT_1d1' may include a first width portion A1a having a first width in the second horizontal direction (Y), a second width portion A2a having a second width less than the first width in the second horizontal direction (Y), and a first width changing portion A3a disposed between the first width portion A1a and the second width portion A2a. The second dummy source region ACT_2d1' may include a third width portion A1b having a first width, a fourth width portion A2b having a second width, and a second width changing portion A3b disposed between the third width portion A1b and the fourth width portion A2b.

[0105] In the first dummy unit F8d, the lengths of the first width portion A1a and the second width portion A2a in the first horizontal direction (X) can be substantially the same. Therefore, the first width-changing portion A3a can be disposed in the middle portion between adjacent line patterns SP. In the first dummy unit F8d, the lengths of the third width portion A1b and the fourth width portion A2b in the first horizontal direction (X) can be substantially the same. Therefore, the second width-changing portion A3b can be disposed in the middle portion between adjacent line patterns SP.

[0106] In the active line ACT', the first active line ACT_1' set in the second dummy unit F9d can be defined as the third dummy active region ACT_1d2'. The second active line ACT_2' set in the second dummy unit F9d can be defined as the fourth dummy active region ACT_2d2'.

[0107] In the second dummy unit F9d, the third dummy source region ACT_1d2' may include a fifth width portion A1a' having a second width, a sixth width portion A2a' having a first width, and a third width-changing portion A3a' disposed between the fifth width portion A1a' and the sixth width portion A2a'. The fourth dummy source region ACT_2d2' may include a seventh width portion A1b' having a second width, an eighth width portion A2b' having a first width, and a fourth width-changing portion A3b' disposed between the seventh width portion A1b' and the eighth width portion A2b'.

[0108] In the second dummy unit F9d, the length of the fifth width portion A1a' in the first horizontal direction (X) can be greater than the length of the sixth width portion A2a' in the first horizontal direction (X). Therefore, in the second dummy unit F9d, the third width-changing portion A3a' can be adjacent to one of the adjacent line patterns SP. In the second dummy unit F9d, the length of the seventh width portion A1b' in the first horizontal direction (X) can be greater than the length of the eighth width portion A2b' in the first horizontal direction (X). Therefore, in the second dummy unit F9d, the fourth width-changing portion A3b' can be adjacent to one of the adjacent line patterns.

[0109] The first dummy source region ACT_1d1' may have a first dummy source-side surface S1 and a second dummy source-side surface S2 that are opposite to each other. The second dummy source region ACT_2d1' may have a third dummy source-side surface S3 and a fourth dummy source-side surface S4 that are opposite to each other. The second dummy source-side surface S2 and the third dummy source-side surface S3 may be opposite to each other.

[0110] In the plan view, each of the first dummy source-side surface S1 of the first dummy source region ACT_1d1' and the fourth dummy source-side surface S4 of the second dummy source region ACT_2d1' can have a straight line shape.

[0111] The second dummy source-side surface S2, which has a first dummy source region ACT_1d1', may have a curved portion in the plan view. The third dummy source-side surface S3, which has a second dummy source region ACT_2d1', may also have a curved portion in the plan view.

[0112] The dummy source / drain region SD_d can include a first dummy source / drain region SD_d1 on the first dummy source region ACT_1d1' and a second dummy source / drain region SD_d2 on the second dummy source region ACT_2d1'. Each of the first dummy source / drain region SD_d1 and the second dummy source / drain region SD_d2 can have an asymmetric structure.

[0113] In an example implementation, the reference unit can be replaced with various other dummy units based on the size and shape of each of the circuit region and the dummy region, as well as the arrangement of the circuit region and the dummy region. Figure 8C and Figure 9 The described dummy units (first and second dummy units F8d and F9d) can be used, for example, with reference to... Figures 5A to 5F The dummy cells formed by the first to thirty-ninth filler cells F1 to F39 described herein replace the first dummy cell F8d and the second dummy cell F9d. Therefore, the semiconductor device in the example embodiment may include dummy cells formed using the first to thirty-ninth filler cells F1 to F39.

[0114] Figures 10A to 10C This is a cross-sectional view showing a semiconductor device according to an example embodiment. Figure 10A It is along Figure 8A A cross-sectional view taken from line I-I' in the diagram. Figure 10B It is along Figure 8A Cross-sectional views taken from lines II-II' and III-III' in the diagram. Figure 10C It is along Figure 8A The cross-sectional view taken from line IV-IV' in the diagram.

[0115] Refer to together Figures 10A to 10C as well as Figures 8A to 8C An active line ACT' can be disposed on the semiconductor substrate 5. The active line ACT' may include a first active line ACT_1' disposed in the N-well region NWELL. The active line ACT' may also include a second active line ACT_2' not disposed in the N-well region NWELL and opposite to the first active line ACT_1'.

[0116] An isolation layer 10 for limiting the active line ACT' can be disposed on the semiconductor substrate 5. The isolation layer 10 can be formed of an insulating material such as silicon oxide.

[0117] In the active line ACT', the active line ACT' set in the circuit region SC can be defined as the circuit active region ACT_a, and the active line ACT' set in the filler cell region FC can be defined as the dummy active region ACT_d.

[0118] The source / drain region SD_a of the circuit can be set on the active region ACT_a of the circuit, and the dummy source / drain region SD_d can be set on the dummy active region ACT_d.

[0119] The virtual source / drain region SD_d can be included in Figure 9 The example embodiment shown depicts a first dummy source / drain region SD_d1 and a second dummy source / drain region SD_d2. The active circuit region ACT_a may include a first active circuit region ACT_a1 and a second active circuit region ACT_a2. The first active circuit region ACT_a1 may be located on a first active line ACT_1', and the second active circuit region ACT_a2 may be located on a second active line ACT_2'.

[0120] The circuit source / drain region SD_a can be included in the first circuit source / drain region SD_a1 on the first circuit active region ACT_a1 and the second circuit source / drain region SD_a2 on the second circuit active region ACT_a2.

[0121] The gate line in the multiple line patterns SP and GATE may include a gate 27 and an insulating capping layer 30 on the gate 27. The gate 27 may include a gate dielectric 20 and a gate electrode 25 on the gate dielectric 20. The gate dielectric 20 may include silicon oxide and / or a high-k dielectric. The gate electrode 25 may include doped silicon, metal nitrides (e.g., TiN, TaN, TiSiN, WN, etc.) and / or metals (e.g., Ti, Ta, W, etc.).

[0122] Multiple semiconductor layers 15, stacked and spaced apart from each other in a direction perpendicular to the upper surface of the semiconductor substrate 5, can be disposed on the active circuit region ACT_a. The multiple semiconductor layers 15 may include multiple first semiconductor layers 15a on the first active circuit region ACT_a1 and multiple second semiconductor layers 15b on the second active circuit region ACT_a2. A gate 27 may overlap with the multiple semiconductor layers 15 and may cover the upper and lower surfaces of the multiple semiconductor layers 15. In an example embodiment, the multiple semiconductor layers 15 may be formed of a semiconductor material (e.g., silicon).

[0123] The plurality of semiconductor layers 15 may be disposed between adjacent circuit source / drain regions SD_a. The plurality of semiconductor layers 15 may be electrically connected to adjacent circuit source / drain regions SD_a.

[0124] In an example embodiment, an internal spacer 40 may be disposed between the source / drain region SD_a and the gate 27. The internal spacer 40 may be formed of an insulating material such as silicon oxide. In another example embodiment, the internal spacer 40 may be omitted.

[0125] In an example embodiment, gate spacers 35 covering the side surface of the gate 27 and the side surface of the insulating cover layer 30 may be disposed on the plurality of semiconductor layers 15.

[0126] The first dummy line SP1 in the plurality of line patterns SP and GATE can extend from the top of the active line ACT' into the active line ACT'. The first dummy line SP1 can electrically isolate the adjacent circuit source / drain regions SD_a and dummy source / drain regions SD_d from each other. The first dummy line SP1 can be formed of an insulating material such as silicon oxide and / or silicon nitride.

[0127] In an example implementation, each second dummy line SP2 in the plurality of line patterns SP and GATE can have the same structure as the gate line GATE. Therefore, the first dummy line SP1 can be formed of an insulating material. The second dummy line SP2 can include the same conductive material as the conductive material of the gate electrode 25 of the gate line GATE. The second dummy line SP2 can also include a material different from that of the first dummy line SP1.

[0128] In another example implementation, the second dummy line SP2 can be configured to have the same structure as the first dummy line SP1. Therefore, the first dummy line SP1 and the second dummy line SP2 can be formed from the same material.

[0129] An interlayer insulating layer 60 covering the dummy source / drain region SD_d and the circuit source / drain region SD_a can be disposed on the isolation layer 10. The interlayer insulating layer 60 can cover the entire upper surface of each dummy source / drain region SD_d.

[0130] Contact plugs (CNTs) can be configured. Contact plugs (CNTs) can be formed of a conductive material. Contact plugs (CNTs) can include: circuit source / drain contact plugs (CNTs)_c1 and CNT_c2 that are in contact with and electrically connected to the circuit source / drain region SD_a; and a gate contact plug (CNT_G) that is in contact with and electrically connected to the gate electrode 25.

[0131] In an example implementation, the circuit source / drain contact plugs CNT_c1 and CNT_c2 may include a first source / drain contact plug CNT_c1 and a second source / drain contact plug CNT_c2 having different lengths in a second horizontal direction (Y).

[0132] Of the source / drain contact plugs CNT_c1 and CNT_c2, the plug with a relatively larger length in the second horizontal direction (Y) can be defined as the first source / drain contact plug CNT_c1. The plug with a relatively shorter length in the second horizontal direction (Y) can be defined as the second source / drain contact plug CNT_c2. Therefore, the length of the first source / drain contact plug CNT_c1 in the second horizontal direction (Y) can be greater than the length of the second source / drain contact plug CNT_c2 in the second horizontal direction (Y).

[0133] In another example implementation, the contact plug CNT may further include a dummy contact plug CNT_d that contacts the dummy source / drain region SD_d on the dummy source / drain region SD_d.

[0134] In another example implementation, the dummy contact plug CNT_d can be omitted. When the dummy contact plug CNT_d is omitted, the entire upper surface of the dummy source / drain region SD_d can contact the interlayer insulation layer 60.

[0135] The first upper interlayer insulation layer 70 and the second upper interlayer insulation layer 80 can be disposed on the interlayer insulation layer 60.

[0136] A lower passage V0, which contacts and is electrically connected to the contact plug CNT, can be provided on the contact plug CNT. A lower conductor M1, electrically connected to the lower passage V0, can be provided on the lower passage V0. An upper passage V1, electrically connected to the lower conductor M1, can be provided on the lower conductor M1. An upper conductor M2, electrically connected to the upper passage V1, can be provided on the upper passage V1. Passages V0 and V1, as well as conductors M1 and M2, can be formed of a conductive material.

[0137] In an example embodiment, each of the lower path V0 and the lower conductor M1 may have an inlay structure in the first upper interlayer insulation layer 70. In an example embodiment, each of the upper path V1 and the upper conductor M2 may have an inlay structure in the second upper interlayer insulation layer 80.

[0138] In the following description, reference will be made to Figure 11 , Figure 12 and Figure 13 A variation of the semiconductor device according to the example implementation is described.

[0139] Figure 11 yes Figure 8C The diagram shows a plan view of the semiconductor device, which also includes a baseline RX'. Figure 12 It is shown Figure 11 The diagram shows a portion of the semiconductor device, which also includes a baseline RX'. Figure 13 It is along Figure 11 The cross-sectional views of the semiconductor device shown by lines II-II' and III-III', which also include baseline RX', will be primarily referenced in the following description. Figures 11 to 13 Add description Figure 8C , Figure 9 and Figure 13 The baseline RX' is shown in the example.

[0140] In the example implementation, refer to Figures 11 to 13 The baseline RX' can be disposed on the semiconductor substrate 5. Active lines ACT' can be disposed on the baseline RX'. The width of each active line ACT' can be smaller than the width of each baseline RX'. In an example embodiment, each baseline RX' can have a planar shape substantially the same as that of each active line ACT', and can have a width greater than the width of each active line ACT'.

[0141] The isolation layer 10 can be extended to cover the side surface of the baseline RX'.

[0142] refer to Figures 5A to 5F The described filler units F1 to F39 can be formed using active lines having a first width and active lines having a second width different from the first width. In another example embodiment, filler units can be formed using active lines having three or more different widths. (See also...) Figure 14A The description includes example implementations of filler units with active lines of varying widths.

[0143] Reference Figure 14A Filler unit F1' may include an active line ACT having a first width W1, filler unit F2' may include an active line ACT having a second width W2 greater than the first width W1, filler unit F3' may include an active line ACT having a third width W3 greater than the second width W2, and filler unit F4' may include an active line ACT having a fourth width W4 greater than the third width W3.

[0144] In the example implementation, filler units can be formed by combining active lines having first to fourth widths W1 to W4 in various ways. (Refer to...) Figure 14B and Figure 14C The description includes an example implementation of a filler unit comprising a single active line, which can be formed using active lines of different widths.

[0145] Reference Figure 14B and Figure 14C Filler unit F5' may include an active line ACT, which includes a portion having a first width W1 and a portion having a second width W2. Filler unit F6' may include an active line ACT, which includes a portion having a first width W1 and a portion having a third width W3. Filler unit F7' may include an active line ACT, which includes a portion having a first width W1 and a portion having a fourth width W4. Filler unit F8' may include an active line ACT, which includes a portion having a second width W2 and a portion having a third width W3. Filler unit F9' may include an active line ACT, which includes a portion having a second width W2 and a portion having a fourth width W4. Filler unit F10' may include an active line ACT, which includes a portion having a third width W3 and a portion having a fourth width W4.

[0146] In the example implementation, the active line ACT having a first width W1 to a fourth width W4 can be applied to either the filler cell or the standard cell. Therefore, the reference can be replaced with an active line having two or more widths instead of two different widths. Figures 8A to 8C Each active line ACT' is described.

[0147] The aforementioned filler cells and standard cells can be formed using active lines with different widths. In another example embodiment, the active line with the narrowest width can be designated as a reference active line, and the portion of the active line with increased width can be replaced by multiple reference active lines. Figures 15A to 15C The above example implementation method is described.

[0148] Figures 15A to 15C It shows the relationship with Figures 14A to 14C The filling units F1' to F10' shown correspond to the filling units F1" to F10".

[0149] Reference Figure 14A and Figure 15A It can provide with Figure 14A The filling unit F1' shown corresponds to the filling unit F1". A filling unit F2" with two active lines ACTa can be provided as a replacement. Figure 14A The filler unit F2' shown in Figure 14 can be replaced by a filler unit F3' with three active lines ACTa. A filler unit F4' with four active lines ACTa can also be replaced by... Figure 14A The filling unit F4' shown is shown.

[0150] Reference Figure 14B , Figure 14C , Figure 15B and Figure 15C Filler units F5' to F10' (in Figure 14B and Figure 14C The active line (described in the text) can be used with reference to Figure 15A The method described is by Figure 15B and Figure 15C The active line replacement of the filler units F5” to F10” (which include multiple active lines) described in the document. For example, in Figure 14B and Figure 14C In this context, an active line with a second width W2 can be replaced by two active lines, an active line with a third width W3 can be replaced by three active lines, and an active line with a fourth width W4 can be replaced by four active lines.

[0151] As described above, semiconductor devices can be formed by applying filler cells (e.g., filler cells F5” to F10”) formed by replacing a single active line with multiple active lines.

[0152] Reference Figures 8A to 8C The first active line ACT_1' described can be configured as a single active line comprising portions of different widths. The second active line ACT_2' can also be a single active line comprising portions of different widths. (Refer to...) Figures 8A to 8C In the first active line ACT_1', sections with different widths can be replaced with different numbers of active lines. Similarly, in the second active line ACT_2', sections with different widths can be replaced with different numbers of active lines. (Refer to...) Figure 16A and Figure 16B The description can replace the reference. Figures 8A to 8C The active lines described are the first active line ACT_1' and the second active line ACT_2'.

[0153] Figure 16A It is shown that Figure 8C The plan view of an example implementation shown, in which the relatively narrow portions (i.e., having a relatively small width) of each of the first active line ACT_1' and the second active line ACT_2' are replaced by two active lines and the relatively wide portions (i.e., having a relatively large width) are replaced by three active lines. Figure 16B It is shown Figure 16A An enlarged plan view of a portion of the semiconductor device shown, in which Figure 9 The relatively narrow portions (i.e., having a relatively small width) of each of the first active line ACT_1' and the second active line ACT_2' shown are replaced by two active lines (or active fins), and the relatively wide portions (i.e., having a relatively large width) are replaced by three active lines (or active fins). In the following description, the portions of each of the first active line ACT_1' and the second active line ACT_2' with relatively small width (and replaced by two active lines (or active fins)) and the portions with relatively large width (replaced by three active lines (or active fins)) will be described primarily.

[0154] Figure 17 , Figure 18 and Figure 19 It is along Figure 16A The cross-sectional view taken from line IVa-IVa' in the diagram. (Refer to...) Figure 16A , Figure 16B and Figure 17 , refer to Figures 8A to 8C and Figure 9 The first active line described is ACT_1' (in Figures 8A to 8C (The first active fin, ACTa_1', can be replaced.) See reference. Figures 8A to 8C and Figure 9 The described second active line ACT_2' can be replaced by the second active fin ACTa_2'. Therefore, refer to Figures 8A to 8C and Figure 9 The described active line ACT' can be replaced by an active line ACTa' that includes first and second active fins ACTa_1' and ACTa_2'.

[0155] In reference Figures 8A to 8C The first active line described is ACT_1' (in Figures 8A to 8C (in Chinese) Figures 8A to 8C The first active line ACT_1' in the first active line has a relatively large width of first active portion AT1, which can be a first active portion AT1a including a relatively large number of first active lines ACTa_1' (in Figure 16A (Chinese) Replace. Refer to... Figures 8A to 8C The first active line described is ACT_1' (in Figures 8A to 8C (in Chinese) Figures 8A to 8C The second active portion AT2, which has a relatively small width, can be a second active portion AT2a that includes a relatively small number of the first active lines ACT_1' (in...). Figure 16A (Chinese) Replace. Refer to... Figures 8A to 8C and Figure 9 The first active line described is ACT_1' (in Figures 8A to 8C In the (middle) section, the first dummy active portion AD1, including the width-changing portion, can be replaced by the dummy active portion AD1a, which includes the first active line ACTa_1' with varying quantity. For example, Figures 8A to 8C and Figure 9 The relatively narrow section of the active line ACT' shown can be replaced with two active fins. Figures 8A to 8C and Figure 9 The relatively wide portion of the active line ACT' shown can be replaced with three active fins.

[0156] In the shown Figures 8A to 8C The cross-sectional structure of the example shown Figure 10A and Figure 10C In this case, semiconductor layer 15 can be omitted (in Figure 10A and Figure 10C middle). Figure 10A and Figure 10C The gate 27 shown (in) Figure 10A and 10C (in) can be the protrusions ACTa_a covering the first and second active fins ACTa_1' and ACTa_2' (in) Figure 17The gate 127 is replaced on the upper and side surfaces of the gate. The gate 127 may include a gate dielectric 120 and a gate electrode 125 on the gate dielectric 120. A gate capping layer 130 may be disposed on the gate 127. The gate 127 and the gate capping layer 130 may be included in the gate line GATE.

[0157] The following description will describe Figure 18 The cross-sectional structure of the semiconductor device shown further includes a baseline RX'.

[0158] Reference Figure 18 ,and Figure 17 Compared to the cross-sectional structure shown, the baseline RX' can be further disposed between the active fin ACTa' and the semiconductor substrate 5. The baseline RX' may include a first baseline RX_1' disposed in the N-well region NWELL and a second baseline RX_2' spaced apart from the first baseline RX_1'.

[0159] Reference Figure 19 ,and Figure 17 Compared to the cross-sectional structure shown, the protrusions ACTa_a of the active fin ACTa' covered by the gate 127 can be replaced with nanowires ACTa_a'. Each nanowire ACTa_a' can be surrounded by the gate 127.

[0160] As described above, the embodiments relate to a method for forming a layout and a semiconductor device manufactured by the method.

[0161] Implementation methods can provide semiconductor devices with increased integration density.

[0162] The implementation can provide semiconductor devices that exhibit improved reliability.

[0163] As described above, the dummy region including the dummy active portion can be disposed between the first circuit region including the first circuit active portion having a first width and the second circuit region including the second circuit active portion having a second width different from the first width.

[0164] The dummy active portion may include a first dummy portion having a first width, a second dummy portion having a second width, and a width-changing portion disposed between the first dummy portion and the second dummy portion. The first dummy portion is continuous with the active portion of the first circuit, and the second dummy portion is continuous with the active portion of the second circuit.

[0165] The first dummy portion can be disposed between the width-changing portion and the active portion of the first circuit. The second dummy portion can be disposed between the width-changing portion and the active portion of the second circuit. The first dummy portion and the second dummy portion can serve as buffers to prevent width changes in the active portions of the first and second circuits.

[0166] Therefore, each of the first and second active circuit portions can be configured to have a uniform width, thereby preventing performance changes in devices (e.g., transistors) formed in the first and second circuit regions. This improves the reliability of the semiconductor device and enhances its distribution performance. Furthermore, it reduces the gap (size of the dummy region) between the first and second circuit regions. Consequently, it enables the manufacture of reliable semiconductor devices and increases their integration density.

[0167] Exemplary embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some cases, it will be apparent to those skilled in the art at the time of filing of this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

[0168] The entire contents of Korean Patent Application No. 10-2019-0147361, filed with the Korean Intellectual Property Office on November 18, 2019, entitled “Semiconductor Device”, are incorporated herein by reference.

Claims

1. A semiconductor device comprising: a pair of first dummy active regions and second dummy active regions extending in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; a pair of first circuit active regions and second circuit active regions extending in the first horizontal direction and spaced apart from each other in the second horizontal direction; a plurality of line patterns extending in the second horizontal direction and spaced apart from each other in the first horizontal direction; a first dummy source / drain region on the first dummy active region and a second dummy source / drain region on the second dummy active region; and a first circuit source / drain region on the first circuit active region and a second circuit source / drain region on the second circuit active region, wherein: the pair of first dummy active regions and second dummy active regions are provided between a pair of line patterns adjacent to each other among the plurality of line patterns, at least one of the first dummy active region and the second dummy active region has a width change portion which is a portion in which a width of the at least one of the first dummy active region and the second dummy active region changes in the second horizontal direction between the pair of line patterns adjacent to each other, each of the first circuit source / drain region and the second circuit source / drain region has a symmetrical structure in a plan view, and at least one of the first dummy source / drain region and the second dummy source / drain region has an asymmetrical structure in a plan view. in a plan view, 2. The semiconductor device of claim 1, wherein, the first dummy active region has a first dummy active side surface and a second dummy active side surface opposite to each other, the second dummy active region has a third dummy active side surface and a fourth dummy active side surface opposite to each other, the second dummy active side surface and the third dummy active side surface face each other, and in a plan view, each of the first dummy active side surface of the first dummy active region and the fourth dummy active side surface of the second dummy active region has a substantially straight linear shape.

3. The semiconductor device according to claim 2, wherein the second dummy active side surface of the first dummy active region has a curved portion in a plan view.

4. The semiconductor device according to claim 3, wherein the third dummy active side surface of the second dummy active region has a curved portion in a plan view.

5. The semiconductor device according to claim 1, wherein: the first dummy active region includes a first width portion, a second width portion, and a first width change portion between the first width portion and the second width portion, a width of the first width portion in the second horizontal direction is larger than a width of the second width portion in the second horizontal direction, and a length of the first width portion in the first horizontal direction is substantially the same as a length of the second width portion in the first horizontal direction.

6. The semiconductor device according to claim 1, wherein: ​ the first dummy active region includes a first width portion, a second width portion, and a first width change portion between the first width portion and the second width portion, a width of the first width portion in the second horizontal direction is greater than a width of the second width portion in the second horizontal direction, and a length of the first width portion in the first horizontal direction is different from a length of the second width portion in the first horizontal direction.

7. The semiconductor device of claim 1, wherein: the first dummy active region includes a first width portion, a second width portion, and a first width change portion between the first width portion and the second width portion, a width of the first width portion in the second horizontal direction is greater than a width of the second width portion in the second horizontal direction, the second dummy active region includes a third width portion, a fourth width portion different from the third width portion, and a second width change portion between the third width portion and the fourth width portion, and a width of the third width portion in the second horizontal direction is greater than a width of the fourth width portion in the second horizontal direction.

8. The semiconductor device of claim 7, wherein the first width portion and the third width portion are opposite each other.

9. The semiconductor device of claim 1, wherein: the first dummy active region includes a first width portion, a second width portion, and a first width change portion between the first width portion and the second width portion, a width of the first width portion in the second horizontal direction is greater than a width of the second width portion in the second horizontal direction, the second dummy active region includes a third width portion, a fourth width portion different from the third width portion, and a second width change portion between the third width portion and the fourth width portion, and a width of the third width portion in the second horizontal direction is less than a width of the fourth width portion in the second horizontal direction.

10. The semiconductor device of claim 1, further comprising: an interlayer insulating layer covering an entire upper surface of each of the first dummy source / drain region and the second dummy source / drain region; a first source / drain contact plug electrically connected to the first circuit source / drain region; and a second source / drain contact plug electrically connected to the second circuit source / drain region.

11. A semiconductor device, comprising: a semiconductor substrate; a first active line extending in a first horizontal direction on the semiconductor substrate and crossing a first circuit region, a dummy region, and a second circuit region, a second active line extending in the first horizontal direction on the semiconductor substrate and crossing the first circuit region, the dummy region, and the second circuit region; and a line pattern extending in a second horizontal direction perpendicular to the first horizontal direction on the semiconductor substrate, wherein: the first active line is disposed in an N-well region of the semiconductor substrate, the second active line is disposed in a P-well region of the semiconductor substrate, and the line pattern includes a first dummy line and a second dummy line. the second active line is spaced apart from the N-well region of the semiconductor substrate, the dummy region is provided between the first circuit region and the second circuit region, the first active line includes a first circuit active portion in the first circuit region, a first dummy active portion in the dummy region, and a second circuit active portion in the second circuit region, the second active line includes a third circuit active portion in the first circuit region, a second dummy active portion in the dummy region, and a fourth circuit active portion in the second circuit region, at least a portion of the first dummy active portion has a width different from a width of at least a portion of the second dummy active portion, the first circuit active portion has a first width in the second horizontal direction, the first width being uniform over an entire width of the first circuit region in the first horizontal direction, the second circuit active portion has a second width in the second horizontal direction, the second width being uniform over an entire width of the second circuit region in the first horizontal direction, the second width being different from the first width.

12. The semiconductor device of claim 11, wherein: the line pattern includes a pair of dummy lines adjacent to each other, the first dummy active region is provided between the pair of dummy lines, the first dummy active portion includes a first width portion having a width identical to the first width, a second width portion having a width identical to the second width, and a first width change portion between the first width portion and the second width portion, the first width change portion is provided between the pair of dummy lines, and the pair of dummy lines confines the first dummy active portion and confines the second dummy active portion.

13. The semiconductor device of claim 12, wherein the first width change portion of the first dummy active portion is adjacent to one of the pair of dummy lines.

14. The semiconductor device of claim 11, further comprising: a plurality of first semiconductor layers stacked in the first circuit active portion and spaced apart from each other; a plurality of second semiconductor layers stacked in the third circuit active portion and spaced apart from each other; a device gate line extending in the second horizontal direction and overlapping the plurality of first semiconductor layers and the plurality of second semiconductor layers in the first circuit region; a first circuit source / drain region provided on the first circuit active portion on both sides of the device gate line and connected to the plurality of first semiconductor layers; a second circuit source / drain region provided on the second circuit active portion on both sides of the device gate line and connected to the plurality of second semiconductor layers; a first source / drain contact plug electrically connected to the first circuit source / drain region; and a second source / drain contact plug electrically connected to the second circuit source / drain region.

15. The semiconductor device of claim 14, wherein: ​ one of the first source / drain contact plugs has a first length in the second horizontal direction, and another of the first source / drain contact plugs has a second length in the second horizontal direction that is different from the first length.

16. The semiconductor device according to claim 15, further comprising: a power supply wire; a wiring wire having a width smaller than a width of the power supply wire; a first lower via provided below the power supply wire; and a second lower via below the wiring wire, wherein: the first length is greater than the second length, the contact plug of the first source / drain contact plugs having the first length is electrically connected to the power supply wire through the first lower via, and the contact plug of the first source / drain contact plugs having the second length is electrically connected to the wiring wire through the second lower via.

17. The semiconductor device according to claim 11, further comprising a first base line extending on the semiconductor substrate in the first horizontal direction, wherein: the first active line is provided on the first base line, and the first base line has a width greater than a width of the first active line.

18. A semiconductor device comprising: a semiconductor substrate; an active line extending on the semiconductor substrate in a first horizontal direction and crossing a first circuit region, a dummy region, and a second circuit region in order; a first line pattern extending on the semiconductor substrate in a second horizontal direction perpendicular to the first horizontal direction on a first side of the first circuit region; a second line pattern extending on the semiconductor substrate in the second horizontal direction on a second side of the first circuit region, the second line pattern being at a boundary of the first circuit region and the dummy region; a third line pattern extending on the semiconductor substrate in the second horizontal direction on a first side of the second circuit region, the third line pattern being at a boundary of the dummy region and the second circuit region; a fourth line pattern extending on the semiconductor substrate in the second horizontal direction on a second side of the second circuit region; a respective circuit source / drain region above the active line in the first circuit region and the second circuit region; and a respective plurality of semiconductor layers provided on the active line in the first circuit region and the second circuit region, wherein: the active line in the first circuit region has a first width in the second horizontal direction, the first width being uniform over an entire width in the first horizontal direction between the first line pattern and the second line pattern, the active line in the second circuit region has a second width in the second horizontal direction, the second width being uniform over an entire width in the first horizontal direction between the third line pattern and the fourth line pattern, the second width being different from the first width, the active line in the dummy region includes a first width portion having the first width and a second width portion having the second width. ​ ​

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